AVG Semiconductors DDi Technical Data ~ Available Q2, 1995 8-Bit Parallel Load Shift DV74HC595 Register This device is an 8-Bit serial shift register and 8 latches with 3-state outputs. The shift register accepts serial data and provides a serial output (Delayed by 8 Clock Cycles). It also N Suffix provides 8 bits of data to the latches. The shift register and Plastic DIP latches have independent clock inputs. An output enable is AVG-003 Case provided for the 8 Tri-State outputs and asynchronous reset is. also provided for the shift register. Output Drive Capability: 10 LSTTL Loads D Suffix Outputs Directly Interface to CMOS, NMOS, and TTL Plastic SOP Operating Voltage Range: 2 to 6 V for HC Devices AVG-004 Case Low Input Current: 1 A DC, AC parameters guaranteed from -55C to 125C | 13 9 09 suet LATCH RECISTER REGISTER k. Oy * O9 PIN ASSIGNMENT SHIFT ith 2 03 Ly CLOCK 4 9, o,U1 16 CC 54 07 2 15 1] Og a Ls 03 [3 14 [] 89 10 05 0 - Output RESET -) Lo 4(f4 13D Enable 7 mn > Latch A 5 5 2 FS Glock LATCH 12 Og (16 11 [Shift CLOCK 4 4 = Clock 7 10 [) ourpur 13 7 05 1 - Reset ENABLE PIN 16 = Voc GND [| 8 9 [07 PIN 8 = GND TRUTH TABLE INPUTS INTERNAL OUTPUTS Reset} Do Shift |Latch|Output; .R. L.R\ Q7 00-07 Clock | Clock | Enable | Contents | Contents x X | LHL L L NC L NC H |HorL| T |LHL) LL | Qn=On1 NG O6 NC Qo=Do H x LHt| T L NC LR=SR NC SRO-7 x x x x H . Z H = High Logic Level T = Low to High Transition LA = Latch Register L = Low Logic Level NC = No Change X% = Don't Care | =High to Low Transition SR = Shift Register * = Depends on Previous Activity 1-800-AVG-SEMI 3-207 DV74HC595 S6SABSOLUTE MAXIMUM RATINGS Maximum ratings are those values beyond which damage to the device may occur. _Symbol Parameter Value Unit Vcc | OC Supply Voltage (Referenced to GND) =0.5 to +7.0 Vv Vin _| DC Input Voltage (Referenced to GND) =1.5 to Voc +1.5 Vv Vout | DC Output Voltage (Referenced to GND) 0.5 to Ver +0.5 V lin DC Input Current, per Pin +20 mA lour | OC Output Current, per Pin +25 mA lee | OC Supply Current, Voc and GND Pins +50 mA Po Power Dissipation in Still Air, Plastic DIP 750 mi | SOP Package 500 Tsta__| Storage Temperature Range 65 to +150 C Ti __| Lead Temperature, 1mm from Case for 10 Seconds 260 C GUARANTEED OPERATING CONDITIONS _Symbol | Parameter _Min Max Unit Vec | DC Supply Voltage (Referenced to GND) 2.0 6.0 V Vix, Vout | DC Input Voltage, Output Voltage (Referenced to GND) 0 Vec Vv Ta Ambient Temperature -55 +125 C t,t | Input Rise and Fall Time Veo=2.0V 0 1000 ns Voec=4.0V 0 500 Vec=6.0V 0 400 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Vee Guaranteed Limits Unit V 25C | <a5C | <125C to Lo Vw | Minimum High-Level | Vout =0.1 V, llourls20uA 2.0 1.5 1.5 1.5 Vv So Input Voltage of Vout = Veo-0.1V 45 | 315 | 315 | 3.15 Lf) 6.0 42 4.2 4.2 Vi Maximum Low-Level Vout =0.1 V, llouri<20nA 2.0 0.5 0.5 0.5 V Input Voltage ot Vour = Veo-0.1V 45 | 135 | 135 | 1.35 6.0 1.8 1.8 1.8 Vou | Minimum High-Level Vin = Vaxvor Vit 2.0 1.9 1.9 1.9 V Output Voltage llourls 20 ww 4.5 4.4 4.4 4.4 6.0 5.9 5.9 5.9 Vin = Via or Vit, llourls 4.0mA 4.5 3.98 3.84 37 | llourls 5.2 mA 60 | 548 | 534 | 52 VoL Maximum Low Level Vin = Vie or Vit 2.0 0.1 0.1 0.1 Vv Output Voltage llourls 20 A 45 0.1 0.1 0.1 6.0 0.1 0.1 0.1 Vin = Vie or Vit. llourls 4.0mA, 4.5 0.26 0.33 0.40 V lous S.2 mA 6.0 0.26 0.33 0.40 ling Maximum Input Vin = Vec or GND 6.0 40.1 | 1.00 | 10 yA | Leakage Current loc Maximum Quiescent Vin = Vcc or GND 6.0 8.0 80 160 pA Package) AC ELECTRICAL CHARACTERISTICS over full operating cond itions (4 =S0pF. Input tir=6ns) | Symbol Parameter Vee Guaranteed Limit Unit Vi | 25 | <a5c | <125C to =55C imax Maximum Clock Frequency (50% Duty Cycle) 2.0 5.0 4.0 3.4 MHz 4.5 25 20 7 6.0 29 24 20 DVT4HC595 5-208 1-800-AVG-SEMISymbol Parameter Vec Guaranteed Limit | Unit Vi | 28c | <asc | <125C to 5C tpun, | Maximum Propagation Delay Time, 2.0 210 265 315 ns tPHL Shift Clock to Q7 4.5 42 53 63 6.0 36 45 | 54 tPLH, Maximum Propagation Delay Time, 2.0 175 220 265 ns {PHL Latch Clock to Oo-O7, Reset to O7 4.5 35 44 53 6.0 30 37 45 tpLz, | Maximum Propagation Delay Time, 2,0 150 190 225 ns tpHz | Output Disable to Oo-O7 4.5 30 38 45 6.0 26 33 38 tezL, | Maximum Propagation Delay Time, 2.0 150 130 225 ns tPZH Output Enable to Op-O7 45 30 38 45 ; 6.0 26 33 38 tTLH, Maximum Output Transition Time 2.0 60 75 90 ns ITHL Oo-O7 4.5 12 15 18 6.0 10 13 15 tTLH, Maximum Output Transition Time 2.0 75 95 110 ns tTHL O; 4.5 15 19 ee 6.0 13 16 1 a Ciw | Maximum Input Capacitance 10 10 10 pF Cout | Maximum three-state Output Capacitance _ 15 15 15 pF (Qutput in High-lmpedence State), Qo through Q7 Cpp Power Dissipation Capacitance (Per Package) Typical @ 25C, Voc = 5 v Used to determine the no-load dynamic power consumption, 300 pF Po = Ceo Vec*f + lee Vee TIMING REQUIREMENTS (Input t=tj=6.0ns) Symbol Parameter Veo Guaranteed Limit Unit | Vo} 25C to) <85C |<125C -55C | tsu Minimum Setup Time, 2.0 50 65 75 ns | Da to Shift Clock 4.5 10 13 15 | 6.0 9.0 11 13 teu Minimum Setup Time, 2.0 100 125 150 ns | Shift Clock to Latch Clock 4.5 20 25 30 | 6.0 17 21 36 | th Minimum hold time, 2.0 5 5 5 ns | Clock to Input 4.5 5 5 5 6.0 5 5 5 trec Minimum Recovery Time, 2.0 50 65 5 ns | Clock te Inhibit 4,5 10 13 15 6.0 9 11 13 tw Minimum Pulse Width, Reset 2.0 50 65 75 ns Shift Clock, Latch Clock 4.5 10 13 15 6.0 9 11 13 1-800-AVG-SEM| 5-209 DV7T4HC595 S6S595 SWITCHING WAVEFORMS VALID V Data 4 WH Wr Enable GAD High teu th = Impedance Vy 10% Wee Vr ve Clock GND Vou 90% Wee Guiput High Impedance Input and output threshold voltage: Vr = 50% Vee for HC; 1.3V for HCT; Vi =Vec for HC, 3V for HCT DV74HC595 5-210 1-800-AVG-SEMIAVG Semiconductors Technical Data Available G2, 1995 8-Bit Parallel Load Serial Output Shift Register This device consists of 8 parallel input latches which feed an 8-bit shift register. The shift register can also be supplied serial data. The output is serial data. A latch clock is provided to load the latches. A separate shift clock is supplied to shift out data. The shift/load input asynchronously loads the shift register when driven low. An asynchronous reset is provided to clear the shift register. * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V for HC Devices Low Input Current: 71 wA DC, AC parameters guaranteed from -55C to 125C an DDi DV74HC597 N Suffix Plastic DIP AVG-003 Case D Suffix Plastic SOP AVG-004 Case 14 0 PIN ASSIGNMENT pp 8 Pp, Cte iwi %ec 1 LATCH SHIFT P 2 15 a REGISTER REGISTER 2U J Po Pa [3 14 Ho p, i Pace 13 [Sit Pp, 4 P5 (15 12 [j batch Pe [] 6 Wy shill 6 Oc F Ps 7 10 |] Reset Py 7 | 3 OF A GND [] 8 91] Q7 LATCH 412 ) _ cock PIN 16 = Ve SHIFT 11 | PIN & = GND Po-P7 : Parallel Inputs CLOCK ~~ Do : Serial Input SHIFT//LOAD reset TRUTH TABLE Latch Shift | Shift! | Reset Function Clock Clock| Load T x x x | Data loaded to input latches T x H H | Data loaded from inputs to shift register No clock edge x L H Data transferred from input flip-flops to shift register x x L L Invalid logic, state of shift register indeterminate when signals removed x L Shift register cleared T H H | Shift register clocked Qn=On-1, Qo=Do H = High Logic Level L = Low Logic Level T = Low to High Transition X= Don't care 1-800-AVG-SEMI 5-211 DV74HC595 Z6SABSOLUTE MAXIMUM RATINGS Maximum ratings are those values beyond which damage to the device may occur. Symbol Parameter Value __ Unit Voc | OC Supply Voltage (Referenced to GND) 0.5 to +7.0 V Vin DC Input Votage (Referenced to GND) 1.5 to Vee +1.5 Vv "Vout _ | OC Output Voltage (Referenced to GND) -0.5 to Vee +0.5 V lm | DC Input Current, per Pin +20 | mA lour | DC Output Current, per Pin +25 | mA icc | DC Supply Current, Vec and GND Pins +50 | mA Pp Power Dissipation in Still Air, Plastic DIP 750 mw SOP Package _ 500 Tsta__| Storage Temperature Range ea!) C TL Lead Temperature, 1mm from Case for 10 Seconds 260 "c GUARANTEED OPERATING CONDITIONS | Symbol _Parameter Min Max Unit _ Vee DC Supply Voltage (Reterenced to GND) 2.0 6.0 V Vin, Vout | OC Input Voltage, Output Voltage (Referenced to GNO) 0 Vee V Ta__| Ambient Temperature -55 +125 | C t,t | Input Rise and Fall Time Vec=2.0V 0 1000 ns Veo=4.0V 0 500 | Vec=6.0V 0 400 Dc ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Vee | Guaranteed Limits | Unit Vv 25C | <85C | <125C to 55C Vie Minimum High-Level Vour =0.1 V, Iloutl<20uA 2.0 1.5 1.5 1.5 V Oo) Input Voltage or Vour = Veo0.1V 4.5 3.15 3.15 3.15 LO 60 | 42 | 42 4.2 Ve | Maximum Low-Level Vour =0.1 V, Hlourls20uA 20 | OS 0.5 0.5 Vv Input Voltage or Vout = Vec-0.1V 45 1.35 1.35 1.35 6.0 1.8 1.8 1.8 Vou | Minimum High-Level Vin = Via or Vir 20 | 19 1.9 1.9 Vv Output Voltage Hour 20 pA 4.5 4.4 4.4 44 6.0 5.9 5.9 5.9 Vin = Vin or Vic. Nlourls 4.0mA 45 3.98 3.84 a7 llourls 5.2 mA 6.0 5.48 5.34 5.2 Vor Maximum Low Level Vin = Vincor Vic 2.0 0.1 0.1 0.1 V Output Voltage llourls 20 nA 4.5 0.1 0.1 0.1 6.0 0.1 0.1 0.1 Vin = Vieor Vir, lloutis 4.0mA 4.5 0.26 0.33 0.40 V llourl< 5.2 mA 6.0 0.26 0.33 0.40 lina Maximum Input Vin = Vcc or GND 6.0 0.1 + 1.0 +1.0 pA Leakage Current lec | Maximum Quiescent Vin = Voc or GND 6.0 8.0 80 160 wa Supply Current (Per lour= OpA Packago) AC ELECTRICAL SRScTERS ES over full operating conditions (C_=-50pF, Input trr=6ns) Symbol Vee Guaranteed Limit Unit Vi | 25c | <e5c | <125C to 55C tmax | Maximum Clock Frequency (50% Duty Cycle) 2.0 | 5.0 4.0 9.4 | MHz 4.5 25 20 17 60 | 29 24 20 DV7T4HC595 5-212 1-800-AVG-SEMISymbol 7 Parameter Vec | Guaranteed Limit Unit Vi | 28 | <es%c | <125c to -55C teu. | Maximum Propagation Delay Time, 2.0 210 265 315 ns teHL Latch Clock to O7 4.5 42 53 63 6.0 36 45 54 teuH, | Maximum Propagation Delay Time, 2.0 175 220 265 ns teu, | Shift Clock or Reset to Q7, Shift/Load to O7 4.5 35 44 53 6.0 30 37 45 tTLH, Maximum Output Transition Time 2.0 75 95 110 ns tra. | Any Output 45 15 19 22 6.0 13 16 19 Cin Maximum Input Capacitance 10 10 10 pF Ceo | Power Dissipation Capacitance (Per Package) Typical @ 25C, Voc = 5 V Used to determine the no-load dynamic power consumption, BO) pF Pp = Cpp Vec*t + lec Vee TIMING REQUIREMENTS (Input tt=6.0ns) Symbol Parameter Vec Guaranteed Limit Unit Vj 25C to!) <65C | <125C 55C teu Minimum Setup Time, Serial Data to Shift Clock, 2.0 100 125 150 ns Shitt(Load to Shift Clock, PO-P7 to Latch Clock 45 20 25 30 6.0 17 21 36 th Minimum hold time, 2.0 25 30 40 Latch Clock to Inputs 45 5 6 8 6.0 5 8 7 th Minimum hold time, 2.0 5 5 5 ns Shift Clock to Input 45 5 5 5 6.0 5 5 5 bree Minimum Recovery Time, 2.0 100 125 150 ns Reset Inacatiave to Shift/Clock 45 20 25 30 6.0 17 21 26 tw Minimum Pulse Width, Reset 2.0 80 100 120 ns Shift(Load, Latch CLock, Shift Clock 4.5 16 20 24 6.0 14 17 20 SWITCHING WAVEFORMS tp ve Cleck VT 10% _ tra Ttum iia oe = oo VI ee lee Vu Bota H " Chock ono GHD thy Yu Vr Clock: _. SND 1-800-AVG-SEMI 5-213 DV74HC595 Z6S