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1www.semtech.com
PROTECTION PRODUCTS
SRDA3.3-6 and SRDA05-6
RailClamp
Low Capacitance TVS Diode Array
Description Features
Circuit Diagram Schematic and PIN Configuration
Revision 01/15/08
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SR series has
been specifically designed to protect sensitive compo-
nents which are connected to data and transmission
lines from overvoltage caused by electrostatic dis-
charge (ESD), electrical fast transients (EFT), and
lightning.
The unique design of the SRDA series devices incorpo-
rates surge rated, low capacitance steering diodes and
a TVS diode in a single package. During transient
conditions, the steering diodes direct the transient to
either the positive side of the power supply line or to
ground. The internal TVS diode prevents over-voltage
on the power line, protecting any downstream compo-
nents.
The low capacitance array configuration allows the user
to protect six high-speed data or transmission lines.
The low inductance construction minimizes voltage
overshoot during high current surges. Applications
Mechanical Characteristics
USB Power & Data Line Protection
T1/E1 secondary IC Side Protection
Token Ring
HDSL, SDSL secondary IC Side Protection
Video Line Protection
Microcontroller Input Protection
Base stations
I2C Bus Protection
Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 24A (8/20µs)
Array of surge rated diodes with internal TVS diode
Protects six I/O lines and power supply line
Low capacitance (<15pF) for high-speed interfaces
Low operating & clamping voltages
Solid-state technology
JEDEC SO-8 package
UL 497B listed
Molding compound flammability rating: UL 94V-0
Marking : Part number, date code, logo
Packaging : Tube or Tape and Reel
S0-8 (Top View)
I/O 1
I/O 2
I/O 3 I/O 4
I/O 5
I/O 6
+VREF
GND
1
2
3
45
6
7
8
22008 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
SRDA3.3-6 and SRDA05-6
Absolute Maximum Rating
Electrical Characteristics
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(1) The SRDA3.3-6 is constructed using Semtech’s propri-
etary EPD process technology. See applications section for
more information.
32008 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
SRDA3.3-6 and SRDA05-6
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Electrical Characteristics (continued)
42008 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
SRDA3.3-6 and SRDA05-6
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve
0.01
0.1
1
10
0.1 1 10 100 1000
Pulse Duration - tp (µs)
Peak Pulse Power - Ppk (kW)
0
10
20
30
40
50
60
70
80
90
100
110
0 25 50 75 100 125 150
Ambient Temperature - TA (oC)
% of Rated Power or I
PP
Clamping Voltage vs. Peak Pulse Current
0
10
20
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30
Time (µs)
Percent of IPP
e-t
td = IPP/2
Waveform
Parameters:
tr = 8µs
td = 20µs
Pulse Waveform
Variation of Capacitance vs. Reverse Voltage Forward Voltage vs. Forward Current
-14
-12
-10
-8
-6
-4
-2
0
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Reverse Voltage - VR (V)
% Change in Capacitance
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35 40 45 50
Forward Current - IF (A)
Forward Voltage - V
F (V)
Waveform
Parameters:
tr = 8µs
td = 20µs
0
2
4
6
8
10
12
14
16
0 5 10 15 20 25 30
Peak Pulse Current - IPP (A)
Clamping Voltage - VC (V)
SRDA05-6
SRDA3.3-6
Waveform
Parameters:
tr = 8µs
td = 20µs
52008 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
SRDA3.3-6 and SRDA05-6
Device Connection Options for Protection of Six High-
Speed Lines
The SRDA TVS is designed to protect four data lines
from transient overvoltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode VF) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 1, 2, 4, 5, 6 and 7.
The negative reference is connected at pin 8. These
pins should be connected directly to a ground plane on
the board for best results. The path length is kept as
short as possible to minimize parasitic inductance.
The positive reference is connected at pins 2 and 3.
In the case of the SRDA3.3-6, pins 2 and 3 are
connected internally to the cathode of the low voltage
TVS. It is not recommended that these pins be directly
connected to a DC source greater than the snap-back
votlage (VSB) as the device can latch on as described
below.
EPD TVS Characteristics
These devices are constructed using Semtech’s
proprietary EPD technology. By utilizing the EPD tech-
nology, the SRDA3.3-6 can effectively operate at 3.3V
while maintaining excellent electrical characteristics.
The EPD TVS employs a complex nppn structure in
contrast to the pn structure normally found in tradi-
tional silicon-avalanche TVS diodes. Since the EPD
TVS devices use a 4-layer structure, they exhibit a
slightly different IV characteristic curve when compared
to conventional devices. During normal operation, the
device represents a high-impedance to the circuit up to
the device working voltage (VRWM). During an ESD
event, the device will begin to conduct and will enter a
low impedance state when the punch through voltage
(VPT) is exceeded. Unlike a conventional device, the low
voltage TVS will exhibit a slight negative resistance
characteristic as it conducts current. This characteris-
tic aids in lowering the clamping voltage of the device,
but must be considered in applications where DC
voltages are present.
When the TVS is conducting current, it will exhibit a
slight “snap-back” or negative resistance characteris-
tics due to its structure. This point is defined on the
Data Line Protection Using Internal TVS Diode as
Reference
Applications Information
curve by the snap-back voltage (VSB) and snap-back
current (ISB). To return to a non-conducting state, the
current through the device must fall below the ISB
(approximately <50mA) and the voltage must fall below
the VSB (normally 2.8 volts for a 3.3V device). If a 3.3V
TVS is connected to 3.3V DC source, it will never fall
below the snap-back voltage of 2.8V and will therefore
stay in a conducting state.
EPD TVS IV Characteristic Curve
IPP
ISB
IPT
IR
V
RWM VV PT VC
VBRR
IBRR
SB
62008 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
SRDA3.3-6 and SRDA05-6
PIN Descriptions
Figure 1 - “Rail-To-Rail” Protection Topology
(First Approximation)
Figure 2 - The Effects of Parasitic Inductance When
Using Discrete Components to Implement Rail-To-Rail
Protection
Figure 3 - Rail-To-Rail Protection Using
RailClamp TVS Arrays
Applications Information (continued)
approximation, the clamping voltage due to the charac-
teristics of the protection diodes is given by:
V
C
= V
CC
+ V
F
(for positive duration pulses)
V
C
= -V
F
(for negative duration pulses)
However, for fast rise time transient events, the
effects of parasitic inductance must also be consid-
ered as shown in Figure 2. Therefore, the actual
clamping voltage seen by the protected circuit will be:
V
C
= V
CC
+ V
F
+ L
P
di
ESD
/dt (for positive duration pulses)
V
C
= -V
F
- L
G
di
ESD
/dt (for negative duration pulses)
ESD current reaches a peak amplitude of 30A in 1ns
for a level 4 ESD contact discharge per IEC 1000-4-2.
Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = L
P
di
ESD
/dt = 1X10-9 (30 / 1X10-9) = 30V
Example:
Consider a V
CC
= 5V, a typical V
F
of 30V (at 30A) for the
steering diode and a series trace inductance of 10nH.
The clamping voltage seen by the protected IC for a
positive 8kV (30A) ESD pulse will be:
V
C
= 5V + 30V + (10nH X 30V/nH) = 335V
This does not take into account that the ESD current is
directed into the supply rail, potentially damaging any
components that are attached to that rail. Also note
the high V
F
of the discrete diode. It is not uncommon
for the V
F
of discrete diodes to exceed the damage
threshold of the protected IC. This is due to the
relatively small junction area of typical discrete compo-
nents. It is also possible that the power dissipation
capability of the discrete diode will be exceeded, thus
destroying the device.
The RailClamp is designed to overcome the inherent
disadvantages of using discrete signal diodes for ESD
suppression. The RailClamp’s integrated TVS diode
helps to mitigate the effects of parasitic inductance in
the power supply connection. During an ESD event,
72008 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
SRDA3.3-6 and SRDA05-6
Applications Information (continued)
the current will be directed through the integrated TVS
diode to ground. The total clamping voltage seen by
the protected IC due to this path will be:
V
C
= V
F(RailClamp)
+ V
TVS
This is given in the data sheet as the rated clamping
voltage of the device. For an SRDA05-6 the typical
clamping voltage is <16V at I
PP
=30A. The diodes
internal to the RailClamp are low capacitance, fast
switching devices that are rated to handle high tran-
sient currents and maintain excellent forward voltage
characteristics.
Using the RailClamp does not negate the need for good
board layout. All other inductive paths must be consid-
ered. The connection between the positive supply and
the SRDA and from the ground plane to the SRDA
must be kept as short as possible. The path between
the SRDA and the protected line must also be mini-
mized. The protected lines should be routed directly to
the SRDA. Placement of the SRDA on the PC board is
also critical for effective ESD protection. The device
should be placed as close as possible to the input
connector. The reason for this is twofold. First,
inductance resists change in current flow. If a signifi-
cant inductance exists between the connector and the
TVS, the ESD current will be directed elsewhere (lower
resistance path) in the system. Second, the effects of
radiated emissions and transient coupling can cause
upset to other areas of the board even if there is no
direct path to the connector. By placing the TVS close
to the connector it will divert the ESD current immedi-
ately and absorb the ESD energy before it can be
coupled into nearby traces.
(Reference Semtech application note SI99-01 for
further information on board layout)
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
82008 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
SRDA3.3-6 and SRDA05-6
Outline Drawing - SO-8
Land Pattern - SO-8
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3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
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CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
DATUMS AND TO BE DETERMINED AT DATUM PLANE
NOTES:
1.
2. -A- -H-
REFERENCE JEDEC STD MS-012, VARIATION AA.
4.
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MIN MAX MAXNOM
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INCHES
DIMENSIONS
Z
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X
DIM
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MILLIMETERS
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
REFERENCE IPC-SM-782A, RLP NO. 300A.
2.
92008 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
PROTECTION PRODUCTS
SRDA3.3-6 and SRDA05-6
Contact Information
Semtech Corporation
Protection Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
Ordering Information
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Note: Lead-free devices are RoHS/WEEE Compliant