UC1526
UC2526
UC3526
DESCRIPTION
The UC1526 is a high performance monolithic pulse width modulator
circuit designed for fixed-frequency switching regulators and other
power control applications. Included in an 18-pin dual-in-line pack-
age are a temperature compensated voltage reference, sawtooth os-
cillator, error amplifier, pulse width modulator, pulse metering and
setting logic, and two low impedance power drivers. Also included
are protective features such as soft-start and under-voltage lockout,
digital current limiting, double pulse inhibit, a data latch for single
pulse metering, adjustable deadtime, and provision for sym met ry cor-
rection in puts. For ease of interface, all digital control ports are TTL
and B-series CMOS compatible. Active LOW logic design allows
wired-OR connections for maximum flexibility. This versatile device
can b e used to impl ement single-ende d or push-p ull switching regu-
lators of either polarity, both transformerless and transformer cou-
pled. The UC1526 is characterized for operation over the full military
temperature range of -55°C to +125°C. The UC2526 is characterized
for operation from -25°C to +85°C, and the UC3526 is characterized
for operat ion from 0° to +70°C.
Reg ulat ing Pulse Wi dth Mod ulator
FEATURES
•8 To 35V Operation
•5V Reference Trimmed To ±1%
•1Hz To 400kHz Oscillator Range
•Dual 100mA Source/Sink Outputs
•Digital Current Limiting
•Double Pulse Suppression
•Programmable Deadtime
•Under-Voltage Lockout
•Single Pu lse Meteri ng
•Progra mmab le Soft-Start
•Wide Current Limit Common Mode Range
•TTL/CMOS Compatible Logic Ports
•Symme try Co rrection C apab ility
•Gu aranteed 6 Unit Synchronization
BL OCK DIAG RAM
6/93
ABSOL UTE MAXIMUM RATING S (Note 1, 2)
Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V
Co llector Supply Voltag e (+V C) . . . . . . . . . . . . . . . . . . . . . +40V
L ogic Input s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V
An alog Input s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 3V to +VIN
So urc e/S ink Load Current (ea ch out pu t) . . . . . . . . . . . . . 200m A
Re fe ren ce Loa d Curr ent. . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0m A
L ogic Sink Cur ren t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5m A
Po wer Dissipa tion at T A = +25°C (Note 2). . . . . . . . . . 1000mW
Po wer Dissipa tion at T C = +25°C (Not e 2). . . . . . . . . . 3000m W
Op era ting Junct ion Te mp era tu re . . . . . . . . . . . . . . . . . . +150°C
Stor age Tem per ature Range . . . . . . . . . . . . . . -65°C t o +150° C
L ead Te mp era ture (solder ing, 10 sec onds ). . . . . . . . . . +300°C
No te 1 : Value s beyo nd which dama ge may occ ur .
No te 2: Consult packaging section of dat abo ok for therm a l
limita tion s and co nsider ations of pac kage .
CONNECTION DIAGRAMS
UC1526
UC2526
UC3526
DIL -18, SO IC- 18 (T O P VIEW )
J or N Package, DW Packag e
RECOMMENDED OPERATING CONDITIONS (Note 3)
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V to + 35 V
Collector Supply Volt age . . . . . . . . . . . . . . . . . . . +4. 5V to +35V
Sink/Sour ce Lo ad Current (each output ). . . . . . . . . 0 to 100mA
Refer ence Load Cur re nt . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA
Oscillat or Frequ ency Range . . . . . . . . . . . . . . . . 1Hz to 400kHz
Oscillat or Timing Resist or . . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ
Oscillat or Timing Capa cito r . . . . . . . . . . . . . . . . . . . 1nF to 20µF
Available Deadt ime Range at 40kHz. . . . . . . . . . . . . 3% to 50%
Oper at ing Am bient Temper at ur e Range
UC1526 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
UC2526 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
UC3526 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0°C to +70°C
Note 3: Ran ge ove r which the de vice is funct ional and
pa ram et er lim its are guarant eed.
PACKAGE PIN FUNCTION
FUNCTION PIN
N/C 1
+Error 2
-Error 3
Comp. 4
CSS 5
Reset
______ 6
- Current Sense 7
+ Curren t Sense 8
Shutdown
_________ 9
RTIMING 10
CT11
RD12
Sync 13
Out put A 14
VC15
N/C 16
Ground 17
Out put B 18
+VIN 19
VREF 20
PLCC-20, LCC-20
(TOP VIEW )
Q and L Packages
ELECTRICAL CHARACTERISTICS:
PARAMETER TEST CONDITIONS UC1526 / UC2526 UC3526 UNITS
MIN TYP MAX MIN TYP MAX
Refere nce S ec tio n (Note 4)
Out put Voltage TJ = + 25°C 4.9 5 5.0 0 5.0 5 4.9 0 5.0 0 5.1 0 V
Line Reg ulat ion +VIN = 8 to 35V 10 20 10 30 mV
Load Regulat ion I L = 0 to 20mA 10 30 10 50 mV
Tempe ratur e Stability Ove r Operating TJ15 50 15 50 mV
Total O ut put
Voltage R an ge Over Recommen ded
Ope rating C on dition s 4.90 5.00 5.10 4.85 5.00 5.15 V
Short Circuit Current VREF = 0V 25 50 100 25 50 100 mA
Under -Voltage Lockout
RESET
_______ Out put Voltage VREF = 3.8 V 0. 2 0.4 0. 2 0.4 V
VREF = 4. 8 V 2. 4 4. 8 2. 4 4.8 V
Note 4: I
L
= 0m A.
+VIN = 15V, and over oper ating am bient temperature, unles s ot herwise
specified , TA = TJ.
2
ELECTRI CAL CHARACTERI ST ICS :
PARAMETER TEST CONDI TION S UC1526 / UC252 6 UC3526 UNITS
MIN TYP MAX MIN TYP MAX
Oscillator Section (Not e 5)
Initial Accuracy TJ = + 25° C ±3±8±3±8%
Vo ltag e Sta bi lity +VIN = 8 t o 35 V 0. 5 1 0. 5 1 %
Temperature Stabi lity Over Operating TJ710 3 5%
Minimu m Frequency RT = 150kΩΩ, CT = 20µµF11Hz
Max imum Frequency RT = 2 kΩΩ, CT = 1. 0nF 400 400 kHz
Sa wto oth Peak Volt age +V IN = 35 V 3. 0 3.5 3. 0 3.5 V
Sawto oth Valley Voltage +V IN = 8V 0. 5 1.0 0. 5 1.0 V
Error A mplif ier S e ction (Note 6)
Inpu t Offset Voltage RS ≤≤ 2kΩΩ 25 210mV
Input Bias Current -350 -1000 -350 -2000 nA
Input Off set Curren t 3 5 100 3 5 200 n A
DC Ope n Loop Gain RL ≥ 10MΩΩ 64 72 60 72 dB
HIG H O utput Volt age VPIN1-VPIN2 ≥≥ 150m V, ISOURCE =
100µµA3.6 4.2 3.6 4.2 V
LO W Outpu t Voltage V PIN2-VPIN1 ≥≥ 150mV, ISINK = 100µµA 0.2 0.4 0.2 0.4 V
Com mon Mode Rejection Rs ≤ 12kΩ70 94 70 94 dB
Su pply Volt age Rejec tion +VIN = 12 to 18V 66 80 66 80 dB
PWM Comparato r (Note 5)
Minimum Duty Cycle VCOMPENSATION = +0.4V 0 0 %
Max imum Dut y Cycle V COMPENSATION = +3.6V 45 49 45 49 %
Digital Ports (SYNC, SHUTDO WN, and RESET)
HIG H Out put Volt age ISOURCE =40µµA 2.4 4.0 2.4 4.0 V
LO W Outpu t Voltage ISINK = 3. 6m A 0. 2 0.4 0. 2 0.4 V
HIG H I nput Curren t VIH = +2.4V -125 -200 -125 -200 µA
LO W Inpu t Current VIL = +0.4V -225 -360 -225 -360 µA
Cur rent LI mit Comparator (Not e 7)
Se nse Volt age R S ≤≤ 50 ΩΩ 90 100 110 80 100 120 mV
Input Bias Current -3 -10 -3 -10 µA
So ft -St art Section
Erro r Clamp Voltage RESET = +0.4V 0.1 0.4 0.1 0.4 V
Cs Charging Current RESET =+2.4 V 50 100 150 50 100 150 µA
Ou tpu t Drive rs ( Each Out put ) ( Note 8)
HIG H Out put Volt age ISOURCE = 20mA 12.5 13.5 12.5 13.5 V
ISOURCE = 100m A 1 2 13 12 1 3 V
LO W Outpu t Voltage ISINK = 20mA 0.2 0.3 0.2 0.3 V
ISINK = 100m A 1.2 2.0 1.2 2. 0 V
Co llector Leakage V C = 40V 50 150 50 150 µA
Rise Time CL = 1000pF 0.3 0 .6 0.3 0.6 µs
Fall Time CL = 1000pF 0.1 0.2 0.1 0.2 µs
Power Consumption (Note 9)
Stan dby Cur re nt SHUTDO W N
____________ = +0.4V 18 30 18 30 mA
+VIN = 15V, and ove r operating am bien t temper at ur e, unless othe rwise
specified, T A = TJ.
UC1526
UC2526
UC3526
Note 4: I
L
= 0mA.
Note 5: F
OSC
= 40kHz (R
T
= 4.12k
Ω ±
1% , C
T
= 0.1
µ
F
±
1% ,
R
D
= 0
Ω
)
Note 6: V
CM
= 0 to +5.2V
Note 8: V
C
= +1 5 V
Note 9: +V
IN
= +35V, R
T
= 4.12k
Ω
3
UC1526
UC2526
UC3526
APPLICATIONS INFORMATION
Volt age Referen ce
The reference regulator of the UC1526 is based on a tem-
perature compensated zener diode. The circuitry is fully
active at supply voltag es above +8V, and provides up to
20mA of load current to extern al circuitry at +5.0V. In sys-
tems where additional current is required, an external
PNP transistor can be used to boost the available current.
A rugged low frequency audio-type transistor should be
used, and lead lengths between the PWM and transistor
shoul d be as sho rt as possible to minimize the risk of os-
cillations. Even so, some types of transistors may require
collector-base capacitance for stability. Up to 1 amp of
load current can be obtained with excellent regulation if
the device selected m aintains high current g ain.
Under-Voltage Lockou t
The under-voltage lockout circuit protects the UC1526
and th e power d evices it controls from inadequate supply
voltage, If +VIN is too low, the circui t disables the output
drivers and holds the RESET
_______ pin LOW. This prevents
spuri ous output pulses whil e the control circuitry i s stabi-
lizing, and holds the soft-start timing capacitor in a dis-
charged state.
The circuit consists of a +1.2V bandgap reference and
comparator circuit which is active when the reference
voltage has risen to 3V BE or +1.8V at 25°C. When the ref-
erence voltage rises to approximately +4.4V, the circuit
enables the output drivers and releases the RESET
_______ pin,
allowing a normal soft-start. The comparator has 200mV
of hysteresis to minimize oscillation at the trip point.
When +VIN to the PWM is removed and the reference
drops to +4.2V, the under-voltage circuit pulls RESET
_______
LOW again. The soft-start capacitor is immediately dis-
charged , a nd the PWM is ready for another soft-start cy-
cle.
The U C1526 can operate from a +5V supply by connect -
ing the VREF pin to the +VIN p in and maintaining the sup-
ply between +4.8 and +5.2V.
Soft-St art Circuit
The soft-start circuit protects the power transistors and
rectifier diodes from high current surges during power
supply turn-on. When supply voltage is first applied to the
UC1526, the under-voltage lockout circuit holds RESET
_______
LOW with Q3. Q1 is turned o n, which holds the soft-start
capacitor voltage at zero. The second collector of Q1
clamps the output of the error amplifier to ground, guaran-
teeing zero duty cycle at the driver outputs. When the
supply voltage reaches normal operating range, RESET
_______
will go HIGH. Q1 turns off, allowing the internal 100mA
current source to charge CS. Q2 clamps the error ampli-
fi er ou tput to 1 VBE above the voltage on CS. As the soft-
start vo ltage ramps up to +5V, the duty cycle of the PWM
linearly increases to whatever value the voltage regula-
tion loop requires for an error null.
Digital Control P orts
The three digital control ports of the UC1526 are bi-direc-
tional. Each pin can drive TTL and 5V CMOS logic di-
rectly, up to a fan-out of 10 low-power Schottky gates.
Each pin can also be directly driven by open-collector
Figure 2. Under -Voltag e Lockout Schem at ic
Figure 1. Extending Re fe ren ce O ut put Current
Figure 3. Soft - Start C ircuit Schematic
4
TTL, open-drai n C MOS, and open -collector voltage com-
parators; fan-in is equivalent to 1 low-power Schottky
gate. Each port is normally HIGH; the pin is pulled LOW
to activate the particular funct ion. Driving SYNC
______ LOW in-
itiates a discharge cycle in the oscillator. Pulling
SHUTDOWN
____________ LOW immediately inhibits all PWM output
pulses. Holding RESET
_______ LOW discharges the soft-start
capacitor. The logic threshold is +1.1V at +25°C. Noise
immunity can be gained at the expense of fan-out with an
external 2k pull-up resist or to +5V.
Oscillator
Th e oscillator is programmed for frequency and dead time
with three compon ents: RT, CT a nd RD. Two waveforms
are gene rated: a sawtooth waveform a t pi n 10 for pulse
width modulati on, and a logic clock at pin 12. The follow-
ing procedure is recommended for choosing timing val-
ues:
1. With RD = 0 (pin 11 shorted to ground) select values
for RT and CT from Figure 7 to give the desired oscillator
peri od. Remember that th e frequency at each drive r out-
put is half the oscillator frequency, and the frequency at
the +VC terminal is the same as the oscillator frequenc y.
2. If more dead ti me is required, select a large value of
RD. At 40kHz dead time increases by 400ns /Ω .
3. Increasing the dead time will cause the oscillator fre-
quency to decrease slightly. Go back and decrease the
value of RT slightly to bring the frequency back to the
nominal design value.
The UC1526 can be synchronized to an external logic
clock by programming the oscillator to free-run at a fre-
quency 10% slower than the sync frequency. A periodic
LOW logic pulse approximately 0.5µs wide at the SYNC
______
pin wi ll then lock the osci llator to the external frequency.
Multiple devices can be synchronized together by pro-
gramming one master uni t for the desi red frequency a nd
then sharing its sawtooth and clock waveforms with the
slave units. All CT te rmi nal s are connected to the CT pi n
of the master, and all SYNC
______ terminals a re likewise con-
nected to the SYNC
______ pin of the master. Slave RT termi-
nals are left open or connected to VREF. Slave RD
term inals may be either left open or grounded.
Erro r Amplifier
The erro r ampl ifi er i s a transconductance design, with an
output impedance of 2MΩ . Since al l voltage gai n takes
place at the output pin, the open-loop gain/frequency
characteristics can be controlled with shunt reactance to
ground. When compensated for unity-gain stability with
100pF, the am plifier has an open-loop pole at 800Hz.
The input connections to the error amplifier are deter-
mined by the polarity of the switchi ng supply output volt-
age. For positive supplies, the common-mode voltage is
+5.0V and the feedback connections in Figure 6A are
used. With negative supplies, the common-mode voltage
is gro und and the fee dback d ivider is connected between
the negative output and the +5.0V reference voltage, as
shown in Figure 6B.
Output Drivers
The totem-pole output drivers of the UC1526 are de-
signed to source and sink 100mA continuously and
200mA peak . Loads can be driven either from the output
pins 13 and 16, or from the +VC, as required.
Since the bottom transistor of the totem-pole is allowed to
saturate, the re is a momentary condu cti on path from the
+VC terminal to ground during switching. To limit the re-
sulting current spikes a small resistor in series with pin 14
is always recommended. The resistor value is deter-
mined by the driver supply voltage, and should be chosen
for 200mA peak currents .
UC1526
UC2526
UC3526
Figure 5. Osc illat or Connec tion s and Wa vefor ms
Figure 4. Digital Cont ro l Port Schem at ic
APPLICATIONS INFORMATION (cont.)
5
UC1526
UC2526
UC3526
Figure 6. Error Amp lifier Conne ctio ns
Figure 7. Push-Pull Configu ration
Fig ure 8. S ingle-En ded Con figu rat ion
Figure 9. Driving N- chan nel Power Mosfe ts
Oscil lati o n Period
T YPICAL CHARACTE RIS TICS Oscillator Period vs RT and CT
6
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
UC1526
UC2526
UC3526
T YPICAL CHARACTE RIS TICS
Shu tdo wn Delay Out put Driver Satu ration Voltage
Ou tput Driver Deadtime vs R D V al u e Un der Voltag e Lockou t Characteristic
Error Ampli fier Open Loop Gai n vs Freq uen cy Curren t Limit Transfer Fun ctio n
7
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UC3526DWTR SOIC DW 18 2000 330.0 24.4 10.9 12.0 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC3526DWTR SOIC DW 18 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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