LM53635MQRNLTQ1 - TEXAS INSTRUMENTS

September, 2016 − Rev. 1 1Publication Order Number:

NCN5121/D

NCN5121

Transceiver for KNX

Twisted Pair Networks

Introduction

NCN5121 is a receiver−transmitter IC suitable for use in KNX

twisted pair networks (KNX TP1−256). It supports the connection of

actuators, sensors, microcontrollers, switches or other applications in

a building network.

NCN5121 handles the transmission and reception of data on the bus.

It generates from the unregulated bus voltage stabilized voltages for its

own power needs as well as to power external devices, for example, a

microcontroller.

NCN5121 assures safe coupling to and decoupling from the bus.

Bus monitoring warns the external microcontroller in case of loss of

power so that critical data can be stored in time.

Key Features

•9600 baud KNX Communication Speed

•Supervision of KNX Bus Voltage and Current

•Supports Bus Current Consumption up to 24 mA

•High Efficient DC−DC Converters

♦3.3 V Fixed

♦1.2 V to 21 V Selectable

•Control and Monitoring of Power Regulators

•Linear 20 V Regulator

•Buffering of Sent Data Frames (Extended Frames Supported)

•Selectable UART or SPI Interface to Host Controller

•Selectable UART and SPI baud Rate to Host Controller

•Optional CRC on UART to the Host

•Optional Received Frame−end with MARKER Service

•Optional Direct Analog Signaling to Host

•Operates with Industry Standard Low Cost 16 MHz Quartz

•Generates Clock of 8 or 16 MHz for External Devices

•Auto Acknowledge (optional)

•Auto Polling (optional)

•Temperature Monitoring

•Extended Operating Temperature Range −40°C to +105°C

•These Devices are Pb−Free and are RoHS Compliant

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QFN40

MN SUFFIX

CASE 485AU

See detailed ordering and shipping information in the package

dimensions section on page 57 of this data sheet.

ORDERING INFORMATION

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

MARKING DIAGRAM

401

NCN5121

21420−005

AWLYYWWG

NCN5121

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BLOCK DIAGRAM

Figure 1. Block Diagram NCN5121

POR

TSD UVD

DC/DC

Converter 1

DC/DC

Converter 2

NCN5121

CAV

VBUS1

CCP

TXO

FANIN

VBUS2

V20V

XTAL1

XTAL2

XSEL

XCLK

SAVEB RESETBANAOUT

VSS2

VDD2

VDD2MV

VDD2MC

VSW2

VSS1

VDD1

VDD1M

VSW1

VIN

MODE2

MODE1

TREQ

CSB/UC1

SDO/TXD

SDI/RXD

SCK/UC2

VSSDVDDDVDDA VSSAVFILTCEQ2

CEQ1

20V LDO

Fan−In

Control

Bus Coupler

Impedance

Control

Transmitter

OSC

Receiver

UART

SPI

KNX

DLL

Interface

Controller

Mode

OSC

Diagnostics

XCLKC

TRIG

ANALOG

BUFFER

PIN OUT

VSSA

VBUS2

TXO

CCP

CAV

VBUS1

CEQ1

CEQ2

VFILT

VDD2MV

VDD2MC

VDD2

VSS2

VSW2

VSW1

VSS1

VDD1

VDD1M

XCLKC

TRIG

MODE1

MODE2

TREQ

CSB/UC1

SDI/RXD

SDO/TXD

SCK/UC2

VDDD

VSSD

XCLK

XSEL

XTAL2

XTAL1

SAVEB

RESETB

FANIN

ANAOUT

VDDA

NCN5121

V20V

Figure 2. Pin Out NCN5121 (Top View)

VIN

NCN5121

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PIN DESCRIPTION

Table 1. PIN LIST AND DESCRIPTION

Name Pin Description Type Equivalent

Schematic

VSSA 1 Analog Supply Voltage Ground Supply

VBUS2 2 Ground for KNX Transmitter Supply

TX0 3 KNX Transmitter Output Analog Output Type 1

CCP 4 AC coupling external capacitor connection Analog I/O Type 2

CAV 5 Capacitor connection to average bus DC voltage Analog I/O Type 3

VBUS1 6 KNX power supply input Supply Type 5

CEQ1 7 Capacitor connection 1 for defining equalization pulse Analog I/O Type 4

CEQ2 8 Capacitor connection 2 for defining equalization pulse Analog I/O Type 4

VFILT 9 Filtered bus voltage Supply Type 5

V20V 10 20V supply output Supply Type 5

VDD2MV 11 Voltage monitor of Voltage Regulator 2 Analog Input Type 8

VDD2MC 12 Current monitor input 1 of Voltage Regulator 2 Analog Input Type 9

VDD2 13 Current monitor input 2 of Voltage Regulator 2 Analog Input Type 8

VSS2 14 Voltage Regulator 2 Ground Supply

VSW2 15 Switch output of Voltage Regulator 2 Analog Output Type 6

VIN 16 Voltage Regulator 1 and 2 Power Supply Input Supply Type 5

VSW1 17 Switch output of Voltage Regulator 1 Analog Output Type 6

VSS1 18 Voltage Regulator 1 Ground Supply

VDD1 19 Current Input 2 and Voltage Monitor Input of Voltage Regulator 1 Analog Input Type 8

VDD1M 20 Current Monitor Input 1 of Voltage Monitor 1 Analog Input Type 9

XCLKC 21 Clock Frequency Configure Digital Input Type 12

TRIG 22 Transmission Trigger Output Digital Output Type 13

MODE1 23 Mode Selection Input 1 Digital Input Type 12

MODE2 24 Mode Selection Input 2 Digital Input Type 12

TREQ 25 Transmit Request Input Digital Input Type 12

CSB/UC1 26 Chip Select Output (SPI) or Configuration Input (UART)

or 20 V LDO Disable (Analog Mode) Digital Output or

Digital Input Type 13 or 14

SDI/RXD 27 Serial Data Input (SPI) or Receive Input (UART) Digital Input Type 14

SDO/TXD 28 Serial Data Output (SPI) or Transmit Output (UART) Digital Output Type 13

SCK/UC2 29 Serial Clock Output (SPI) or Configuration Input (UART)

or Voltage Regulator 2 Disable (Analog Mode) Digital Output or

Digital Input Type 13 or 14

VDDD 30 Digital Supply Voltage Input Supply Type 7

VSSD 31 Digital Supply Voltage Ground Supply

XCLK 32 Oscillator Clock Output Digital Output Type 13

XSEL 33 Clock Selection (Quartz or Digital Clock) Digital Input Type 12

XTAL2 34 Clock Generator Output (Quartz) or Input (Digital Clock) Analog Output or

Digital Input Type 10 or 14

XTAL1 35 Clock Generator Input (Quartz) Analog Input Type 10

SAVEB 36 Save Signal (open drain with pull−up) Digital Output Type 15

RESETB 37 Reset Signal (open drain with pull−up) Digital Output Type 15

FANIN 38 Fan−In Input Digital Input Type 11

ANAOUT 39 Analog Signal Output Analog Output Type 16

VDDA 40 Analog Supply Voltage Input Supply Type 7

NOTE: Type of CSB/UC1 and SCK/UC2 is depending on status MODE1 − MODE2 pin

Type of XTAL1 and XTAL2 pin is depending on status XSEL pin.

NCN5121

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EQUIVALENT SCHEMATICS

Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified

representations of the circuits used.

TXO

60V

CCP

60V

CAV

CEQx

60V

Type 1: TXO−pin Type 2: CCP−pin Type 3: CAV−pin Type 4: CEQ1 and CEQ2−pin

VBUS1

60V

VBUS1

VFILT

60V

VFILT

V20V

60V

V20V

VIN

60V

VIN

VSWx

VIN

60V

Type 5: VBUS1−, VFILT−, V20V and VIN−pin Type 6: VSW1 and VSW2−pin

VDDA

VDDD

VDD2MV

VDD2

60V

VDD1

Type 7: VDDD− and VDDA−pin

Type 8: VDD1−, VDD2− and VDD2MV−pin

VDD1M

VDD1

VDD2MC

VDD2

60V

XTAL2

VDDD

XTAL1

VDDD

Type 9: VDD1M− and VDD2MC−pin

Type 10: XTAL1− and XTAL2−pin

VDDD

RDOWN

OUT

VDDD

OUT

VDDD

RUP

Type 12: MODE1−, MODE2−,

TREQ−, XCLKC− and XSEL−pin

Type 13: CSB/UC1−,

SDO/TXD−, SCK/UC2−,

TRIG− and XCLK−pin

Type 14: CSB/UC1−,

SDI/RXD−, SCK/UC2

and XTAL2−pin

Type 15: RESETB− and

SAVEB−pin

Type 11: FANIN−pin

ANAOUT

VDDA

Type 16: ANAOUT

FANIN

VAUX

NOTE: Type of CSB/UC1 and SCK/UC2 is depending on status MODE1 − MODE2 pin

Type of XTAL1 and XTAL2 pin is depending on status XSEL pin.

Figure 3. In− and Output Equivalent Diagrams

NCN5121

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ELECTRICAL SPECIFICATION

Table 2. ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2)

Symbol Parameter Min Max Unit

VTXO KNX T ransmitter Output Voltage −0.3 +45 V

ITXO KNX T ransmitter Output Current (Note 3) 250 mA

VCCP Voltage on CCP−pin −10.5 +14.5 V

VCAV Voltage on CAV−pin −0.3 +3.6 V

VBUS1 Voltage on VBUS1−pin −0.3 +45 V

VANAOUT Voltage on ANAOUT pin −0.3 +3.6 V

IBUS1 Current Consumption VBUS1−pin 0 120 mA

VCEQ Voltage on pins CEQ1 and CEQ2 −0.3 +45 V

VFILT Voltage on VFILT−pin −0.3 +45 V

V20V Voltage on V20V−pin −0.3 +25 V

VDD2MV Voltage on VDD2MV−pin −0.3 +3.6 V

VDD2MC Voltage on VDD2MC−pin −0.3 +45 V

VDD2 Voltage on VDD2−pin −0.3 +45 V

VSW Voltage on VSW1− and VSW2−pin −0.3 +45 V

VIN Voltage on VIN−pin −0.3 +45 V

VDD1 Voltage on VDD1−pin −0.3 +3.6 V

VDD1M Voltage on VDD1M−pin −0.3 +3.6 V

VDIG Voltage on pins MODE1, MODE2, TREQ, CSB/UC1, SDI/TXD, SDO/RXD, SCK/

UC2, XCLK, XSEL, SAVEB, RESETB, XCLKC, TRIG, and FANIN −0.3 +3.6 V

VDD Voltage on VDDD− and VDDA−pin −0.3 +3.6 V

VXTAL Voltage on XTAL1− and XTAL2−pin −0.3 +3.6 V

TST Storage temperature −55 +150 °C

TJJunction Temperature (Note 4) −40 +155 °C

VHBM Human Body Model electronic discharge immunity (Note 5) −2 +2 kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. Convention: currents flowing in the circuit are defined as positive.

2. VBUS2, VSS1, VSS2, VSSA and VSSD form the common ground. They are hard connected to the PCB ground layer.

3. Room temperature, 27 W shunt resistor for transmitter, 250 mA over temperature range.

4. Normal performance within the limitations is guaranteed up to the Thermal Warning level. Between Thermal Warning and Thermal Shutdown

temporary loss of function or degradation of performance (which ceases after the disturbance ceases) is possible.

5. According to JEDEC JESD22−A114.

NCN5121

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Recommend Operation Conditions

Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the

functionality of the chip outside these operating ranges is not guaranteed. Operating outside the recommended operating ranges

for extended periods of time may affect device reliability.

Table 3. OPERATING RANGES

Symbol Parameter Min Max Unit

VBUS1 VBUS1 Voltage (Note 6) +20 +33 V

VDD Digital and Analog Supply Voltage (VDDD− and VDDA−pin) +3.13 +3.47 V

VIN Input Voltage DC−DC Converter 1 and 2 (Note 7) +33 V

VCCP Input Voltage at CCP−pin −10.5 +14.5 V

VCAV Input Voltage at CAV−pin 0 +3.3 V

VDD1 Input Voltage on VDD1−pin +3.13 +3.47 V

VDD1M Input Voltage on VDD1M−pin +3.13 +3.57 V

VDD2 Input Voltage on VDD2−pin +1.2 +21 V

VDD2MC Input Voltage on VDD2MC−pin +1.2 +21.1 V

VDD2MV Input Voltage on VDD2MV−pin +1.2 VDD V

VDIG Input Voltage on pins MODE1, MODE2, TREQ, CSB/UC1, SDI/RXD, SCK/UC2,

XCLKC, and XSEL 0 VDD V

VFANIN Input Voltage on FANIN−pin 0 3.6 V

fclk Clock Frequency External Quartz 16 MHz

TAAmbient Temperature −40 +105 °C

TJJunction Temperature (Note 8) −40 +125 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

6. Voltage indicates DC value. With equalization pulse bus voltage must be between 11 V and 45 V.

7. Minimum operating voltage on VIN−pin should be at least 1 V larger than the highest value of VDD1 and VDD2.

8. Higher junction temperature can result in reduced lifetime.

NCN5121

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Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions

unless otherwise specified. Convention: currents flowing in the circuit are defined as positive.

Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit

POWER SUPPLY

VBUS1

Bus DC voltage Excluding active and

equalization pulse 20 33 V

IBUS1_Int Bus Current Consumption VBUS = 30 V, IBUS = 10 mA,

DC2, V20V disabled, no crystal

or clock 2.00 2.70 mA

Bus Current Consumption VBUS = 20 V, IBUS = 20 mA 3.20 4.10

VBUSH Undervoltage release level VBUS1 rising, see Figure 4 17.1 18.0 18.9 V

VBUSL Undervoltage trigger level VBUS1 falling, see Figure 4 15.9 16.8 17.7 V

VBUS_Hyst Undervoltage hysteresis 0.6 V

VDDD VDDD Digital Power Supply 3.13 3.3 3.47 V

VDDA VDDA Analog Power Supply 3.13 3.3 3.47 V

VAUX Auxiliary Supply Internal supply, for info only 2.8 3.3 3.6 V

KNX BUS COUPLER

DIcoupler/D

VBUS1 Bus Coupler Current Slope

Limitation FANIN floating, VFILT > VFILTH 0.40 0.50 A/s

FANIN = 0, VFILT > VFILTH 0.80 1.00 A/s

Icoupler_lim,

startup VBUS1 Bus Coupler Startup Current

Limitation FANIN floating, VFILT > VFILTH 20.0 25.0 30.0 mA

FANIN = 0, VFILT > VFILTH 40.0 50.0 60.0 mA

Icoupler_lim VBUS1 Bus Coupler Current Limitation FANIN floating, VFILT > VFILTH 10.6 11.4 12.0 mA

FANIN = 0, VFILT > VFILTH 20.5 22.3 24.0 mA

Vcoupler_drop VBUS1,

VFILT Coupler Voltage Drop

(Vcoupler_drop = VBUS1 − VFILT)IBUS1 = 10 mA 1.72 2.32 V

IBUS1 = 20 mA 2.34 2.80 V

VFILTH VFILT Undervoltage release level VFILT rising, see Figure 5 10.1 10.6 11.2 V

VFILTL Undervoltage trigger level VFILT falling, see Figure 5 8.4 8.9 9.4 V

FIXED DC−DC CONVERTER

VIN VIN Input Voltage 4.47 33 V

VDD1 VDD1 Output Voltage 3.13 3.3 3.47 V

VDD1_rip Output Voltage Ripple VIN = 25 V, IDD1 = 40 mA,

L1 = 220 mH40 mV

IDD1_lim Overcurrent Threshold R2 = 1 W, see Figure 13 −100 −200 mA

hVDD1 Power Efficiency

(DC Converter Only) Vin = 25 V, IDD1 = 35 mA,

L1 = 220 mH (1.26 W ESR),

see Figure 12 90 %

RDS(on)_p1 RDS(on) of power switch See Figure 18 9W

RDS(on)_n1 RDS(on) of flyback switch See Figure 18 4W

VDD1M VDD1M Input voltage VDD1M−pin 3.57 V

NCN5121

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Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions

unless otherwise specified. Convention: currents flowing in the circuit are defined as positive.

Symbol UnitMaxTypMinRemark/Test ConditionsParameterPin(s)

ADJUSTABLE DC−DC CONVERTER

VIN VIN Input Voltage VDD2

+ 1 33 V

VDD2

Output Voltage VIN ≥ VDD2 1.2 21 V

VDD2H Undervoltage release level VDD2 rising, see Figure 6 0.9 x

VDD2 V

VDD2L Undervoltage trigger level VDD2 falling, see Figure 6 0.8 x

VDD2 V

VDD2_rip Output Voltage Ripple VIN = 25 V, VDD2 = 3.3 V,

IDD2 = 40 mA, L2 = 220 mH40 mV

IDD2_lim Overcurrent Threshold R3 = 1 W, see Figure 13 −100 −250 mA

hVDD2 Power Efficiency

(DC Converter Only) Vin = 25 V, VDD2 = 3.3 V,

IDD2 = 35 mA, L2 = 220 mH

(1.26 W ESR), see Figure 13 90 %

RDS(on)_p2 RDS(on) of power switch See Figure 18 8W

RDS(on)_n2 RDS(on) of flyback switch See Figure 18 4W

VDD2M VDD2MC Input voltage VDD2MC−pin 21.1 V

RVDD2M VDD2MV Input Resistance VDD2MV−pin 1MW

Ileak,vsw2 Half−bridge leakage 20 mA

V20V REGULATOR

V20V

V20V Output Voltage I20V < I20V_lim, VFILT ≥ 21 V 18 20 22 V

DI20V, STEP V20V Output Current

Limitation Step FANIN floating 1.25 mA

FANIN = 0 2.50 mA

I20V_lim V20V Output Current Limitation

(for V20VCLIMIT[2:0] = 100) FANIN floating 6 7.5 9 mA

FANIN = 0 12 15 18 mA

V20VH V20V Undervoltage release

level V20V rising, see Figure 7 14.2 15.0 15.8 V

V20VL V20V Undervoltage trigger

level V20V falling, see Figure 7 13.2 14.0 14.8 V

V20V_hyst V20V Undervoltage hysteresis V20V_hyst = V20VH – V20VL 1.0 V

XTAL OSCILLATOR

VXTAL XTAL1, XTAL2 Voltage on XTAL−pin VDDD V

FAN−IN CONTROL

Ipu,fanin FANIN Pull−Up Current FANIN−pin FANIN shorted to GND,

Pull−up connected to VAUX 10 20 40 mA

NCN5121

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Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions

unless otherwise specified. Convention: currents flowing in the circuit are defined as positive.

Symbol UnitMaxTypMinRemark/Test ConditionsParameterPin(s)

DIGITAL INPUTS

VIL SCK/UC2,

SDI/RXD,

CSB/UC1,

TREQ,

MODE1,

MODE2,

XSEL, XCLKC

XTAL2

Logic Low Threshold 0 0.7 V

VIH Logic High Threshold 2.65 VDDD V

RDOWN Internal Pull−Down Resistor SCK/UC2−, SDI/RXD− and

CSB/UC1 pin excluded. Only

valid in Normal State. 5 10 28 kW

DIGITAL OUTPUTS

VOL SCK/UC2,

SDO/TXD,

CSB/UC1,

XCLK, TRIG

Logic low output level 0 0.4 V

VOH Logic high output level VDDD −

0.45 VDDD V

SCK/UC2,

XCLK, TRIG Load Current 8 mA

SDO/TXD,

CSB/UC1 4 mA

VOL SAVEB,

RESETB Logic low level open drain IOL = 4 mA 0.4 V

Rup Internal Pull−up Resistor 20 40 80 kW

ANALOG OUTPUT

PVBUS

ANAOUT

Analog output division ratio for VBUS 0.067 0.071 0.075

PVFILT Analog output division ratio for VFILT 0.071 0.075 0.079

PV20V Analog output division ratio for V20V 0.086 0.091 0.096

PVDDA Analog output division ratio for VDDA 0.438 0.462 0.485

PVDD2 Analog output division ratio for VDD2MV 0.950 1.000 1.050

PIBUS Analog output conversion ratio for IBUS 14.0 20.9 28.8 V/A

PTJAnalog output conversion ratio for Tjunction −4 mV/K

VTJOFF Analog output offset for Tjunction at 300K 1.309 V

VOFF Analog output offset voltage −12 12 mV

tSW,ANA Time between writing Analog Control Register 1 and stable

ANAOUT voltage (<1 nF capacitive load) 33 ms

TEMPERATURE MONITOR

TTW Thermal Warning Rising temperature

See Figure 8 105 115 125 °C

TTSD Thermal shutdown Rising temperature

See Figure 8 130 140 150 °C

THyst Thermal Hysteresis See Figure 8 511 15 °C

DTDelta TTSD and TTW See Figure 8 21.7 °C

PACKAGE THERMAL RESISTANCE VALUE

Rq,ja Thermal Resistance

Junction−to−Ambient

Simulated Conform

JEDEC JESD−51, (2S2P) 30 K/W

Simulated Conform

JEDEC JESD−51, (1S0P) 60 K/W

Rq,jp Thermal Resistance

Junction−to−Exposed Pad 0.95 K/W

NCN5121

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Table 5. AC PARAMETERS The AC parameters are given for a device operating within the Recommended Operating Conditions

unless otherwise specified.

Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit

POWER SUPPLY

tBUS_FILTER VBUS1 VBUS1 filter time See Figure 4 2 ms

FIXED DC−DC CONVERTER

tVSW1_rise VSW1 Rising slope at VSW1−pin 0.45 V/ns

tVSW1_fall Falling slope at VSW1−pin 0.6 V/ns

ADJUSTABLE DC−DC CONVERTER

tVSW2_rise VSW2 Rising slope at VSW2−pin 0.45 V/ns

tVSW2_fall Falling slope at VSW2−pin 0.6 V/ns

XTAL OSCILLATOR

fXTAL XTAL1, XTAL2 XTAL Oscillator Frequency 16 MHz

WATCHDOG

tWDPR

Prohibited Watchdog

Acknowledge Delay See Watchdog, p22 2 33 ms

tWDTO Watchdog Timeout Interval Selectable over UART or SPI 33 524 ms

tWDTO_acc Watchdog Timeout Interval

Accuracy =Xtal accuracy

tWDRD Watchdog Reset Delay 0 ns

tRESET Reset Duration 8 ms

MASTER SERIAL PERIPHERAL INTERFACE (MASTER SPI)

tsck

SCK

SPI Clock period SPI Baudrate depending on

configuration input bits (see

Interface Mode, p26). Toleranc

is equal to Xtal oscillator

tolerance.

See also Table 7.

FANIN−pin

The FANIN−pin defines the maximum allowed bus

current and bus current slopes. If the FANIN−pin is kept

floating, pulled up to VDD, or pulled down with a resistance

higher than 250 kW, NCN5121 will limit the KNX bus

current slopes to 0.5 mA/ms at all times. NCN5121 will also

limit the KNX bus current to 30 mA during start−up. During

normal operation, NCN5121 is capable of taking 12 mA (=

Icoupler) from the KNX bus for supplying external loads

(DC1, DC2 and V20V).

If the FANIN−pin is pulled to ground with a resistance

smaller than 2 kW the operation is similar as above with the

exception that the KNX bus current slopes will be limited to

1 mA/ms at all times, the KNX bus current will be limited

to 60 mA during start−up and up to 24 mA (Icoupler) can be

taken from the KNX bus during normal operation.

Definitions for Start−Up and Normal Operation (as given

above) can be found in the KNX Specification.

Transmit Trigger

When bit 3 of analog control register 0 is set, the

TRIG−pin will output a signal that goes high 1 bit time

before the start of a scheduled transmission, and goes low

when the transmission is complete or a collision is detected.

This can be used during development as verification of

transmission. Note that a scheduled transmission is a frame

that is sent less than tBUS,IDLE (TODO s) after previous

communication on the bus. When a frame is transmitted on

a bus which has been idle for a longer time, or an

ACK/NACK/BUSY response is sent, the transmission will

start immediately after the trigger goes high, and the time

between trigger high and frame transmission start will not be

consistent.

RESETB− and SAVEB−pin

The RESETB signal can be used to keep the host

controller in a reset state. When RESETB is low this

indicates that the bus voltage is too low for normal operation

and that the fixed DC−DC converter has not started up. It

could also indicate a Thermal Shutdown (TSD). The

RESETB signal also indicates if communication between

host and NCN5121 is possible.

The SAVEB signal indicates correct operation. When

SAVEB goes low, this indicates a possible issue (loss of bus

power or too high temperature) which could trigger the host

controller to save critical data or go to a save state. SAVEB

goes low immediately when VFILT goes below 14 V (due

to sudden large current usage) or after 2 ms when VBUS

goes below 20 V. RESETB goes low when VFILT goes

below 12 V.

RESETB− and SAVEB−pin are open−drain pins with an

internal pull−up resistor to VDDD.

Voltage Supervisors

NCN5121 has different voltage supervisors monitoring

VBUS, VFILT, VDD2 and V20V. The general function of a

voltage supervisor is to detect when a voltage is above or

below a certain level. The levels for the different voltages

monitored can be found back in Table 4 (see also Figures 4,

5, 6 and 7).

The status of the voltage supervisors can be monitored by

the host controller (see System Status Service, p37).

Depending on the voltage supervisor outputs, the device

can enter different states (see Analog State Diagram, p23).

3. The 4 MHz clock signal is internally generated and will be less accurate as the crystal generated clock signal of 8 or 16 MHz.

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Figure 18. Fixed (VDD1) and Adjustable (VDD2) DC−DC Converter

VSW1

VIN

VSS1

VDD1M

VDD1

VSW2

VSS2

VDD2MV

VDD2MC

VDD2

COMP

Switch

Controller

COMP

Switch

Controller

From VFILT

1Ω

10μF

VDD1 = 3.3V

0.47Ω

10μFVDD2 = 3.3V – 20V

NCN5121 R5

0.47Ω

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Table 7. STATUS OF SEVERAL BLOCKS DURING THE DIFFERENT (ANALOG) STATES

State Osc XCLK VDD1 VDD2/V20V SPI/UART KNX

Reset Off Off Off Off Inactive Inactive

Start−Up Off Off Start−up Off Inactive Inactive

Stand−By (Note 17) Off 4 MHz On Start−Up Active Inactive

(Note 22)

Stand−By (Note 18) On

(Note 20) On

(Note 20) On On (Note 21) Active Inactive

(Note 22)

Normal On On

(Note 19) On On Active Active

17.Only valid when entering Stand−By from Start−Up State.

18.Only valid when entering Stand−By from Normal State.

19.8 MHz or 16 MHz depending on XCLKC.

20.4 MHz signal if Stand−By state was entered due to oscillator issue. Otherwise 8 MHz or 16 MHz clock signal.

21.Only operational if Stand−By state was not entered due to VDD2 or V20V issue.

22.Under certain conditions KNX bus is (partly) active. See Digital State Diagram for more details.

Temperature Monitor

The device produces an over−temperature warning (TW)

and a thermal shutdown warning (TSD). Whenever the

junction temperature rises above the Thermal Warning level

(TTW), the SAVEB−pin will go low to signal the issue to the

host controller. Because the SAVEB−pin will not only go

low on a Thermal Warning (TW), the host controller needs

to verify the issue by requesting the status (<TW>, see

System Status Service, p37). When the junction temperature

is above TW, the host controller should undertake actions to

reduce the junction temperature and/or store critical data.

When the junction temperature reaches Thermal

Shutdown (T TSD), the device will go to the Reset State. The

Thermal Shutdown will be stored (<TSD>, see Analog

Status Register, p56) and the analog and digital power

supply will be stopped (to protect the device). The device

will stay in the Reset State as long as the temperature stays

above TTSD.

If the temperature drops below TTSD, Start−Up State will

be entered (see also Figure 19). At the moment VDD1 is

back up and the OTP memory is read, Stand−By State will

be entered and RESETB will go high. The Xtal oscillator

will be started. Once the temperature has dropped below

TTW and all voltages are high enough, Normal State will be

entered. SAVEB will go high and KNX communication is

again possible.

The TW−bit will be reset at the moment the junction

temperature drops below TTW. The TSD−bit will only be

reset when the junction temperature is below TTSD and the

<TSD> bit is read (see Analog Status Register, p56).

Figure 8 gives a better view on the temperature monitor.

Watchdog

NCN5121 provides a Watchdog function to the host

controller. The Watchdog function can be enabled by means

of the WDEN−bit (<WDEN>, see Watchdog Register , p 54).

Once this bit is set to ‘1’, the host controller needs to re−write

this bit to clear the internal timer before the Watchdog

Timeout Interval expires (Watchdog Timeout Interval =

<WDT>, see Watchdog Register, p54).

In case the Watchdog is acknowledged too early (before

tWDPR) or not within the Watchdog Timeout Interval

(tWDTO), the RESETB−pin will be made low (= reset host

controller).

Table 8 gives the Watchdog timings tWDTO and tWDPR.

Details on <WDT> can be found in the Watchdog Register,

p54.

Table 8. WATCHDOG TIMINGS

WDT[3:0] tWDTO [ms] tWDPR [ms]

0000 33 2

0001 66 4

0010 98 6

0011 131 8

0100 164 10

0101 197 12

0110 229 14

0111 262 16

1000 295 18

1001 328 20

1010 360 23

1011 393 25

1100 426 27

1101 459 29

1110 492 30

1111 524 31

NCN5121

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Analog State Diagram

The analog state diagram of NCN5121 is given in

Figure 19. The status of the oscillator, XCLK−pin, DC−DC

converters, V20V regulator, serial and KNX

communication during the different (analog) states is given

in Table 7.

Figure 20 gives a detailed view on the start−up behavior

of NCN5121. After applying the bus voltage, the filter

capacitor starts to charge. During this Reset State, the

current drawn from the bus is limited to Icoupler (for details

see the KNX Standards). Once the voltage on the filter

capacitor reaches 10 V (typ.), the fixed DC−DC converter

(powering VDDA) will be enabled and the device enters the

Start−Up State. When VDD1 gets above 2.8 V (typ.), the

OTP memory is read out to trim some analog parameters

(OTP memory is not accessible by the user). When done, the

Stand−By State is entered and the RESETB−pin is made

high. I f a t this moment VBUS is above VBUSH, the VBUS−bit

will be set (<VBUS>, see System Status Service, p37). After

aprox. 2 ms the Xtal oscillator will start. When VFILT is

above V FILTH DC2 and V20V will be started. When the Xtal

oscillator has started, no Thermal Warning (TW) or Thermal

Shutdown (TSD) was detected and the VBUS−, VFILT−,

VDD2− and V20V−bits are set, the Normal State will be

entered and SAVEB−pin will go high.

Figure 21 gives a detailed view on the shut−down

behavior. If the KNX bus voltage drops below VBUSL for

more than tbus_filter, the VBUS−bit will be reset (<VBUS>,

see System Status Service, p37) and the Standy−By State is

entered. SAVEB will go low to signal this. When VFILT

drops below VFILTL, DC2 and the V20V regulator will be

switched off. When VFILT drops below 6.5 V (typ), DC1

will be switched off and VDD1 drops below 2.8 V (typ.) the

device goes to Reset State (RESETB low).

Analog Output

A multiplexed analog signal is available on the

ANAOUT−pin for monitoring signal levels. The signal read

out on this pin can be configured through the Analog Output

Control bits (<ANAOUTCTRL>, see Analog Control

Figure 19. Analog State Diagram

Reset

RESETB = ‘0’

SAVEB = ‘0’

Start−Up

RESETB = ‘0’

SAVEB = ‘0’

Stand−By

RESETB = ‘1’

SAVEB = ‘0’

Normal

RESETB = ‘1’

SAVEB = ‘1’

VFILT > 12V

and

Temp < TSD

VFILT < 6.5V

VDDA OK

and

OTP read done

<TSD> = ‘1’

VDDA nOK

Remarks:

− <TW>, <XTAL>, <VBUS>, <VFILT>, <VDD2> and <V20V> are internal status bits which can be verified with the System State Service.

− <TSD> is an internal signal indicating a Thermal Shutdown. This internal signal cannot be read out.

− Although Reset State could be entered from Normal State on a TSD, Stand−By State will be entered first due to a TW.

Enable DC1 Disable DC1

Enable DC2 and V20V

VFILT > VFILTH

Disable DC2 and V20V

VFILT < VFILTL

Disable DC1

VFILT < 6.5V

<TW> = ‘0’ and <XTAL> = ‘1’ and

Disable DC1, DC2 and V20V

<TSD> = ‘1’

VDDA nOK

<VBUS> = ‘1’ and <VFILT> = ‘1’ and

<VDD2> = ‘1’ and <V20V> = ‘1’

<TW> = ‘1’ or <XTAL> = ‘0’ or

<VBUS> = ‘0’ or <VFILT> = ‘0’ or

<VDD2> = ‘0’ or <V20V> = ‘0’

and clock present

NCN5121

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Figure 20. Start−Up Behavior

<VFILT>

<VDD2>

<V20V>

RESETB

SAVEB

XCLK

BUS

VFILT

IBUS

Icoupler_lim,startup

VDD1

12V

VFILTH

2.8V

VXTAL

Xtal Oscillator

±2ms

<VBUS>

VBUSH

VDD2

0.9 x VDD2

V20V

V20VH

Reset Start−Up Stand−By Normal t

Remarks:

VDD1 directly connected to VDDA.

±2ms

NCN5121

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Figure 21. Shut−Down Behavior

<VFILT>

<VDD2>

<V20V>

RESETB

SAVEB

XCLK

VBUS

VFILT

IBUS

VDD1

6.5V

VFILTL

2.8V

VXTAL

Xtal Oscillator

<VBUS>

VBUSH

VDD2

0.9 x VDD2

V20V

ResetStand-ByNormal

Remarks:

VDD1 directly connected to VDDA.

VBUSL

tbus_filter tbus_filter

Normal Stand-By

NCN5121

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Interface Mode

The device can communicate with the host controller by

means of a UART interface or an SPI interface. The selection of the interface is done by the pins MODE1,

MODE2, TREQ, SCK/UC2 and CSB/UC1.

Table 9. INTERFACE SELECTION

TREQ MODE2 MODE1 SCK/UC2 CSB/UC1 SDI/RXD SDO/TXD Description

0 0 0 0 0

RXD TXD

9−bit UART−Mode, 19200 bps

0 0 0 0 1 9−bit UART−Mode, 38400 bps

0 0 0 1 0 8−bit UART−Mode, 19200 bps

0 0 0 1 1 8−bit UART−Mode, 38400 bps

1 0 0 DC2EN V20VEN Driver Receiver Analog Mode

TREQ 0 1 SCK (out) CSB (out) SDI SDO SPI Master, 125 kbps

TREQ 1 0 SPI Master, 500 kbps

NOTE: X = Don‘t Care

UART Interface

The UART interface is selected by pulling pins TREQ,

MODE1 and MODE2 to ground. Pin UC2 is used to select

the UART Mode (‘0’ = 9−bit, ‘1’ = 8−bit) and pin UC1 is

used to select the baudrate (‘0’ = 19200 bps, ‘1’ =

38400 bps). The UART interface allows full duplex,

asynchronous communication.

The difference between 8−bit mode and 9−bit mode is that

in 9−bit an additional parity bit is transmitted. This parity bit

is used as an even parity bit (with exception of the internal

meaningless and should be ignored). However, when the

NCN5121 detects an acceptance window error or pulse

duration error on the KNX bus, the parity bit is also encoded

to indicate an error in the byte. In 8−bit mode one extra

service is available (U_FrameState.ind). The SDI/RXD−pin

is the NCN5121 UART receive pin and is used to send data

from the host controller to the device. Pin SDO/TXD is the

NCN5121 UART transmit pin and is used to transmit data

between the device and the host controller. Figure 12 gives

an UART application example (9−bit, 19200 bps). Data is

transmitted LSB first.

Start

(= 0) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop

(= 1)

Figure 22. 8−bit UART Mode

Start

(= 0) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Parity Stop

(= 1)

Figure 23. 9−bit UART Mode

One special UART Mode is foreseen called Analog Mode.

When this mode is selected (TREQ = ‘1’, MODEx = ‘0’) an

immediate connection is made with the KNX transmitter

receiver (see Figure 24). Bit level coding/decoding has to be

done by the host controller. Keep in mind that the signals on

the SDI/RXD− and SDO/TXD−pin are inverted. Figure 14

gives an Analog Mode application example. In Analog

Mode, the UC1 and UC2 pins are used to enable or disable

the 20 V regulator and DC2 controller. When pulled low,

these blocks are enabled. When one of these pins is pulled

to VDDD, the respective block is disabled. When using the

device i n Analog Mode, no clock needs to be provided to the

device.

NCN5121

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Figure 24. Analog UART Mode

POR

TW/

TSD UVD

DC/DC

Converter 1

DC/DC

Converter 2

OSC

NCN5121

CAV

VBUS1

CCP

TXO

FANIN

VBUS2

V20V

XTAL1

XTAL2

XSEL

XCLKC

SAVEB RESETBANAOUT

VSS2

VDD2

VDD2MV

VDD2MC

VSW2

VSS1

VDD1

VDD1M

VSW1

VIN

MODE2

MODE1

TREQ (TREQ = 1)

CSB/UC1

SDO/TXD

SDI/RXD

SCK/UC2

VSSDVDDDVDDA VSSAVFILTCEQ2CEQ1

20V LDO

Fan−In

Control

Bus Coupler

Impedance

Control

Transmitter

Receiver

Osc

Diagnostics

OSC

XCLK

NCN5121

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SPI Interface

The SPI interface is selected by MODE1− and

MODE2−pin. The baudrate is determined by which

MODE−pin is pulled high (MODE1 pulled high = 125 kbps,

MODE2 pulled high = 500 kbps).

The SPI interface allows full duplex synchronous

communication between the device and the host controller.

The interface operates in Mode 0 (CPOL and CPHA = ‘0’)

meaning that the data is clocked out on the falling edge and

sampled on the rising edge. The LSB is transmitted first.

ÉÉ

SCK

SDI

CSB

LSB 1 2 3 4 5 6 MSBSDO

10 32 54 76

LSB 1 2 3 4 5 6 MSB

Figure 25. SPI Transfer

During SPI transmission, data is transmitted (shifted out

serially) on the SDO/TXD−pin and received (shifted in

serially) on the SDI/RXD−pin simultaneously. SCK/UC2 is

set as output and is used as the serial clock (SCK) to

synchronize shifting and sampling of the data on the SDI−

and SDO−pin. The speed of this clock signal is selectable

(see Table 9). The slave select line (CSB/UC1−pin) will go

low during each transmission allowing to selection the host

controller (CSB−pin is high when SPI is in idle state).

Shift Register

Control

NCN5121

SDO/TXD

SDI/RXD

SCK/UC2

CSB/UC1

Shift Register

Host Controller

MISO

MOSI

SCLK

SS Control

Figure 26. SPI Master

In an SPI network only one SPI Master is allowed (in this

case NCN5121). To allow the host controller to

communicate with the device the TREQ−pin can be used

(Transmit Request). When NCN5121 detects a negative

edge on TREQ, the device will issue dummy transmission

of 8 bits which will result in a transmission of data byte from

the host controller to the device. See Figure 1 1 for details on

the timings. See Figure 13 for an SPI application example.

SCK

SDI

CSB

SDO

TREQ

01234567

DDDDDDDD

01234

DDDDD

Dummy

Start dummy transmission

Figure 27. Transmission Request

NCN5121

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DIGITAL FUNCTIONAL DESCRIPTION

The implementation of the Data Link Layer as specified in the KNX standard is divided in two parts. All functions related

to communication with the Physical Layer and most of the Data Link Layer services are inside NCN5121, the rest of the

functions and the upper communication layers are implemented into the host controller (see Figure 28).

The host controller is responsible for handling:

•Checksum

•Parity

•Addressing

•Length

The NCN5121 is responsible for handling:

•Checksum

•Parity

•Acknowledge

•Repetition

•Timing

Digital State Diagram

The digital state diagram is given in Figure 29.

The current mode of operation can be retrieved by the host controller at any time (when RESETB−pin is high) by issuing

the U_SystemStat.req service and parsing back U_SystemStat.ind service (see System Status Service, p37).

Table 10. NCN5121 DIGITAL STATES

State Explanation

RESET Entered after Power On Reset (POR) or in response to a U_Reset.req service issued by the host controller. In this

state NCN5121 gets initialized, all features disabled and services are ignored and not executed.

POWER−UP /

POWER−UP

STOP

Entered after Reset State or when VBUS, VFILT or Xtal are not operating correctly (operation of VBUS, VFILT and

XTAL can be verified by means of the System Status Service, p37). Communication with KNX bus is not allowed.

U_SystemStat.ind can be used to verify this state (code 00).

SYNC NCN5121 remains in this state until it detects silence on the KNX bus for at least 40 Tbits. Although the receiver of

NCN5121 is on, no frames are transmitted to the host controller.

U_SystemStat.ind can be used to verify this state (code 01).

STOP This state is useful for setting−up NCN5121 safely or temporarily interrupting reception from the KNX bus.

U_SystemStat.ind can be used to verify this state (code 10).

NORMAL In this state the device is fully functional. Communication with the KNX bus is allowed.

U_SystemStat.ind can be used to verify this state (code 11).

NCN5121

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Application Layer

Presentation Layer

Session Layer

Transport Layer

Network Layer

Data Link Layer

Logic Link Control

Media Access Control

Physical Layer

NCN5121 Host Controller

Figure 28. OSI Model Reference

Reset

Initialize device

Deactivate all features

POR or U_Reset.req

Power−Up

Code: 00

KNX Rx = off

KNX Tx = off

Sync

Code: 01

KNX Rx = on

KNX Tx = off

Stop

Code: 10

KNX Rx = off

KNX Tx = off

Normal

Code: 11

KNX Rx = on

KNX Tx = on

Power−Up Stop

Code: 00

KNX Rx = off

KNX Tx = off

<XTAL>=‘1’

and

<VBUS> = ‘1’

and

<VFILT> = ‘1’

<XTAL>=‘0’

<VBUS> =‘0’

<VFILT> =‘0’

<XTAL> =‘1’

and

<VBUS> =‘1’

and

<VFILT> =‘1’

<XTAL> = ‘0’

<VBUS> = ‘0’

<VFILT> = ‘0’

<XTAL> = ‘0’

<VBUS> = ‘0’

<VFILT> = ‘0’

Send U_Reset.ind

to host

KNX bus idle for w40 Tbits

U_ExitStopMode.req

Send U_StopMode.ind

to host

U_StopMode.req

U_StopMode.req and

no activity for w30 Tbits

U_ExitStopMode .req

Send U_StopMode.ind

to host

U_StopMode.req

Figure 29. Digital State Diagram

NCN5121

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Services

Execution of services depends on the digital state (Figure 29). Certain services are rejected if received outside the Normal

State. The following table gives a view of all services and there acceptance during the different digital states.

Table 11. ACCEPTANCE OF SERVICES

Service

State

Normal Stop Sync Power−Up Bus Monitor

U_Reset.req E E E E E

U_State.req E E E E I

U_SetBusy.req E E E E I

U_QuitBusy.req E E E E I

U_Busmon.req E E E E I

U_SetAddress.req E E E E I

U_SetRepetition.req E E E E I

U_L_DataOffset.req E E E E I

U_SystemStat.req E E E E I

U_StopMode.req E I E E E

U_ExitStopMode.req I E I I E

U_Ackn.req E R R R I

U_Configure.req E E E E I

U_IntRegWr.req E E E E E

U_IntRegRd.req E E E E E

U_L_DataStart.req E R R R I

U_L_DataCont.req E R R R I

U_L_DataEnd.req E R R R I

U_PollingState.req E E E E I

NOTE: Bus Monitor state is not a separate state. It is applied on top of Normal, Stop, Sync or Power−Up State.

Legend: E = service is executed

I = service is ignored (not executed and no feedback sent to the host controller)

R = service is rejected (not executed, protocol error is sent back to the host controller through U_State.ind)

See Internal Register Read Service (p39) for limitations of U_IntRegRd.req

NCN5121

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Table 12. SERVICES FROM HOST CONTROLLER

Control Field

Service Name Hex Remark Extra Following

Bytes Total

Bytes

76543210

INTERNAL COMMANDS – DEVICE SPECIFIC

00 0 0 0 0 0 1 U_Reset.req 01 1

0 0 0 0 0 0 1 0 U_State.req 02 1

0 0 0 0 0 0 1 1 U_SetBusy.req 03 1

0 0 0 0 0 1 0 0 U_QuitBusy.req 04 1

0 0 0 0 0 1 0 1 U_Busmon.req 05 1

1 1 1 1 0 0 0 1 U_SetAddress.req F1 AddrHigh

AddrLow

X (don’t care)

1 1 1 1 0 0 1 0 U_SetRepetition.req F2 RepCntrs

X (don’t care)

0 0 0 0 1 i i i U_L_DataOffset.req 08−0C iii = MSB byte

index (0…4) 1

0 0 0 0 1 1 0 1 U_SystemState.req 0D 1

0 0 0 0 1 1 1 0 U_StopMode.req 0E 1

0 0 0 0 1 1 1 1 U_ExitStopMode.req 0F 1

0 0 0 1 0 n b a U_Ackn.req 10−17 n = nack

b = busy

a = addressed

0 0 0 1 1 p c m U_Configure.req 18−1F p = auto−polling

c = CRC−CCITT

m = frame end

with MARKER

0 0 1 0 1 0 a a U_IntRegWr.req 28−2B aa = address of

internal register Data to be written 2

0 0 1 1 1 0 a a U_IntRegRd.req 38−3B 1

1 1 1 0 s s s s U_PollingState.req E0−EE s = slot number

(0 … 14) PollAddrHigh

PollAddrLow

PollState

KNX TRANSMIT DATA COMMANDS

10 0 0 0 0 0 0 U_L_DataStart.req 80 Control Octet (CTRL) 2

1 0 i i i i i i U_L_DataCont.req 81−BF i = index (1…63) Data octet (CTRLE,

SA, DA, AT, NPCI, LG,

TPDU)

0 1 l l l l l l U_L_DataEnd.req 47−7F l = last index + 1

(7 … 63) Check Octet (FCS) 2

With respect to command length, there are two types of services from the host controller:

•Single−byte commands: the control byte is the only data sent from the host controller to NCN5121.

•Multiple−byte commands: the following data byte(s) need to be handled according to the already received control byte.

With respect to command purpose there are two types of services from the host controller:

•Internal command: does not initiate any communication on the KNX bus.

•KNX transmit data command: initiates KNX communication

NCN5121

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Table 13. SERVICES TO HOST CONTROLLER

Control Field

Service Name Remark

Extra

Following

Bytes Total

Bytes

7 6 5 4 3 2 1 0

DLL (LAYER 2) SERVICES (DEVICE IS TRANSPARENT)

10 r 1 p1 p0 0 0 L_Data_Standard.ind r = not repeated (‘1’) or

repeated L_Data frame (‘0’)

p1, p0 = priority

0 0 r 1 p1 p0 0 0 L_Data_Extended.ind n

1 1 1 1 0 0 0 0 L_Poll_Data.ind n

ACKNOWLEDGE SERVICES (DEVICE IS TRANSPARENT IN BUS MONITOR MODE)

xx 0 0 x x 0 0 L_Ackn.ind x = acknowledge frame 1

z 0 0 0 1 0 1 1 L_Data.con z = positive (‘1’) or negative

(‘0’) confirmation 1

CONTROL SERVICES – DEVICE SPECIFIC

00 0 0 0 0 1 1 U_Reset..ind 1

sc re te pe tw 1 1 1 U_State.ind sc = slave collision

re = receive error

te = transmit error

pe = protocol error

tw = temperature warning

re ce te 1 res 0 1 1 U_FrameState.ind re = parity or bit error

ce = checksum or length

error

te = timing error

res = reserved

0 b aa ap c m 0 1 U_Configure.ind b = reserved

aa = auto−acknowledge

ap = auto−polling

c = CRC−CCITT

m = frame end with

MARKER

1 1 0 0 1 0 1 1 U_FrameEnd.ind 1

0 0 1 0 1 0 1 1 U_StopMode.ind 1

0 1 0 0 1 0 1 1 U_SystemStat.ind V20V, VDD2,

VBUS, VFILT,

XTAL, TW,

Mode

Each data byte received from the KNX bus is transparently transmitted to the host controller. An exception is the

Acknowledge byte which is transmitted to the host controller only in bus monitoring mode. Other useful information can be

transmitted to the host controller by request using internal control services.

A detailed description of the services is given on the next pages. For all figures, the MSB bit is always given on the left side

no matter how the arrow is drawn.

Host Ctrl NCN5121 KNX Bus

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

Figure 30. Bit Order of Services

NCN5121

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Reset Service

Reset the device to the initial state.

0 0 0 0 0 0 0 1

U_Reset.req

0 0 0 0 0 0 1 1

U_Reset.ind

Host Ctrl NCN5121 KNX Bus

Figure 31. Reset Service

Remark: U_Reset.Ind will be send when entering Normal State (see Digital State Diagram, p29).

State Service

Get internal communication state of the device.

0 0 0 0 0 0 1 0

U_State.req

sc re te pe tw 1 1 1

U_State.ind

Host Ctrl NCN5121 KNX Bus

Figure 32. State Service

sc (slave collision): ‘1’ if collision is detected during transmission of polling state

re (receive error): ‘1’ if corrupted bytes were sent by the host controller. Corruption involves incorrect parity (9−bit

UART only) and stop bit of every byte as well as incorrect control octet, length or checksum of frame

for transmission.

te (transceiver error): ‘1’ if error detected during frame transmission (sending ‘0’ but receiving ‘1’).

pe (protocol error): ‘1’ if an incorrect sequence of commands sent by the host controller is detected.

tw (thermal warning): ‘1’ if thermal warning condition is detected.

Set Busy Service

Activate BUSY mode.

During this time and when autoacknowledge is active (see Set Address Service p35), NCN5121 rejects the frames whose

destination address corresponds to the stored physical address by sending the BUSY acknowledge. This service has no ef fect

if autoacknowledge is not active.

0 0 0 0 0 0 1 1

U_SetBusy.req

Host Ctrl NCN5121 KNX Bus

Figure 33. Set Busy Service

Remark: BUSY mode is deactivated immediately if the host controller confirms a frame by sending U_Ackn.req service.

Quit Busy Service

Deactivate the BUSY mode.

Restores back to the normal autoacknowledge behavior with ACK sent on the bus in response to addressing frame (only if

autoacknowledge is active). This service has no effect if autoacknowledge is not active or BUSY mode was not set.

0 0 0 0 0 1 0 0

U_QuitBusy.req

Host Ctrl NCN5121 KNX Bus

Figure 34. Quit Busy Service

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Bus Monitor Service

Activate bus monitoring state.

In this mode all data received from the KNX bus is sent to the host controller without performing any filtering on Data Link

Layer. Acknowledge Frames are also transmitted transparently. This state can only be exited by the Reset Service (see p34).

0 0 0 0 0 1 0 1

U_Busmon.req

x x x x x x x x

KNX Message

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

KNX Message

x x x x x x x x

KNX Message

x x x x x x x x

KNX Message

0 0 0 0 0 0 0 1

U_Reset.req

0 0 0 0 0 0 1 1

U_Reset.ind

x x 0 0 x x 0 0

Acknowledge

x x 0 0 x x 0 0

Acknowledge

Figure 35. Bus Monitor Service

Remark:

x = don‘t care

Set Address Service

Sets the physical address of the device and activates the auto−acknowledge function.

NCN5121 starts accepting all frames whose destination address corresponds to the stored physical address or whose

destination address is the group address by sending IACK on the bus. In case of an error detected during such frame reception,

NCN5121 sends NACK instead of IACK.

When issued several times after each other, the first call will set the physical address and activate the auto−acknowledge.

Following calls will only set the physical address because auto−acknowledge is already activated.

NCN5121 confirms activation of auto−acknowledge function by sending the U_Configure.ind service to the host controller.

1 1 1 1 0 0 0 1

U_SetAddress.req

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Address High Byte

x x x x x x x x

Address Low Byte

0 b aa ap c m 0 1

U_Configure.ind

x x x x x x x x

Dummy

Figure 36. Set Address Service

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b (busy mode): ‘1’ if busy mode is active. Can be enabled with U_SetBusy.req (see Set Busy Service, p34) and

disabled with U_QuitBusy.req service (see Quit Busy Service, p34) or U_Ackn.req service

(see Receive Frame Service, p47).

aa (auto−acknowledge):‘1’ if auto−acknowledge feature is active. Can be enabled with U_SetAddress.req service

(see Set Address Service, p35).

ap (auto−polling): ‘1’ if auto−polling feature is active. This feature can be enabled with U_Configure.req service

(see Configure Service, p38).

c (CRC−CCITT): ‘1’ if CRC−CCITT feature is active. This feature can be enabled with U_Configure.req service

(see Configure Service, p38).

m (frame end with MARKER): ‘1’ when feature is active. This feature can be enabled with U_Configure.req service

(see Configure Service, p38).

Remarks:

•Set Address Service can be issued any time but the new physical address and the autoacknowledge function will only

get active after the KNX bus becomes idle.

•Autoacknowledge can only be deactivated by a Reset Service (p34)

•x = don’t care

•Dummy byte can be anything. NCN5121 completely disregards this information.

Set Repetition Service

Specifies the maximum repetition count for transmitted frames when not acknowledged with IACK.

Separate counters can be set for NACK and BUSY frames. Initial value of both counters is 3.

If the acknowledge from remote Data Link Layer is BUSY during frame transmission, NCN5121 tries to repeat after at least

150 bit times KNX bus idle. The BUSY counter determines the maximum amount of times the frame is repeated. If the BUSY

acknowledge is still received after the last try, an L_Data.con with a negative conformation is sent back to the host controller.

For all other cases (NACK acknowledgment received, invalid/corrupted acknowledge received or time−out after 30 bit

times) NCN5121 will repeat after 50 bit times of KNX bus idle. The NACK counter determines the maximum retries.

L_Data.con with a negative confirmation is send back to the host controller when the maximum retries were reached.

In worst case, the same request is transmitted (NACK + BUSY + 1) times before NCN5121 stops retransmission.

Figure 37. Set Repetition Service

1 1 1 1 0 0 1 0

U_SetRepetition.req

Host Ctrl NCN5121 KNX Bus

0 b 0 n

Maximum Repetitions

bb nn

x x x x

Dummy

xx xx

x x x x

Dummy

xx xx

bbb: BUSY counter (a frame will be retransmitted bbb−times if acknowledge with BUSY).

nnn: NACK counter (a frame will be retransmitted nnn−times if acknowledge with NACK).

Remark: Bit 3 and 7 of the second byte need to be zero (‘0’)!

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System Status Service

Request the internal system state of the device.

0 0 0 0 1 1 0 1

U_SystemStat.req

Host Ctrl NCN5121 KNX Bus

0 1 0 0 1 0 1 1

U_SystemStat.ind

2nd byte

XTAL

VFILT

VBUS

VDD2

V20V

Mode

Figure 38. System State Service

V20V: ‘1’ if V20V linear voltage regulator is within normal operating range

VDD2: ‘1’ if DC2 regulator is within normal operating range

VBUS: ‘1’ if KNX bus voltage is within normal operating range

VFILT: ‘1’ if voltage on tank capacitor is within normal operating range State Service

XTAL: ‘1’ if crystal oscillator frequency is within normal operating range

TW: ‘1’ if thermal warning condition is present (can also be verified with U_State.ind service (see State Service,

p34)

Mode: Operation mode (see also Digital State Diagram, p29).

Bit

Mode

1 0

0 0 Power−Up

0 1 Sync

1 0 Stop

1 1 Normal

Note: SAVEB−pin is low if any of bits 3 to 7 is ‘0’ (zero) or bit 2 is ‘1’.

Stop Mode Service

Go to Stop State. A confirmation is sent to indicate that device has switched to the Stop State. See also Digital State Diagram,

p29

0 0 0 0 1 1 1 0

U_StopMode.req

Host Ctrl NCN5121 KNX Bus

0 0 1 0 1 0 1 1

U_StopMode.ind

Figure 39. Stop Mode Service

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Exit Stop Mode Service

Request transition from Stop to Sync State. An acknowledge service is send later to confirm that device has switched from

Sync to Normal State. See also Digital State Diagram, p29.

0 0 0 0 1 1 1 1

U_ExitStopMode.req

Host Ctrl NCN5121 KNX Bus

0 0 0 0 0 0 1 1

U_Reset.ind

Figure 40. Exit Stop Mode Service

Configure Service

Activate additional features (which are disabled after reset).

U_Configure.ind service is send back to the host controller at the exact moment when the new features get activated. This

is done during bus idle or outside the Normal State. It confirms the execution of the request service.

Host Ctrl NCN5121 KNX Bus

0 0 0 1 1 m

U_Configure.req

0 b aa ap c 1

U_Configure.ind

Figure 41. Configure Service

p (auto polling): when active, NCN5121 automatically fills in corresponding poll slot of polling telegrams.

Host controller is responsible to provide appropriate polling information with the

U_PollingState.req service (See Slave Polling Frame Service and Master Polling Frame

Service, p50 and 51).

c (CRC−CCITT): when active, NCN5121 accompanies every received frame with a 2−byte CRC−CCITT

value. CRC−CCITT is also known as CRC−16−CCITT.

m (frame end with MARKER): End of received frames is normally reported with a silence of 2.6 ms on the Tx line to the host

controller. With this feature active, NCN5121 marks end of frame with U_FrameEnd.ind +

U_FrameState.ind s ervices ( See S end F rame S ervice and Receive F rame S ervice, p 39 a nd 47).

b: ‘1’ if busy mode is active. Can be enabled with U_SetBusy.req (see Set Busy Service, p34)

and disabled with U_QuitBusy.req service (see Quit Busy Service, p34) or U_Ackn.req

service (see Receive Frame Service, p47).

aa: ‘1’ if auto−acknowledge feature is active. Can be enabled with U_SetAddress.req service

(see Set Address Service, p35).

ap (auto−polling): ‘1’ if auto−polling feature i s a ctive. T his f eature c a n b e en abled w ith U _Configure.req s ervice.

c (CRC−CCITT): ‘1’ if CRC−CCITT feature is active. See p53 for info on CRC−CCITT.

This feature can be enabled with U_Configure.req service.

m (frame end with MARKER): ‘1’ when feature is active. This feature can be enabled with U_Configure.req service.

Remark:

Activation of the additional features is done by setting the corresponding bit to ‘1’. Setting the bit to ‘0’ (zero) has no e ffect

(will not deactivate feature). Features can only be deactivated by a reset. Set all bits (m, c and p) to ‘0‘ (zero) to poll the current

configuration status.

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Internal Register Write Service

Write a byte to an internal device−specific register (see Internal Device−Specific Registers, p 54). The address of the register

is specified in the request. The data to be written is transmitted after the request.

0 0 1 0 1 0 a a

U_IntRegWr.req

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Data Byte

Figure 42. Internal Register Write Service

aa: address of the internal register

Remarks:

•x = don’t care (in line with Internal Device−Specific Registers, p54).

•Internal Register Write is not synchronized with other services. One should only use this service when all previous

services are ended. When using communication over SPI, it is recommended to go to stop mode when performing a

Internal Register Read Service

Read a byte from an internal device−specific register (see Internal Device−Specific Registers, p54). The address of the

0 0 1 1 1 0 a a

U_IntRegRd.req

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Data Byte

Figure 43. Internal Register Read Service

aa: address of the internal register

Remarks:

•x = don’t care (in line with Internal Device−Specific Registers, p54).

•It’s advised to only use this service in Stop, Power−Up Stop or Power−Up State. In the other state erroneous behavior

could occur.

•Internal Register Read is not synchronized with other services. One should only use this service when all previous

services are ended. When using communication over SPI or UART, it is recommended to go to stop mode when

performing a register write.

Send Frame Service

Send data over the KNX bus.

The U_L_DataStart.req is used to start transmission of a new frame. The byte following this request is the control byte of

the KNX telegram.

The different bytes following the control byte are assembled by using U_L_DataCont.req. The byte following

U_L_DataCont.req is the data byte of the KNX telegram. U_L_DataCont.req contains the index which specifies the position

of the data byte inside the KNX telegram. It‘s allowed to transmit bytes in random order and even overwrite bytes (= write

several times into the same index). It‘s up to the host controller to correctly populate all data bytes of the KNX telegram.

U_L_DataEnd.req is used to finalize the frame and start the KNX transfer. The byte following U_L_DataEnd.req is the

checksum of the KNX telegram. If the checksum received by the device corresponds to the calculated checksum, the device

starts the transmission on the KNX bus. If not, the device returns U_State.ind message to the host controller with Receive Error

flag set (see State Service p34 for U_State.ind).

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U_L_DataStart/DataCont/DataEnd only provides space for 6 index bits. Because an extended frame can consist out of

263 bytes, an index of 9 bits long is needed. U_DataOf fset.req provides the 3 most significant bits of the data byte index. The

value is stored internally until a new offset is provided with another call.

Each transmitted data octet on the KNX bus will also be transmitted back to the host controller.

Each transmission is ended with a L_Data.con service where the MSB indicates if an acknowledgment was received or not.

When operating in SPI or UART 8−bit Mode, L_Data.con is preceded with U_FrameState.ind.

Depending on the activated features, a CRC−CCITT service and/or a MARKER could be included.

Next figures give different examples of send frames.

1 0 0 0 0 0 0 0

U_L_DataStart.req

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet 1

0 0 0 0 1 i i i

U_L_DataOffSet.req

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet N

0 1 l l l l l l

U_L_DataEnd.req

x x x x x x x x

Checksum

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

re ce te 1 res 0 1 1

U_FrameState.ind

x 0 0 0 1 0 1 1

L_Data.con

2.6ms silence

Figure 44. Send Frame, SPI or 8−bit UART Mode, Frame End with Silence, No CRC−CCITT

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1 0 0 0 0 0 0 0

U_L_DataStart.req

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet 1

0 0 0 0 1 i i i

U_L_DataOffSet.req

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet N

0 1 l l l l l l

U_L_DataEnd.req

x x x x x x x x

Checksum

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

x 0 0 0 1 0 1 1

L_Data.con

2.6ms silence

Figure 45. Send Frame, 9−bit UART Mode, Frame End with Silence, No CRC−CCITT

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1 0 0 0 0 0 0 0

U_L_DataStart.req

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet 1

0 0 0 0 1 i i i

U_L_DataOffSet.req

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet N

0 1 l l l l l l

U_L_DataEnd.req

x x x x x x x x

Checksum

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

x x x x x x x x

CRC−CCITT Low Byte

2.6 ms silence

x x x x x x x x

CRC−CCITT High Byte

x 0 0 0 1 0 1 1

L_Data.con

Figure 46. Send Frame, 9−bit UART Mode, Frame End with Silence, with CRC−CCITT

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1 0 0 0 0 0 0 0

U_L_DataStart.req

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet 1

0 0 0 0 1 i i i

U_L_DataOffSet.req

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet N

0 1 l l l l l l

U_L_DataEnd.req

x x x x x x x x

Checksum

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

x x x x x x x x

CRC−CCITT Low Byte

w2.6ms silence

x x x x x x x x

CRC−CCITT High Byte

re ce te 1 res 0 1 1

U_FrameState.ind

x 0 0 0 1 0 1 1

L_Data.con

Figure 47. Send Frame, SPI or 8−bit UART Mode, Frame End with Silence, with CRC−CCITT

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1 0 0 0 0 0 0 0

U_L_DataStart.req

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet 1

0 0 0 0 1 i i i

U_L_DataOffSet.req

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet N

0 1 l l l l l l

U_L_DataEnd.req

x x x x x x x x

Checksum

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

re ce te 1 res 0 1 1

U_FrameState.ind

x 0 0 0 1 0 1 1

L_Data.con

1 1 0 0 1 0 1 1

U_FrameEnd.ind

Figure 48. Send Frame, All Modes, Frame End with MARKER, No CRC−CCITT

NCN5121

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1 0 0 0 0 0 0 0

U_L_DataStart.req

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet 1

0 0 0 0 1 i i i

U_L_DataOffSet.req

1 0 i i i i i i

U_L_DataCont.req

x x x x x x x x

Data Octet N

0 1 l l l l l l

U_L_DataEnd.req

x x x x x x x x

Checksum

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

x x x x x x x x

CRC−CCITT Low Byte

x x x x x x x x

CRC−CCITT High Byte

re ce te 1 res 0 1 1

U_FrameState.ind

x 0 0 0 1 0 1 1

L_Data.con

1 1 0 0 1 0 1 1

U_FrameEnd.ind

Figure 49. Send Frame, All Modes, Frame End with MARKER and with CRC−CCITT

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re (receive error): ‘1’ if newly received frame contained corrupted bytes (wrong parity, wrong stop bit or

incorrect bit timings)

ce (checksum or length error): ‘1’ if newly received frame contained wrong checksum or length which does not correspond

to the number of received bytes

te (timing error): ‘1’ if newly received frame contained bytes whose timings do not comply with the KNX

standard

res (reserved): Reserved for future use (will be ‘0’).

Remarks:

− If the repeat flag is not set (see Set Repetition Service p36), the device will only perform one attempt to send the KNX

telegram.

− Sending of the KNX telegram over the KNX bus is only started after all data bytes are received and the telegram is

assembled.

− When starting transmission of a new frame with U_L_DataStart.req, the device automatically resets the internal offset of

the data index to zero.

− Data offsets of 5, 6 and 7 are forbidden (U_L_DataOffset.req)!

Remarks on Figures 44 to 49:

− x = don‘t care (in respect with KNX standard)

− See Tables 12 and 13 for more details on all the bits

− Code of U_FrameEnd.ind (0xCB) can also be part of the KNX frame content (Data Octet). When NCN5121 transmits

the data octet (0xCB) on the KNX bus, 2 bytes (2 times 0xCB) will be transmitted back to the host controller to make it

possible for the host controller to distinguish between a data octet (0xCB) and U_FrameEnd.ind. This remark is only

valid if frame end with MARKER is enabled.

− See p53 for info on CRC−CCITT.

NCN5121

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Receive Frame Service

Receive data over the KNX bus.

Upon reception from the control byte, the control byte is checked by the device. If correct, the control byte is transmitted

back to the host (L_Data_Standard.ind or L_Data_Extended.ind depending if standard or extended frame type is received).

After the control byte, all data bytes are transparently transmitted back to the host controller. Handling of this data is a task

for the Data Link Layer which should be implemented in the host controller.

The host controller can indicate if the device is addressed by setting the NACK, BUSY or ACK flag (U_Ackn.req).

When working in SPI or 8−bit UART Mode, each frame is ended with an U_FrameState.ind. Depending on the activated

features, a CRC−CCITT or MARKER could be added to the complete frame.

Below figures give different examples of receive frames.

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

re ce te 1 0 0 1 1

U_FrameState .ind

0 0 0 1 0 n b a

U_Ackn.req

x x x x x x x x

Data Octet N

w2. 6 ms silence

Figure 50. Receive Frame, SPI or 8−bit UART Mode, Frame End with Silence, No CRC−CCITT

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Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

0 0 0 1 0 n b a

U_Ackn.req

x x x x x x x x

Data Octet N

2.6 ms silence

Figure 51. Receive Frame, 9−bit UART Mode, Frame End with Silence, No CRC−CCITT

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

0 0 0 1 0 n b a

U_Ackn.req

x x x x x x x x

Data Octet N

2.6ms silence

x x x x x x x x

CRC−CCITT Low Byte

x x x x x x x x

CRC−CCITT High Byte

Figure 52. Receive Frame, 9−bit UART Mode, Frame End with Silence, with CRC−CCITT

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Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

0 0 0 1 0 n b a

U_Ackn.req

x x x x x x x x

Data Octet N

2.6ms silence

x x x x x x x x

CRC−CCITT Low Byte

x x x x x x x x

CRC−CCITT High Byte

re ce te 1 res 0 1 1

U_FrameState.ind

Figure 53. Receive Frame, SPI or 8−bit UART Mode, Frame End with Silence, with CRC−CCITT

Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

0 0 0 1 0 n b a

U_Ackn.req

x x x x x x x x

Data Octet N

re ce te 1 res 0 1 1

U_FrameState.ind

1 1 0 0 1 0 1 1

U_FrameEnd.ind

Figure 54. Receive Frame, All Modes, Frame End with MARKER, No CRC−CCITT

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Host Ctrl NCN5121 KNX Bus

x x x x x x x x

Control Byte

x x x x x x x x

Data Octet 1

x x x x x x x x

Checksum

x 0 r 1 p1 p0 0 0

L_Data.ind

x x x x x x x x

Data Octet 1

x x x x x x x x

Data Octet N

x x x x x x x x

Checksum

x x x x x x x x

Immediate Ackn

0 0 0 1 0 n b a

U_Ackn.req

x x x x x x x x

Data Octet N

x x x x x x x x

CRC−CCITT Low Byte

x x x x x x x x

CRC−CCITT High Byte

re ce te 1 res 0 1 1

U_FrameState .ind

1 1 0 0 1 0 1 1

U_FrameEnd.ind

Figure 55. Receive Frame, All Modes, Frame End with MARKER, with CRC−CCITT

re (receive error): ‘1’ if newly received frame contained corrupted bytes (wrong parity, wrong stop bit or

incorrect bit timings)

ce (checksum or length error): ‘1’ if newly received frame contained wrong checksum or length which does not correspond

to the number of received bytes

te (timing error) : ‘1’ if newly received frame contained bytes whose timings do not comply with the KNX

standard

res (reserved) : Reserved for future use (will be ‘0’).

Remarks on Figures 50 to 55:

− x = don‘t care (in respect with KNX standard)

− See Tables 12 and 13 for more details on all the bits

− Code of U_FrameEnd.ind (0xCB) can also be part of the KNX frame content (Data Octet). To make a distinguish

between a data octet and U_FrameEnd.ind, NCN5121 duplicates the data content (if 0xCB). This will result in 2 bytes

transmitted to the host controller (two times 0xCB) corresponding to 1 byte received on the KNX bus.

Above is only valid if frame end with MARKER is enabled.

− See p53 for info on CRC−CCITT.

Slave Polling Frame Service

Upon reception and consistency check of the polling control byte, the control byte is send back to the host controller

(L_Poll_Data.ind). The host controller will send the slot number to the device (U_PollingState.req), followed by the polling

address and the polling state. At the same time the source address, polling address, slot count and checksum is received over

the KNX bus. If the polling address received from the KNX bus is equal to the polling address received from the host controller,

NCN5121 will send the polling data in the slot as define by U_PollingState.req (only if the slotcount is higher as the define

slot).

U_PollingState.req can be sent at any time (not only during a transmission of a polling telegram). The information is stored

internally in NCN5121 and can be reused for further polling telegrams if auto−polling function gets activated.

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Host Ctrl NCN5121 KNX Bus

1 1 1 1 0 0 0 0

Control Byte

x x x x x x x x

Source Address

x x x x x x x x

Checksum

1 1 1 1 0 0 0 0

L_Poll_Data.ind

1 1 1 0 s s s s

U_PollingState.req

x x x x x x x x

Slot 0

x x x x x x x x

PollAddrHigh x x x x x x x x

Source Address

x x x x x x x x

PollAddrLow x x x x x x x x

Poll Address

x x x x x x x x

Poll Address

x x x x x x x x

Slot Count

x x x x x x x x

PollState

x x x x x x x x

Slot N

Figure 56. Slave Polling Frame Service

Remarks: x = don’t care (in respect with KNX standard)

ssss = slot number

Master Polling Frame Service

When NCN5121 receives the polling frame from the host controller, the polling frame will be transmitted over the KNX bus.

NCN5121

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Host Ctrl NCN5121 KNX Bus

1 1 1 1 0 0 0 0

Control Byte

x x x x x x x x

Source Address

x x x x x x x x

Checksum

1 1 1 1 0 0 0 0

L_Poll_Data.ind

1 1 1 0 s s s s

U_PollingState.req

x x x x x x x x

Slot 0

x x x x x x x x

Poll Address

x x x x x x x x

Source Address

x x x x x x x x

PollAddrLow

x x x x x x x x

Poll Address

x x x x x x x x

Poll Address

x x x x x x x x

Slot Count

x x x x x x x x

PollState

x x x x x x x x

Slot N

x x x x x x x x

Source Address

x x x x x x x x

PollAddrHigh

x x x x x x x x

Source Address

x x x x x x x x

Poll Address

x x x x x x x x

Slot Count

x x x x x x x x

Checksum

x x x x x x x x

Slot 0

x x x x x x x x

Slot N

1 1 1 1 0 0 0 0

Control Byte

x x x x x x x x

Source Address

x x x x x x x x

Checksum

x x x x x x x x

Source Address

x x x x x x x x

Poll Address

x x x x x x x x

Poll Address

x x x x x x x x

Slot Count

Figure 57. Master Polling Frame Service

Remarks: x = don‘t care (in respect with KNX standard)

ssss = slot number

NCN5121

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CRC−CCITT

CRC order - 16 bit

CRC polynom (hex) - 1021

Initial value (hex) − FFFF

Final XOR value (hex) − 0

No reverse on output CRC

Test string „123456789“ is 29B1h

CRC−CCITT value over a buffer of bytes can be calculated with following code fragment in C, where

pBuf is pointer to the start of frame buffer

uLength is the frame length in bytes

unsigned short calc_CRC_CCITT(unsigned char* pBuf, unsigned short uLength)

{unsigned short u_crc_ccitt;

for (u_crc_ccitt = 0xFFFF; uLength−−; p++)

{u_crc_ccitt = get_CRC_CCITT(u_crc_ccitt, *p);

}

return u_crc_ccitt;

}

unsigned short get_CRC_CCITT(unsigned short u_crc_val, unsigned char btVal)

{u_crc_val = ((unsigned char)(u_crc_val >> 8)) | (u_crc_val << 8);

u_crc_val ^= btVal;

u_crc_val ^= ((unsigned char)(u_crc_val & 0xFF)) >> 4;

u_crc_val ^= u_crc_val << 12;

u_crc_val ^= (u_crc_val & 0xFF) << 5;

return u_crc_val;

}

NCN5121

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Internal Device−Specific Registers

In total 4 device-specific register are available:

•Watchdog Register (0x00)

•Analog Control Register 0 (0x01)

•Analog Control Register 1 (0x02)

•Analog Status Register 0 (0x03)

•Revision ID Register (0x05)

Watchdog Register

The Watchdog Register is located at address 0x00 and can be used to enable the watchdog and set the watchdog time.

Table 14. WATCHDOG REGISTER

ExtWatchdogCtrl (ExtWR)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x00

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 1 1 1 1

Data WDEN - - - WDT

Table 15. WATCHDOG REGISTER PARAMETERS

Parameter Value Description Info

WDEN 0 Disable Enables/disables the watchdog

p22

1 Enable

WDT

0000 33 ms

Defines the watchdog time. The watchdog needs to be re-enabled (WDEN)

within this time or a watchdog event will be triggered.

0001 66 ms

0010 98 ms

0011 131 ms

0100 164 ms

0101 197 ms

0110 229 ms

0111 262 ms

1000 295 ms

1001 328 ms

1010 360 ms

1011 393 ms

1100 426 ms

1101 459 ms

1110 492 ms

1111 524 ms

Remark: Bit 4 … 6 are reserved.

Analog Control Register 0

The Analog Control Register 0 is located at address 0x01 and can be used to disable the V20V and the DC2 regulator, to

disable the XCLK-pin, to enable the transmit trigger signal and to set the 20 V LDO current limit.

Table 16. ANALOG CONTROL REGISTER 0

Analog Control Register 0 (AnaCtrl0)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x01

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 1 1 1 0 1 0 0

Data − V20VEN DC2EN XCLKEN TRIGEN V20VCLIMIT

NCN5121

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Table 17. ANALOG CONTROL REGISTER 0 PARAMETERS

Parameter Value Description Info

V20VEN 0 Disable Enables/disables the V20V regulator p 19

1 Enable

DC2EN 0 Disable Enables/disables the DC2 converter p 19

1 Enable

XCLKEN 0 Disable Enables/disables the XCLK output signal p 19

1 Enable

TRIGEN 0 Disable TRIG/ARXD pin outputs the Tx activity monitor signal when enabled.

When disabled the TRIG/ARXD pin is tri−state. p 19

1 Enable

V20VCLIMIT 000 − 111 Adjustment of the V20V current limit as configured by R6 by DI20V, STEP per bit p 19

Remark: Bit 7 is reserved.

Analog Control Register 1

The Analog Control Register 1 is located at address 0x02 and can be used to configure the voltage monitors.

Table 18. ANALOG CONTROL REGISTER 1

Analog Control Register 1 (AnaCtrl1)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x02

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 1 1 0 0 0 0 0

Data −V20V_OK_M VDD2_OK_M VFILT_OK_M ANAOUTCTRL -

Table 19. ANALOG CONTROL REGISTER 1 PARAMETERS

Parameter Value Description Info

V20V_OK_M 0 Enable Enable to include the voltage monitor output in the SAVEB calculation. p 19

1 Disable

VDD2_OK_M 0 Enable Enable to include the voltage monitor output in the SAVEB calculation. p 19

1 Disable

VFILT_OK_M 0 Enable Enable to include the voltage monitor output in the SAVEB calculation. p 18

1 Disable

ANAOUTCTR

000 Disable Analog output is disabled

p 23

001 Enable Analog output monitors VBUS1

010 Enable Analog output monitors VFILT

011 Enable Analog output monitors V20V

100 Enable Analog output monitors VDD2

101 Enable Analog output monitors VDDA

110 Enable Analog output monitors Bus current

111 Enable Analog output monitors Temperature

Remark: Bit 0 and bit 7 are reserved.

NCN5121

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Analog Status Register

The Analog Status Register is located at address 0x03 and can be used to verify the voltage monitors, Xtal and thermal status.

Table 20. ANALOG STATUS REGISTER

Analog Status Register (AnaStat)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x03

Access R R R R R R R R

Reset 0 0 0 0 0 0 0 0

Data − V20V VDD2 VBUS VFILT XTAL TW TSD

Table 21. ANALOG STATUS REGISTER PARAMETERS

Parameter Value Value Description Info

V20V 0 nOK ‘1’ if voltage on V20V-pin is above the V20V undervoltage level p 19

1 OK

VDD2 0 nOK ‘1’ if voltage on VDD2-pin is above the VDD2 undervoltage level p 19

1 OK

VBUS 0 nOK ‘1’ if bus voltage is above the VBUS undervoltage level P 18

1 OK

VFILT 0 nOK ‘1’ if voltage on VFILT-pin is above the VFILT undervoltage level p 18

1 OK

XTAL 0 nOK ‘1’ if XTAL is up and running p 19

1 OK

TW 0No TW ‘1’ if Thermal Warning detected

p 22

1 TW

TSD 0No TSD Contains information about the previous Thermal Shutdown situation

1 TSD

Remark: Bit 7 is reserved.

Revision ID register

The Revision ID register is located at address 0x05 and can be read out to check the revision ID of the silicon and by the

firmwire of the host controller to determine the part number of the transceiver

Table 22. REVISION ID REGISTER

Revision ID Register (RevID)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x05

Access R R R R R R R R

Reset X X X 0 1 1 0 1

Data Revision Part Number

Table 23. REVISION ID REGISTER PARAMETERS

Parameter Value Value Description Info

Revision Silicon revision ID

Part Number 01101 NCN5121 Transceiver Part Number

NCN5121

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PACKAGE THERMAL CHARACTERISTICS

The NCN5121 is available in a QFN40 package. For cooling optimizations, the QFN40 has an exposed thermal pad which

has to be soldered to the PCB ground plane. The ground plane needs thermal vias to conduct the heat to the bottom layer.

Figure 58 gives an example of good heat transfer. The exposed thermal pad is soldered directly on the top ground layer (left

picture of Figure 58). It‘s advised to make the top ground layer as l a rge as possible (see arrows Figure 58). To improve the heat

transfer even more, the exposed thermal pad is connected to a bottom ground layer by using thermal vias (see right picture of

Figure 58). It‘s advised to make this bottom ground layer as large as possible and with as less as possible interruptions.

For precise thermal cooling calculations the major thermal resistances of the device are given (Table 4). The thermal media

to which the power of the devices has to be given are:

− Static environmental air (via the case)

− PCB board copper area (via the exposed pad)

The major thermal resistances of the device are the Rth from the junction to the ambient (Rthja) and the overall Rth from

the junction to exposed pad (Rthjp). In Table 4 one can find the values for the Rthja and Rthjp, simulated according to JESD−51.

The Rthja for 2S2P is simulated conform JEDEC JESD−51 as follows:

− A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used

− Board thickness is 1.46 mm (FR4 PCB material)

− The 2 signal layers: 70 mm thick copper with an area of 5500 mm2 copper and 20% conductivity

− The 2 power internal planes: 36 mm thick copper with an area of 5500 mm2 copper and 90% conductivity

The Rthja for 1S0P is simulated conform to JEDEC JESD−51 as follows:

− A 1−layer printed circuit board with only 1 layer

− Board thickness is 1.46 mm (FR4 PCB material)

− The layer has a thickness of 70 mm copper with an area of 5500 mm2 copper and 20% conductivity

Figure 58. PCB Ground Plane Layout Condition (left picture displays the top ground layer, right picture displays

the bottom ground layer)

ORDERING INFORMATION

Device Number Temperature Range Package Shipping†

NCN5121MNG −40°C to 105°CQFN−40

(Pb−Free) 50 Units / Tube

100 Tubes / Box

NCN5121MNTWG −40°C to 105°CQFN−40

(Pb−Free) 3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

NCN5121

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PACKAGE DIMENSIONS

QFN40 6x6, 0.5P

CASE 485AU

ISSUE O

SEATING

NOTE 4

0.15 C

(A3)

11 20

40X

30 L

BOTTOM VIEW

TOP VIEW

SIDE VIEW

DA B

0.15 C

ÉÉ

PIN ONE

LOCATION

0.10 C

0.08 C

A0.10 B

0.05 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30mm FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.18 0.30

D6.00 BSC

D2 3.10 3.30

E6.00 BSC

3.30E2 3.10

e0.50 BSC

L0.30 0.50

PLANE

DIMENSIONS: MILLIMETERS

0.50 PITCH

3.32

0.28

3.32

40X

0.63

40X

6.30

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

DETAIL A

OPTIONAL

CONSTRUCTIONS

ÉÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

OPTIONAL

CONSTRUCTIONS

DETAIL B

DET AIL A

0.20 MIN

L1 −−− 0.15

A0.10 BC

PACKAGE

OUTLINE

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