LT1965 Series
1
1965fa
FEATURES
APPLICATIONS
DESCRIPTION
1.1A, Low Noise,
Low Dropout Linear Regulator
The LT
®
1965 series are low noise, low dropout linear regu-
lators. The devices supply 1.1A of output current with a
310mV typical dropout voltage. Operating quiescent current
is 500μA for the adjustable version, reducing to <1μA in
shutdown. Quiescent current is well controlled; it does not
rise in dropout as with many other regulators. The LT1965
regulators have very low output noise which makes them
ideal for sensitive RF and DSP supply applications.
Output voltage ranges from 1.20V to 19.5V. The LT1965
regulators are stable with output capacitors as low as
10μF. Internal protection circuitry includes reverse battery
protection, current limiting with foldback, thermal limiting
and reverse current protection. The LT1965 series are
available in fi xed output voltages of 1.5V, 1.8V, 2.5V, 3.3V,
and as an adjustable device with a 1.20V reference voltage.
The package offerings include the 5-lead TO-220, 5-lead
DD-PAK as well as the thermally enhanced 8-lead MSOP
and low-profi le (0.75mm) 8-lead 3mm × 3mm DFN.
3.3V to 2.5V Regulator
n Output Current: 1.1A
n Dropout Voltage: 310mV
n Low Noise: 40μVRMS (10Hz to 100kHz)
n 500μA Quiescent Current (Adjustable Version)
n Wide Input Voltage Range: 1.8V to 20V
n No Protection Diodes Needed
n Controlled Quiescent Current in Dropout
n Adjustable Output from 1.20V to 19.5V
n Fixed Output Voltages: 1.5V, 1.8V, 2.5V, 3.3V
n < 1μA Quiescent Current in Shutdown
n Stable with 10μF Output Capacitor
n Stable with Ceramic, Tantalum or Aluminum
Electrolytic Capacitors
n Reverse Battery Protection
n No Reverse Current
n Current Limit with Foldback Protection
n Thermal Limiting
n 5-Lead TO-220, DD-PAK, Thermally Enhanced 8-Lead
MSOP and 8-Lead 3mm × 3mm DFN Packages
n Logic Power Supplies
n Post Regulator for Switching Supplies
n Low Noise Instrumentation
Dropout Voltage
TYPICAL APPLICATION
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
OUTPUT CURRENT (A)
0
0
DROPOUT VOLTAGE (mV)
100
200
300
0.2 0.4 0.6 0.8 1
400
50
150
250
350
1.2
1965 TA01b
TJ = 25°C
IN
SHDN
10μF*
*CERAMIC, TANTALUM OR
ALUMINUM ELECTROLYTIC
1965 TA01
OUT
VIN > 3V
TO 20V
SENSE
GND
LT1965-2.5
2.5V
1.1A
10μF*
++
LT1965 Series
2
1965fa
ABSOLUTE MAXIMUM RATINGS
IN Pin Voltage .........................................................±22V
OUT Pin Voltage ......................................................±22V
Input to Output Differential Voltage (Note 2) ......... ±22V
SENSE Pin Voltage ..................................................±22V
ADJ Pin Voltage ........................................................±9V
SHDN Pin Voltage ...................................................±22V
(Note 1)
TOP VIEW
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
5
6
7
8
9
4
3
2
1OUT
OUT
SENSE/ADJ*
GND
IN
IN
SHDN
GND
TJMAX = 125°C, θJA = 65°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
*PIN 3 = SENSE FOR LT1965-1.5/LT1965-1.8/LT1965-2.5/LT1965-3.3
*PIN 3 = ADJ FOR LT1965
1
2
3
4
OUT
OUT
SENSE/ADJ*
GND
8
7
6
5
9
IN
IN
SHDN
GND
TOP VIEW
MS8E PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 60°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
*PIN 3 = SENSE FOR LT1965-1.5/LT1965-1.8/LT1965-2.5/LT1965-3.3
*PIN 3 = ADJ FOR LT1965
Q PACKAGE
5-LEAD PLASTIC DD-PAK
FRONT VIEW
SENSE/ADJ*
OUT
GND
IN
SHDN
TAB IS
GND
5
4
3
2
1
TJMAX = 125°C, θJA = 30°C/W, θJC = 3°C/W
*PIN 5 = SENSE FOR LT1965-1.5/LT1965-1.8/LT1965-2.5/LT1965-3.3
*PIN 5 = ADJ FOR LT1965
T PACKAGE
5-LEAD PLASTIC TO-220
SENSE/ADJ*
OUT
GND
IN
SHDN
FRONT VIEW
5
4
3
2
1
TAB IS
GND
TJMAX = 125°C, θJA = 50°C/W, θJC = 3°C/W
*PIN 5 = SENSE FOR LT1965-1.5/LT1965-1.8/LT1965-2.5/LT1965-3.3
*PIN 5 = ADJ FOR LT1965
Output Short-Circuit Duration .......................... Indefi nite
Operating Junction Temperature Range (E, I Grade)
(Notes 2, 13) ......................................–40°C to 125°C
Storage Temperature Range ...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
(Only for MSOP, TO-220, DD-PAK Packages) .... 300°C
LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1965EDD#PBF LT1965EDD#TRPBF LCXW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT1965IDD#PBF LT1965IDD#TRPBF LCXW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT1965EDD-1.5#PBF LT1965EDD-1.5#TRPBF LDKW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT1965IDD-1.5#PBF LT1965IDD-1.5#TRPBF LDKW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT1965EDD-1.8#PBF LT1965EDD-1.8#TRPBF LDKY 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT1965IDD-1.8#PBF LT1965IDD-1.8#TRPBF LDKY 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT1965EDD-2.5#PBF LT1965EDD-2.5#TRPBF LDMB 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT1965IDD-2.5#PBF LT1965IDD-2.5#TRPBF LDMB 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT1965EDD-3.3#PBF LT1965EDD-3.3#TRPBF LDMD 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT1965IDD-3.3#PBF LT1965IDD-3.3#TRPBF LDMD 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
PIN CONFIGURATION
ORDER INFORMATION
LT1965 Series
3
1965fa
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1965EMS8E#PBF LT1965EMS8E#TRPBF LTCXX 8-Lead Plastic MSOP –40°C to 125°C
LT1965IMS8E#PBF LT1965IMS8E#TRPBF LTCXX 8-Lead Plastic MSOP –40°C to 125°C
LT1965EMS8E-1.5#PBF LT1965EMS8E-1.5#TRPBF LTDKX 8-Lead Plastic MSOP –40°C to 125°C
LT1965IMS8E-1.5#PBF LT1965IMS8E-1.5#TRPBF LTDKX 8-Lead Plastic MSOP –40°C to 125°C
LT1965EMS8E-1.8#PBF LT1965EMS8E-1.8#TRPBF LTDKZ 8-Lead Plastic MSOP –40°C to 125°C
LT1965IMS8E-1.8#PBF LT1965IMS8E-1.8#TRPBF LTDKZ 8-Lead Plastic MSOP –40°C to 125°C
LT1965EMS8E-2.5#PBF LT1965EMS8E-2.5#TRPBF LTDMC 8-Lead Plastic MSOP –40°C to 125°C
LT1965IMS8E-2.5#PBF LT1965IMS8E-2.5#TRPBF LTDMC 8-Lead Plastic MSOP –40°C to 125°C
LT1965EMS8E-3.3#PBF LT1965EMS8E-3.3#TRPBF LTDMF 8-Lead Plastic MSOP –40°C to 125°C
LT1965IMS8E-3.3#PBF LT1965IMS8E-3.3#TRPBF LTDMF 8-Lead Plastic MSOP –40°C to 125°C
LT1965EQ#PBF LT1965EQ#TRPBF LT1965Q 5-Lead Plastic DD-PAK –40°C to 125°C
LT1965IQ#PBF LT1965IQ#TRPBF LT1965Q 5-Lead Plastic DD-PAK –40°C to 125°C
LT1965EQ-1.5#PBF LT1965EQ-1.5#TRPBF LT1965Q-1.5 5-Lead Plastic DD-PAK –40°C to 125°C
LT1965IQ-1.5#PBF LT1965IQ-1.5#TRPBF LT1965Q-1.5 5-Lead Plastic DD-PAK –40°C to 125°C
LT1965EQ-1.8#PBF LT1965EQ-1.8#TRPBF LT1965Q-1.8 5-Lead Plastic DD-PAK –40°C to 125°C
LT1965IQ-1.8#PBF LT1965IQ-1.8#TRPBF LT1965Q-1.8 5-Lead Plastic DD-PAK –40°C to 125°C
LT1965EQ-2.5#PBF LT1965EQ-2.5#TRPBF LT1965Q-2.5 5-Lead Plastic DD-PAK –40°C to 125°C
LT1965IQ-2.5#PBF LT1965IQ-2.5#TRPBF LT1965Q-2.5 5-Lead Plastic DD-PAK –40°C to 125°C
LT1965EQ-3.3#PBF LT1965EQ-3.3#TRPBF LT1965Q-3.3 5-Lead Plastic DD-PAK –40°C to 125°C
LT1965IQ-3.3#PBF LT1965IQ-3.3#TRPBF LT1965Q-3.3 5-Lead Plastic DD-PAK –40°C to 125°C
LT1965ET#PBF LT1965ET#TRPBF LT1965T 5-Lead Plastic TO-220 –40°C to 125°C
LT1965IT#PBF LT1965IT#TRPBF LT1965T 5-Lead Plastic TO-220 –40°C to 125°C
LT1965ET-1.5#PBF LT1965ET-1.5#TRPBF LT1965T-1.5 5-Lead Plastic TO-220 –40°C to 125°C
LT1965IT-1.5#PBF LT1965IT-1.5#TRPBF LT1965T-1.5 5-Lead Plastic TO-220 –40°C to 125°C
LT1965ET-1.8#PBF LT1965ET-1.8#TRPBF LT1965T-1.8 5-Lead Plastic TO-220 –40°C to 125°C
LT1965IT-1.8#PBF LT1965IT-1.8#TRPBF LT1965T-1.8 5-Lead Plastic TO-220 –40°C to 125°C
LT1965ET-2.5#PBF LT1965ET-2.5#TRPBF LT1965T-2.5 5-Lead Plastic TO-220 –40°C to 125°C
LT1965IT-2.5#PBF LT1965IT-2.5#TRPBF LT1965T-2.5 5-Lead Plastic TO-220 –40°C to 125°C
LT1965ET-3.3#PBF LT1965ET-3.3#TRPBF LT1965T-3.3 5-Lead Plastic TO-220 –40°C to 125°C
LT1965IT-3.3#PBF LT1965IT-3.3#TRPBF LT1965T-3.3 5-Lead Plastic TO-220 –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *Temperature grades are identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LT1965 Series
4
1965fa
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage (Notes 4, 12) ILOAD = 0.5A
ILOAD = 1.1A l
1.65
1.8 2.3
V
V
Regulated Output Voltage (Note 5) LT1965-1.5, VIN = 2.1V, ILOAD = 1mA
LT1965-1.5, 2.5 < VIN < 20V, 1mA < ILOAD < 1.1A l
1.477
1.455
1.5
1.5
1.523
1.545
V
V
LT1965-1.8, VIN = 2.3V, ILOAD = 1mA
LT1965-1.8, 2.8 < VIN < 20V, 1mA < ILOAD < 1.1A l
1.773
1.746
1.8
1.8
1.827
1.854
V
V
LT1965-2.5, VIN = 3V, ILOAD = 1mA
LT1965-2.5, 3.5 < VIN < 20V, 1mA < ILOAD < 1.1A l
2.462
2.425
2.5
2.5
2.538
2.575
V
V
LT1965-3.3, VIN = 3.8V, ILOAD = 1mA
LT1965-3.3, 4.3 < VIN < 20V, 1mA < ILOAD < 1.1A l
3.25
3.201
3.3
3.3
3.35
3.399
V
V
ADJ Pin Voltage (Notes 4, 5) VIN = 2.1V, ILOAD = 1mA
2.3V < VIN < 20V, 1mA < ILOAD < 1.1A l
1.182
1.164
1.2
1.2
1.218
1.236
V
V
Line Regulation LT1965-1.5, ΔVIN = 2.1V to 20V, ILOAD = 1mA
LT1965-1.8, ΔVIN = 2.3V to 20V, ILOAD = 1mA
LT1965-2.5, ΔVIN = 3V to 20V, ILOAD = 1mA
LT1965-3.3, ΔVIN = 3.8V to 20V, ILOAD = 1mA
LT1965, ΔVIN = 2.1V to 20V, ILOAD = 1mA (Note 4)
l
l
l
l
l
3.5
4
4.5
5.5
3
9
10
11.5
16
8
mV
mV
mV
mV
mV
Load Regulation LT1965-1.5, VIN = 2.5V, ΔILOAD = 1mA to 1.1A
LT1965-1.5, VIN = 2.5V, ΔILOAD = 1mA to 1.1A l
5.25 10
20
mV
mV
LT1965-1.8, VIN = 2.8V, ΔILOAD = 1mA to 1.1A
LT1965-1.8, VIN = 2.8V, ΔILOAD = 1mA to 1.1A l
6.25 12
24
mV
mV
LT1965-2.5, VIN = 3.5V, ΔILOAD = 1mA to 1.1A
LT1965-2.5, VIN = 3.5V, ΔILOAD = 1mA to 1.1A l
8.75 16.5
33
mV
mV
LT1965-3.3, VIN = 4.3V, ΔILOAD = 1mA to 1.1A
LT1965-3.3, VIN = 4.3V, ΔILOAD = 1mA to 1.1A l
11.5 22
44
mV
mV
LT1965, VIN = 2.3V, ΔILOAD = 1mA to 1.1A (Note 4)
LT1965, VIN = 2.3V, ΔILOAD = 1mA to 1.1A (Note 4) l
4.25 8
16
mV
mV
Dropout Voltage
VIN = VOUT(NOMINAL)
(Notes 6, 7, 12)
ILOAD = 1mA
ILOAD = 1mA l
0.055 0.08
0.14
V
V
ILOAD = 100mA
ILOAD = 100mA l
0.12 0.175
0.28
V
V
ILOAD = 500mA
ILOAD = 500mA l
0.21 0.25
0.36
V
V
ILOAD = 1.1A
ILOAD = 1.1A l
0.31 0.36
0.49
V
V
GND Pin Current
VIN = VOUT(NOMINAL) + 1V
(Notes 6, 8)
ILOAD = 0mA
ILOAD = 1mA
ILOAD = 100mA
ILOAD = 500mA
ILOAD = 1.1A
l
l
l
l
l
0.5
0.6
2.2
8.2
21
1.1
1.5
5.5
20
40
mA
mA
mA
mA
mA
Output Voltage Noise COUT = 10μF, ILOAD = 1.1A, BW = 10Hz to 100kHz 40 μVRMS
ADJ Pin Bias Current (Notes 4, 9) 1.3 4.5 μA
Shutdown Threshold VOUT = Off to On
VOUT = On to Off
l
l0.2
0.85
0.45
2V
V
SHDN Pin Current (Note 10) VSHDN = 0V
VSHDN = 20V
0.01
5.5
1
10
μA
μA
Quiescent Current in Shutdown VIN = 6V, VSHDN = 0V 0.01 1 μA
Ripple Rejection VIN – VOUT = 1.5V (AVG), VRIPPLE = 0.5VP-P,
fRIPPLE = 120Hz, ILOAD = 0.75A
57 75 dB
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 3)
LT1965 Series
5
1965fa
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Absolute maximum input to output differential voltage is not
achievable with all combinations of rated IN pin and OUT pin voltages.
With the IN pin at 22V, the OUT pin may not be pulled below 0V. The total
measured voltage from IN to OUT must not exceed ±22V.
Note 3: The LT1965 regulators are tested and specifi ed under pulse load
conditions such that TJ ≅ TA. The LT1965E regulators are 100% tested
at TA = 25°C. Performance at –40°C and 125°C is assured by design,
characterization, and correlation with statistical process controls. The
LT1965I regulators are guaranteed over the full –40°C to 125°C operating
junction temperature range.
Note 4: The LT1965 adjustable version is tested and specifi ed for these
conditions with the ADJ connected to the OUT pin.
Note 5: Maximum junction temperature limits operating conditions. The
regulated output voltage specifi cation does not apply for all possible
combinations of input voltage and output current. Limit the output current
range if operating at the maximum input voltage. Limit the input-to-output
voltage differential if operating at the maximum output current.
Note 6: To satisfy minimum input voltage requirements, the LT1965
adjustable version is tested and specifi ed for these conditions with an
external resistor divider (bottom 4.02k, top 4.32k) for an output voltage of
2.5V. The external resistor divider adds 300μA of output DC load current.
This external current is not factored into GND pin current.
Note 7: Dropout voltage is the minimum input-to-output voltage
differential needed to maintain regulation at a specifi ed output current. In
dropout, the output voltage equals: (VIN – VDROPOUT)
Note 8: GND pin current is tested with VIN = VOUT(NOMINAL) + 1V and a
current source load. GND pin current increases slightly in dropout. For
the fi xed output versions, an internal resistor divider will typically add
100μA to the GND pin current. See GND pin current curves in the Typical
Performance Characteristics section.
Note 9: ADJ pin bias current fl ows into the ADJ pin.
Note 10: SHDN pin current fl ows into the SHDN pin.
Note 11: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current fl ows into the OUT
pin and out of the GND pin.
Note 12: For the LT1965, LT1965-1.5 and LT1965-1.8, the minimum
input voltage specifi cation limits the dropout voltage under some output
voltage/load conditions.
Note 13: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature is active.
Continuous operation above the specifi ed maximum operating junction
temperature may impair device reliability.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Limit VIN = 7V, VOUT = 0
VIN = VOUT(NOMINAL) + 1V, ΔVOUT = -0.1V (Note 6) l1.2
2.4 A
A
Input Reverse Leakage Current VIN = –20V, VOUT = 0 1 mA
Reverse Output Current (Note 11) LT1965-1.5, VOUT = 1.5V, VIN = 0
LT1965-1.8, VOUT = 1.8V, VIN = 0
LT1965-2.5, VOUT = 2.5V, VIN = 0
LT1965-3.3, VOUT = 3.3V, VIN = 0
LT1965 (Note 4), VOUT = 1.2V, VIN = 0
275
275
275
275
175
525
525
525
525
400
μA
μA
μA
μA
μA
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 3)
LT1965 Series
6
1965fa
LT1965-2.5 Output Voltage LT1965-3.3 Output Voltage LT1965 ADJ Pin Voltage
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Dropout Voltage Guaranteed Dropout Voltage Dropout Voltage
Quiescent Current LT1965-1.5 Output Voltage LT1965-1.8 Output Voltage
OUTPUT CURRENT (A)
0
0
DROPOUT VOLTAGE (mV)
100
200
300
0.2 0.4 0.6 0.8 1
400
500
50
150
250
350
450
1.2
1965 G01
TJ = 125°C
TJ = 25°C
OUTPUT CURRENT (A)
0
0
GUARANTEED DROPOUT VOLTAGE (mV)
100
200
300
0.2 0.4 0.6 0.8 1
400
500
50
150
250
350
450
1.2
1965 G02
= TEST POINTS
TJ = 125°C
TJ = 25°C
0
DROPOUT VOLTAGE (mV)
100
200
300
400
500
50
150
250
350
450
1965 G03
IL = 1.1A
IL = 500mA
IL = 100mA
IL = 1mA
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
0
QUIESCENT CURRENT (mA)
0.2
0.4
0.6
0.8
1.0
0.1
0.3
0.5
0.7
0.9
1965 G04
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
VIN = 6V
RL = ∞, IL = 0
VSHDN = VIN
LT1965-1.5/-1.8/-2.5/-3.3
LT1965
1.182
ADJ PIN VOLTAGE (V)
1.190
1.198
1.206
1.218
1.186
1.194
1.202
1.210
1.214
1965 G09
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
IL = 1mA
1.477
OUTPUT VOLTAGE (V)
1.487
1.497
1.507
1.522
1.482
1.492
1.502
1.512
1.517
1965 G05
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
IL = 1mA
1.773
OUTPUT VOLTAGE (V)
1.785
1.797
1.809
1.827
1.779
1.791
1.803
1.815
1.821
1965 G06
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
IL = 1mA
2.460
OUTPUT VOLTAGE (V)
2.484
2.500
2.516
2.540
2.476
2.468
2.492
2.508
2.524
2.532
1965 G07
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
IL = 1mA
3.250
OUTPUT VOLTAGE (V)
3.280
3.300
3.320
3.350
3.270
3.260
3.290
3.310
3.330
3.340
1965 G08
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
IL = 1mA
LT1965 Series
7
1965fa
TYPICAL PERFORMANCE CHARACTERISTICS
LT1965-1.5 Quiescent Current LT1965-1.8 Quiescent Current LT1965-2.5 Quiescent Current
LT1965-3.3 Quiescent Current LT1965 Quiescent Current
LT1965-1.5 GND Pin Current
(Light Load)
LT1965-1.5 GND Pin Current
(Heavy Load)
LT1965-1.8 GND Pin Current
(Light Load)
LT1965-1.8 GND Pin Current
(Heavy Load)
0
QUIESCENT CURRENT (mA)
0.2
0.4
0.6
0.8
1.0
0.1
0.3
0.5
0.7
0.9
1965 G14
INPUT VOLTAGE (V)
0164 8 12 20142 6 10 18
TJ = 25°C
RL = 4.02k
VSHDN = VIN
VSHDN = 0V
0
QUIESCENT CURRENT (mA)
1
3
5
2
4
1965 G10
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
RL = ∞
VSHDN = VIN
VSHDN = 0V 0
QUIESCENT CURRENT (mA)
1
3
5
2
4
1965 G11
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
RL = ∞
VSHDN = VIN
VSHDN = 0V 0
QUIESCENT CURRENT (mA)
2
6
10
4
8
1965 G12
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
RL = ∞
VSHDN = VIN
VSHDN = 0V
0
QUIESCENT CURRENT (mA)
2
6
10
4
8
1965 G13
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
RL = ∞
VSHDN = VIN
VSHDN = 0V
0
GND PIN CURRENT (mA)
5
15
25
10
20
1965 G16
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 1.5V
RL= 3Ω, IL= 500mA*
RL= 15Ω, IL= 100mA*
RL= 1.363Ω, IL= 1.1A*
0
GND PIN CURRENT (mA)
1
3
5
2
4
1965 G15
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 1.5V
RL= 30Ω, IL= 50mA*
RL= 150Ω, IL= 10mA*
RL= 1.5k, IL= 1mA*
0
GND PIN CURRENT (mA)
1
3
5
2
4
1965 G17
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 1.8V
RL= 36Ω, IL= 50mA*
RL= 180Ω, IL= 10mA*
RL= 1.8k, IL= 1mA*
0
GND PIN CURRENT (mA)
5
15
25
10
20
1965 G18
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 1.8V
RL= 3.6Ω, IL= 500mA*
RL= 18Ω, IL= 100mA*
RL= 1.636Ω, IL= 1.1A*
LT1965 Series
8
1965fa
TYPICAL PERFORMANCE CHARACTERISTICS
LT1965-2.5 GND Pin Current
(Light Load)
LT1965-2.5 GND Pin Current
(Heavy Load)
LT1965-3.3 GND Pin Current
(Light Load)
LT1965-3.3 GND Pin Current
(Heavy Load)
LT1965 GND Pin Current
(Light Load)
LT1965 GND Pin Current
(Heavy Load)
GND Pin Current vs ILOAD SHDN Pin Threshold
0
GND PIN CURRENT (mA)
0.4
0.8
1.2
1.6
2.0
0.2
0.6
1.0
1.4
1.8
1965 G23
INPUT VOLTAGE (V)
08246 107135 9
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 1.2V RL = 24Ω, IL = 50mA*
RL = 120Ω, IL = 10mA*
RL = 1.2k, IL = 1mA*
0
GND PIN CURRENT (mA)
5
10
15
20
25
1965 G24
INPUT VOLTAGE (V)
08246 107135 9
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 1.2V
RL = 1.091Ω, IL = 1.1A*
RL = 2.4Ω, IL = 500mA*
RL = 12Ω, IL = 100mA*
LOAD CURRENT (A)
0
0
GND PIN CURRENT (mA)
5.00
10.0
15.0
0.2 0.4 0.6 0.8 1.0
20.0
25.0
2.50
7.50
12.5
17.5
22.5
1.2
1965 G09
VIN = VOUT(NOMINAL) + 1V
0
SHDN PIN THRESHOLD (V)
0.2
0.4
0.6
0.8
1.0
0.1
0.3
0.5
0.7
0.9
1965 G26
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
OFF TO ON
ON TO OFF
0
GND PIN CURRENT (mA)
2
4
8
12
6
10
1965 G19
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 2.5V
RL= 250Ω, IL= 10mA*
RL= 50Ω, IL= 50mA*
RL= 2.5k, IL= 1mA*
0
GND PIN CURRENT (mA)
5
15
25
10
20
1965 G20
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 2.5V
RL= 5Ω, IL= 500mA*
RL= 25Ω, IL= 100mA*
RL= 2.272Ω, IL= 1.1A*
0
GND PIN CURRENT (mA)
2
4
8
12
6
10
1965 G21
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 3.3V
RL= 330Ω, IL= 10mA*
RL= 66Ω, IL= 50mA*
RL= 3.3k, IL= 1mA*
0
GND PIN CURRENT (mA)
5
15
25
10
20
1965 G22
INPUT VOLTAGE (V)
012345678910
TJ = 25°C
VSHDN = VIN
*FOR VOUT = 3.3V
RL= 6.6Ω, IL= 500mA*
RL= 33Ω, IL= 100mA*
RL= 3Ω, IL= 1.1A*
LT1965 Series
9
1965fa
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN Pin Input Current ADJ Pin Bias Current
Current Limit vs VIN – VOUT Current Limit vs Temperature Reverse Output Current
Reverse Output Current Ripple Rejection vs Frequency
SHDN Pin Input Current
SHDN PIN VOLTAGE (V)
0
SHDN PIN INPUT CURRENT (μA)
2
4
6
1
3
5
4 8 12 16 20
20 6 10 14 18
1965 G11
5.0
SHDN PIN INPUT CURRENT (μA)
5.2
5.4
5.6
5.8
6.0
5.1
5.3
5.5
5.7
5.9
1965 G12
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
VSHDN = 20V
0
ADJ PIN BIAS CURRENT (μA)
1.0
2.0
3.0
4.0
4.5
0.5
1.5
2.5
3.5
1965 G13
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
0.0
CURRENT LIMIT (A)
0.5
1.5
2.5
1.0
2.0
1965 G30
INPUT/OUTPUT DIFFERENTIAL (V)
02468101214161820
ΔVOUT = 100mV
TJ= –50°C
TJ= 125°C TJ= 25°C
0
CURRENT LIMIT (A)
1.0
2.0
3.0
0.5
1.5
2.5
1965 G15
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
VIN = 7V
VOUT = 0V
0
REVERSE OUTPUT CURRENT (mA)
2
4
6
1
3
5
1965 G32
OUTPUT VOLTAGE (V)
01 432 56789
LT1965
LT1965-1.5
LT1965-1.8
LT1965-3.3
TJ = 25°C
VIN = 0V
VOUT = VADJ (LT1965)
VOUT = VSENSE
(LT1965-1.5/-1.8/-2.5/-3.3)
CURRENT FLOWS INTO
OUTPUT PIN
LT1965-2.5
0.00
REVERSE OUTPUT CURRENT (mA)
0.10
0.45
0.40
0.35
0.30
0.25
0.20
0.50
0.05
0.15
1965 G33
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
LT1965
VIN = 0V
VOUT = 1.2V (LT1965)
VOUT = 1.5V (LT1965-1.5)
VOUT = 1.8V (LT1965-1.8)
VOUT = 2.5V (LT1965-2.5)
VOUT = 3.3V (LT1965-3.3)
LT1965-1.5/-1.8/-2.5/-3.3
FREQUENCY (Hz)
20
RIPPLE REJECTION (dB)
30
50
60
80
90
10 1k 10k 1M
10
100 100k
70
40
0
1965 G34
IL = 0.75A
COUT = 10μF CERAMIC
VIN = VOUT(NOMINAL)
+ 1V + 50mVRMS RIPPLE
LT1965 Series
10
1965fa
TYPICAL PERFORMANCE CHARACTERISTICS
Load Regulation
Output Noise Spectral Density
RMS Output Noise vs Load
Current (10Hz to 100kHz)
LT1965-1.8 10Hz to 100kHz
Output Noise
LT1965-3.3 Transient Response
LT1965-2.5 SHDN Transient
Response
Ripple Rejection vs Temperature LT1965 Minimum Input Voltage
60
RIPPLE REJECTION (dB)
80
100
70
90
1965 G35
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
IL = 0.75A
VIN = VOUT(NOMINAL) + 1V + 0.5P-P
RIPPLE AT f = 120Hz 0
MINIMUM INPUT VOLTAGE (V)
0.5
1.0
1.5
2.0
2.5
1965 G36
TEMPERATURE (°C)
–50 0 50 100 125–25 25 75
IL = 1.1A
IL = 500mA IL = 100mA
–30
–25
LOAD REGULATION (mV)
–20
–15
–10
–5
0
1965 G37
TEMPERATURE (°C)
–50 0 50 100 125–25 25 75
LT1965
LT1965-2.5
VIN = VOUT(NOMINAL) + 1V
(LT1965-1.5/-1.8/-2.5/-3.3)
VIN = 2.3V (LT1965)
ΔIL = 1mA TO 1.1A
LT1965-3.3
LT1965-1.8
LT1965-1.5
0.01
0.10
1.00
FREQUENCY (Hz)
10
OUTPUT NOISE SPECTRAL DENSITY (μV Hz)
100 1k 10k 100k
1965 G38
LT1965-3.3
LT1965
LT1965-1.5
LT1965-1.8
LT1965-2.5
COUT = 10μF
IL = 1.1A
LOAD CURRENT (A)
20
OUTPUT NOISE VOLTAGE (μVRMS)
30
50
70
80
0.0001 0.01 0.1 10
10
0.001 1
60
40
0
1965 G39
LT1965-2.5
LT1965-3.3
LT1965-1.8
LT1965
COUT = 10μF
IL = 1.1A
LT1965-1.5 400μs/DIV
VOUT
100μV/DIV
1965 G40
0
0.0
–100
OUTPUT VOLTAGE
DEVIATION (mV)
LOAD CURRENT (A)
–50
0
50
100
0.5
1.0
1.5
10 20 30 40 50 60 70 80
1965 G41
TIME (μs)
VIN = 4.3V
CIN = 10μF CERAMIC
COUT = 10μF CERAMIC
VOUT = 3.3V
TIME (μs)
0
SHDN AND OUTPUT VOLTAGE (V)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0 8020 40 60 1007010 30 50 90
1965 G42
OUTPUT
SHDN
VIN = 3.3V
COUT = 10μF CERAMIC
RL = 2.5k, IL = 1mA FOR VOUT = 2.5V
LT1965 Series
11
1965fa
PIN FUNCTIONS
OUT (Pins 1, 2 / 1, 2 / 4 / 4): Output. This pin supplies
power to the load. Use a minimum output capacitor of
10μF to prevent oscillations. Large load transient applica-
tions require larger output capacitors to limit peak volt-
age transients. See the Applications Information section
for more information on output capacitance and reverse
output characteristics.
SENSE (Pin 3 / 3 / 5 / 5): Sense. For fi xed voltage ver-
sions of the LT1965 (LT1965-1.5/LT1965-1.8/ LT1965-2.5/
LT1965-3.3), the SENSE pin is the input to the error ampli-
fi er. Optimum regulation is obtained when the SENSE pin
is connected to the OUT pin of the regulator. In critical ap-
plications, small voltage drops are caused by the resistance
(RP) of PCB traces between the regulator and the load.
These drops may be eliminated by connecting the SENSE
pin to the output at the load as shown in Figure 1 (Kelvin
Sense Connection). Note that the voltage drop across
the external PCB traces will add to the dropout voltage
of the regulator. The SENSE pin bias current is 100μA at
the nominal rated output voltage. The SENSE pin can be
pulled below ground (as in a dual supply system where
the regulator load is returned to a negative supply) while
still allowing the device to start and operate.
ADJ (Pin 3 / 3 / 5 / 5): Adjust. This pin is the input to the
error amplifi er. It has a typical bias current of 1.3μA that
fl ows into the pin. The ADJ pin voltage is 1.20V referenced
to ground.
GND (Pins 4, 5 / 4, 5 / 3 / 3): Ground. For the adjustable
LT1965, connect the bottom of the resistor divider, setting
output voltage, directly to GND for optimum regulation.
SHDN (Pin 6 / 6 / 1 / 1): Shutdown. Pulling the SHDN
pin low puts the LT1965 into a low power state and turns
the output off. Drive the SHDN pin with either logic or an
open collector/drain with a pull-up resistor. The resistor
supplies the pull-up current to the open collector/drain
logic, normally several microamperes and the SHDN pin
current, typically less than 5.5μA. If unused, connect the
SHDN pin to VIN. The SHDN pin cannot be driven below
GND unless it is tied to the IN pin. If the SHDN pin is
driven below GND while IN is powered, the output will
turn on. SHDN pin logic cannot be referenced to a nega-
tive supply rail.
IN (Pins 7, 8 / 7, 8 / 2 / 2): Input. This pin supplies power
to the device. The LT1965 requires a bypass capacitor at IN
if located more than six inches from the main input fi lter
capacitor. Include a bypass capacitor in battery-powered
circuits as a battery’s output impedance generally rises with
frequency. A bypass capacitor in the range of 1μF to 10μF
suffi ces. The LT1965’s design withstands reverse voltages
on the IN pin with respect to ground and the OUT pin. In
the case of a reversed input, which occurs if a battery is
plugged in backwards, the LT1965 behaves as if a diode
is in series with its input. No reverse current fl ows into
the LT1965 and no reverse voltage appears at the load.
The device protects itself and the load.
Exposed Pad (Pin 9 / 9, DFN and MSOP Packages Only):
Ground. Tie this pin directly to Pins 4 and 5 and the PCB
ground. This pin provides enhanced thermal performance
with its connection to the PCB ground. See the Applica-
tions Information section for thermal considerations and
calculating junction temperature.
(DFN/MSOP/DD-PAK/TO-220)
Figure 1. Kelvin Sense Connection
IN
1965 F01
RP
RP
OUT
VIN
SENSESHDN
GND
LT1965
+ + LOAD
LT1965 Series
12
1965fa
APPLICATIONS INFORMATION
The LT1965 series are 1.1A low dropout regulators with
shutdown. The devices are capable of supplying 1.1A at
a typical dropout voltage of 310mV. The low operating
quiescent current (500μA for the adjustable version, 600μA
for the fi xed voltage versions) drops to less than 1μA in
shutdown. In addition to the low quiescent current, the
LT1965 regulators incorporate several protection features
that makes them ideal for use in battery-powered systems.
The devices protect themselves against both reverse input
and reverse output voltages. In battery backup applications,
if a backup battery holds up the output when the input is
pulled to ground, the LT1965 performs like it has a diode
in series with its output, preventing reverse current fl ow.
Also, in dual supply applications where the regulator load
is returned to a negative supply, the output can be pulled
below ground by as much as 20V. The LT1965 still starts
and operates normally in this situation.
Adjustable Operation
The LT1965 adjustable version has an output voltage range
of 1.20V to 19.5V. Figure 2 illustrates that the ratio of two
external resistors sets the output voltage. The device ser-
vos the output to maintain the ADJ pin voltage at 1.20V
referenced to ground. R1’s current equals 1.20V/R1. R2’s
current equals R1’s current plus the ADJ pin bias current.
The ADJ pin bias current, 1.3μA at 25°C, fl ows through
R2 into the ADJ pin. Use the formula in Figure 2 to calcu-
late output voltage. Linear Technology recommends that
R1’s value be less than 12.1k to minimize output voltage
errors due to the ADJ pin bias current. In shutdown, the
output turns off and the divider current is zero. For curves
depicting ADJ Pin Voltage vs Temperature and ADJ Pin
Bias Current vs Temperature, see the Typical Performance
Characteristics section.
The adjustable device is tested and specifi ed with the ADJ
pin tied to the OUT pin for an output voltage of 1.20V.
Specifi cations for output voltages greater than 1.20V are
proportional to the ratio of the desired output voltage to
1.20V: VOUT/1.20V. For example, load regulation for an
output current change of 1mA to 1.1A is typically –4.25mV
at VOUT = 1.20V. At VOUT = 5V, load regulation is:
5V
1.20V • –4.25mV =–17.71mV
Output Capacitance
The LT1965’s design is stable with a wide range of out-
put capacitors. The ESR of the output capacitor affects
stability, most notably with small capacitors. A minimum
output capacitor of 10μF with an ESR of 3Ω or less is
recommended to prevent oscillations. The LT1965 is a
low quiescent current device and output load transient
response is a function of output capacitance. Larger values
of output capacitance decrease the peak deviations and
provide improved transient response for larger current
changes.
Ceramic capacitors require extra consideration. Manufac-
turers make ceramic capacitors with a variety of dielectrics,
each with different behavior across temperature and applied
voltage. The most common dielectrics used are specifi ed
with EIA temperature characteristic codes of Z5U, Y5V,
X5R and X7R. The Z5U and Y5V dielectrics provide high
C-V products in a small package at low cost, but exhibit
strong voltage and temperature coeffi cients as shown in
Figures 3 and 4. When used with a 5V regulator, a 16V
10μF Y5V capacitor can exhibit an effective value as low
as 1μF to 2μF for the DC bias applied and over the operat-
ing temperature range. The X5R and X7R dielectrics yield
much more stable characteristics and are more suitable
for use as the output capacitor. The X7R type works over
a wider temperature range and has better temperature
stability whereas X5R is less expensive and is available in
higher values. Care still must be exercised when using X5R
and X7R capacitors; the X5R and X7R codes only specify
operating temperature range and maximum capacitance
change over temperature. Capacitance change due to DC
bias with X5R and X7R capacitors is better than Y5V and
Z5U capacitors, but can still be signifi cant enough to drop
Figure 2. Adjustable Operation
IN
1965 F02
R2
OUT
VIN
VOUT
ADJ
GND
LT1965
R1
+
VOUT =1.20V 1+R2
R1
+IADJ •R2
VADJ =1.20V
IADJ =1.3µA AT 25ºC
OUTPUT RANGE =1.20V TO 19.5V
LT1965 Series
13
1965fa
APPLICATIONS INFORMATION
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as component case
size increases, but expected capacitance at operating
voltages should be verifi ed.
Voltage and temperature coeffi cients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor, the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise. A ceramic capacitor produced the trace
in Figure 5 in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
increased output voltage noise.
Overload Recovery
Like many IC power regulators, the LT1965 has safe oper-
ating area protection. The safe area protection decreases
current limit as input-to-output voltage increases and keeps
the power transistor inside a safe operating region for all
values of input-to-output voltage. The protective design
provides some output current at all values of input-to-
output voltage up to the device breakdown.
When power is fi rst applied, as input voltage rises, the
output follows the input, allowing the regulator to start up
into very heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small,
allowing the regulator to supply large output currents.
With a high input voltage, a problem can occur wherein
removal of an output short will not allow the output to
Figure 3. Ceramic Capacitor DC Bias Characteristics Figure 4. Ceramic Capacitor Temperature Characteristics
Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
1965 F03
20
0
–20
–40
–60
–80
–100 04810
26 12 14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100 25 75
1965 F04
–25 0 50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
1ms/DIV
1mV/DIV
1965 F05
VOUT = 1.3V
COUT = 10μF
ILOAD = 0
LT1965 Series
14
1965fa
recover. Other regulators, such as the LT1083/LT1084/
LT1085 family, also exhibit this phenomenon, so it is not
unique to the LT1965.
The problem occurs with a heavy output load when the
input voltage is high and the output voltage is low. Com-
mon situations occur immediately after the removal of a
short-circuit or if the shutdown pin is pulled high after the
input voltage has already been turned on. The load line for
such a load may intersect the output current curve at two
points. If this happens, there are two stable output operating
points for the regulator. With this double intersection, the
input power supply may need to be cycled down to zero
and brought up again to make the output recover.
Output Voltage Noise
The LT1965 regulators are designed to provide low output
voltage noise over the 10Hz to 100kHz bandwidth while
operating at full load. Output voltage noise is approximately
80nV/√Hz over this frequency bandwidth for the LT1965
adjustable version. For higher output voltages (generated
by using a resistor divider), the output voltage noise gains
up accordingly.
Higher values of output voltage noise may be measured
if care is not exercised with regard to circuit layout and
testing. Crosstalk from nearby traces can induce unwanted
noise onto the LT1965’s output. Power supply ripple rejec-
tion must also be considered; the LT1965 regulators do
not have unlimited power supply rejection and will pass a
small portion of the input noise through to the output.
APPLICATIONS INFORMATION
Thermal Considerations
The LT1965’s maximum rated junction temperature of
125°C limits its power handling capability. Two compon-
ents comprise the power dissipated by the device:
1. Output current multiplied by the input/output voltage
differential: IOUT • (VIN – VOUT), and
2. GND pin current multiplied by the input voltage:
IGND • VIN
GND pin current is determined using the GND Pin Current
curves in the Typical Performance Characteristics section.
Power dissipation equals the sum of the two components
listed.
The LT1965 regulators have internal thermal limiting that
protect the device during overload conditions. For con-
tinuous normal conditions, do not exceed the maximum
junction temperature rating of 125°C. Carefully consider
all sources of thermal resistance from junction to ambi-
ent including other heat sources mounted in proximity to
the LT1965.
The underside of the LT1965 DFN package has exposed
metal (4mm2) from the lead frame to the die attachment.
The underside of the LT1965 MSOP package also has
exposed metal (3.7mm2). Both packages allow heat to
directly transfer from the die junction to the printed circuit
board metal to control maximum operating junction tem-
perature. The dual-in-line pin arrangement allows metal
to extend beyond the ends of the package on the topside
(component side) of a PCB. Connect this metal to GND
on the PCB. The multiple IN and OUT pins of the LT1965
also assist in spreading heat to the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
LT1965 Series
15
1965fa
APPLICATIONS INFORMATION
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 1/16" FR-4 board with one ounce
copper.
Table 1. Measured Thermal Resistance for DFN Package
Copper Area Thermal Resistance
Topside* Backside Board Area (Junction-to-Ambient)
2500mm22500mm22500mm260°C/W
1000mm22500mm22500mm262°C/W
225mm22500mm22500mm265°C/W
100mm22500mm22500mm268°C/W
50mm22500mm22500mm270°C/W
*Device is mounted on topside
Table 2. Measured Thermal Resistance for MSOP Package
Copper Area Thermal Resistance
Topside* Backside Board Area (Junction-to-Ambient)
2500mm22500mm22500mm255°C/W
1000mm22500mm22500mm257°C/W
225mm22500mm22500mm260°C/W
100mm22500mm22500mm265°C/W
50mm22500mm22500mm268°C/W
*Device is mounted on topside
Table 3. Measured Thermal Resistance for DD-PAK Package
Copper Area Thermal Resistance
Topside* Backside Board Area (Junction-to-Ambient)
2500mm22500mm22500mm225°C/W
1000mm22500mm22500mm230°C/W
125mm22500mm22500mm235°C/W
*Device is mounted on topside
Measured Thermal Resistance for TO-220 Package
Thermal Resistance (Junction-to-Case) = 3°C/W
Calculating Junction Temperature
Example: Given an output voltage of 2.5V, an input voltage
range of 3.3V ± 5%, an output current range of 0mA to
500mA and a maximum ambient temperature of 85°C,
what will the maximum junction temperature be?
The power dissipated by the device equals:
I
OUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX)
where:
I
OUT(MAX) = 500mA
V
IN(MAX) = 3.465V
I
GND at (IOUT = 500mA, VIN = 3.465V) = 8.2mA
So,
P = 500mA(3.465V – 2.5V) + 8.2mA(3.465V) = 0.511W
Using a DFN package, the thermal resistance will be in
the range of 60°C/W to 70°C/W depending on the cop-
per area. So the junction temperature rise above ambient
approximately equals:
0.511W • 65°C/W = 33.22°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction tempera-
ture rise above ambient or:
T
JMAX = 85°C + 33.22°C = 118.22°C
LT1965 Series
16
1965fa
Protection Features
The LT1965 regulators incorporate several protection
features that makes them ideal for use in battery-powered
circuits. In addition to the normal protection features
associated with monolithic regulators, such as current
limiting and thermal limiting, the devices also protect
against reverse input voltages, reverse output voltages
and reverse output-to-input voltages.
Current limit protection and thermal overload protection
protect the device against current overload conditions
at its output. For normal operation, do not exceed the
maximum rated junction temperature of 125°C.
The input of the device withstands reverse voltages of 22V.
The LT1965 limits current fl ow to less than 1mA (typically
less than 300μA) and no negative voltage appears at the
output. The device protects both itself and the load against
batteries that are plugged in backwards.
The LT1965 incurs no damage if its output is pulled be-
low ground. If the input is left open circuit or grounded,
the output can be pulled below ground by 22V. For fi xed
voltage versions, the output will act like a large resistor,
typically 5k or higher, limiting current fl ow to typically
less than 300μA. For the adjustable version, the output
acts like an open circuit and no current fl ows from the
output. However, current fl ows in (but is limited by) the
resistor divider that sets the output voltage. If the input
is powered by a voltage source, the output sources cur-
rent equal to its current limit capability and the LT1965
protects itself by thermal limiting. In this case, grounding
the SHDN pin turns off the device and stops the output
from sourcing current.
The LT1965 adjustable version incurs no damage if the
ADJ pin is pulled above or below ground by 9V. If the input
is left open circuit or grounded, the ADJ pin performs
like an open circuit when pulled below ground and like a
large resistor (typically 5k up to 3V on the ADJ pin and
then 1.5k up to 9V) in series with a diode when pulled
above ground.
In situations where the ADJ pin connects to a resistor
divider that would pull the ADJ pin above its 9V clamp volt-
age if the output is pulled high, the ADJ pin input current
must be limited to less than 5mA. For example, a resistor
divider is used to provide a regulated 1.5V output from the
1.20V reference when the output is forced to 20V. The top
resistor of the resistor divider must be chosen to limit the
current into the ADJ pin to less than 5mA when the ADJ
pin is at 9V. The 11V difference between the OUT and ADJ
pins divided by the 5mA maximum current into the ADJ
pin yields a minimum top resistor value of 2.2k.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled
to ground, pulled to some intermediate voltage, or is left
open circuit. Current fl ow back into the output follows the
curve shown in Figure 6.
If the LT1965’s IN pin is forced below the OUT pin or the
OUT pin is pulled above the IN pin, input current typically
drops to less than 2μA. This occurs if the LT1965 input is
connected to a discharged (low voltage) battery and either
a backup battery or a second regulator holds up the output.
The state of the SHDN pin has no effect on the reverse
output current if the output is pulled above the input.
Figure 6. Reverse Output Current
APPLICATIONS INFORMATION
OUTPUT VOLTAGE (V)
0
0
REVERSE OUTPUT CURRENT (mA)
1
2
3
4
5
6
214365879
1965 F06
LT1965
LT1965-1.5
LT1965-1.8
LT1965-3.3
TJ = 25°C
VIN = 0V
VOUT = VADJ (LT1965)
VOUT = VSENSE
(LT195-1.5/-1.8/-2.5/-3.3)
CURRENT FLOWS INTO
OUTPUT PIN
LT1965-2.5
LT1965 Series
17
1965fa
TYPICAL APPLICATIONS
Paralleling of Regulators for Higher Output Current
R1
0.01Ω
R2
0.01Ω
R5
10k
R4
2.2k
R7
4.02k
1%
C2
22μF
1965 TA03
VIN > 3.7V
3.3V
2.2A
8
1
3
2
4
C3
0.01μF
IN OUT
SENSE
GND
LT1965-3.3
SHDN
IN
SHDN
OUT
ADJ
GND
LT1965
SHDN
+
C1
100μF
+
–
+1/2
LT1366
R6
6.65k
1%
R3
2.2k
LT1965 Series
18
1965fa
PACKAGE DESCRIPTION
MSOP (MS8E) 0603
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR
GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE
PLANE
12
34
4.90 ± 0.152
(.193 ± .006)
8
8
1
BOTTOM VIEW OF
EXPOSED PAD OPTION
765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
1.83 ± 0.102
(.072 ± .004)
2.06 ± 0.102
(.081 ± .004)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
2.083 ± 0.102
(.082 ± .004)
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
3.00 ±0.10
(4 SIDES)
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN 1203
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50 BSC
0.675 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
MS8E Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1662)
LT1965 Series
19
1965fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
T5 (TO-220) 0801
.028 – .038
(0.711 – 0.965)
.067
(1.70) .135 – .165
(3.429 – 4.191)
.700 – .728
(17.78 – 18.491)
.045 – .055
(1.143 – 1.397)
.095 – .115
(2.413 – 2.921)