PurePath HDTM
Class G Power Supply
Ref design
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TAS5630
18V-36V
+12V
PurePath HDTM
TAS5624A
TASxxxx
Digital Audio
Processor
DIGITAL
AUDIO
INPUT
+3.3V
REG.
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TAS5624A
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TAS5624A 150-W Stereo and 300-W Mono PurePath™ HD Digital Input Class-D Power
Stage
1 Features 3 Description
The TAS5624A device is a thermally-enhanced
1• PurePath™ HD Integrated Feedback Provides: version of the class-D power amplifier based on the
– 0.025% THD at 1 W into 4 ΩTAS5614A using large MOSFETs for improved power
– > 65-dB PSRR (No Input Signal) efficiency and a novel gate-drive scheme for reduced
losses in idle and at low-output signals leading to
– > 105-dB (A-Weighted) SNR reduced heat sink size.
• Preclipping Output for Control of a Class-G Power The unique preclipping output signal can be used to
Supply control a Class-G power supply. This combined with
• Reduced Heat Sink Size Due to Use of 40-mΩthe low idle loss and high power efficiency of the
Output MOSFET With > 90% Efficiency at Full TAS5624A leads to industry leading levels of
Output Power efficiency ensuring a super green system.
• Output Power at 10% THD+N The TAS5624A uses constant voltage gain. The
– 150-W and 4-ΩBTL Stereo Configuration internally-matched gain resistors ensure a high power
– 300-W and 2-ΩPBTL Mono Configuration supply rejection ratio giving an output voltage only
dependent on the audio input voltage and free from
• Output Power at 10% THD+N any power supply artifacts.
– 125-W and 4-ΩBTL Stereo Configuration The high integration of the TAS5624A makes the
– 250-W and 2-ΩPBTL Mono Configuration amplifier easy to use; and, using TI’s reference
• Click-Free and Pop-Free Start-Up schematics and PCB layouts leads to fast design in
• Error Reporting Self-Protected Design With UVP, time. The TAS5624A is available in the space-saving,
Overtemperature, and Short-Circuit Protection surface-mount 44-pin HTSSOP package.
• EMI-Compliant When Used With Recommended Device Information(1)
System Design PART NUMBER PACKAGE BODY SIZE (NOM)
• 44-Pin HTSSOP (DDV) Package for Reduced TAS5624A HTSSOP (44) 14.00 mm × 6.10 mm
Board Size (1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
• Blu-ray™ and DVD Receivers Typical TAS5624A Application Block Diagram
• High-Power Sound Bars
• Powered Subwoofer and Active Speakers
• Mini Combo Systems
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5624A
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Table of Contents
9.2 Functional Block Diagrams ..................................... 12
1 Features.................................................................. 19.3 Feature Description................................................. 14
2 Applications ........................................................... 19.4 Device Functional Modes........................................ 18
3 Description............................................................. 110 Application and Implementation........................ 19
4 Revision History..................................................... 210.1 Application Information.......................................... 19
5 Device Comparison Table..................................... 310.2 Typical Applications .............................................. 19
6 Pin Configuration and Functions......................... 411 Power Supply Recommendations ..................... 27
7 Specifications......................................................... 611.1 Power Supplies..................................................... 27
7.1 Absolute Maximum Ratings ...................................... 611.2 Boot Strap Supply................................................. 27
7.2 ESD Ratings ............................................................ 612 Layout................................................................... 28
7.3 Recommended Operating Conditions....................... 612.1 Layout Guidelines ................................................. 28
7.4 Thermal Information.................................................. 712.2 Layout Example .................................................... 30
7.5 Electrical Characteristics........................................... 713 Device and Documentation Support................. 32
7.6 Electrical Characteristics – Audio Specification 13.1 Device Support .................................................... 32
Stereo (BTL) .............................................................. 813.2 Documentation Support ....................................... 32
7.7 Electrical Characteristics – Audio Specification 4
Channels (SE)............................................................ 813.3 Community Resources.......................................... 32
7.8 Electrical Characteristics – Audio Specification Mono 13.4 Trademarks........................................................... 32
(PBTL) ....................................................................... 913.5 Electrostatic Discharge Caution............................ 32
7.9 Typical Characteristics.............................................. 913.6 Glossary................................................................ 32
8 Parameter Measurement Information ................ 12 14 Mechanical, Packaging, and Orderable
9 Detailed Description............................................ 12 Information ........................................................... 32
9.1 Overview................................................................. 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2012) to Revision A Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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5 Device Comparison Table
FEATURES TAS5624A TAS5612A TAS5612LA TAS5614A TAS5614LA TAS5622A
Maximum Power to Single- 75 65 75 65
Ended Load
Maximum Power to Bridge 200 165 125 200 150 150
Tied Load
Maximum Power to Parallel 400 250 250 300 300 300
Bridge Tied Load
Minimum Supported Single- 2 2 2 2
Ended Load
Minimum Supported Bridge 3 3 4 3 4 3
Tied Load
Minimum Supported Parallel 1.5 2 2 2 2 2
Bridge Tied Load
Closed-Loop and Open-Loop Closed Closed Closed Closed Closed Closed
Maximum Speaker Outputs (#) 4 2 4 2 4 2
Input Type PWM PWM PWM PWM PWM PWM
Control Type Hardware Hardware Hardware Hardware Hardware Hardware
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VDD
OC_ADJ
RESET
INPUT_A
INPUT_B
C_START
DVDD
GND
GND
GND
GND
AVDD
INPUT_C
INPUT_D
FAULT
OTW
CLIP
M1
M2
M3
GVDD_CD
BST_C
GVDD_ABGVDD_AB
GND
GND
OUT_D
OUT_D
PVDD_CD
PVDD_CD
PVDD_CD
OUT_C
GND
GND
OUT_B
PVDD_AB
PVDD_AB
PVDD_AB
OUT_A
OUT_A
GND
GND
BST_B
BST_A
BST_D
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6 Pin Configuration and Functions
DDV Package
44-Pin HTSSOP
Top View
Pin Functions
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
AVDD 13 P Internal voltage regulator, analog section
BST_A 44 P Bootstrap pin, A-side
BST_B 43 P Bootstrap pin, B-side
BST_C 24 P Bootstrap pin, C-side
BST_D 23 P Bootstrap pin, D-side
C_START 7 O Start-up ramp
CLIP 18 O Clipping warning; open-drain; active-low
DVDD 8 P Internal voltage regulator, digital section
FAULT 16 O Shutdown signal, open-drain; active-low
9, 10, 11, 12, 25,
GND P Ground
26, 33, 34, 41, 42
GVDD_AB 1 P Gate-drive voltage supply; AB-side
GVDD_CD 22 P Gate-drive voltage supply; CD-side
INPUT_A 5 I PWM Input signal for half-bridge A
INPUT_B 6 I PWM Input signal for half-bridge B
INPUT_C 14 I PWM Input signal for half-bridge C
INPUT_D 15 I PWM Input signal for half-bridge D
M1 19 I Mode selection 1 (LSB)
M2 20 I Mode selection 2
M3 21 I Mode selection 3 (MSB)
(1) I = Input, O = Output, and P = Power
(2) Located on the top side of the device for convenient thermal coupling to the heat sink.
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Pin Functions (continued)
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
OC_ADJ 3 O Overcurrent threshold programming pin
OTW 17 O Overtemperature warning; open-drain; active-low
OUT_A 39, 40 O Output, half-bridge A
OUT_B 35 O Output, half-bridge B
OUT_C 32 O Output, half-bridge C
OUT_D 27, 28 O Output, half-bridge D
PowerPAD™ — P Ground, connect to grounded heat sink
PVDD_AB 36, 37, 38 P PVDD supply for half-bridge A and B
PVDD_CD 29, 30, 31 P PVDD supply for half-bridge C and D
RESET 4 I Device reset Input; active-low
VDD 2 P Input power supply
Mode Selection Pins
MODE PINS PWM Input(1) OUTPUT CONFIGURATION INPUT A INPUT B INPUT C INPUT D MODE
M3 M2 M1
0 0 0 2N + 1 2 × BTL PWMa PWMb PWMc PWMd AD Mode
0 0 1 1N + 1(2) 2 × BTL PWMa Unused PWMc Unused AD Mode
0 1 0 2N + 1 2 × BTL PWMa PWMb PWMc PWMd BD Mode
0 1 1 1N + 1(2) 1 × BTL + 2 × SE PWMa Unused PWMc PWMd AD Mode
1 0 0 2N + 1 1 × PBTL PWMa PWMb 0 0 AD Mode
1 0 0 1N + 1(2) 1 × PBTL PWMa Unused 0 1 AD Mode
1 0 0 2N + 1 1 × PBTL PWMa PWMb 1 0 BD Mode
1 0 1 1N + 1 4 × SE(3) PWMa PWMb PWMc PWMd AD Mode
(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals.
(3) The 4 × SE mode can be used as 1 × BTL + 2 × SE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD for
improved DC offset accuracy
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1)
MIN MAX UNIT
VDD to GND, GVDD_X(2) to GND –0.3 13.2 V
PVDD_X(2) to GND, OUT_X to GND, BST_X to GVDD_X(2) –0.3 50 V
BST_X to GND(3) –0.3 62.5 V
DVDD to GND –0.3 4.2 V
AVDD to GND –0.3 8.5 V
OC_ADJ, M1, M2, M3, C_START, INPUT_X to GND –0.3 4.2 V
RESET, FAULT, OTW, CLIP, to GND –0.3 4.2 V
Maximum continuous sink current (FAULT, OTW, CLIP) 9 mA
Maximum operating junction temperature, TJ0 150 °C
Lead temperature 260 260 °C
Storage temperature, Tstg –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) GVDD_X and PVDD_X represents a full-bridge gate drive or power supply. GVDD_X is GVDD_AB or GVDD_CD, PVDD_X is
PVDD_AB or PVDD_CD
(3) Maximum BST_X to GND voltage is the sum of maximum PVDD to GND and GVDD to GND voltages minus a diode drop.
7.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Electrostatic
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions MIN NOM MAX UNIT
PVDD_X Full-bridge supply DC supply voltage 12 36 38 V
Supply for logic regulators and gate-drive
GVDD_X DC supply voltage 10.8 12 13.2 V
circuitry
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
BTL 2.5 4
Output filter: L = 10 uH, 1 µF.
RLLoad impedance SE Output AD modulation, 1.5 3 Ω
switching frequency > 350 kHz.
PBTL 1.5 2
Minimum inductance at overcurrent limit,
LOUTPUT Output filter inductance including inductor tolerance, temperature 5 μH
and possible inductor saturation
FPWM PWM frame rate 352 384 500 kHz
CPVDD PVDD close decoupling capacitors 0.44 1 μF
BTL and PBTL configuration 100 nF
C_START Start-up ramp capacitor SE and 1 × BTL+ 2 × SE configuration 1 μF
ROC Overcurrent programming resistor Resistor tolerance = 5% 24 33 kΩ
ROC_LATCHED Overcurrent programming resistor Resistor tolerance = 5% 47 62 68 kΩ
TJJunction temperature 0 125 °C
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7.4 Thermal Information TAS5624A
THERMAL METRIC(1) DDV (HTSSOP) UNIT
44 PINS
RθJA Junction-to-ambient thermal resistance 1.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.6 °C/W
RθJB Junction-to-board thermal resistance 1.7 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 1.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, TC(case temperature) = 75°C, fS= 384 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as a reference
DVDD VDD = 12 V 3 3.3 3.6 V
node
Voltage regulator, only used as a reference
AVDD VDD = 12 V 7.8 V
node
Operating, 50% duty cycle 20
IVDD VDD supply current mA
Idle, reset mode 20
50% duty cycle 12
IGVDD_X Gate-supply current per full-bridge mA
Reset mode 3
50% duty cycle without load 15
IPVDD_X Full-bridge idle current RESET low 1.9 mA
VDD and GVDD_X at 0 V 0.4
OUTPUT-STAGE MOSFETs
RDS(on), LS Drain-to-source resistance, low-side (LS) 40 mΩ
TJ= 25°C, excludes metallization resistance,
GVDD = 12 V
RDS(on), HS Drain-to-source resistance, high-side (HS) 40 mΩ
I/O PROTECTION
Vuvp,GVDD Undervoltage protection limit, GVDD_X 8.5 V
Vuvp,GVDD, hyst (1) Undervoltage protection limit, GVDD_X 0.7 V
Vuvp,VDD Undervoltage protection limit, VDD 8.5 V
Vuvp,VDD, hyst(1) Undervoltage protection limit, VDD 0.7 V
Vuvp,PVDD Undervoltage protection limit, PVDD_X 8.5 V
Vuvp,PVDD,hyst(1) Undervoltage protection limit, PVDD_X 0.7 V
OTW(1) Overtemperature warning 115 125 135 °C
Temperature drop needed below OTW
OTWhyst (1) temperature for OTW to be inactive after 25 °C
OTW event.
OTE(1) Overtemperature error 145 155 165 °C
OTE-OTWdifferential(1) OTE-OTW differential 30 °C
A device reset is needed to clear FAULT
OTEHYST (1) 25 °C
after an OTE event
OLPC Overload protection counter fPWM = 384 kHz 2.6 ms
Resistor-programmable, nominal peak current in
IOC Overcurrent limit protection 15 A
1-Ωload, ROC = 24 kΩ
Resistor-programmable, nominal peak current in
IOC_LATCHED Overcurrent limit protection, latched 15 A
1-Ωload, ROC = 62 kΩ
Time from application of short condition to Hi-Z of
IOCT Overcurrent response time 150 ns
affected half-bridge
Internal pulldown resistor at output of each Connected when RESET is active to provide
IPD 3 mA
half-bridge bootstrap charge. Not used in SE mode.
(1) Specified by design.
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Electrical Characteristics (continued)
PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, TC(case temperature) = 75°C, fS= 384 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC DIGITAL SPECIFICATIONS
VIH High level input voltage 1.9 V
INPUT_X, M1, M2, M3, RESET
VIL Low level input voltage 0.8 V
LEAKAGE Input leakage current 100 μA
OTW / SHUTDOWN (FAULT)
Internal pullup resistance, OTW, CLIP,
RINT_PU 20 26 33 kΩ
FAULT to DVDD
VOH High level output voltage Internal pullup resistor 3 3.3 3.6 V
VOL Low level output voltage IO= 4 mA 200 500 mV
FANOUT Device fanout OTW, FAULT, CLIP No external pullup 30 devices
7.6 Electrical Characteristics – Audio Specification Stereo (BTL)
Audio performance is recorded as a chipset consisting of a TAS5558 8-Channel HD Compatible Audio Processor with ASRC
and PWM Output (SLES273), PWM Processor (modulation index limited to 97.7%) and a TAS5624A power stage with PCB
and system configurations in accordance with recommended guidelines.
Audio frequency = 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL= 4 Ω, fS= 384 kHz, ROC = 24 kΩ, TC= 75°C, Output Filter:
LDEM = 10 μH, CDEM = 1 µF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL= 3 Ω, 10% THD+N 200
RL= 4 Ω, 10% THD+N 150
POPower output per channel W
RL= 3 Ω, 1% THD+N 160
RL= 4 Ω, 1% THD+N 125
THD+N Total harmonic distortion + noise 1-W, 1-kHz signal 0.025%
VnOutput integrated noise A-weighted, AES17 measuring filter 180 μV
VOS Output offset voltage No signal 10 20 mV
SNR Signal-to-noise ratio(1) A-weighted, AES17 measuring filter 105 dB
DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD+N) 105 dB
Power dissipation due to idle losses
Pidle PO= 0, channels switching(2) 1 W
(IPVDD_X)
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
7.7 Electrical Characteristics – Audio Specification 4 Channels (SE)
Audio performance is recorded as a chipset consisting of a TASxxxx, PWM Processor (modulation index limited to 97.7%)
and a TAS5624A power stage with PCB and system configurations in accordance with recommended guidelines.
Audio frequency = 1 kHz, PVDD_X = 36 V, GVDD_X = 12V, RL= 4 Ω, fS= 384 kHz, R = 24 kΩ, TC= 75°C, Output Filter:
LDEM = 10 μH, CDEM = 1 µF, CDCB = 470 µF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL= 3 Ω, 10% THD+N 50
POPower output per channel W
RL= 3 Ω, 1% THD+N 42
THD+N Total harmonic distortion + noise 1-W, 1-kHz signal 0.025%
VnOutput integrated noise A-weighted, AES17 measuring filter 180 μV
SNR Signal-to-noise ratio(1) A-weighted, AES17 measuring filter 102 dB
DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD+N) 102 dB
Power dissipation due to Idle losses
Pidle PO= 0, channels switching(2) 1 W
(IPVDD_X)
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
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0.005
0.01
0.1
1
10
0.02 0.1 1 10 100 300
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
3Ω
4Ω
8Ω
TC = 75°C
G001
0
20
40
60
80
100
120
140
160
180
200
220
240
260
10 15 20 25 30 35 40
PVDD − Supply Voltage − V
PO − Output Power − W
3Ω
4Ω
8Ω
TC = 75°C
THD+N at 10%
G003
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7.8 Electrical Characteristics – Audio Specification Mono (PBTL)
Audio performance is recorded as a chipset consisting of a TASxxxx, PWM Processor (modulation index limited to 97.7%)
and a TAS5624A power stage with PCB and system configurations in accordance with recommended guidelines.
Audio frequency = 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL= 4 Ω, fS= 384 kHz, ROC = 24 kΩ, TC= 75°C, Output Filter:
LDEM = 10 μH, CDEM = 1 μF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL= 1.5 Ω, 10%, THD+N 400
RL= 2 Ω, 10% THD+N 300
RL= 4 Ω, 10% THD+N 160
POPower output per channel W
RL= 1.5 Ω, 1% THD+N 320
RL= 2 Ω, 1% THD+N 250
RL= 4 Ω, 1% THD+N 130
THD+N Total harmonic distortion + noise 1-W, 1-kHz signal 0.025%
VnOutput integrated noise A-weighted, AES17 measuring filter 180 μV
VOS Output offset voltage No signal 10 20 mV
SNR Signal-to-noise ratio(1) A-weighted, AES17 measuring filter 105 dB
DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD) 105 dB
Power dissipation due to idle losses
Pidle PO= 0, All channels switching(2) 1 W
(IPVDD_X)
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
7.9 Typical Characteristics
7.9.1 BTL Configuration
Measurement conditions are: 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL= 4 Ω, fS= 384 kHz, ROC = 24 kΩ, TC= 75°C,
Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20-Hz to 20-kHz BW (AES17 lowpass filter), unless otherwise noted.
1 kHz
Figure 1. Total Harmonic + Noise vs Output Power Figure 2. Output Power vs Supply Voltage
vs Distortion + Noise = 10%
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0
20
40
60
80
100
120
140
160
180
200
220
240
260
−10 0 10 20 30 40 50 60 70 80 90 100 110
TC − Case Temperature − °C
PO − Output Power − W
3Ω
4Ω
8ΩTHD+N at 10%
G007
−200
−190
−180
−170
−160
−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k
f − Frequency − Hz
Noise Amplitude − dB
4Ω
TC = 75°C
VREF = 22.5 V
Sample Rate = 48kHz
FFT Size = 16384
G008
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
0 100 200 300 400 500
Total Output Power − W
Efficiency − %
3Ω
4Ω
8ΩTC= 75°C
G005
0.001
0.01
0.1
1
10
20 100 1k 10k 20k
Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
1 W
10 W
100 W
TC = 75°C
G002
0
20
40
60
80
100
120
140
160
180
200
220
10 15 20 25 30 35 40
PVDD − Supply Voltage − V
PO − Output Power − W
3Ω
4Ω
8Ω
TC = 75°C
G004
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BTL Configuration (continued)
Measurement conditions are: 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL= 4 Ω, fS= 384 kHz, ROC = 24 kΩ, TC= 75°C,
Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20-Hz to 20-kHz BW (AES17 lowpass filter), unless otherwise noted.
4Ω
Figure 3. Total Harmonic Distortion + Noise Figure 4. Output Power vs Supply Voltage,
vs Frequency Distortion + Noise = 1%
Figure 5. System Efficiency vs Output Power Figure 6. System Power Loss vs Output Power
Figure 7. Output Power vs Temperature Figure 8. Noise Amplitude vs Frequency
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0.005
0.01
0.1
1
10
0.02 0.1 1 10 100 500
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
2Ω
3Ω
4Ω
TC = 75°C
G011
0
50
100
150
200
250
300
350
400
450
10 15 20 25 30 35 40
PVDD − Supply Voltage − V
PO − Output Power − W
2Ω
3Ω
4Ω
TC = 75°C
THD+N at 10%
G012
0.005
0.01
0.1
1
10
0.02 0.1 1 10 100
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
2Ω
3Ω
4Ω
TC = 75°C
G009
0
20
40
60
80
100
10 15 20 25 30 35 40
PVDD − Supply Voltage − V
PO − Output Power − W
2Ω
3Ω
4Ω
TC = 75°C
THD+N at 10%
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7.9.2 SE Configuration
Measurement conditions are: 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL= 4 Ω, fS= 384 kHz, ROC = 24 kΩ, TC= 75°C,
Output Filter: LDEM = 10 μH, CDEM = 1 µF, CDCB = 470 µF, 20-Hz to 20-kHz BW (AES17 lowpass filter), unless otherwise
noted.
Figure 9. Total Harmonic Distortion + Noise vs Output Figure 10. Output Power vs Supply Voltage
Power
7.9.3 PBTL Configuration
Measurement conditions are: 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL= 4 Ω, fS= 384 kHz, ROC = 24 kΩ, TC= 75°C,
Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20-Hz to 20-kHz BW (AES17 lowpass filter), unless otherwise noted.
Figure 11. Total Harmonic Distortion + Noise Figure 12. Output Power vs Supply Voltage
vs Output Power
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Product Folder Links: TAS5624A
2-CHANNEL
H-BRIDGE
BTL MODE
Output
H-Bridge 2
PVDD_AB, CD
GND
Hardwire
Over-
Current
Limit
GND
VDD
DVDD
AVDD
OC_ADJ
PVDD
Power Supply
Decoupling
GVDD, VDD,
& VREG
Power Supply
Decoupling
SYSTEM
Power
Supplies
PVDD
GVDD (12V)/VDD (12V)
GND
36V
12V
GND
VAC
Bootstrap
Capacitors
BST_C
BST_D
2nd Order
L-C Output
Filter for
each
H-Bridge
OUT_C
OUT_D
GVDD_AB, CD
Bootstrap
Capacitors
BST_A
BST_B
INPUT_A 2nd Order
L-C Output
Filter for
each
H-Bridge
OUT_A
OUT_B
Output
H-Bridge 1
Input
H-Bridge 1
INPUT_B
M2
M1
M3
Hardwire
Mode
Control
Input
H-Bridge 2
INPUT_C
INPUT_D
C_START
Capacitors for
External
Filtering
&
Startup/Stop
/OTW
/CLIP
System
microcontroller
/FAULT
PWM_A
PWM_B
PWM_C
PWM_D
TASxxxx
PWM Modulator
I2C
Left-
Channel
Output
Right-
Channel
Output
VALID /RESET
/AMP RESET
*NOTE1
TAS5624A
SLAS844A –MAY 2012–REVISED JANUARY 2016
www.ti.com
8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
9 Detailed Description
9.1 Overview
TAS5624A is a PWM input, audio PWM (class-D) amplifier. the output of the TAS5624A can be configured for
single-ended, bridge-tied load (BTL) or parallel BTL (PBTL) output. It requires two railes for power supply, PVDD
and 12 V (GVDD and VDD). Figure 13 shows typical connections for BTL outputs. A detailed schematic can be
viewed in TAS5624A EVM User's Guide (SLAU376).
9.2 Functional Block Diagrams
(1) Logic AND is inside or outside the microprocessor
Figure 13. Typical System Block Diagram
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Product Folder Links: TAS5624A
MODE1-3
/RESET
/FAULT
OUT_A
GND
PVDD_AB
BST_A
INPUT_A
GATE-DRIVE
PWM &
TIMING
CONTROL
-
+
PROTECTION & I/O LOGIC
STARTUP
CONTROL
POWER-UP
RESET
TEMP
SENSE
CB3C OVER-
LOAD
PROTECTION
C_START
/OTW
/CLIP
ANALOG
LOOP FILTER
UVP
AVDD
VDD
OUT_B
GND
PVDD_AB
BST_B
INPUT_B
GATE-DRIVE
PWM &
TIMING
CONTROL
-
+
ANALOG
LOOP FILTER
OUT_C
GND
PVDD_CD
BST_C
INPUT_C
GATE-DRIVE
PWM &
TIMING
CONTROL
-
+
ANALOG
LOOP FILTER
OUT_D
GND
PVDD_CD
BST_D
INPUT_D
GATE-DRIVE
PWM &
TIMING
CONTROL
-
+
ANALOG
LOOP FILTER
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
DVDD
DVDD
AVDD
DVDD
AVDD
GVDD_X
BST_X
GVDD_AB
GVDD_CD
TAS5624A
www.ti.com
SLAS844A –MAY 2012–REVISED JANUARY 2016
Functional Block Diagrams (continued)
Figure 14. Functional Block Diagram
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/RESET
OUT_X
3.3V
0V
Hi-Z
DC_RAMP
PVDD_X
0V
SPEAKER OUT_X
VI_CM
0V
50%
PVDD_X/2
0V
Ramp Start Ramp End Ramp Start Ramp End
OUT_X IS SWITCHING (MUTE) OUT_X IS SWITCHING (MUTE)
INPUT_X Hi-Z
3.3V
0V
INPUT_X IS SWITCHING (MUTE)
NOISE SHAPER OFF
INPUT_X IS SWITCHING (MUTE)
NOISE SHAPER OFF
tStartup Ramp tStartup Ramp
(UNMUTED)
(UNMUTED)
INPUT_X IS SWITCHING (MUTE)
NOISE SHAPER ON
TAS5624A
SLAS844A –MAY 2012–REVISED JANUARY 2016
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9.3 Feature Description
9.3.1 System Power-Up and Power-Down Sequence
9.3.1.1 Powering Up
The TAS5624A does not require a power-up sequence. The outputs of the H-bridges remain in a high-
impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not
specifically required, TI recommends to hold RESET in a low state while powering up the device. This allows an
internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
9.3.1.2 Powering Down
The TAS5624A does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
9.3.2 Start-Up and Shutdown Ramp Sequence
The integrated start-up and stop sequence ensures a click-free and pop-free start-up and shutdown sequence of
the amplifier. The start-up sequence uses a voltage ramp with a duration set by the CSTART capacitor. The
sequence uses the input PWM signals to generate output PWM signals, hence input idle PWM must be present
during both start-up and shutdown ramping sequences.
VDD, GVDD_X and PVDD_X power supplies must be turned on and with settled outputs before starting
the start-up ramp by setting RESET high.
During start-up and shutdown ramp, the input PWM signals must be in muted condition with the PWM processor
noise shaper activity turned off (50% duty cycle).
The duration of the start-up and shutdown ramp is 100 ms + X ms, where X is the CSTART capacitor value in
nF.
TI recommends using a 100-nF CSTART in BTL and PBTL mode and 1 µF in SE mode configuration. This
results in ramp times of 200 ms and 1.1 s respectively. The longer ramp time in SE configuration allows charge
and discharge of the output AC-coupling capacitor without audible artifacts.
Figure 15. Start-Up and Shutdown Ramp
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Feature Description (continued)
9.3.3 Unused Output Channels
If all available output channels are not used, TI recommends disabling of unused output nodes to reduce power
consumption. Furthermore by disabling unused output channels the cost of unused output LC demodulation
filters can be avoided.
Disabling a channel is done by leave the bootstrap capacitor (BST) unstuffed and connecting the respective input
to GND. The unused output pins can be left floating.
NOTE
The PVDD decoupling capacitors must still be mounted.
Table 1. Unused Output Channels
OPERATIN PWM OUTPUT UNUSED INPUT_A INPUT_B INPUT_C INPUT_D UNSTUFFED COMPONENT
G MODE INPUT CONFIGURATION CHANNEL
000 2N + 1 AB GND GND PWMc PWMd BST_A & BST_B capacitor
001 1N + 1 2 × BTL CD PWMa PWMb GND GND BST_C & BST_D capacitor
010 2N + 1
A GND PWMb PWMc PWMd BST_A capacitor
B PWMa GND PWMc PWMd BST_B capacitor
101 1N + 1 4 × SE C PWMa PWMb GND PWMd BST_C capacitor
D PWMa PWMb PWMc GND BST_D capacitor
9.3.4 Device Protection System
The TAS5624A contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5624A responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other
than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has
been removed, that is, the supply voltage has increased.
The device will function on errors, as shown in Table 2.
Table 2. Device Protection
BTL MODE PBTL MODE SE MODE
CHANNEL FAULT TURNS OFF CHANNEL FAULT TURNS OFF CHANNEL FAULT TURNS OFF
A A A
A + B A + B
B B B
A + B + C + D
C C C
C + D C + D
D D D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective high-side FET.
9.3.5 Pin-to-Pin Short-Circuit Protection (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at
start-up, for example, when VDD is supplied, consequently a short to either GND or PVDD_X after system start-
up does not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all
half-bridges are kept in a Hi-Z state until the short is removed, the device then continues the start-up sequence
and starts switching. The detection is controlled globally by a two-step sequence. The first step ensures that
there are no shorts from OUT_X to GND, the second step tests that there are no shorts from OUT_X to
PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The
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typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the device will
not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and
FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and
PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC
detection system, TI recommends not to insert resistive load to GND or PVDD_X.
9.3.6 Overtemperature Protection
The TAS5624A has a two-level, temperature-protection system that asserts an active-low warning signal (OTW)
when the device junction temperature exceeds 125°C (typical). If the device junction temperature exceeds 155°C
(typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-
impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,
RESET must be asserted. Thereafter, the device resumes normal operation.
9.3.7 Overtemperature Warning, OTW
The overtemperature warning OTW asserts when the junction temperature has exceeded recommended
operating temperature. Operation at junction temperatures above OTW threshold is exceeding recommended
operation conditions and is strongly advised to avoid.
If OTW asserts, take action to reduce power dissipation to allow junction temperature to decrease until it gets
below the OTW hysteresis threshold. This action can be decreasing audio volume or turning on a system cooling
fan.
9.3.8 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5624A fully protect the device in any power-up, power-down, or brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
9.3.9 Error Reporting
NOTE
Asserting RESET low forces the FAULT signal high, independent of faults being present.
TI recommends monitoring the OTW signal using the system microcontroller and responding to an
overtemperature warning signal by, for example, turning down the volume to prevent further heating of the device
resulting in device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on FAULT, CLIP, and OTW
outputs. See Electrical Characteristics table for actual values.
The FAULT and OTW pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a
PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Likewise, OTW goes low when
the device junction temperature exceeds 125°C (see Table 3).
Table 3. Error Reporting
FAULT OTW DESCRIPTION
0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
0 1 Overload (OLP) or undervoltage (UVP)
1 0 Junction temperature higher than 125°C (overtemperature warning)
1 1 Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
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SLAS844A –MAY 2012–REVISED JANUARY 2016
9.3.10 Fault Handling
If a fault situation occurs while in operation, the device will act accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to shut down, and will
assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires resetting
the device by toggling RESET. Toggling RESET must never be allowed with excessive system temperature, so it
is advised to monitor RESET by a system microcontroller and only allow releasing RESET (RESET high) if the
OTW signal is cleared (high). A channel fault will result in shutdown of the PWM activity of the affected channels.
Asserting RESET low forces the FAULT signal high, independent of faults being present. TI recommends
monitoring the OTW signal using the system microcontroller and responding to an overtemperature warning
signal by, for example, turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
Table 4. Fault Handling
FAULT AND GLOBAL OR LATCHED AND
REPORTING ACTION NEEDED TO
EVENT
FAULT AND EVENT OUTPUT FETs
METHOD CLEAR
CHANNEL SELF CLEARING
DESCRIPTION
PVDD_X UVP
VDD UVP Increase affected supply
Voltage Fault Global FAULT Pin Self-Clearing Hi-Z
voltage
GVDD_X UVP
AVDD UVP
Power On
POR (DVDD UVP) Global FAULT Pin Self-Clearing Allow DVDD to rise H-Z
Reset
Allow BST cap to recharge
Channel
BST UVP Voltage Fault None Self-Clearing HighSide Off
(half-bridge) (lowside on, VDD 12 V)
Thermal Cool below lower OTW
OTW Global OTW Pin Self-Clearing Normal operation
Warning threshold
Thermal
OTE (OTSD) Global FAULT Pin Latched Toggle RESET Hi-Z
Shutdown
OLP (CBC > 2.6ms) OC shutdown Channel FAULT Pin Latched Toggle RESET Hi-Z
Latched OC (ROC > 47k) OC shutdown Channel FAULT Pin Latched Toggle RESET Hi-Z
Reduce signal level or Flip state, cycle by
CBC (24k < ROC < 33k) OC Limiting Channel None Self-Clearing remove short cycle at fs / 2
Stuck at Fault(1) No PWM Channel None Self-Clearing Resume PWM Hi-Z
(1 to 3 channels)
Stuck at Fault(1) No PWM Global None Self-Clearing Resume PWM Hi-Z
(All channels)
(1) Stuck at Fault occurs when input PWM drops below minimum PWM frame rate given in Recommended Operating Conditions.
9.3.11 Device Reset
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the
FAULT output, that is, FAULT is forced high. A rising-edge transition on reset input allows the device to resume
operation after an overload fault. To ensure thermal reliability, the rising edge of RESET must occur no sooner
than 4 ms after the falling edge of FAULT.
9.3.12 System Design Consideration
A rising-edge transition on RESET input allows the device to execute the start-up sequence and starts switching.
Apply audio only according to the timing information for start-up and shutdown sequence. That will start and stop
the amplifier without audible artifacts in the output transducers.
The CLIP signal indicates that the output is approaching clipping (when output PWM starts skipping pulses due
to loop filter saturation). The signal can be used to initiate an audio volume decrease or to adjust the power
supply rail.
The device inverts the audio signal from input to output.
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The DVDD and AVDD pins are not recommended to be used as a voltage source for external circuitry.
9.4 Device Functional Modes
There are three main output modes that the user can configure the device as per application requirement. In
addition, there are two PWM modulation modes, AD and BD. AD modulation can have single-ended (SE) or
differential analog inputs. AD modulation can also be configured to have SE, BTL, BTL + SE, or PBTL outputs.
BD modulation requires differential analog inputs. BD modulation can only be configured in BTL or PBTL mode.
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SLAS844A –MAY 2012–REVISED JANUARY 2016
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device in several popular use cases. Each of these configurations can be realized using
the evaluation modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the
most common modes of operation. Any design variation can be supported by TI through schematic and layout
reviews. Visit the E2E Forum at www.e2e.ti.com for design assistance and join the audio amplifier discussion
forum for additional information.
10.2 Typical Applications
10.2.1 Typical BTL Application
See Figure 16 for application schematic. In this application, differential PWM inputs are used with AD modulation
from the PWM modulator (TAS5558). AD modulation scheme is defined as PWM(+) as opposite polarity from
PWM(–).
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Product Folder Links: TAS5624A
44
43
42
41
31
13
14
15
16
17
18 27
28
29
30
32
1
2
3
4
5
6
7
8
9
10
11
12 33
34
35
36
40
39
38
37
M3
19
20
21
22
OC _ADJ
VDD
23
24
25
26
M2
M1
/OTW
/FAULT
INPUT_D
INPUT_C
GND
GND
GND
INPUT_B
INPUT_A
C_START
/RESET
PVDD_CD
GND
BST_A
PVDD_AB
GND
OUT_B
BST_B
GND
OUT_C
PVDD_CD
OUT_A
PVDD_AB
GND
BST_C
BST_D
OUT_D
GVDD_AB
GVDD_CD
GND
GND
OUT_D
OUT_A
PVDD_AB
PVDD_CD
/CLIP
GND
DVDD
AVDD
33nF
220 nF
100 nF
33nF
470 uF
10 µH
10 µH
10nF
10nF
100 nF
33nF
220 nF
100 nF
33nF
470 uF
10 µH
10 µH
100 nF
PVDD
GND
/RESET
1uF
1uF
100 nF
ROC-ADJUST
100 nF
100 nF
100 nF
PWM_A
PWM_B
PWM_C
PWM_D
/FAULT
/OTW
/CLIP
10uF
+12V
GND
3R3
10nF
10nF
1nF
1nF
1nF
1nF
220 nF
220 nF 470 nF
470 nF
3.3R
3.3R
3R3
3R3
3R3
TAS5624A
TAS5624A
SLAS844A –MAY 2012–REVISED JANUARY 2016
www.ti.com
Figure 16. Typical Differential (2N) BTL Application With AD Modulation Filters
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10.2.1.1 Design Requirements
Table 5 lists the design parameters of Figure 16.
Table 5. Design Requirements
PARAMETER VALUE
Digital regulator supply 12 V
Full-bridge power supply 12 V to 38 V
PWM modulator TAS5558
Output filters Inductor-capacitor lowpass filter
Speaker 2.5 Ωminimum
10.2.1.2 Detailed Design Procedure
Using Figure 16 as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, schematic layout and routing given in Layout Example,
integrate the device and its supporting components into the system PCB file.
• The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the high-
frequency signals which go to the serial audio port. TI recommends that these be constructed to ensure they
are given precedent as design trade-offs are made.
• For questions and support go to the E2E Forum at www.e2e.ti.com. If it is necessary to deviate from the
recommended layout, please visit the E2E Forum to request a layout review.
10.2.1.2.1 Pin Connections
• Pin 1 - GVDD_AB is the gate-drive voltage for half-bridges A and B. It needs a 3.3-Ωisolation resistor and a
0.1-µF decoupling capacitor.
• Pin 2 - VDD is the supply for internal voltage regulators AVDD and DVDD. It needs a 10-µF bulk capacitor
and a 0.1-µF decoupling capacitor.
• Pin 3 - Roc adjust is the overcurrent programming resistor. Depending on the application, this resistor can be
between 24 kΩto 68 kΩ.
• Pin 4 - RESET pin when asserted, it keeps outputs Hi-Z and no PWM switching. This pin can be controlled by
a microprocessor.
• Pins 5 and 6 - These are PWM(+) and PWM(–) pins with signals provided by a PWM modulator such as the
TAS5558. These are PWM differential pairs.
• Pin 7 - Start-up ramp capacitor must be 1 µF for SE configuration.
• Pin 8 - Digital output supply pin is connected to 1-µF decoupling capacitor.
• Pins 9-12 - Ground pins are connected to board ground.
• Pin 13 - Analog output supply pin is connected to 1-µF decoupling capacitor.
• Pins 14 and 15 - These are PWM(+) and PWM(–) pins with signals provided by a PWM modulator such as
the TAS5558. These are PWM differential pair.
• Pin 16 - Fault pin can be monitored by a microcontroller through GPIO pin. System can decide to assert reset
or shutdown.
• Pin 17 - Overtemperature warning pin can be monitored by a microcontroller through a GPIO pin. System can
decide to turn on fan or lower output power.
• Pin 18 - Output clip indicator can be monitored by a microcontroller through a GPIO pin. System can decide
to lower the volume.
• Pins 19-21 - Mode pins set the input and output configurations. For this configuration M1-M3 are grounded.
These mode pins must be hardware configured, such as, not through GPIO pins from a microcontroller.
• Pin 22 - GVDD_CD is the gate-drive voltage for half-bridges C and D. This pin needs a 3.3-Ωisolation
resistor and a 0.1-µF decoupling capacitor.
• Pins 23, 24, 43, 44 - Bootstrap pins for half-bridges A, B, C, and D. Connect 33 nF from this pin to
corresponding output pins.
• Pins 25, 26, 33, 34, 41, 42 - These ground pins must be used to ground decoupling capacitors from PVDD_X.
• Pins 27, 28, 32, 35, 39, 40 - Output pins from half-bridges A, B, C, and D. Connect appropriate bootstrap
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0
20
40
60
80
100
120
140
160
180
200
220
240
260
−10 0 10 20 30 40 50 60 70 80 90 100 110
TC − Case Temperature − °C
PO − Output Power − W
3Ω
4Ω
8ΩTHD+N at 10%
G007
0
5
10
15
20
25
30
35
40
45
50
55
60
0 100 200 300 400 500
Total Output Power − W
Power Loss − W
3Ω
4Ω
8Ω
TC= 75°C
G006
TAS5624A
SLAS844A –MAY 2012–REVISED JANUARY 2016
www.ti.com
capacitors and differential LC filter as shown in Figure 20.
• Pins 29, 30, 31, 36, 37, 38 - Power supply pins to half-bridges A, B, C, and D. A and B form a full-bridge and
C and D form another full-bridge. A 470-µF bulk capacitor is recommended for each full-bridge power pins.
Two 0.22-µF decoupling capacitors are placed on each full-bridge power pins. See Figure 20 for details.
10.2.1.3 Application Curves
Figure 17. System Power Loss vs Output Power Figure 18. Output Power vs Temperature
10.2.2 Typical SE Configuration
See Figure 19 for application schematic. In this application, four single-ended PWM inputs are used with AD
modulation from the PWM modulator such as the TAS5558. AD modulation scheme is defined as PWM(+) is
opposite polarity from PWM(–). The single-ended (SE) output configuration is often used to drive four
independent channels in one TAS5622A device.
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44
43
42
41
31
13
14
15
16
17
18 27
28
29
30
32
1
2
3
4
5
6
7
8
9
10
11
12 33
34
35
36
40
39
38
37
M3
19
20
21
22
OC_ADJ
VDD
23
24
25
26
M2
M1
/OTW
/FAULT
INPUT_D
INPUT_C
GND
GND
GND
INPUT_B
INPUT_A
C_START
/RESET
PVDD_CD
GND
BST_A
PVDD_AB
GND
OUT_B
BST_B
GND
OUT_C
PVDD_CD
OUT_A
PVDD_AB
GND
BST_C
BST_D
OUT_D
GVDD_AB
GVDD_CD
GND
GND
OUT_D
OUT_A
PVDD_AB
PVDD_CD
/CLIP
GND
DVDD
AVDD
33nF
220nF
1µF
33nF
470uF
10uH
10uH
3R3
10nF
3R3
10nF
1µF
33nF
220nF
1µF
33nF
470uF
10uH
10uH
1µF
PVDD
GND
/RESET
1uF
1uF
1µF
ROC-ADJUST
100nF
100nF
100nF
PWM_A
PWM_B
PWM_C
PWM_D
/FAULT
/OTW
/CLIP
10uF
+12V
GND
470uF
µF
3R3
10nF
3R3
10nF
µF
470uF
470uF
470uF
*85°C,Low ESR
*85°C,Low ESR
*85°C,Low ESR
*85°C,Low ESR
1nF
1nF
1nF
1nF
220nF
220nF
3.3R
3.3R
TAS5624A
TAS5624A
www.ti.com
SLAS844A –MAY 2012–REVISED JANUARY 2016
Figure 19. Typical (1N) SE Application
Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TAS5624A
0.005
0.01
0.1
1
10
0.02 0.1 1 10 100
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
2Ω
3Ω
4Ω
TC = 75°C
G009
0
20
40
60
80
100
10 15 20 25 30 35 40
PVDD − Supply Voltage − V
PO − Output Power − W
2Ω
3Ω
4Ω
TC = 75°C
THD+N at 10%
G010
TAS5624A
SLAS844A –MAY 2012–REVISED JANUARY 2016
www.ti.com
10.2.2.1 Design Requirements
Design Requirements lists the design parameters of Figure 19.
10.2.2.2 Detailed Design Procedure
Using Figure 16 as a guide, follow the design procedure in Detailed Design Procedure.
10.2.2.3 Application Curves
Figure 20. Total Harmonic Distortion + Noise Figure 21. Output Power vs Supply Voltage
vs Output Power
24 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: TAS5624A
44
43
42
41
31
13
14
15
16
17
18 27
28
29
30
32
1
2
3
4
5
6
7
8
9
10
11
12 33
34
35
36
40
39
38
37
M3
19
20
21
22
OC_ADJ
VDD
23
24
25
26
M2
M1
/OTW
/FAULT
INPUT_D
INPUT_C
GND
GND
GND
INPUT_B
INPUT_A
C_START
/RESET
PVDD_CD
GND
BST_A
PVDD_AB
GND
OUT_B
BST_B
GND
OUT_C
PVDD_CD
OUT_A
PVDD_AB
GND
BST_C
BST_D
OUT_D
GVDD_AB
GVDD_CD
GND
GND
OUT_D
OUT_A
PVDD_AB
PVDD_CD
/CLIP
GND
DVDD
AVDD
33 nF
220 nF
33 nF
470 uF
10µH
10 µH
33nF
220 nF
33nF
470 uF
10 µH
10 µH
PVDD
GND
/RESET
1uF
1uF
100nF
ROC-ADJUST
100 nF
100 nF
100 nF
PWM_A
PWM_B
/FAULT
/OTW
/CLIP
10uF
+12V
GND
220 nF
220 nF
100 nF
3R3
10nF
3R3
10nF
100 nF
1 nF
1 nF
470 nF
3.3R
100 nF
3.3R
TAS5624A
TAS5624A
www.ti.com
SLAS844A –MAY 2012–REVISED JANUARY 2016
10.2.3 Typical PBTL Configuration
Figure 22. Typical Differential (2N) PBTL Application With AD Modulation Filter
Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TAS5624A
0.005
0.01
0.1
1
10
0.02 0.1 1 10 100 500
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
2Ω
3Ω
4Ω
TC = 75°C
G011
0
50
100
150
200
250
300
350
400
450
10 15 20 25 30 35 40
PVDD − Supply Voltage − V
PO − Output Power − W
2Ω
3Ω
4Ω
TC = 75°C
THD+N at 10%
G012
TAS5624A
SLAS844A –MAY 2012–REVISED JANUARY 2016
www.ti.com
10.2.3.1 Design Requirements
Design Requirements lists the design parameters of Figure 19.
10.2.3.2 Detailed Design Procedure
Using Figure 16 as a guide, follow the design procedure in Detailed Design Procedure.
10.2.3.3 Application Curves
Figure 23. Total Harmonic Distortion + Noise Figure 24. Output Power vs Supply Voltage
vs Output Power
26 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: TAS5624A
TAS5624A
www.ti.com
SLAS844A –MAY 2012–REVISED JANUARY 2016
11 Power Supply Recommendations
11.1 Power Supplies
To facilitate system design, the TAS5624A needs only a 12-V supply in addition to the (typical) 36-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and
output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
bootstrap pins (BST_X) and each full-bridge has separate power stage supply (PVDD_X) and gate supply
(GVDD_X) pins. Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although
supplied from the same 12-V source, TI highly recommends separating GVDD_AB, GVDD_CD, and VDD on the
printed-circuit-board (PCB) by RC filters (see Layout Example for details). These RC filters provide the
recommended high-frequency isolation. Pay special attention to placing all decoupling capacitors as close to their
associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors
must be avoided.
Pay special attention to the power-stage power supply; this includes component selection, PCB placement, and
routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical
performance, EMI compliance, and system reliability, it is important that each PVDD_X connection is decoupled
with minimum 2x, 220-nF ceramic capacitors placed as close as possible to each supply pin. TI recommends
following the PCB layout of the TAS5624A reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply must be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36-V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on reset circuit. Moreover, the TAS5624A is fully protected against erroneous
power-stage turn on due to parasitic gate charging when power supplies are applied. Thus, voltage-supply ramp
rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions table of this
data sheet).
11.2 Boot Strap Supply
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 400 kHz, TI recommends using 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TAS5624A
TAS5624A
SLAS844A –MAY 2012–REVISED JANUARY 2016
www.ti.com
12 Layout
12.1 Layout Guidelines
12.1.1 PCB Material Recommendation
FR-4 Glass Epoxy material with 1-oz. (35-μm) is recommended for use with the TAS5624A. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
12.1.2 PVDD Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors must be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well-designed system power supply, 1000-μF, 50-V capacitors support most
applications. The PVDD capacitors must be low-ESR types because they are used in a circuit associated with
high-speed switching.
12.1.3 Decoupling Capacitor Recommendation
To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, good-quality decoupling capacitors must be used. In practice, X5R or better must be used in this
application.
The voltage of the decoupling capacitors must be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the close decoupling capacitor that is placed on the power supply to each half-bridge. It must
withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power
output, and the ripple current created by high power output. A minimum voltage rating of 50 V is required for use
with a 36-V power supply.
See the TAS5624A EVM User's Guide, (SLAU376) for more details including bill of materials.
12.1.4 Circuit Component and Printed-Circuit-Board Recommendation
These requirements must be followed to achieve best performance and reliability and minimum ground bounce at
rated output power of TAS5624A.
12.1.4.1 Circuit Component Requirements
A number of circuit components are critical to performance and reliability. They include LC filter inductors and
capacitors, decoupling capacitors and the heat sink. The best detailed reference for these is the TAS5624A EVM
BOM in the user's guide, which includes components that meet all the following requirements.
• High-frequency decoupling capacitors: small high-frequency decoupling capacitors are placed next to the IC
to control switching spikes and keep high-frequency currents in a tight loop to achieve best performance and
reliability and EMC. They must be high-quality ceramic parts with material like X7R or X5R and voltage
ratings at least 30% greater than PVDD, to minimize loss of capacitance caused by applied DC voltage.
(Capacitors made of materials like Y5V or Z5U must never be used in decoupling circuits or audio circuits
because their capacitance falls dramatically with applied DC and AC voltage, often to 20% of rated value or
less.)
• Bulk decoupling capacitors: large bulk decoupling capacitors are placed as close as possible to the IC to
stabilize the power supply at lower frequencies. They must be high-quality aluminum parts with low ESR and
ESL and voltage ratings at least 25% more than PVDD to handle power supply ripple currents and voltages.
• LC filter inductors: to maintain high efficiency, short-circuit protection, and low distortion, LC filter inductors
must be linear to at least the OCP limit and must have low DC resistance and core losses. For SCP,
minimum working inductance, including all variations of tolerance, temperature and current level, must be 5
µH. Inductance variation of more than 1% over the output current range can cause increased distortion.
• LC filter capacitors: to maintain low distortion and reliable operation, LC filter capacitors must be linear to
twice the peak output voltage. For reliability, capacitors must be rated to handle the audio current generated
in them by the maximum expected audio output voltage at the highest audio frequency.
• Heat sink: The heat sink must be fabricated with the PowerPAD contact area spaced 1.0 mm ±0.01 mm
28 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: TAS5624A
TAS5624A
www.ti.com
SLAS844A –MAY 2012–REVISED JANUARY 2016
Layout Guidelines (continued)
above mounting areas that contact the PCB surface. It must be supported mechanically at each end of the IC.
This mounting ensures the correct pressure to provide good mechanical, thermal and electrical contact with
TAS5624A PowerPAD. The PowerPAD contact area must be bare and must be interfaced to the PowerPAD
with a thin layer (about 1 mill) of a thermal compound with high thermal conductivity.
12.1.4.2 Printed-Circuit-Board Requirements
PCB layout, audio performance, EMC, and reliability are linked closely together, and solid grounding improves
results in all these areas. The circuit produces high, fast-switching currents, and take care controlling current flow
and minimizing voltage spikes and ground bounce at IC ground pins. Critical components must be placed for
best performance and PCB traces must be sized for the high audio currents that the IC circuit produces.
Grounding: ground planes must be used to provide the lowest impedance and inductance for power and audio
signal currents between the IC and its decoupling capacitors, LC filters and power supply connection. The area
directly under the IC must be treated as central ground area for the device, and all IC grounds must be
connected directly to that area. A matrix of vias must be used to connect that area to the ground plane. Ground
planes can be interrupted by radial traces (traces pointing away from the IC), but they must never be interrupted
by circular traces, which disconnect copper outside the circular trace from copper between it and the IC. Top and
bottom areas that do not contain any power or signal traces must be flooded and connected with vias to the
ground plane.
Decoupling capacitors: high-frequency decoupling capacitors must be located within 2 mm of the IC and
connected directly to PVDD and GND pins with solid traces. Vias must not be used to complete these
connections, but several vias must be used at each capacitor location to connect top ground directly to the
ground plane. Placement of bulk decoupling capacitors is less critical, but they still must be placed as close as
possible to the IC with strong ground return paths. Typically the heat sink sets the distance.
LC filters: LC filters must be placed as close as possible to the IC after the decoupling capacitors. The capacitors
must have strong ground returns to the IC through top and bottom grounds for effective operation.
PCB copper must be at least 1-oz. thickness. PVDD and output traces must be wide enough to carry expected
average currents without excessive temperature rise. PWM input traces must be kept short and close together on
the input side of the IC and must be shielded with ground flood to avoid interference from high power switching
signals.
The heat sink must be grounded well to the PCB near the IC, and a thin layer of highly conductive thermal
compound (about 1 mill) must be used to connect the heat sink to the PowerPAD.
Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TAS5624A
T1
T2
T4
T3
T5
T5
TAS5624A
SLAS844A –MAY 2012–REVISED JANUARY 2016
www.ti.com
12.2 Layout Example
Note T1: Bottom and top layer ground plane areas are used to provide strong ground connections. The area under
the IC must be treated as central ground, with IC grounds connected there and a strong via matrix connecting the
area to bottom ground plane. The ground path from the IC to the power supply ground through top and bottom layers
must be strong to provide very low impedance to high power and audio currents.
Note T2: Low impedance X7R or X5R ceramic high frequency decoupling capacitors must be placed within 2mm of
PVDD and GND pins and connected directly to them and to top ground plane to provide good decoupling of high
frequency currents for best performance and reliability. Their DC voltage rating must be 2 times PVDD.
Note T3: Low impedance electrolytic bulk decoupling capacitors must be placed as close as possible to the IC.
Typically the heat sink sets the distance. Wide PVDD traces are routed on the top layer with direct connections to the
pins, without going through vias.
Note T4: LC filter inductors and capacitors must be placed as close as possible to the IC after decoupling capacitors.
Inductors must have low DC resistance and switching losses and must be linear to at least the OCP (over current
protection) limit. Capacitors must be linear to at least twice the maximum output voltage and must be capable of
conducting currents generated by the maximum expected high frequency output.
Note T5: Bulk decoupling capacitors and LC filter capacitors must have strong ground return paths through ground
plane to the central ground area under the IC.
Note T6: The heat sink must have a good thermal and electrical connection to PCB ground and to the IC PowerPAD.
It must be connected to the PowerPad through a thin layer, about 1 mil, of highly conductive thermal compound.
Figure 25. Printed-Circuit-Board - Top Layer
30 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: TAS5624A
B1
B1
B2
TAS5624A
www.ti.com
SLAS844A –MAY 2012–REVISED JANUARY 2016
Layout Example (continued)
Note B1: A wide PVDD bus and a wide ground path must be used to provide very low impedance to high power and
audio currents to the power supply. Top and bottom ground planes must be connected with vias at many points to
reinforce the ground connections.
Note B2: Wide output traces can be routed on the bottom layer and connected to output pins with strong via arrays.
Figure 26. Printed-Circuit-Board - Bottom Layer
Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: TAS5624A
TAS5624A
SLAS844A –MAY 2012–REVISED JANUARY 2016
www.ti.com
13 Device and Documentation Support
13.1 Device Support
•8-Channel HD Compatible Audio Processor with ASRC and PWM Output, (TAS5558)
•150-W Stereo / 300-W Mono PurePath HD Digital-Input Class-D Power Stage, (TAS5624A)
13.2 Documentation Support
13.2.1 Related Documentation
•Audio Characterization Primer, (SLAA641)
•Calculating Gain for Audio Amplifiers, (SLOA105)
•TAS5558 8-Channel HD Compatible Audio Processor with ASRC and PWM Output, (SLES273)
•TAS5624A EVM User's Guide, (SLAU376)
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
PurePath, PowerPAD, E2E are trademarks of Texas Instruments.
Blu-ray is a trademark of Blu-ray Disk Association Association (BDA).
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: TAS5624A
PACKAGE OPTION ADDENDUM
www.ti.com 19-Jun-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TAS5624ADDV ACTIVE HTSSOP DDV 44 35 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TAS5624A
TAS5624ADDVR ACTIVE HTSSOP DDV 44 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TAS5624A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Jun-2015
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TAS5624ADDVR HTSSOP DDV 44 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jun-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5624ADDVR HTSSOP DDV 44 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jun-2015
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
8.3
7.9
42X 0.635
44X 0.27
0.17
2X
13.335
(0.15) TYP
0 - 8 0.15
0.05
1.2
1.0
7.30
6.72
4.43
3.85
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
14.1
13.9
B6.2
6.0
(0.15) TYP
NOTE 6
2X (0.6)
NOTE 6
2X (0.3)
NOTE 6
PowerPAD TSSOP - 1.2 mm max heightDDV0044D
PLASTIC SMALL OUTLINE
4218830/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. The exposed thermal pad is designed to be attached to an external heatsink.
6. Features may differ or may not be present.
PowerPAD is a trademark of Texas Instruments.
TM
144
0.08 C A B
23
22
PIN 1 ID
AREA
EXPOSED
THERMAL
PAD
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.250
www.ti.com
EXAMPLE BOARD LAYOUT
(7.5)
0.05 MAX
AROUND 0.05 MIN
AROUND
44X (1.45)
44X (0.4)
42X (0.635)
(R0.05) TYP
PowerPAD TSSOP - 1.2 mm max heightDDV0044D
PLASTIC SMALL OUTLINE
4218830/A 08/2016
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:6X
1
22 23
44
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
TM
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED SOLDER MASK DETAILS
NOT TO SCALE
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
44X (1.45)
44X (0.4)
42X (0.635)
(7.5)
PowerPAD TSSOP - 1.2 mm max heightDDV0044D
PLASTIC SMALL OUTLINE
4218830/A 08/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE :6X
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44
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