High Voltage, Low Noise, Low Distortion,
Unity-Gain Stable, High Speed Op Amp
ADA4898-1
Rev. B
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FEATURES
Ultralow noise
0.9 nV/√Hz
2.4 pA/√Hz
1.2 nV/√Hz @ 10 Hz
Ultralow distortion: −93 dBc at 500 kHz
Wide supply voltage range: ±5 V to ±16 V
High speed
−3 dB bandwidth: 65 MHz (G = +1)
Slew rate: 55 V/µs
Unity gain stable
Low input offset voltage: 150 µV maximum
Low input offset voltage drift: 1 V/°C
Low input bias current: −0.1 µA
Low input bias current drift: 2 nA/°C
Supply current: 8 mA
Power-down feature
APPLICATIONS
Instrumentation
Active filters
DAC buffers
SAR ADC drivers
Optoelectronics
CONNECTION DIAGRAM
NC
1
–IN
2
+IN
3
–V
S4
PD
8
+V
S
7
OUT
6
NC
5
NC = NO CONNECT
ADA4898-1
07037-001
Figure 1. Single 8-Lead ADA4898-1 SOIC_N_EP (RD-8-1)
GENERAL DESCRIPTION
The ADA4898-1 is an ultralow noise and distortion, unity gain
stable, voltage feedback op amp that is ideal for use in 16-bit and
18-bit systems with power supplies from ±5 V to ±16 V. The
ADA4898-1 features a linear, low noise input stage and internal
compensation that achieves high slew rates and low noise.
With the wide supply voltage range, low offset voltage, and wide
bandwidth, the ADA4898-1 is extremely versatile, and it features a
cancellation circuit that reduces input bias current.
The ADA4898-1 is available in an 8-lead SOIC package that
features an exposed metal paddle to improve power dissipation
and heat transfer to the negative supply plane. This EPAD offers
a significant thermal relief over traditional plastic packages.
The ADA4898-1 is rated to work over the extended industrial
temperature range of −40°C to +105°C.
07037-002
FREQUENCY (Hz)
VOLTAGE NOISE (nV/√Hz)
CURRENT NOISE (pA/√Hz)
1
0.1
1
10
0.1
1
10
10 100 1k 10k 100k
CURRENT
VOLTAGE
Figure 2. Input Voltage Noise and Current Noise vs. Frequency
ADA4898-1
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Supply ................................................................................. 3
±5 V Supply ................................................................................... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 13
Theory of Operation ...................................................................... 14
PD (Power-Down) Pin .............................................................. 14
Current Noise Measurement .................................................... 14
0.1 Hz to 10 Hz Noise ................................................................ 15
Applications Information .............................................................. 16
Higher Feedback Resistor Gain Operation ............................. 16
Recommended Values for Various Gains ................................ 16
Noise ............................................................................................ 17
Circuit Considerations .............................................................. 17
PCB Layout ................................................................................. 17
Power Supply Bypassing ............................................................ 17
Grounding ................................................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
6/09—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Specifications Section .................................................. 3
Changes to Figure 29 and Figure 31 ............................................. 11
Added Figure 32 .............................................................................. 12
Added Figure 41 .............................................................................. 13
Changes to PD (Power-Down) Pin Section ................................ 14
Added Table 6 .................................................................................. 14
Changes to Figure 45 ...................................................................... 15
8/08—Rev. 0 to Rev. A
Changes to General Description Section ...................................... 1
Changes to Table 5 ............................................................................ 6
Changes to Figure 17 ........................................................................ 9
Changes to Figure 28 ...................................................................... 10
Changes to Figure 29 and Figure 32 ............................................. 11
Added 0.1 Hz to 10 Hz Noise Section .......................................... 14
Added Figure 42 and Figure 43; Renumbered Sequentially ..... 14
Changes to Grounding Section ..................................................... 16
Updated Outline Dimensions ....................................................... 17
5/08—Revision 0: Initial Release
ADA4898-1
Rev. B | Page 3 of 20
SPECIFICATIONS
±15 V SUPPLY
TA = 25°C, G = +1, RF = 0 Ω, RG open, RL = 1 kΩ to GND (for G > 1, RF = 100 Ω), unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT = 100 mV p-p 65 MHz
V
OUT = 2 V p-p 14 MHz
Bandwidth for 0.1 dB Flatness G = +2, VOUT = 2 V p-p 3.3 MHz
Slew Rate VOUT = 5 V step 55 V/μs
Settling Time to 0.1% VOUT = 5 V step 85 ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion SFDR f = 100 kHz, VOUT = 2 V p-p −116 dBc
f = 500 kHz, VOUT = 2 V p-p −93 dBc
f = 1 MHz, VOUT = 2 V p-p −79 dBc
Input Voltage Noise f = 100 kHz 0.9 nV/√Hz
Input Current Noise f = 100 kHz 2.4 pA/√Hz
DC PERFORMANCE RF = 1 kΩ
Input Offset Voltage 20 120 μV
Input Offset Voltage Drift 1 μV/°C
Input Bias Current −0.1 −0.4 μA
Input Bias Offset Current 0.03 0.3 μA
Input Bias Current Drift 2 nA/°C
Open-Loop Gain VOUT = ±5 V 99 103 dB
INPUT CHARACTERISTICS
Input Resistance Differential mode 5 kΩ
Common mode 30 MΩ
Input Capacitance Differential mode 3.2 pF
Common mode 2.5 pF
Input Common-Mode Voltage Range See Figure 41 ±11 V
Common-Mode Rejection Ratio ΔVCM = 2 V p-p −103 −126 dB
PD (POWER-DOWN) PIN
PD Input Voltages Chip powered down ≤−14 V
Chip enabled ≥−13 V
Input Leakage Current PD = +VS −0.1 μA
PD = −VS −0.2 μA
OUTPUT CHARACTERISTICS
Output Voltage Swing RL // (RF + RG) = 500 Ω, see Figure 41 −11.4 to +11.8 −11.7 to +12.1 V
R
L // (RF + RG) = 1 kΩ, see Figure 41 −12.7 to +12.5 −12.8 to +12.7 V
Linear Output Current (RMS) f = 100 kHz, SFDR = −70 dBc, RL = 150 Ω 40 mA
Short-Circuit Current Sinking/sourcing 150 mA
Off Isolation f = 1 MHz, PD = −VS 80 dB
POWER SUPPLY
Operating Range ±4.5 ±16.5 V
Quiescent Current PD = +VS 8.1 8.7 mA
PD = −VS 0.1 0.3 mA
Positive Power Supply Rejection Ratio +VS = 15 V to 17 V, −VS = −15 V −98 −107 dB
Negative Power Supply Rejection Ratio +VS = 15 V, −VS = −15 V to −17 V −100 −114 dB
ADA4898-1
Rev. B | Page 4 of 20
±5 V SUPPLY
TA = 25°C, G = +1, RF = 0 Ω, RG open, RL = 1 kΩ to GND (for G > 1, RF = 100 Ω), unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT = 100 mV p-p 57 MHz
V
OUT = 2 V p-p 12 MHz
Bandwidth for 0.1 dB Flatness G = +2, VOUT = 2 V p-p 3 MHz
Slew Rate VOUT = 2 V step 50 V/μs
Settling Time to 0.1% VOUT = 2 V step 90 ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion SFDR f = 500 kHz, VOUT = 2 V p-p −95 dBc
f = 1 MHz, VOUT = 2 V p-p −78 dBc
Input Voltage Noise f = 100 kHz 0.9 nV/√Hz
Input Current Noise f = 100 kHz 2.4 pA/√Hz
DC PERFORMANCE
Input Offset Voltage 30 150 μV
Input Offset Voltage Drift 1 μV/°C
Input Bias Current −0.1 −0.5 μA
Input Bias Offset Current 0.01 0.3 μA
Input Bias Current Drift 2 nA/°C
Open-Loop Gain VOUT = ±1 V 90 94 dB
INPUT CHARACTERISTICS
Input Resistance Differential mode 5 kΩ
Common mode 30 MΩ
Input Capacitance Differential mode 3.2 pF
Common mode 2.5 pF
Input Common-Mode Voltage Range See Figure 41 −3 to +2.5 V
Common-Mode Rejection Ratio ΔVCM = 1 V p-p −102 −120 dB
PD (POWER-DOWN) PIN
PD Input Voltages Chip powered down ≤−4 V
Chip enabled ≥−3 V
Input Leakage Current PD = +VS 0.1 μA
PD = −VS −2 μA
OUTPUT CHARACTERISTICS
Output Voltage Swing RL // (RF + RG) = 500 Ω, see Figure 41 ±3.1 ±3.2 V
R
L // (RF + RG) = 1 kΩ, see Figure 41 ±3.3 ±3.4 V
Linear Output Current (RMS) f = 100 kHz, SFDR = −70 dBc, RL = 150 Ω 8 mA
Short-Circuit Current Sinking/sourcing 150 mA
Off Isolation f = 1 MHz, PD = −VS 80 dB
POWER SUPPLY
Operating Range ±4.5 ±16.5 V
Quiescent Current PD = +VS 7.7 8.4 mA
PD = −VS 0.1 0.2 mA
Positive Power Supply Rejection Ratio +VS = 5 V to 7 V, −VS = −5 V −95 −100 dB
Negative Power Supply Rejection Ratio +VS = 5 V, −VS = −5 V to −7 V −97 −104 dB
ADA4898-1
Rev. B | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 36 V
Power Dissipation See Figure 3
Differential Mode Input Voltage ±1.5 V
Common-Mode Input Voltage ±11.4 V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the output load drive. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS). The power dissipated due to the load drive depends
upon the particular application. For each output, the power due
to load drive is calculated by multiplying the load current by the
associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 3 shows the maximum power dissipation in the package
for the ADA4898-1 vs. the ambient temperature for the 8-lead
SOIC_N_EP on a JEDEC standard 4-layer board, with its
underside paddle soldered to a pad that is thermally connected
to a PCB plane. θJA values are approximations.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane, with zero airflow.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
07037-003
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
0 2040608010010 30 50 70 90–40 –20–30 –10
Table 4.
Package Type θJA θ
JC Unit
8-Lead SOIC_N_EP on 4-Layer Board (Single) 47 29 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4898-1 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4898-1. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
ADA4898-1
Rev. B | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
07037-046
NC
1
–IN
2
+IN
3
–V
S4
PD
8
+V
S
7
OUT
6
NC
5
ADA4898-1
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD (EP) CAN BE CONNECTED
TO –V
S
OR LEFT FLOATING.
Figure 4. Single 8-Lead SOIC_N_EP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 NC No Connect.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 −VS Negative Supply.
5 NC No Connect.
6 OUT Output.
7 +VS Positive Supply.
8 PD Power Down.
EP −VS Exposed Pad. Can be connected to negative supply (−VS) or can
be left floating.
ADA4898-1
Rev. B | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
1 10 100
07037-004
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
R
L
= 1kΩ
V
OUT
= 100mV p-p
V
S
= ±15V
G = +1
R
F
= 0Ω
G = +1
R
F
= 100Ω
G = +2
R
F
= 100Ω
G = +5
R
F
= 100Ω
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
1 10 100
07037-007
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
R
L
= 1kΩ
V
OUT
= 2V p-p
V
S
= ±15V
G = +1
R
F
= 0Ω
G = +1
R
F
= 100Ω
G = +5
R
F
= 100Ω
G = +2
R
F
= 100Ω
Figure 5. Small Signal Frequency Response for Various Gains
Figure 8. Large Signal Frequency Response for Various Gains
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
1 10 100
07037-005
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
R
L
= 1kΩ
R
L
= 100Ω
R
L
= 200Ω
G = +1
V
OUT
= 100mV p-p
V
S
= ±15V
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
1 10 100
07037-008
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
R
L
= 1kΩ
R
L
= 100Ω
G = +1
V
OUT
= 2V p-p
V
S
= ±15V
R
L
= 200Ω
Figure 6. Small Signal Frequency Response for Various Loads
Figure 9. Large Signal Frequency Response for Various Loads
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1 10 100
07037-009
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
G = +1
R
L
= 1kΩ
V
OUT
= 2V p-p
V
S
= ±15V
T
A
= –40°C
T
A
= +105°C
T
A
= +25°C
T
A
= 0°C
T
A
= +85°C
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1 10 100
07037-006
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
T
A
= +25°C
G = +1
R
L
= 1kΩ
V
OUT
= 100mV p-p
V
S
= ±15V
T
A
= +105°C T
A
= +85°C
T
A
= –40°C
T
A
= 0°C
Figure 10. Large Signal Frequency Response for Various Temperatures
Figure 7. Small Signal Frequency Response for Various Temperatures
ADA4898-1
Rev. B | Page 8 of 20
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1 10 100
07037-010
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
G = +1
R
L
= 1kΩ
V
OUT
= 100mV p-p
V
S
= ±15V
V
S
= ±5V
Figure 11. Small Signal Frequency Response for Various Supply Voltages
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
1 10 100
07037-011
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
G = +1
R
L
= 1kΩ
V
OUT
= 100mV p-p
V
S
= ±15V
C
L
= 33pF
C
L
= 15pF
C
L
= 5pF
C
L
= 0pF
Figure 12. Small Signal Frequency Response for Various Capacitive Loads
0.1
1
10
1 10 100 1k 10k 100k
07037-012
FREQUENCY (Hz)
VOLTAGE NOISE (nV/√Hz)
Figure 13. Voltage Noise vs. Frequency
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1 10 100
07037-013
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
V
S
= ±15V
G = +1
R
L
= 1kΩ
V
OUT
= 2V p-p
V
S
= ±5V
Figure 14. Large Signal Frequency Response for Various Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
100k 1M 10M
0
7037-014
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
G = +2
R
L
= 1kΩ
V
S
= ±15V
V
OUT
= 2V p-p
V
OUT
= 0.1V p-p
Figure 15. 0.1 dB Flatness for Various Output Voltages
07037-035
FREQUENCY (Hz)
INPUT CURRENT NOISE (pA/ Hz)
1
1
10
100
10 100 1k 10k 100k
Figure 16. Input Current Noise vs. Frequency
ADA4898-1
Rev. B | Page 9 of 20
–20
–10
0
10
20
30
40
50
60
70
80
110
90
100
07037-016
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
100k 1M 1G10M 100M
PHASE
GAIN
–
70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
–200
OPEN-LOOP PHASE (Degrees)
ΔV
OUT
= ±5V
V
S
= ±15V
Figure 17. Open-Loop Gain and Phase vs. Frequency
07037-017
FREQUENCY (Hz)
DISTORTION (dBc)
–140
–120
–100
–80
–60
–40
–20
0
100k 1M 10M
G = +1, HD2
G = +1, HD3
G = +2, HD3, R
F
= 250Ω
G = +2, HD2, R
F
= 250Ω
R
L
= 1kΩ
V
S
= ±15V
V
OUT
= 2V p-p
Figure 18. Harmonic Distortion vs. Frequency and Gain
07037-018
FREQUENCY (Hz)
DISTORTION (dBc)
–140
–120
–100
–80
–60
–40
–20
0
100k 1M 10M
R
L
= 1kΩ, HD3
R
L
= 100Ω, HD3
G = +1
V
S
= ±15V
V
OUT
= 2V p-p
R
L
= 1kΩ, HD2
R
L
= 100Ω, HD2
Figure 19. Harmonic Distortion vs. Frequency and Loads
1
07073-019
OUTPUT VOLTAGE (V p-p)
DISTORTION (dBc)
–135
–125
–120
–130
–115
–110
–105
–100
–
95
23456
HD2
HD3
f = 100kHz
G = +1
R
L
= 1kΩ
V
S
= ±15V
Figure 20. Harmonic Distortion vs. Output Amplitude
07037-020
FREQUENCY (Hz)
DISTORTION (dBc)
–140
–120
–100
–80
–60
–40
–20
0
100k 1M 10M
R
L
= 1kΩ, HD3
R
L
= 100Ω, HD3
R
L
= 100Ω, HD2
G = +1
V
S
= ±5V
V
OUT
= 2V p-p
R
L
= 1kΩ, HD2
Figure 21. Harmonic Distortion vs. Frequency and Loads
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
C
L
= 0pF
C
L
= 5pF
C
L
= 15pF
C
L
= 33pF
07037-021
TIME (20ns/DIV)
OUTPUT VOLTAGE (V)
V
OUT
= 100mV p-p
G = +1
R
L
= 1kΩ
V
S
= ±15V
Figure 22. Small Signal Transient Response for Various Capacitive Loads
ADA4898-1
Rev. B | Page 10 of 20
G = +1
G = +2
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
07037-022
TIME (20ns/DIV)
OUTPUT VOLTAGE (V)
V
OUT
= 100mV p-p
R
L
=1kΩ
V
S
= ±15V
Figure 23. Small Signal Transient Response for Various Gains
–0.5
0
0.5
1.0
1.5
2.0
2.5
V
S
= ±15V
V
S
= ±5V
07037-023
TIME (100ns/DIV)
OUTPUT VOLTAGE (V)
V
OUT
= 2V p-p
G = +1
R
L
= 100Ω
Figure 24. Large Signal Transient Response for
Various Supply Voltages, RL = 100 Ω
INPUT
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
07037-026
TIME (10ns/DIV)
SETTLING TIME (%)
G = +1
R
L
= 1kΩ
V
OUT
= 5V p-p
V
S
= ±15V
Δt = 85ns
OUTPUT
Figure 25. Settling Time
–0.5
0
0.5
1.0
1.5
2.0
2.5
07037-025
TIME (100ns/DIV)
OUTPUT VOLTAGE (V)
V
OUT
= 2V p-p
G = +1
R
L
= 1kΩ
V
S
= ±15V
V
S
= ±5V
Figure 26. Large Signal Transient Response for
Various Supply Voltages, RL = 1 kΩ
–0.5
0
0.5
1.0
1.5
2.0
2.5
G = +1
07037-024
TIME (100ns/DIV)
OUTPUT VOLTAGE (V)
V
OUT
= 2V p-p
R
L
= 1kΩ
V
S
= ±15V
G = +2
Figure 27. Large Signal Transient Response for Various Gains
0.1
10k
1k
100
10
1
07037-028
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
100k 1M 100M10M
V
OUT
= 2V p-p,
PD HIGH
V
OUT
= 2V p-p,
PD LOW
V
OUT
= 0.1V p-p,
PD HIGH
G = +1
R
F
= 0Ω
R
L
= 0Ω
V
S
= ±15V
V
OUT
= 0.1V p-p,
PD LOW
Figure 28. Output Impedance vs. Frequency
ADA4898-1
Rev. B | Page 11 of 20
–140
–120
–100
–80
–60
–40
–20
0
07037-029
FREQUENCY (Hz)
CMRR (dB)
100 10M1k 100k 1M10k
G = +1
R
F
= 0Ω
R
L
= 1kΩ
V
S
= ±15V
ΔV
CM
= 1V p-p
ΔV
CM
= 100mV p-p
Figure 29. Common-Mode Rejection Ratio (CMRR) vs. Frequency
–75
–65
–55
–
45
100k 1M 10M 100M
V
OUT
= 0.1V p-p
07037-031
FREQUENCY (Hz)
PD ISOLATION (dB)
G = +1
R
L
= 1kΩ
V
S
= ±15V
V
OUT
= 2V p-p
Figure 30. PD Isolation vs. Frequency
–120
–100
–80
–60
–40
–20
0
07037-030
FREQUENCY (Hz)
PSRR (dB)
100 1k 10k 100k 1M 10M
G = +1
R
F
= 0Ω
R
L
= 1kΩ
V
S
= ±15V
V
OUT
= 2V p-p
+PSRR
–PSRR
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency
07037-100
15
12
9
6
3
0
5
4
3
2
1
0
50 100 1000 4000
OUTPUT VOLTAGE SWING (V), V
S
= ±15
V
OUTPUT VOLTAGE SWING (V), V
S
= ±5V
LOAD RESISTANCE (Ω)
POSITIVE SWING,
V
S
= +15V
NEGATIVE SWING,
V
S
=–15V
POSITIVE SWING, V
S
= +5V
NEGATIVE SWING,
V
S
= –5V
Figure 32 Output Swing vs. Load, G = +2, Load = RL // (RF + RG)
ADA4898-1
Rev. B | Page 12 of 20
1000
800
600
400
200
0
INPUT OFFSET VOLTAGE (µV)
COUNT
N = 6180
MEAN: –2.8
SD: 20
V
S
= ±5V
07037-034
0–30–60 30 9060–90
1000
800
600
400
200
0
07037-032
INPUT BIAS CURRENT (µA)
COUNT
–0.15–0.20–0.25 –0.10 0–0.05
N = 6180
MEAN: –0.13
SD: 0.02
V
S
= ±15V
Figure 33. Input Bias Current Distribution
Figure 35. Input Offset Voltage Distribution, VS = ±5 V
1000
800
600
400
200
0
07037-033
INPUT OFFSET VOLTAGE (µV)
COUNT
0–30–60 30 1209060
N = 6180
MEAN: 27
SD: 20
V
S
= ±15V
Figure 34. Input Offset Voltage Distribution, VS = ±15 V
ADA4898-1
Rev. B | Page 13 of 20
TEST CIRCUITS
IN
V
OUT
0.1µF 0.1µF
0.1µF
10µF
+
V
S
–V
S
49.9Ω
R
L
+
10µF
07037-052
+
Figure 36. Typical Noninverting Load Configuration
V
OUT
0.1µF
49.9Ω
+
V
S
–V
S
R
L
10µF
+
AC
07037-053
Figure 37. Positive Power Supply Rejection
IN V
OUT
0.1µF 0.1µF
0.1µF
10µF
+
V
S
–V
S
1kΩ
1kΩ
1kΩ
1kΩ
53.6Ω
R
L
+
10µF
+
07037-054
Figure 38. Common-Mode Rejection
IN
V
OUT
0.1µF 0.1µF
0.1µF
10µF
+
V
S
–V
S
R
G
R
F
49.9Ω
R
L
C
L
+
10µF
07037-055
+
Figure 39. Typical Capacitive Load Configuration
0.1µF
V
OUT
+
V
S
–V
S
R
L
10µF
+
AC
49.9Ω
07037-056
Figure 40. Negative Power Supply Rejection
0
7037-139
+V
S
–V
S
+I
B
–I
B
20Ω
1kΩ
V
CONTROL
R
IN
= 20
Ω
R
F
= 1k
Ω
IN-AMP
V
OU
T
R
L
Figure 41.DC Test Circuit
ADA4898-1
Rev. B | Page 14 of 20
THEORY OF OPERATION
The ADA4898-1 is a voltage feedback op amp that combines
unity gain stability with 0.9 nV/√Hz input noise. It employs a
highly linear input stage that can maintain greater than −90 dBc
(at 2 V p-p) distortion out to 500 kHz while in a unity-gain
configuration. This rare combination of low gain stability, low
input-referred noise, and extremely low distortion is the result
of Analog Devices, Inc., proprietary op amp architecture and
high voltage bipolar processing technology.
The simplified ADA4898-1 topology, shown in Figure 42, is a
single gain stage with a unity gain output buffer. It has over 100 dB
of open-loop gain and maintains precision specifications, such
as CMRR, PSRR, and offset, to levels that are normally associated
with topologies having two or more gain stages.
BUFFERg
m
C
C
R1
R
L
V
OUT
07037-041
Figure 42. Topology
PD (POWER-DOWN) PIN
The PD pin saves power by decreasing the quiescent power
dissipated in the device. It is very useful when power is an issue
and the device does not need to be turned on at all times. The
response of the device is rapid when going from power-down
mode to full power operation mode. Note that PD does not put
the output in a high-Z state, which means that the ADA4898-1
is not recommended for use as a multiplexer. Leaving the PD
pin floating keeps the amplifier in full power operation mode.
Table 6. Power-Down Voltage Control
PD Pin ±15 V ±10 V ±5 V
Power-Down Mode <−14 V <−9 V <−4 V
Full Power Mode >−13 V >−8 V >−3 V
CURRENT NOISE MEASUREMENT
To measure the very low (2.4 pA/√Hz) input current noise of
the ADA4898-1, 10 kΩ resistors were used on both inputs of the
amplifier. Figure 43 shows the noise measurement circuit used.
The 10 kΩ resistors are used on both inputs to balance the input
impedance and cancel the common-mode noise. In addition, a
high gain configuration is used to increase the total output noise
and bring it above the noise floor of the instrument.
07037-042
100
Ω
10
10kΩ
10kΩV
OUT
Figure 43. Current Noise Measurement Circuit
The current noise density (In) is calculated by
[
]
11k20
2)HznV/18.4(11 2/12
2
×
××−
=no
n
e
I
ADA4898-1
Rev. B | Page 15 of 20
0.1 Hz TO 10 Hz NOISE
Figure 44 shows the 0.1 Hz to 10 Hz voltage and current noise
of the ADA4898-1. The peak-to-peak noise voltage is below 0.5 µV.
Figure 45 shows the circuit used to measure the low frequency
noise. It uses a band-pass filter of approximately 0.1 Hz and 10 Hz
and a high gain stage feeding into an instrumentation amplifier.
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
02 46 8101214161820
TIME (s)
OUTPUT VOLTAGE (µV)
07037-047
Figure 44. 0.1 Hz to 10 Hz Noise
DUT
ADA4898-1
+IN
–IN
1µF
10nF
10nF
50Ω
50Ω
+IN
–IN
AD743
–V
S
= –9V
+V
S
= +9V
1µF
15.8kΩ
13kΩ
13Ω
MOMENTARY
1kΩ
806kΩ
806kΩ
7805
7905
+V
S
= +9V
(BATTERY)
–V
S
= –9V
(BATTERY)
+V
R
= +5V
–V
R
= –5V
+V
R
= +5V
–V
R
= –5V
AD620
R
G
–IN
+IN
–V
S
R
G
+V
S
OUTPUT
REF
R = 5.36kΩ, GAIN APPROX. 10Ω
10nF
1
2
4
3
8
7
5
6
10nF
+V
S
= +9V
–V
S
= –9V
FLOATING SHIELD
COAX
TEK
TDS 754A SCOPE
IN
FARADAY CAGE
07037-048
OUT
Figure 45. Low Frequency Noise Circuit
ADA4898-1
Rev. B | Page 16 of 20
APPLICATIONS INFORMATION
HIGHER FEEDBACK RESISTOR GAIN OPERATION
The ADA4898-1 schematic for the noninverting gain confi-
guration is nearly a textbook example (see Figure 46). The only
exception is the feedback capacitor in parallel with the feedback
resistor, RF, but this capacitor is recommended only when using
a large RF value (>300 Ω). Figure 47 shows the difference between
using a 100 Ω resistor and a 1 kΩ resistor. Due to the input
capacitance in the ADA4898-1 when using a higher feedback
resistor, more peaking appears in the closed-loop gain. Using
the lower feedback resistor resolves this issue; however, when
running at higher supplies (±15 V) with an RF of 100 Ω, the
system draws extra current into the feedback network. To
avoid this problem, a higher feedback resistor can be used with
a feedback capacitor in parallel. Figure 47 also shows the effect of
placing a feedback capacitor in parallel with a larger RF. In this
gain-of-2 configuration, RF = RG = 1 kΩ and CF = 2.7 pF. When
using CF, the peaking drops from 6 dB to less than 2 dB.
07037-043
V
IN
V
OUT
0.1µF 0.1µF
0.1µF
10µF
+V
S
–V
S
R
T
R
L
+
10µF
+
C
F
R
F
R
F
Figure 46. Noninverting Gain Schematic
–15
–12
–9
–6
–3
0
3
6
9
12
07037-044
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
100k 10M1M 100M
R
F
= 1kΩ, C
F
= 2.7pF
R
F
= 1kΩ
R
F
= 100Ω
G = +2
R
L
= 1kΩ
V
S
= ±15V
Figure 47. Small Signal Frequency Response for
Various Feedback Impedances
RECOMMENDED VALUES FOR VARIOUS GAINS
Table 7 provides a useful reference for determining various
gains and associated performance. RF is set to 100 Ω for gains
greater than 1. A low feedback RF resistor value reduces peaking
and minimizes the contribution to the overall noise performance
of the amplifier.
Table 7. Various Gains and Associated Recommended Resistor Values (Conditions: VS = ±5 V, TA = 25°C, RL = 1 kΩ, RT = 49.9 Ω)
Gain RF (Ω) RG (Ω)
−3 dB SS BW (MHz),
VOUT = 100 mV p-p
Slew Rate (V/μs),
VOUT = 2 V Step
ADA4898-1 Voltage
Noise (nV/√Hz), RTO
Total System Noise
(nV/√Hz), RTO
+1 0 N/A 65 55 0.9 1.29
+2 100 100 30 50 1.8 3.16
+5 100 24.9 9 45 4.5 7.07
ADA4898-1
Rev. B | Page 17 of 20
NOISE
To analyze the noise performance of an amplifier circuit, identify
the noise sources, and then determine if each source has a
significant contribution to the overall noise performance of the
amplifier. To simplify the noise calculations, noise spectral densities
were used rather than actual voltages to leave bandwidth out of the
expressions. Noise spectral density, which is generally expressed
in nV/√Hz, is equivalent to the noise in a 1 Hz bandwidth.
The noise model shown in Figure 48 has six individual noise
sources: the Johnson noise of the three resistors, the op amp
voltage noise, and the current noise in each input of the amplifier.
Each noise source has its own contribution to the noise at the
output. Noise is generally specified referred to input (RTI), but
it is often simpler to calculate the noise referred to the output
(RTO) and then divide by the noise gain to obtain the RTI noise.
GAIN FROM
B TO OUTPUT = – R2
R1
GAIN FROM
A TO OUTPUT =
NOISE GAIN =
NG = 1 + R2
R1
I
N–
V
N
V
N, R1
V
N, R3
R1
R2
I
N+
R3
4kTR2
4kTR1
4kTR3
V
N, R2
B
A
V
N2
+ 4kTR3 + 4kTR1 R2
2
R1 + R2
I
N+2
R3
2
+ I
N–2
R1 × R2
2
+ 4kTR2 R1
2
R1 + R2 R1 + R2
RTI NOISE =
RTO NOISE = NG × RTI NOISE
V
OUT
+
0
7037-045
Figure 48. Op Amp Noise Analysis Model
All resistors have a Johnson noise that is calculated by
)(4kBTR
where:
k is Boltzmann’s constant (1.38 × 10−23 J/K).
B is the bandwidth in Hertz.
T is the absolute temperature in Kelvin.
R is the resistance in ohms.
A simple relationship that is easy to remember is that a 50 Ω
resistor generates a Johnson noise of 1 nV/√Hz at 25°C.
In applications where noise sensitivity is critical, care must
be taken not to introduce other significant noise sources to
the amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
performance for the amplifier and associated resistors is shown
in Table 7.
CIRCUIT CONSIDERATIONS
Careful and deliberate attention to detail when laying out the
ADA4898-1 board yields optimal performance. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier.
PCB LAYOUT
Because the ADA4898-1 bandwidth extends up to 65 MHz, it
is essential that RF board layout techniques be employed. All
ground and power planes under the pins of the ADA4898-1
should be cleared of copper to prevent the formation of parasitic
capacitance between the input pins to ground and the output pins
to ground. A single mounting pad on a SOIC footprint can add
as much as 0.2 pF of capacitance to ground if the ground plane
is not cleared from under the mounting pads.
POWER SUPPLY BYPASSING
Power supply bypassing for the ADA4898-1 has been optimized
for frequency response and distortion performance. Figure 46
shows the recommended values and location of the bypass
capacitors. Power supply bypassing is critical for stability,
frequency response, distortion, and PSR performance. The 0.1 µF
capacitors shown in Figure 46 should be as close to the supply
pins of the ADA4898-1 as possible. The 10 µF electrolytic
capacitors should be adjacent to but not necessarily close to
the 0.1 µF capacitors. The capacitor between the two supplies
helps improve PSR and distortion performance. In some cases,
additional paralleled capacitors can help improve frequency
and transient response.
GROUNDING
Ground and power planes should be used where possible. Ground
and power planes reduce the resistance and inductance of the
power planes and ground returns. The returns for the input
and output terminations, bypass capacitors, and RG should all
be kept as close to the ADA4898-1 as possible. The output load
ground and the bypass capacitor grounds should be returned to
the same point on the ground plane to minimize parasitic trace
inductance, ringing, and overshoot and to improve distortion
performance.
The ADA4898-1 package features an exposed paddle. For optimum
electrical and thermal performance, solder this paddle to negative
supply plane. For more information on high speed circuit design,
see A Practical Guide to High-Speed Printed-Circuit-Board
Layout, Analog Dialogue: PCB Layout at www.analog.com.
ADA4898-1
Rev. B | Page 18 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
072808-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.050)
0.40 (0.016)
0.50 (0.020)
0.25 (0.010) 45°
8°
0°
1.75 (0.069)
1.35 (0.053)
1.65 (0.065)
1.25 (0.049)
SEATING
PLANE
85
41
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
1.27 (0.05)
BSC
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
0.51 (0.020)
0.31 (0.012)
COPLANARITY
0.10
TOP VIEW
2.29 (0.090)
BOTTOM VIEW
(PINS UP)
2.29 (0.090)
0.10 (0.004)
MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 49. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
(RD-8-1)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model Temperature Range Package Description Package Option Ordering Quantity
ADA4898-1YRDZ1 −40°C to +105°C 8-Lead SOIC_N_EP RD-8-1 1
ADA4898-1YRDZ-R71 −40°C to +105°C 8-Lead SOIC_N_EP RD-8-1 1,000
ADA4898-1YRDZ-RL1 −40°C to +105°C 8-Lead SOIC_N_EP RD-8-1 2,500
1 Z = RoHS Compliant Part.
ADA4898-1
Rev. B | Page 19 of 20
NOTES
ADA4898-1
Rev. B | Page 20 of 20
NOTES
©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07037-0-6/09(B)