MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com MIXED SIGNAL MICROCONTROLLER FEATURES 1 * * * * * * * * Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption - Active Mode: 250 A at 1 MHz, 2.2 V - Standby Mode: 0.7 A - Off Mode (RAM Retention): 0.1 A Ultra-Fast Wake-Up From Standby Mode in Less Than 1 s 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations - Internal Frequencies up to 16 MHz With Four Calibrated Frequencies to 1% - 32-kHz Crystal - High-Frequency Crystal up to 16 MHz - Resonator - External Digital Clock Source 16-Bit Timer_A With Three Capture/Compare Registers On-Chip Comparator for Analog Signal Compare Function or Slope Analog-to-Digital (A/D) Conversion Brownout Detector * * * * * * Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse Bootstrap Loader On Chip Emulation Module Family Members: - MSP430F2101 - 1KB + 256B Flash Memory - 128B RAM - MSP430F2111 - 2KB + 256B Flash Memory - 128B RAM - MSP430F2121 - 4KB + 256B Flash Memory - 256B RAM - MSP430F2131 - 8KB + 256B Flash Memory - 256B RAM Available in a 20-Pin Plastic Small-Outline Wide Body (SOWB) Package, 20-Pin Plastic Small-Outline Thin (TSSOP) Package, 20-Pin TVSOP Package, and 24-Pin QFN Package For Complete Module Descriptions, See the MSP430x2xx Family User's Guide (SLAU144) DESCRIPTION The Texas Instruments MSP430 family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 s. The MSP430x21x1 series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer, versatile analog comparator, and sixteen I/O pins. Typical applications include sensor systems that capture analog signals, convert themto digital values, and then process the data for display or for transmission to a host system. Stand-alone RF sensor front end is another area of application. The analog comparator provides slope A/D conversion capability. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Table 1. Available Options PACKAGED DEVICES TA -40C to 85C -40C to 105C PLASTIC 20-PIN SOWB (DW) PLASTIC 20-PIN TSSOP (PW) PLASTIC 20-PIN TVSOP (DGV) PLASTIC 24-PIN QFN (RGE) MSP430F2101IDW MSP430F2101IPW MSP430F2101IDGV MSP430F2101IRGE MSP430F2111IDW MSP430F2111IPW MSP430F2111IDGV MSP430F2111IRGE MSP430F2121IDW MSP430F2121IPW MSP430F2121IDGV MSP430F2121IRGE MSP430F2131IDW MSP430F2131IPW MSP430F2131IDGV MSP430F2131IRGE MSP430F2101TDW MSP430F2101TPW MSP430F2101TDGV MSP430F2101TRGE MSP430F2111TDW MSP430F2111TPW MSP430F2111TDGV MSP430F2111TRGE MSP430F2121TDW MSP430F2121TPW MSP430F2121TDGV MSP430F2121TRGE MSP430F2131TDW MSP430F2131TPW MSP430F2131TDGV MSP430F2131TRGE Development Tool Support All MSP430 microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging and programming through easy-to-use development tools. Recommended hardware options include: * Debugging and Programming Interface with Target Board - MSP-FET430U28 (PW package) * Debugging and Programming Interface - MSP-FET430UIF (USB) - MSP-FET430PIF (Parallel Port) * Target Board - MSP-TS430PW28 (PW package) * Production Programmer - MSP-GANG430 2 Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Device Pinout DW, PW, or DGV PACKAGE (TOP VIEW) TEST VCC P2.5/CA5 VSS XOUT/P2.7/CA7 XIN/P2.6/CA6 RST/NMI P2.0/ACLK/CA2 P2.1/INCLK/CA3 P2.2/CAOUT/TA0/CA4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2/CA1 P2.3/TA1/CA0 P2.5/CA5 VCC TEST P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK NC RGE PACKAGE (TOP VIEW) 24 23 22 21 20 19 18 1 17 2 16 3 Exposed 4 Thermal Pad 15 5 14 6 13 7 8 9 10 11 12 P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.1/INCLK/CA3 P2.2/CAOUT/TA0/CA4 NC P2.3/TA1/CA0 P2.4/TA2/CA1 NC NC VSS XOUT/P2.7/CA7 XIN/P2.6/CA6 RST/NMI P2.0/ACLK/CA2 A. NC = Not internally connected B. Exposed thermal pad connection to VSS recommended. Copyright (c) 2004-2011, Texas Instruments Incorporated 3 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Functional Block Diagram VCC VSS P1.x, JTAG 8 P2.x, XIN/XOUT 8 XOUT XIN Basic Clock System+ ACLK SMCLK MCLK 16MHz CPU incl. 16 Registers Flash RAM 8kB 4kB 2kB 1kB 256B 256B 128B 128B Port P1 Comparator _A+ 8 Channel Input Mux 8 I/ O Interrupt capability, pullup/down resistors Port P2 8 I/ O Interrupt capability, pullup/down resistors MAB MDB Emulation (2BP) JTAG Interface Brownout Protection Watchdog WDT+ 15/16 Bit Timer_A3 3 CC Registers RST/NMI NOTE: See port schematics section for detailed I/O information. 4 Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Table 2. Terminal Functions TERMINAL NO. DW, PW, or DGV RGE P1.0/TACLK 13 13 I/O P1.1/TA 14 14 I/O P1.2/TA1 15 15 I/O P1.3/TA2 16 16 I/O P1.4/SMCLK/TCK 17 17 I/O P1.5/TA/TMS 18 18 I/O P1.6/TA1/TDI/TCLK 19 20 I/O P1.7/TA2/TDO/TDI (1) 20 21 I/O P2.0/ACLK/CA2 8 6 I/O P2.1/INCLK/CA3 9 7 I/O P2.2/CAOUT/TA/CA4 10 8 I/O NAME I/O DESCRIPTION General-purpose digital I/O pin Timer_A, clock signal TACLK input General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin / SMCLK signal output Test Clock input for device programming and test General-purpose digital I/O pin / Timer_A, compare: Out0 output Test Mode Select input for device programming and test General-purpose digital I/O pin / Timer_A, compare: Out1 output Test Data Input or Test Clock Input for programming and test General-purpose digital I/O pin / Timer_A, compare: Out2 output Test Data Output or Test Data Input for programming and test General-purpose digital I/O pin / ACLK output Comparator_A+, CA2 input General-purpose digital I/O pin / Timer_A, clock signal at INCLK Comparator_A+, CA3 input General-purpose digital I/O pin Timer_A, capture: CCI0B input/BSL receive Comparator_A+, output / CA4 input P2.3/CA0/TA1 11 10 I/O P2.4/CA1/TA2 12 11 I/O P2.5/CA5 3 24 I/O General-purpose digital I/O pin / Timer_A, compare: Out1 output Comparator_A+, CA0 input General-purpose digital I/O pin / Timer_A, compare: Out2 output Comparator_A+, CA1 input General-purpose digital I/O pin Comparator_A+, CA5 input Input terminal of crystal oscillator XIN/P2.6/CA6 6 4 I/O General-purpose digital I/O pin Comparator_A+, CA6 input Output terminal of crystal oscillator XOUT/P2.7/CA7 (2) 5 3 I/O RST/NMI 7 5 I Reset or nonmaskable interrupt input TEST 1 22 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. VCC 2 23 Supply voltage VSS 4 2 Ground reference NA Pad General-purpose digital I/O pin Comparator_A+, CA7 input QFN Pad (1) (2) NA QFN package thermal pad. Connect to VSS. TDO or TDI is selected via JTAG instruction. If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. Copyright (c) 2004-2011, Texas Instruments Incorporated 5 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430TM CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 SR/CG1/R2 Status Register Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 Instruction Set General-Purpose Register R11 The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 3 shows examples of the three types of instruction formats; Table 4 shows the address modes. General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses and can be handled with all instructions. Table 3. Instruction Word Formats EXAMPLE OPERATION Dual operands, source-destination INSTRUCTION FORMAT ADD R4,R5 R4 + R5 R5 Single operands, destination only CALL R8 PC (TOS), R8 PC JNE Jump-on-equal bit = 0 Relative jump, unconditional/conditional Table 4. Address Mode Descriptions ADDRESS MODE SYNTAX EXAMPLE OPERATION MOV Rs,Rd MOV R10,R11 R10 R11 Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) M(6+R6) Symbolic (PC relative) MOV EDE,TONI M(EDE) M(TONI) Absolute MOV &MEM,&TCDAT M(MEM) M(TCDAT) Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) M(Tab+R6) Indirect autoincrement MOV @Rn+,Rm MOV @R10+,R11 M(R10) R11 R10 + 2 R10 Immediate MOV #X,TONI MOV #45,TONI #45 M(TONI) 6 D (2) Register (1) (2) S (1) S = source D = destination Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 www.ti.com SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 Operating Modes The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: * Active mode (AM) - All clocks are active. * Low-power mode 0 (LPM0) - CPU is disabled. - ACLK and SMCLK remain active. MCLK is disabled. * Low-power mode 1 (LPM1) - CPU is disabled ACLK and SMCLK remain active. MCLK is disabled. - DCO dc-generator is disabled if DCO not used in active mode. * Low-power mode 2 (LPM2) - CPU is disabled. - MCLK and SMCLK are disabled. - DCO dc-generator remains enabled. - ACLK remains active. * Low-power mode 3 (LPM3) - CPU is disabled. - MCLK and SMCLK are disabled. - DCO dc-generator is disabled. - ACLK remains active. * Low-power mode 4 (LPM4) - CPU is disabled. - ACLK is disabled. - MCLK and SMCLK are disabled. - DCO dc-generator is disabled. - Crystal oscillator is stopped. Copyright (c) 2004-2011, Texas Instruments Incorporated 7 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up. Table 5. Interrupt Vector Addresses INTERRUPT SOURCE INTERRUPT FLAG Power-up PORIFG External reset RSTIFG Watchdog WDTIFG Flash key violation KEYV (1) SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset 0xFFFE 31, highest 0xFFFC 30 0xFFFA 29 PC out of range (2) NMI NMIIFG (non)-maskable Oscillator fault OFIFG (non)-maskable Flash memory access violation ACCVIFG (1) (3) (non)-maskable 0xFFF8 28 Comparator_A+ CAIFG maskable 0xFFF6 27 Watchdog Timer+ WDTIFG maskable 0xFFF4 26 maskable 0xFFF2 25 maskable 0xFFF0 24 0xFFEE 23 0xFFEC 22 0xFFEA 21 0xFFE8 20 Timer_A3 Timer_A3 (1) (2) (3) (4) (5) (6) 8 TACCR0 CCIFG (4) TACCR2, TACCR1 CCIFG, TAIFG (1) (4) I/O port P2 (eight flags) P2IFG.0 to P2IFG.7 (1) (4) maskable 0xFFE6 19 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7 (1) (4) maskable 0xFFE4 18 0xFFE2 17 0xFFE0 16 See (5) 0xFFDE 15 See (6) 0xFFDC to 0xFFC0 14 to 0, lowest Multiple source flags A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF) or from within unused address range. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Interrupt flags are located in the module. This location is used as bootstrap loader security key (BSLSKEY). A value of 0xAA55 at this location disables the BSL completely. A value of 0x0 disables the erasure of the flash if an invalid password is supplied. The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if necessary. Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw rw-0, 1 rw-(0), (1) Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device. Table 6. Interrupt Enable 1 Address 7 6 00h WDTIE OFIE NMIIE ACCVIE 5 4 ACCVIE rw-0 3 2 1 0 NMIIE OFIE WDTIE rw-0 rw-0 rw-0 Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable Table 7. Interrupt Enable 2 Address 7 6 7 6 5 4 3 2 1 0 01h Table 8. Interrupt Flag Register 1 Address 5 02h WDTIFG OFIFG RSTIFG PORIFG NMIIFG 4 3 2 1 0 NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. Flag set on oscillator fault External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up. Power-on reset interrupt flag. Set on VCC power up. Set via RST/NMI pin Table 9. Interrupt Flag Register 2 Address 7 6 5 4 3 2 1 0 03h Copyright (c) 2004-2011, Texas Instruments Incorporated 9 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Memory Organization Table 10. Memory Organization MSP430F2101 MSP430F2111 MSP430F2121 Size 1 KB Flash 2 KB Flash 4 KB Flash 8 KB Flash Main: interrupt vector Flash 0xFFFF to 0xFFE0 0xFFFF to 0xFFE0 0xFFFF to 0xFFE0 0xFFFF to 0xFFE0 Main: code memory Flash 0xFFFF to 0xFC00 0xFFFF to 0xF800 0xFFFF to 0xF000 0xFFFF to 0xE000 Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte Flash 0x10FF to 0x1000 0x10FF to 0x1000 0x10FF to 0x1000 0x10FF to 0x1000 Size 1 KB 1 KB 1 KB 1 KB ROM 0x0FFF to 0x0C00 0x0FFF to 0x0C00 0x0FFF to 0x0C00 0x0FFF to 0x0C00 Size 128 B 128 B 256 Byte 256 Byte 0x027F to 0x0200 0x027F to 0x0200 0x02FF to 0x0200 0x02FF to 0x0200 16-bit 0x01FF to 0x0100 0x01FF to 0x0100 0x01FF to 0x0100 0x01FF to 0x0100 8-bit 0x0FF to 0x010 0x0FF to 0x010 0x0FF to 0x010 0x0FF to 0x010 0x0F to 0x00 0x0F to 0x00 0x0F to 0x00 0x0F to 0x00 Memory Boot memory RAM Peripherals 8-bit SFR MSP430F2131 Bootstrap Loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to theMSP430memoryvia theBSLis protected by user-defined password.Abootstrap loader security key is provided at address 0FFDEh to disable the BSL completely or to disable the erasure of the flash if an invalid password is supplied. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide, literature number SLAU319. Table 11. BSL Keys BSLKEY DESCRIPTION 00000h Erasure of flash disabled if an invalid password is supplied 0AA55h BSL disabled any other value BSL enabled Table 12. BSL Function Pins BSL FUNCTION DW, PW, DGV PACKAGE PINS RGE PACKAGE PINS Data transmit 14 - P1.1 14 - P1.1 Data receive 10 - P2.2 8 - P2.2 Flash Memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: * Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. * Segments 0 to n may be erased in one step, or each segment may be individually erased. * Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. * Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required. 10 Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144). Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 s. The basic clock module provides the following clock signals: * Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal * Main clock (MCLK), the system clock used by the CPU * Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules Table 13. DCO Calibration Data, Provided From Factory In Flash Info Memory Segment A DCO FREQUENCY CALIBRATION REGISTER SIZE CALBC1_1MHZ byte 0x010FF CALBC0_1MHZ byte 0x010FE CALBC1_8MHZ byte 0x010FD CALBC0_8MHZ byte 0x010FC CALBC1_12MHZ byte 0x010FB CALBC0_12MHZ byte 0x010FA CALBC1_16MHZ byte 0x010F9 CALBC0_16MHZ byte 0x010F8 1 MHz 8 MHz 12 MHz 16 MHz ADDRESS Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. Digital I/O There are two 8-bit I/O ports implemented--ports P1 and P2. * All individual I/O bits are independently programmable. * Any combination of input, output, and interrupt condition is possible. * Edge-selectable interrupt input capability for all eight bits of port P1 and P2. * Read/write access to port-control registers is supported by all instructions. * Each I/O has an individually programmable pullup/pulldown resistor. Watchdog Timer (WDT+) The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. Comparator_A+ The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. Copyright (c) 2004-2011, Texas Instruments Incorporated 11 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 14. Timer_A3 Signal Connections INPUT PIN NUMBER DW, PW, DGV RGE DEVICE INPUT SIGNAL 13 - P1.0 13 - P1.0 TACLK TACLK ACLK ACLK SMCLK SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER DW, PW, DGV RGE 9 - P2.1 7 - P2.1 INCLK INCLK 14 - P1.1 14 - P1.1 TA CCI0A 14 - P1.1 14 - P1.1 10 - P2.2 8 - P2.2 TA CCI0B 18 - P1.5 18 - P1.5 VSS GND 11 - P2.3 10 - P2.3 15 - P1.2 15 - P1.2 19 - P1.6 20 - P1.6 15 - P1.2 16 - P1.3 12 MODULE INPUT NAME 15 - P1.2 16 - P1.3 VCC VCC TA1 CCI1A CAOUT (internal) CCI1B VSS GND CCR0 CCR1 TA TA1 VCC VCC TA2 CCI2A 12 - P2.4 11 - P2.4 ACLK (internal) CCI2B 16 - P1.3 16 - P1.3 VSS GND 20 - P1.7 21 - P1.7 VCC VCC CCR2 TA2 Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Peripheral File Map Table 15. Peripherals With Word Access MODULE Timer_A SHORT NAME ADDRESS OFFSET Capture/compare register REGISTER NAME TACCR2 0x0176 Capture/compare register TACCR1 0x0174 Capture/compare register TACCR0 0x0172 TAR 0x0170 Capture/compare control TACCTL2 0x0166 Capture/compare control TACCTL1 0x0164 Capture/compare control TACCTL0 0x0162 Timer_A3 register Timer_A3 control TACTL 0x0160 TAIV 0x012E Flash control 3 FCTL3 0x012C Flash control 2 FCTL2 0x012A Flash control 1 FCTL1 0x0128 WDTCTL 0x0120 SHORT NAME ADDRESS OFFSET CAPD 0x005B CACTL2 0x005A Timer_A3 interrupt vector Flash Memory Watchdog Timer+ Watchdog/timer control Table 16. Peripherals With Byte Access MODULE Comparator_A+ REGISTER NAME Comparator_A port disable Comparator_A control 2 Comparator_A control 1 Basic Clock Port P2 CACTL1 0x0059 Basic clock system control 3 BCSCTL3 0x0053 Basic clock system control 2 BCSCTL2 0x0058 Basic clock system control 1 BCSCTL1 0x0057 DCO clock frequency control DCOCTL 0x0056 Port P2 resistor enable P2REN 0x002F Port P2 selection P2SEL 0x002E P2IE 0x002D Port P2 interrupt edge select P2IES 0x002C Port P2 interrupt flag P2IFG 0x002B Port P2 direction P2DIR 0x002A Port P2 output P2OUT 0x0029 P2IN 0x0028 Port P1 resistor enable P1REN 0x0027 Port P1 selection P1SEL 0x0026 P1IE 0x0025 Port P1 interrupt edge select P1IES 0x0024 Port P1 interrupt flag P1IFG 0x0023 Port P1 direction P1DIR 0x0022 Port P1 output P1OUT 0x0021 Port P1 input P1IN 0x0020 SFR interrupt flag 2 IFG2 0x0003 SFR interrupt flag 1 IFG1 0x0002 SFR interrupt enable 2 IE2 0x0001 SFR interrupt enable 1 IE1 0x0000 Port P2 interrupt enable Port P2 input Port P1 Port P1 interrupt enable Special Function Copyright (c) 2004-2011, Texas Instruments Incorporated 13 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS Voltage applied to any pin -0.3 V to 4.1 V (2) -0.3 V to (VCC + 0.3 V) 2 mA Diode current at any device terminal Storage temperature, Tstg (1) (3) Unprogrammed device -55C to 150C Programmed device -55C to 150C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. (2) (3) Recommended Operating Conditions (1) MIN VCC Supply voltage, AVCC = DVCC = VCC VSS Supply voltage, AVSS = DVSS = VSS TA Operating free-air temperature fSYSTEM Processor frequency (maximum MCLK frequency) (2) (1) (see Figure 1) (1) (2) NOM MAX During program execution 1.8 3.6 During flash memory programming 2.2 3.6 0 UNIT V V I version -40 85 T version -40 105 VCC = 1.8 V, Duty cycle = 50% 10% 0 6 VCC = 2.7 V, Duty cycle = 50% 10% 0 12 VCC 3.3 V, Duty cycle = 50% 10% 0 16 C MHz Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Legend : System Frequency -MHz 16 MHz Supply voltage range during flash memory programming 12 MHz Supply voltage range during program execution 6 MHz 1.8 V 2.2 V 2.7 V 3.3 V 3.6 V Supply Voltage - V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Operating Area 14 Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Active Mode Supply Current (into DVCC + AVCC ) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER IAM,1MHz IAM,1MHz IAM,4kHz IAM,100kHz (1) (2) TEST CONDITIONS TA VCC MIN TYP MAX 2.2 V 250 300 Active mode (AM) current (1 MHz) fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32768 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 3V 350 410 2.2 V 200 Active mode (AM) current (1 MHz) fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32768 Hz, Program executes in RAM, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 3V 300 Active mode (AM) current (4 kHz) fMCLK = fSMCLK = fACLK = 32768 Hz / 8 = 4096 Hz, fDCO = 0 Hz, Program executes in flash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0 -40C to 85C 3 3V 105C A A 5 6 -40C to 85C fMCLK = fSMCLK = fDCO(0, 0) 100 kHz, fACLK = 0 Hz, Program executes in flash, RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1 Active mode (AM) current (100 kHz) 2 2.2 V 105C UNIT 9 A 9 2.2 V 60 85 3V 72 95 A All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Typical Characteristics - Active-Mode Supply Current (Into VCC) ACTIVE-MODE CURRENT vs SUPPLY VOLTAGE TA = 25C ACTIVE-MODE CURRENT vs DCO FREQUENCY 7.0 5.0 Active ModeCurrent - mA Active Mode Current - mA 5.0 fDCO = 16 MHz 6.0 fDCO = 12 MHz 4.0 fDCO = 8 MHz 3.0 2.0 4.0 TA = 85C TA = 25C 3.0 VCC = 3 V 2.0 TA = 85C TA = 25C 1.0 VCC = 2.2 V 1.0 fDCO = 1 MHz 0.0 1.5 0.0 2.0 2.5 3.0 VCC - Supply Voltage - V Figure 2. Copyright (c) 2004-2011, Texas Instruments Incorporated 3.5 4.0 0 4 8 12 16 fDCO - DCO Frequency - MHz Figure 3. 15 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ILPM0,1MHz ILPM0,100kHz ILPM2 TEST CONDITIONS TA VCC 65 80 Low-power mode 0 (LPM0) current (3) 3V 85 100 2.2 V 37 48 Low-power mode 0 (LPM0) current (3) fMCLK = 0 MHz, fSMCLK = fDCO(0, 0) 100 kHz, fACLK = 0 Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1 3V 41 52 22 29 Low-power mode 2 (LPM2) current (4) fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 -40C to 85C 105C 2.2 V -40C to 85C 105C 3V Low-power mode 3 (LPM3) current (4) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (3) (4) (5) 16 Low-power mode 4 (LPM4) current (5) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 32 1 2.3 105C 3 6 -40C 0.9 1.2 0.9 1.2 1.6 2.8 3V 105C 3 7 -40C 0.1 0.5 0.1 0.5 0.8 1.9 2 4 25C 85C 105C 2.2 V/3 V A A 1.2 1.6 25C A 34 0.7 2.2 V UNIT 31 25 0.7 85C 85C (1) (2) MAX 2.2 V 25C ILPM4 TYP fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 -40C ILPM3,LFXT1 MIN A A All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Current for brownout and WDT clocked by SMCLK included. Current for brownout and WDT clocked by ACLK included. Current for brownout included. Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Schmitt-Trigger Inputs (Ports P1, P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIT+ TEST CONDITIONS Positive-going input threshold voltage VCC Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ - VIT- ) RPull Pullup/pulldown resistor For pullup: VIN = VSS, For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC TYP MAX 0.45 VCC 0.75 VCC 1 1.65 1.35 2.25 0.25 VCC 0.55 VCC 2.2 V 0.55 1.20 3V 0.75 1.65 2.2 V 0.2 1 3V 0.3 1 2.2 V 3V VIT- MIN 20 35 UNIT V V V 50 k 5 pF Inputs (Ports P1, P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) External interrupt timing TEST CONDITIONS VCC Port P1, P2: P1.x to P2.x, External trigger pulse width to set interrupt flag (1) 2.2 V/3 V MIN MAX UNIT 20 ns An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set with trigger signals shorter than t(int). Leakage Current (Ports P1, P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) High-impedance leakage current TEST CONDITIONS (1) (2) VCC 2.2 V/3 V MIN MAX UNIT 50 nA The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. Copyright (c) 2004-2011, Texas Instruments Incorporated 17 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Outputs (Ports P1, P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IOH(max) = -1.5 mA VOH High-level output voltage 2.2 V IOH(max) = -6 mA (2) IOH(max) = -1.5 mA (1) 3V IOH(max) = -6 mA (2) IOL(max) = 1.5 mA VOL Low-level output voltage (2) MIN MAX VCC - 0.25 VCC VCC - 0.6 VCC VCC - 0.25 VCC VCC - 0.6 VCC VSS VSS + 0.25 (1) 2.2 V IOL(max) = 6 mA (2) IOL(max) = 1.5 mA (1) 3V IOL(max) = 6 mA (2) (1) VCC (1) VSS VSS + 0.6 VSS VSS + 0.25 VSS VSS + 0.6 UNIT V V The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. Output Frequency (Ports P1, P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fPx.y Port output frequency (with load) P1.4/SMCLK, CL = 20 pF, RL = 1 k (1) (2) fPort_CLK Clock output frequency P2.0/ACLK, P1.4/SMCLK, CL = 20 pF (2) (1) (2) 18 MIN MAX 2.2 V 10 3V 12 2.2 V 12 3V 16 UNIT MHz MHz Alternatively, a resistive divider with two 0.5-k resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Typical Characteristics - Outputs One output loaded at a time. TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P2.4 TA = 25C 20.0 I OL - Typical Low-Level Output Current - mA I OL - Typical Low-Level Output Current - mA 25.0 TA = 85C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P2.4 40.0 TA = 85C 30.0 20.0 10.0 0.0 0.0 2.5 VOL - Low-Level Output Voltage - V 0.5 1.0 1.5 2.0 2.5 3.0 Figure 4. Figure 5. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 I OH - Typical High-Level Output Current - mA VCC = 2.2 V P2.4 -5.0 -10.0 -15.0 -20.0 -25.0 0.0 3.5 VOL - Low-Level Output Voltage - V 0.0 I OH - Typical High-Level Output Current - mA TA = 25C TA = 85C TA = 25C 0.5 1.0 1.5 2.0 VOH - High-Level Output Voltage - V Figure 6. Copyright (c) 2004-2011, Texas Instruments Incorporated 2.5 VCC = 3 V P2.4 -10.0 -20.0 -30.0 -40.0 -50.0 0.0 TA = 85C TA = 25C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH - High-Level Output Voltage - V Figure 7. 19 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com POR/Brownout Reset (BOR) (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC(start) See Figure 8 dVCC /dt 3 V/s V(B_IT-) See Figure 8 through Figure 10 dVCC /dt 3 V/s Vhys(B_IT-) See Figure 8 dVCC /dt 3 V/s td(BOR) See Figure 8 t(reset) Pulse length needed at RST/NMI pin to accepted reset internally (1) (2) TA VCC MIN TYP MAX 0.7 x V(B_IT-) V 1.71 -40C to 85C 70 130 180 105C 70 130 210 2000 2.2 V/3 V 2 UNIT V mV s s The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT-) is 1.8 V. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. VCC Vhys(B_IT-) V(B_IT-) VCC(start) 1 0 t d(BOR) Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage 20 Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) - V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw - Pulse Width - s 1 ns t pw - Pulse Width - s Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) - V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.001 tf = tr 1 t pw - Pulse Width - s 1000 tf tr t pw - Pulse Width - s Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal Copyright (c) 2004-2011, Texas Instruments Incorporated 21 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Main DCO Characteristics * * * All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: faverage = 32 x fDCO(RSEL,DCO) x fDCO(RSEL,DCO+1) MOD x fDCO(RSEL,DCO) + (32 - MOD) x fDCO(RSEL,DCO+1) DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX RSELx < 14 1.8 3.6 RSELx = 14 2.2 3.6 UNIT VCC Supply voltage range 3.0 3.6 fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 2.2 V/3 V 0.06 0.14 MHz fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 2.2 V/3 V 0.07 0.17 MHz fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 2.2 V/3 V 0.10 0.20 MHz fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 2.2 V/3 V 0.14 0.28 MHz fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 2.2 V/3 V 0.20 0.40 MHz fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V 0.28 0.54 MHz fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 2.2 V/3 V 0.39 0.77 MHz fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 2.2 V/3 V 0.54 1.06 MHz fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 2.2 V/3 V 0.80 1.50 MHz fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 2.2 V/3 V 1.10 2.10 MHz fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 2.2 V/3 V 1.60 3.00 MHz fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 2.2 V/3 V 2.50 4.30 MHz fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 2.2 V/3 V 3.00 5.50 MHz fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 2.2 V/3 V 4.30 7.30 MHz fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 2.2 V/3 V 6.00 9.60 MHz fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 2.2 V/3 V 8.60 13.9 MHz fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V 12.0 18.5 MHz fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V 16.0 26.0 MHz SRSEL Frequency step between range RSEL and RSEL+1 SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO) 2.2 V/3 V 1.55 ratio SDCO Frequency step between tap DCO and DCO+1 SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO) 2.2 V/3 V 1.05 1.08 1.12 ratio Duty cycle Measured at P1.4/SMCLK 2.2 V/3 V 40 50 60 RSELx = 15 22 V % Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Calibrated DCO Frequencies - Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25C 3V -1 0.2 +1 25C 3V 0.990 1 1.010 MHz % fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms fCAL(8MHz) 8-MHz calibration value BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 25C 3V 7.920 8 8.080 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 25C 3V 11.88 12 12.12 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 25C 3V 15.84 16 16.16 MHz MAX UNIT Calibrated DCO Frequencies - Tolerance Over Temperature 0C to 85C over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fCAL(1MHz) fCAL(8MHz) fCAL(12MHz) fCAL(16MHz) TA VCC 1-MHz tolerance over temperature 0C to 85C 3V -2.5 0.5 +2.5 % 8-MHz tolerance over temperature 0C to 85C 3V -2.5 1 +2.5 % 12-MHz tolerance over temperature 0C to 85C 3V -2.5 1 +2.5 % 16-MHz tolerance over temperature 0C to 85C 3V -3 2 +3 % 2.2 V 0.97 1 1.03 3V 0.975 1 1.025 3.6 V 0.97 1 1.03 2.2 V 7.76 8 8.4 3V 7.8 8 8.2 3.6 V 7.6 8 8.24 2.2 V 11.7 12 12.3 3V 11.7 12 12.3 3.6 V 11.7 12 12.3 3V 15.52 16 16.48 15 16 16.48 1-MHz calibration value 8-MHz calibration value 12-MHz calibration value 16-MHz calibration value TEST CONDITIONS BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms 0C to 85C BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 0C to 85C BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 0C to 85C BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 0C to 85C Copyright (c) 2004-2011, Texas Instruments Incorporated 3.6 V MIN TYP MHz MHz MHz MHz 23 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25C 8-MHz tolerance over VCC 25C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 2 +3 % 1.8 V to 3.6 V -3 2 +3 % 25C 2.2 V to 3.6 V -3 2 +3 % 25C 3 V to 3.6 V -3 2 +3 % fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms 25C 1.8 V to 3.6 V 0.97 1 1.03 MHz fCAL(8MHz) 8-MHz calibration value BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 25C 1.8 V to 3.6 V 7.76 8 8.24 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 25C 2.2 V to 3.6 V 11.64 12 12.36 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 25C 3 V to 3.6 V 15 16 16.48 MHz MIN TYP MAX UNIT Calibrated DCO Frequencies - Overall Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TA VCC 1-MHz tolerance overall I: -40C to 85C T: -40C to 105C 1.8 V to 3.6 V -5 2 +5 % 8-MHz tolerance overall I: -40C to 85C T: -40C to 105C 1.8 V to 3.6 V -5 2 +5 % 12-MHz tolerance overall I: -40C to 85C T: -40C to 105C 2.2 V to 3.6 V -5 2 +5 % 16-MHz tolerance overall I: -40C to 85C T: -40C to 105C 3 V to 3.6 V -6 3 +6 % fCAL(1MHz) BCSCTL1 = CALBC1_1MHZ, 1-MHz DCOCTL = CALDCO_1MHZ, calibration value Gating time: 5 ms I: -40C to 85C T: -40C to 105C 1.8 V to 3.6 V 0.95 1 1.05 MHz fCAL(8MHz) BCSCTL1 = CALBC1_8MHZ, 8-MHz DCOCTL = CALDCO_8MHZ, calibration value Gating time: 5 ms I: -40C to 85C T: -40C to 105C 1.8 V to 3.6 V 7.6 8 8.4 MHz fCAL(12MHz) BCSCTL1 = CALBC1_12MHZ, 12-MHz DCOCTL = CALDCO_12MHZ, calibration value Gating time: 5 ms I: -40C to 85C T: -40C to 105C 2.2 V to 3.6 V 11.4 12 12.6 MHz fCAL(16MHz) BCSCTL1 = CALBC1_16MHZ, 16-MHz DCOCTL = CALDCO_16MHZ, calibration value Gating time: 2 ms I: -40C to 85C T: -40C to 105C 3 V to 3.6 V 15 16 17 MHz 24 TEST CONDITIONS Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Typical Characteristics - Calibrated 1-MHz DCO Frequency CALIBRATED 1-MHz FREQUENCY vs TEMPERATURE CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE 1.03 1.03 1.02 1.02 1.00 VCC = 3 V VCC = 2.2 V 0.99 Frequency - MHz Frequency - MHz VCC = 1.8 V 1.01 1.01 TA = 105C TA = 85C 1.00 TA = 25C 0.99 VCC = 3.6 V TA = -40C 0.98 0.97 -50 0.98 -25 0 25 50 TA - Temperature - C Figure 11. Copyright (c) 2004-2011, Texas Instruments Incorporated 75 100 0.97 1.5 2.0 2.5 3.0 3.5 4.0 VCC - Supply Voltage - V Figure 12. 25 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Wake-Up From Lower-Power Modes (LPM3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 (1) (2) UNIT 2 BCSCTL1 = CALBC1_8MHZ, DCO clock wake-up time DCOCTL = CALDCO_8MHZ from LPM3/4 (1) BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ 2.2 V/3 V 1.5 s 1 BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ tCPU,LPM3/4 MAX 3V CPU wake-up time from LPM3/4 (2) 1 1 / fMCLK + tClock,LPM3/4 The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK. Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4 DCO WAKE-UP TIME FROM LPM3 vs DCO FREQUENCY DCO Wake Time - s 10.00 RSELx = 0 to 11 RSELx = 12 to 15 1.00 0.10 0.10 1.00 10.00 DCO Frequency - MHz Figure 13. 26 Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Crystal Oscillator LFXT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 fLFXT1,LF,logic LFXT1 oscillator logic level square wave input frequency, XTS = 0, LFXT1Sx = 3 LF mode OALF Oscillation allowance for LF crystals CL,eff fFault,LF (1) (2) (3) (4) Integrated effective load capacitance, LF mode (2) XTS = 0, LFXT1Sx = 0 or 1 VCC MIN 1.8 V to 3.6 V 1.8 V to 3.6 V TYP MAX 32768 10000 32768 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 6 pF 500 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 12 pF 200 UNIT Hz 50000 Hz k XTS = 0, XCAPx = 0 1 XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 11 Duty cycle, LF mode XTS = 0, Measured at P2.0/ACLK, fLFXT1,LF = 32768 Hz 2.2 V/3 V 30 Oscillator fault frequency, LF mode (3) XTS = 0, LFXT1Sx = 3 (4) 2.2 V/3 V 10 50 pF 70 % 10000 Hz To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the crystal that is used. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Copyright (c) 2004-2011, Texas Instruments Incorporated 27 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Crystal Oscillator LFXT1, High-Frequency Mode (1) PARAMETER VCC MIN XTS = 1, LFXT1Sx = 0 1.8 V to 3.6 V LFXT1 oscillator crystal frequency, HF mode 1 XTS = 1, LFXT1Sx = 1 LFXT1 oscillator crystal frequency, HF mode 2 XTS = 1, LFXT1Sx = 2 fLFXT1,HF0 LFXT1 oscillator crystal frequency, HF mode 0 fLFXT1,HF1 fLFXT1,HF2 TEST CONDITIONS MAX UNIT 0.4 1 MHz 1.8 V to 3.6 V 1 4 MHz 1.8 V to 3.6 V 2 10 2.2 V to 3.6 V 2 12 3 V to 3.6 V fLFXT1,HF,logic OAHF CL,eff LFXT1 oscillator logic-level square-wave input frequency, HF mode Oscillation allowance for HF crystals (see Figure 14 and Figure 15) Integrated effective load capacitance, HF mode (2) (1) (2) (3) (4) (5) 28 Oscillator fault frequency 2 16 1.8 V to 3.6 V 0.4 10 2.2 V to 3.6 V 0.4 12 3 V to 3.6 V 0.4 16 XTS = 1, LFXT1Sx = 0, fLFXT1,HF = 1 MHz, CL,eff = 15 pF 2700 XTS = 1, LFXT1Sx = 1, fLFXT1,HF = 4 MHz, CL,eff = 15 pF 800 XTS = 1, LFXT1Sx = 2, fLFXT1,HF = 16 MHz, CL,eff = 15 pF 300 XTS = 1 (3) XTS = 1, Measured at P2.0/ACLK, fLFXT1,HF = 10 MHz Duty cycle, HF mode fFault,HF XTS = 1, LFXT1Sx = 3 XTS = 1, Measured at P2.0/ACLK, fLFXT1,HF = 16 MHz (4) TYP XTS = 1, LFXT1Sx = 3 (5) MHz 1 pF 40 50 60 40 50 60 2.2 V/3 V 2.2 V/3 V MHz % 30 300 kHz To improve EMI on the XT2 oscillator the following guidelines should be observed: (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag. Measured with logic-level input frequency, but also applies to operation with crystals. Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1) OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25C OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25C 800 100000 LFXT1Sx = 3 XT Oscillator Supply Current - A Oscillation Allowance - W 700 10000 1000 LFXT1Sx = 3 100 LFXT1Sx = 1 LFXT1Sx = 2 600 500 400 300 LFXT1Sx = 2 200 100 LFXT1Sx = 1 10 0.1 1 10 Crystal Frequency - MHz Figure 14. Copyright (c) 2004-2011, Texas Instruments Incorporated 100 0 0 4 8 12 16 20 Crystal Frequency - MHz Figure 15. 29 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTA Timer_A clock frequency Internal: SMCLK, ACLK External: TACLK, INCLK Duty cycle = 50% 10% tTA,cap Timer_A capture timing TA0, TA1, TA2 VCC MIN TYP MAX 2.2 V 10 3V 16 2.2 V/3 V 20 UNIT MHz ns Comparator_A+ (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS I(DD) CAON = 1, CARSEL = 0, CAREF = 0 I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 TYP MAX 2.2 V VCC MIN 25 40 3V 45 60 2.2 V 30 50 3V 45 71 UNIT A A V(IC) Common-mode input voltage range CAON = 1 2.2 V/3 V 0 V(Ref025) (Voltage at 0.25 VCC node) / VCC PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 2.2 V/3 V 0.23 0.24 0.25 V(Ref050) (Voltage at 0.5 VCC node) / VCC PCA0 = 1, CARSEL = 1, CAREF = 2, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 2.2 V/3 V 0.47 0.48 0.5 See Figure 19 and Figure 20 PCA0 = 1, CARSEL = 1, CAREF = 3, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2, TA = 85C 2.2 V 390 480 540 V(RefVT) 3V 400 490 550 V(offset) Offset voltage (2) 2.2 V/3 V -30 30 mV Vhys Input hysteresis 2.2 V/3 V 0 0.7 1.4 mV TA = 25C, Overdrive 10 mV, Without filter: CAF = 0 (3) (see Figure 16 and Figure 17) 2.2 V 80 165 300 3V 70 120 240 TA = 25C, Overdrive 10 mV, With filter: CAF = 1 (3) (see Figure 16 and Figure 17) 2.2 V 1.4 1.9 2.8 3V 0.9 1.5 2.2 t(response) (1) (2) (3) 30 Response time (low-high and high-low) CAON = 1 VCC - 1 V mV ns s The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The two successive measurements are then summed together. Response time measured at P2.2/CAOUT. Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com 0V VCC 0 1 CAF CAON To Internal Modules Low-Pass Filter + _ V+ V- 0 0 1 1 CAOUT Set CAIFG Flag 2.0 s Figure 16. Comparator_A+ Module Block Diagram VCAOUT Overdrive V- 400 mV t (response) V+ Figure 17. Overdrive Definition CASHORT CA0 CA1 1 VIN + - Comparator_A+ CASHORT = 1 IOUT = 10A Figure 18. Comparator_A+ Short Resistance Test Condition Copyright (c) 2004-2011, Texas Instruments Incorporated 31 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Typical Characteristics - Comparator_A+ V(RefVT) vs TEMPERATURE VCC = 2.2 V V(RefVT) vs TEMPERATURE VCC = 2.2 V 650 650 VCC = 2.2 V 600 V(REFVT) - Reference Volts - mV V(REFVT) - Reference Volts - mV VCC = 3 V Typical 550 500 450 400 -45 -25 15 55 75 35 -5 TA - Free-Air Temperature - C 600 Typical 550 500 450 400 -45 95 -25 15 55 75 35 -5 TA - Free-Air Temperature - C Figure 19. Figure 20. SHORT RESISTANCE vs VIN/VCC 100 Short Resistance - kW 95 VCC = 1.8 V VCC = 2.2 V VCC = 3 V 10 VCC = 3.6 V 1 0 0.2 0.4 0.6 0.8 1.0 VIN/VCC - Normalized Input Voltage - V/V Figure 21. 32 Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC (PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 3 5 mA IERASE Supply current from VCC during erase 2.2 V/3.6 V 3 7 mA 10 ms (1) tCPT Cumulative program time tCMErase Cumulative mass erase time 2.2 V/3.6 V 2.2 V/3.6 V 20 ms 104 Program/erase endurance 105 cycles tRetention Data retention duration TJ = 25C tWord Word or byte program time See (2) 30 tFTG tBlock, 0 Block program time for first byte or word See (2) 25 tFTG tBlock, 1-63 Block program time for each additional byte or word See (2) 18 tFTG Block program end-sequence wait time See (2) 6 tFTG Mass erase time See (2) 10593 tFTG See (2) 4819 tFTG tBlock, End tMass Erase tSeg Erase (1) (2) Segment erase time 100 years The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG). RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage (1) TEST CONDITIONS MIN CPU halted MAX UNIT 1.6 V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. JTAG Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fTCK TCK input frequency (1) RInternal Internal pulldown resistance on TEST (1) VCC MIN TYP MAX UNIT 2.2 V 0 5 MHz 3V 0 10 MHz 2.2 V/3 V 25 60 90 k MAX fTCK may be restricted to meet the timing requirements of the module selected. JTAG Fuse (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TA MIN VCC(FB) Supply voltage during fuse-blow condition PARAMETER 25C 2.5 VFB Voltage level on TEST for fuse blow 25C 6 IFB Supply current into TEST during fuse blow 25C 100 mA tFB Time to blow fuse 25C 1 ms (1) UNIT V 7 V Once the fuse is blown, no further access to the JTAG/Test and emulation features is possible, and the JTAG block is switched to bypass mode. Copyright (c) 2004-2011, Texas Instruments Incorporated 33 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 P1OUT.x 0 1 0 1 1 Direction 0: Input 1: Output 1 Module XOUT DVSS DVCC P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1SEL.x P1IN.x EN Module XIN D P1IE.x P1IRQ.x EN Q P1IFG.x P1SEL.x P1IES.x Set Interrupt Edge Select Table 17. Port P1 (P1.0 to P1.3) Pin Functions PIN NAME (P1.x) x FUNCTION P1.0 P1.0/TACLK 0 (1) (I/O) 1 2 0 0 1 DVSS 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.3 (1) (I/O) P1.3/TA2 (1) 34 3 P1SEL.x I: 0; O: 1 P1.2 (1) (I/O) P1.2/TA1 P1DIR.x TACLK P1.1 (1) (I/O) P1.1/TA0 CONTROL BITS / SIGNALS Default after reset (PUC/POR) Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.1 P1DIR.1 0 P1OUT.1 0 1 0 1 1 Direction 0: Input 1: Output 1 Module XOUT DVSS DVCC P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI P1.7/TA2/TDO/TDI Bus Keeper P1SEL.1 EN P1IN.1 EN Module XIN D P1IE.1 P1IRQ.1 EN Q P1IFG.1 P1SEL.1 P1IES.1 Set Interrupt Edge Select To JTAG From JTAG TDO From JTAG P1.7/TA2/TDO/TDI only TEST pad TEST JTAG Fuse DVSS Copyright (c) 2004-2011, Texas Instruments Incorporated 35 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Table 18. Port P1 (P1.4 to P1.7) Pin Functions PIN NAME (P1.x) x FUNCTION P1.4 P1.4/SMCLK/TCK 4 (2) (I/O) 5 P1.7/TA2/TDO/TDI (1) (2) (3) 36 6 7 P1SEL.x TEST I: 0; O: 1 0 0 1 1 0 TCK X X 1 I: 0; O: 1 0 0 Timer_A3.TA0 1 1 0 TMS X X 1 I: 0; O: 1 0 0 P1.6 (2) (I/O) P1.6/TA1/TDI/TCLK P1DIR.x SMCLK P1.5 (2) (I/O) P1.5/TA0/TMS CONTROL BITS / SIGNALS (1) Timer_A3.TA1 1 1 0 TDI/TCLK (3) X X 1 P1.7 (2) (I/O) I: 0; O: 1 0 0 Timer_A3.TA2 1 1 0 TDO/TDI (3) X X 1 X = don't care Default after reset (PUC/POR) Function controlled by JTAG Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x P2REN.x P2DIR.x 0 0 Module XOUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS P2.0/ACLK/CA2 P2.1/INCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/TA1/CA0 P2.4/TA2/CA1 P2.5/CA5 Bus Keeper P2SEL.x EN P2IN.x EN Module XIN D P2IE.x P2IRQ.x EN Q Set P2IFG.x P2SEL.x P2IES.x Interrupt Edge Select Table 19. Control Signal " From Comparator_A+" PIN NAME FUNCTION SIGNAL "From Comparator_A+" = 1 (1) P2CA4 P2CA0 P2CA3 P2CA2 P2CA1 P2.0/ACLK/CA2 CA2 1 1 0 1 0 P2.1/INCLK/CA3 CA3 N/A N/A 0 1 1 P2.2/CAOUT/TA0/CA4 CA4 N/A N/A 1 0 0 P2.3/TA1/CA0 CA0 0 1 N/A N/A N/A P2.4/TA2/CA1 CA1 1 0 0 0 1 P2.5/CA5 CA5 N/A N/A 1 0 1 (1) OR N/A = Not available or not applicable Copyright (c) 2004-2011, Texas Instruments Incorporated 37 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Table 20. Port P2 (P2.0 to P2.5) Pin Functions PIN NAME (P2.x) x FUNCTION P2.0 P2.0/ACLK/CA2 0 (2) (I/O) 1 2 3 0 0 1 0 CA2 (3) X X 1 I: 0; O: 1 0 0 Timer_A3.INCLK 0 1 0 DVSS 1 1 0 CA3 (3) X X 1 P2.5/CA5 (1) (2) (3) 38 4 5 (2) I: 0; O: 1 0 0 Timer_A3.CCI0B 0 1 0 CAOUT 1 1 0 (3) X X 1 P2.3 (2) (I/O) I: 0; O: 1 0 0 Timer_A3.TA1 1 1 0 CA0 (3) X X 1 P2.4 P2.4/TA2/CA1 CAPD.x 1 CA4 P2.3/TA1/CA0 P2SEL.x I: 0; O: 1 P2.2 P2.2/CAOUT/TA0/CA4 P2DIR.x ACLK P2.1 (2) (I/O) P2.1/INCLK/CA3 CONTROL BITS / SIGNALS (1) (2) (I/O) I: 0; O: 1 0 0 Timer_A3.TA2 1 1 0 CA1 (3) X X 1 I: 0; O: 1 0 0 X X 1 P2.5 (2) CA5 (3) (I/O) (I/O) X = don't care Default after reset (PUC/POR) Setting theCAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currentswhen applying analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless of the state of the associated CAPD.x bit. Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 P2.7/XOUT/CA7 LFXT1 off 0 LFXT1CLK 1 P2SEL.7 P2REN.6 P2DIR.6 0 0 Module XOUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS P2.6/XIN/CA6 Bus Keeper P2SEL.6 EN P2IN.6 EN Module XIN D P2IE.6 P2IRQ.6 EN Q P2IFG.6 P2SEL.6 P2IES.6 Set Interrupt Edge Select Table 21. Control Signal " From Comparator_A+" PIN NAME P2.6/XIN/CA6 FUNCTION CA6 Copyright (c) 2004-2011, Texas Instruments Incorporated SIGNAL "From Comparator_A+" = 1 P2CA3 P2CA2 P2CA1 1 1 0 39 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Table 22. Port P2 (P2.6) Pin Functions PIN NAME (P2.x) x FUNCTION P2.6 (I/O) P2.6/XIN/CA6 (1) (2) (3) 40 6 CONTROL BITS / SIGNALS (1) P2DIR.x P2SEL.x CAPD.x I: 0; O: 1 0 0 XIN (2) X 1 0 CA6 (3) X X 1 X = don't care Default after reset (PUC/POR) Setting theCAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currentswhen applying analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless of the state of the associated CAPD.x bit. Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output Pad Logic To Comparator_A+ From Comparator_A+ CAPD.x LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 LFXT1 off 0 LFXT1CLK 1 From P2.6/XIN P2.6/XIN/CA6 Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module XOUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS P2.7/XOUT/CA7 Bus Keeper P2SEL.7 EN P2IN.7 EN Module XIN D P2IE.7 P2IRQ.7 EN Q P2IFG.7 P2SEL.7 P2IES.7 Set Interrupt Edge Select Table 23. Control Signal " From Comparator_A+" PIN NAME FUNCTION P2.7/XOUT/CA7 CA7 Copyright (c) 2004-2011, Texas Instruments Incorporated SIGNAL "From Comparator_A+" = 1 P2CA3 P2CA2 P2CA1 1 1 1 41 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com Table 24. Port P2 (P2.7) Pin Functions PIN NAME (P2.x) P2.7/XOUT/CA7 (1) (2) (3) (4) 42 x 6 FUNCTION CONTROL BITS / SIGNALS (1) P2DIR.x P2SEL.x CAPD.x P2.7 (I/O) I: 0; O: 1 0 0 XOUT (2) (3) X 1 0 CA7 (4) X X 1 X = don't care Default after reset (PUC/POR) If the pin XOUT/P2.7/CA7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this pin after reset. Setting theCAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currentswhen applying analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless of the state of the associated CAPD.x bit. Copyright (c) 2004-2011, Texas Instruments Incorporated MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see Figure 22). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITF ITEST Figure 22. Fuse Check Mode Current NOTE The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the Bootstrap Loader section for more information. Copyright (c) 2004-2011, Texas Instruments Incorporated 43 MSP430F21x1 SLAS439F - SEPTEMBER 2004 - REVISED AUGUST 2011 www.ti.com REVISION HISTORY Literature Number Summary SLAS439 PRODUCT PREVIEW release SLAS439A PRODUCTION DATA release SLAS439B Corrected instruction cycle time to 62.5ns, pg 1. Updated Figure 1, pg 12. Updated Figures 2 and 3, pg 13. RPull unit corrected from to k, pg 15. MAX load current specification and Note 3 removed from "outputs" table, pg 16. MIN and MAX percentages for "calibrated DCO frequencies - tolerance over supply voltage VCC" corrected from 2.5% to 3% to match the specified frequency ranges., pg 22. SLAS439C MSP430x21x1T production data sheet release. 105C characterization results added. SLAS439D Corrected Timer_A2 to Timer_A3 and added TACCR2 to Interrupt Flag column in "interrupt vector addresses", pg 6 SLAS439E Changed Tstg, Programmed device, to -40C to 150C in Absolute Maximum Ratings. Corrected Test Conditions for OAHF row and and Duty Cycle row in Crystal Oscillator LFXT1, High-Frequency Mode. SLAS439F Changed Tstg, Programmed device, to -55C to 150C in Absolute Maximum Ratings. 44 Copyright (c) 2004-2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 29-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430F2101IDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2101IDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2101IDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2101IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2101IPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2101IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2101IRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2101IRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2101TDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2101TDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2101TDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2101TDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2101TPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2101TPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2101TRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2101TRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2111IDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 29-Jul-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430F2111IDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2111IDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2111IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2111IPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2111IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2111IRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2111IRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2111TDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2111TDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2111TDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2111TDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2111TPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2111TPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2111TRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2111TRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2121IDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2121IDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2121IDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 29-Jul-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430F2121IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2121IPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2121IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2121IRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2121IRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2121TDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2121TDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2121TDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2121TDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2121TPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2121TPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2121TRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2121TRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2131IDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2131IDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2131IDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2131IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2131IPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 3 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 29-Jul-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430F2131IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2131IRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2131IRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2131TDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2131TDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2131TDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2131TDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2131TPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2131TPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430F2131TRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2131TRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 4 PACKAGE OPTION ADDENDUM www.ti.com 29-Jul-2011 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 5 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSP430F2101IDGVR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2101IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 MSP430F2101IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430F2101IRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2101IRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2101TDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2101TDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 MSP430F2101TPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430F2101TRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2101TRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2111IDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2111IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 MSP430F2111IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430F2111IRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2111IRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2111TDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2111TDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 MSP430F2111TPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F2111TRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2111TRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2121IDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2121IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 MSP430F2121IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430F2121IRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2121IRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2121TDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2121TDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 MSP430F2121TPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430F2121TRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2121TRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2131IDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2131IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 MSP430F2131IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 MSP430F2131IRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2131IRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2131TDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430F2131TDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 MSP430F2131TRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430F2131TRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2101IDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F2101IDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F2101IPWR TSSOP PW 20 2000 367.0 367.0 38.0 MSP430F2101IRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F2101IRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F2101TDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F2101TDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F2101TPWR TSSOP PW 20 2000 367.0 367.0 38.0 MSP430F2101TRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F2101TRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F2111IDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F2111IDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F2111IPWR TSSOP PW 20 2000 367.0 367.0 38.0 MSP430F2111IRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F2111IRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F2111TDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F2111TDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F2111TPWR TSSOP PW 20 2000 367.0 367.0 38.0 MSP430F2111TRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F2111TRGET VQFN RGE 24 250 210.0 185.0 35.0 Pack Materials-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2121IDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F2121IDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F2121IPWR TSSOP PW 20 2000 367.0 367.0 38.0 MSP430F2121IRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F2121IRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F2121TDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F2121TDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F2121TPWR TSSOP PW 20 2000 367.0 367.0 38.0 MSP430F2121TRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F2121TRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F2131IDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F2131IDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F2131IPWR TSSOP PW 20 2000 367.0 367.0 38.0 MSP430F2131IRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F2131IRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F2131TDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F2131TDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F2131TRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F2131TRGET VQFN RGE 24 250 210.0 185.0 35.0 Pack Materials-Page 4 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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