SN54AHC00, SN74AHC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS227F - OCTOBER 1995 - REVISED JANUARY 2000 D D D D EPIC (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs SN54AHC00 . . . J OR W PACKAGE SN74AHC00 . . . D, DB, DGV, N, OR PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y SN54AHC00 . . . FK PACKAGE (TOP VIEW) description 1Y NC 2A NC 2B The 'AHC00 devices perform the Boolean function Y A * B or Y A B in positive logic. + 1 1B 1A NC VCC 4B D + ) 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A The SN54AHC00 is characterized for operation over the full military temperature range of -55C to 125C. The SN74AHC00 is characterized for operation from -40C to 85C. 4 NC - No internal connection FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H L L X H X L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54AHC00, SN74AHC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS227F - OCTOBER 1995 - REVISED JANUARY 2000 logic symbol 1A 1B 2A 2B 3A 3B 4A 4B 1 & 2 3 1Y 4 6 5 2Y 9 8 10 3Y 12 11 13 4Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages. logic diagram, each gate (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54AHC00, SN74AHC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS227F - OCTOBER 1995 - REVISED JANUARY 2000 recommended operating conditions (see Note 3) SN54AHC00 VCC Supply voltage VIH VCC = 2 V VCC = 3 V High-level input voltage Low-level input voltage VI VO 2 5.5 Output voltage t/v 5.5 2.1 V V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC -50 0 VCC -50 mA VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V VCC = 3.3 V 0.3 V Input transition rise or fall rate 2 UNIT 1.5 3.85 VCC = 2 V VCC = 3.3 V 0.3 V Low-level output current MAX 2.1 VCC = 5 V 0.5 V VCC = 2 V IOL MIN 3.85 VCC = 3 V VCC = 5.5 V High-level output current SN74AHC00 0.5 Input voltage IOH MAX 1.5 VCC = 5.5 V VCC = 2 V VIL MIN VCC = 5 V 0.5 V -4 -4 -8 -8 50 50 4 4 8 8 100 100 20 20 V mA mA mA ns/V TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -50 mA VOH IOH = -4 mA IOH = -8 mA IOL = 50 mA VOL IOL = 4 mA IOL = 8 mA MIN TA = 25C TYP MAX 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 3V 2.58 2.48 2.48 4.5 V 3.94 3.8 VCC SN54AHC00 MIN MAX SN74AHC00 MIN MAX UNIT V 3.8 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 V 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 0 V to 5.5 V 0.1 1* 1 mA IO = 0 5.5 V 2 VI = VCC or GND 5V 2 10 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. 20 20 mA 10 pF II ICC VI = VCC or GND VI = VCC or GND, Ci POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54AHC00, SN74AHC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS227F - OCTOBER 1995 - REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A or B Y CL = 15 pF tPLH tPHL A or B Y CL = 50 pF MIN TA = 25C TYP MAX SN54AHC00 SN74AHC00 MIN MAX MIN MAX 5.5* 7.9* 1* 9.5* 1 9.5 5.5* 7.9* 1* 9.5* 1 9.5 8 11.4 1 13 1 13 8 11.4 1 13 1 13 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A or B Y CL = 15 pF tPLH tPHL A or B Y CL = 50 pF MIN TA = 25C TYP MAX SN54AHC00 SN74AHC00 MIN MAX MIN MAX 3.7* 5.5* 1* 6.5* 1 6.5 3.7* 5.5* 1* 6.5* 1 6.5 5.2 7.5 1 8.5 1 8.5 5.2 7.5 1 8.5 1 8.5 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25C (see Note 4) SN74AHC00 PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.3 0.8 V Quiet output, minimum dynamic VOL -0.3 -0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.6 High-level dynamic input voltage V 3.5 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. V 1.5 V TYP UNIT 9.5 pF operating characteristics, VCC = 5 V, TA = 25C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 f = 1 MHz SN54AHC00, SN74AHC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS227F - OCTOBER 1995 - REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION RL = 1 k From Output Under Test Test Point From Output Under Test S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH - 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated