Precision, Dual-Channel, JFET Input
Rail-to-Rail Instrumentation Amplifier
Preliminary Technical Data AD8224
FEATURES FUNCTIONAL BLOCK DIAGRAM
Two channels in a small 4 mm × 4 mm LFCSP
Low input currents
10 pA maximum input bias current (B grade)
0.6 pA maximum input offset current (B grade)
–IN1
+V
S
OUT1
OUT2
–V
S
AD8224
1
2
3
4
12
11
10
9
5 6 7 8
13141516
–IN2
RG2
RG2
+IN2
High CMRR
RG1
100 dB CMRR (minimum), G = 10 (B grade)
RG1
+IN1
80 dB CMRR (minimum) to 5 kHz, G = 1 (B grade)
Excellent ac specifications and low power
1.5 MHz bandwidth (G = 1)
14 nV/√Hz input noise (1 kHz)
Slew rate 2 V/s
750 A quiescent supply current per amplifier (maximum)
–V
S
06286-001
+V
S
REF1
REF2
Figure 1. 4mm × 4 mm LFCSP
Versatility
Rail-to-rail output
Input voltage range to below negative supply rail Table 1. In Amps and Difference Amplifiers by Category
High
Perform.
Low
Cost
High
Volt.
Mil
Grade
Low
Power
Digital
Gain
AD82201
AD8221
AD8222
AD82241
AD85531
AD6231
AD628
AD629
AD620
AD621
AD524
AD526
AD624
AD6271 AD85551
AD85561
AD85571
4 kV ESD protection
4.5 V to 36 V single supply
±2.25 V to ±18 V dual supply
Gain set with single resistor (G = 1 to 1000)
APPLICATIONS
Medical instrumentation
Precision data acquisition
Transducer interface
Differential drive for
High resolution input ADCs
Remote sensors
GENERAL DESCRIPTION
The AD8224 is the first single-supply junction field effect
transistor (JFET) input instrumentation amplifier available in
the space-saving 16-lead, 4 mm×4 mm LFCSP. It requires the
same board area as a typical single instrumentation amplifier,
yet doubles the channel density and offers a lower cost per
channel without compromising performance.
Designed to meet the needs of high performance, portable
instrumentation, the AD8224 has a minimum common-mode
rejection ratio (CMRR) of 86 dB at dc and a minimum CMRR
of 80 dB at 5 kHz for G = 1. Maximum input bias current is
10 pA and typically remains below 300 pA over the entire
industrial temperature range. Despite the JFET inputs, the
AD8224 typically has a noise corner of only 10 Hz.
With the proliferation of mixed-signal processing, the number of
power supplies required in each system has grown.
1 Rail-to-rail output.
Designed to alleviate this problem, the AD8224 can operate on a
±18 V dual supply, as well as on a single +5 V supply. The device’s
rail-to-rail output stage maximizes dynamic range on the low
voltage supplies common in portable applications. Its ability to run
on a single 5 V supply eliminates the need for higher voltage, dual
supplies. The AD8224 draws a maximum of 750 A of quiescent
current per amplifier, making it ideal for battery-powered devices.
In addition, the AD8224 can be configured as a single-channel,
differential output instrumentation amplifier. Differential
outputs provide high noise immunity, which can be useful when
the output signal must travel through a noisy environment, such
as with remote sensors. The configuration can also be used to
drive differential input ADCs.
For a single-channel version, use the AD8220 device.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
rightsof third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
AD8224 Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History .......................... Error! Bookmark not defined.
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 20
Gain Selection ............................................................................. 20
Reference Terminal .................................................................... 21
Layout .......................................................................................... 21
Solder Wash................................................................................. 22
Input Bias Current Return Path ............................................... 22
Input Protection ......................................................................... 22
RF Interference ........................................................................... 22
Common-Mode Input Voltage Range ..................................... 23
Applications..................................................................................... 24
Driving an Analog-to-Digital Converter ................................ 24
Differential Output .................................................................... 24
Driving a Differential Input ADC............................................ 25
Driving Cabling .......................................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
Rev. PrB | Page 2 of 27
Preliminary Technical Data AD8224
SPECIFICATIONS
VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 k, unless otherwise noted.
Table 2. Single-Ended and Differential1 Output Configuration
Parameter Test Conditions Min
A Grade
Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ Source Imbalance VCM = ±10 V
G = 1 78 dB
G = 10 94 dB
G = 100 94 dB
G = 1000 94 dB
CMRR at 5 kHz VCM = ±10 V
G = 1 74 dB
G = 10 84 dB
G = 100 84 dB
G = 1000 84 dB
NOISE RTI noise = √(eni
2 + (eno/G)2)
Voltage Noise, 1 kHz
Input Voltage Noise, eni VIN+, VIN− = 0 V 14 nV√Hz
Output Voltage Noise, eno VIN+, VIN− = 0 V 90 nV√Hz
RTI, 0.1 Hz to 10 Hz
G = 1 5 V p-p
G = 1000 0.8 V p-p
Current Noise f = 1 kHz 1 fA/√Hz
VOLTAGE OFFSET RTI VOS = (VOSI) + (VOSO/G)
Input Offset, VOSI 250 V
Average TC T = −40°C to +85°C 10 V/°C
Output Offset, VOSO 750 V
Average TC T = −40°C to +85°C 10 V/°C
Offset RTI vs. Supply (PSR)
G = 1 86 dB
G = 10 96 dB
G = 100 96 dB
G = 1000 96 dB
INPUT CURRENT (PER CHANNEL)
Input Bias Current 25 pA
Over Temperature2 T = −40°C to +85°C 300 pA
Input Offset Current 2 pA
Over Temperature2 T = −40°C to +85°C 5 pA
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 V/V
Gain Error VOUT = ±10 V
G = 1 0.06 %
G = 10 0.3 %
G = 100 0.3 %
G = 1000 0.3 %
Gain Nonlinearity VOUT = −10 V to +10 V
G = 1 RL = 10 kΩ 10 15 ppm
G = 10 RL = 10 kΩ 5 10 ppm
G = 100 RL = 10 kΩ 30 60 ppm
Rev. PrB | Page 3 of 27
AD8224 Preliminary Technical Data
Parameter Test Conditions Min
A Grade
Typ Max Unit
G = 1000 RL = 10 kΩ 400 500 ppm
G = 1 RL = 2 kΩ 10 15 ppm
G = 10 RL = 2 kΩ 10 15 ppm
G = 100 RL = 2 kΩ 50 75 ppm
Gain vs. Temperature
G = 1 3 10 ppm/°C
G > 10 −50 ppm/°C
INPUT
Impedance (Pin to Ground)3 104||5 GΩ||pF
Input Operating Voltage Range4 VS = ±2.25 V to ±18 V for dual supplies −VS − 0.1 +VS − 2 V
Over Temperature T = −40°C to +85°C −VS − 0.1 +VS − 2.1 V
OUTPUT
Output Swing RL = 2 kΩ −14.3 +14.3 V
Over Temperature T = −40°C to +85°C −14.3 +14.1 V
Output Swing RL = 10 kΩ −14.7 +14.7 V
Over Temperature T = −40°C to +85°C −14.6 +14.6 V
Short-Circuit Current 15 mA
REFERENCE INPUT
RIN 40 kΩ
IIN VIN+, VIN− = 0 V 70 A
Voltage Range −VS +VS V
Gain to Output 1 ± 0.0001 V/V
POWER SUPPLY (PER AMPLIFIER)
Operating Range ±2.255 ±18 V
Quiescent Current 750 A
Over Temperature T = −40°C to +85°C 850 A
TEMPERATURE RANGE
For Specified Performance −40 +85 °C
Operational6 −40 +125 °C
1 Refers to differential configuration shown in Figure 64.
2 Please refer to Figure 16 and Figure 17 for the relationship between input current and temperature.
3 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
4 The AD8224 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification.
5 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification.
6 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in this temperature range.
Rev. PrB | Page 4 of 27
Preliminary Technical Data AD8224
VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 k, unless otherwise noted.
Table 3. Single-Ended Output Configuration—Dynamic Performance (Both Amplifiers)
Parameter Conditions Min
A Grade
Typ Max Unit
DYNAMIC RESPONSE
Small Signal Bandwidth −3 dB
G = 1 TBD kHz
G = 10 TBD kHz
G = 100 TBD kHz
G =1000 TBD kHz
Settling Time 0.01% 10 V step
G = 1 TBD µs
G = 10 TBD µs
G = 100 TBD µs
G =1000 TBD µs
Settling Time 0.001% 10 V step
G = 1 TBD µs
G = 10 TBD µs
G = 100 TBD µs
G =1000 TBD µs
Slew Rate
G = 1 to 100 TBD V/µs
Please fill in TBDs if you can.
VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 k, unless otherwise noted.
Table 4. Differential Output Configuration1—Dynamic Performance
Parameter Conditions Min
A Grade
Typ Max Unit
DYNAMIC RESPONSE
Small Signal Bandwidth−3 dB
G = 1 TBD kHz
G = 10 TBD kHz
G = 100 TBD kHz
G =1000 TBD kHz
Settling Time 0.01% 10 V step
G = 1 TBD µs
G = 10 TBD µs
G = 100 TBD µs
G =1000 TBD µs
Settling Time 0.001% 10 V step
G = 1 TBD µs
G = 10 TBD µs
G = 100 TBD µs
G =1000 TBD µs
Slew Rate
G = 1 to 100 TBD V/µs
1 Refers to differential configuration shown in Figure 64.
Rev. PrB | Page 5 of 27
AD8224 Preliminary Technical Data
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = +25°C, G = 1, RL = 2 k, unless otherwise noted.
Table 5. Single-Ended and Differential1 Output Configuration
Parameter Test Conditions Min
A Grade
Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ Source Imbalance VCM = 0 to 2.5 V
G = 1 78 dB
G = 10 94 dB
G = 100 94 dB
G = 1000 94 dB
CMRR at 5 kHz
G = 1 74 dB
G = 10 84 dB
G = 100 84 dB
G = 1000 84 dB
NOISE RTI noise = √(eni
2 + (eno/G)2)
Voltage Noise, 1 kHz
Input Voltage Noise, eni VIN+, VIN− = 0 V, VREF = 0 V 14 nV√Hz
Output Voltage Noise, eno VIN+, VIN− = 0 V, VREF = 0 V 90 nV√Hz
RTI, 0.1 Hz to 10 Hz
G = 1 5 V p-p
G = 1000 0.8 V p-p
Current Noise f = 1 kHz 1 fA/√Hz
VOLTAGE OFFSET RTI VOS = (VOSI) + (VOSO/G)
Input Offset, VOSI 300 V
Average TC T = −40°C to +85°C 10 V/°C
Output Offset, VOSO 800 V
Average TC T = −40°C to +85°C 10 V/°C
Offset RTI vs. Supply (PSR)
G = 1 86 dB
G = 10 96 dB
G = 100 96 dB
G = 1000 96 dB
INPUT CURRENT (PER CHANNEL)
Input Bias Current 25 pA
Over Temperature2 T = −40°C to +85°C 300 pA
Input Offset Current 2 pA
Over Temperature2 T = −40°C to +85°C 5 pA
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 V/V
Gain Error VOUT = 0.3 V to 2.9 V for G = 1
VOUT = 0.3 V to 3.8 V for G > 1
G = 1 0.06 %
G = 10 0.3 %
G = 100 0.3 %
G = 1000 0.3 %
Nonlinearity VOUT = 0.3 V to 2.9 V for G = 1
VOUT = 0.3 V to 3.8 V for G > 1
G = 1 RL = 10 kΩ 35 50 ppm
G = 10 RL = 10 kΩ 35 50 ppm
G = 100 RL = 10 kΩ 50 75 ppm
Rev. PrB | Page 6 of 27
Preliminary Technical Data AD8224
Parameter Test Conditions Min
A Grade
Typ Max Unit
G = 1000 RL = 10 kΩ 650 750 ppm
G = 1 RL = 2 kΩ 35 50 ppm
G = 10 RL = 2 kΩ 35 50 ppm
G = 100 RL = 2 kΩ 50 75 ppm
Gain vs. Temperature
G = 1 3 10 ppm/°C
G > 10 −50 ppm/°C
INPUT
Impedance (Pin to Ground)3 104||6 GΩ||pF
Input Voltage Range4 −0.1 +VS − 2 V
Over Temperature T = −40°C to +85°C −0.1 +VS − 2. V
OUTPUT
Output Swing RL = 2 kΩ 0.25 4.75 V
Over Temperature T = −40°C to +85°C 0.3 4.70 V
Output Swing RL = 10 kΩ 0.15 4.85 V
Over Temperature T = −40°C to +85°C 0.2 4.80 V
Short-Circuit Current 15 mA
REFERENCE INPUT
RIN 40 kΩ
IIN VIN+, VIN− = 0 V 70 A
Voltage Range −VS +VS V
Gain to Output 1 ± 0.0001 V/V
POWER SUPPLY (PER AMPLIFIER)
Operating Range +4.5 +36 V
Quiescent Current 750 A
Over Temperature T = −40°C to +85°C 850 A
TEMPERATURE RANGE
For Specified Performance −40 +85 °C
Operational5 −40 +125 °C
1 Refers to differential configuration shown in Figure 64.
2 Refer to Figure 16 and Figure 17 for the relationship between input current and temperature.
3 Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
4 The AD8224 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification.
5 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in that temperature range.
Rev. PrB | Page 7 of 27
AD8224 Preliminary Technical Data
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = +25°C, G = 1, RL = 2 k, unless otherwise noted.
Table 6. Single-Ended Output Configuration—Dynamic Performance (Both Amplifiers)
A Grade
Parameter Conditions Min Typ Max
DYNAMIC RESPONSE
Small Signal Bandwidth −3 dB
G = 1 TBD
G = 10 TBD
G = 100 TBD
G =1000 TBD
Settling Time 0.01%
G = 1 3 V Step TBD
G = 10 4 V Step TBD
G = 100 4 V Step TBD
G =1000 4 V Step TBD
Settling Time 0.001%
G = 1 3 V Step TBD
G = 10 4 V Step TBD
G = 100 4 V Step TBD
G =1000 4 V Step TBD
Slew Rate
G = 1 to 100 TBD
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = +25°C, G = 1, RL = 2 k, unless otherwise noted.
Table 7. Differential Output Configuration1—Dynamic Performance
Parameter Conditions Min
A Grade
Typ Max Unit
DYNAMIC RESPONSE
Small Signal Bandwidth −3 dB
G = 1 TBD kHz
G = 10 TBD kHz
G = 100 TBD kHz
G =1000 TBD kHz
Settling Time 0.01%
G = 1 3 V Step TBD µs
G = 10 4 V Step TBD µs
G = 100 4 V Step TBD µs
G =1000 4 V Step TBD µs
Settling Time 0.001%
G = 1 3 V Step TBD µs
G = 10 4 V Step TBD µs
G = 100 4 V Step TBD µs
G =1000 4 V Step TBD µs
Slew Rate
G = 1 to 100 TBD V/µs
1 Refers to differential configuration shown in Figure 64.
Rev. PrB | Page 8 of 27
Preliminary Technical Data AD8224
ABSOLUTE MAXIMUM RATINGS
Maximum Power Dissipation
The maximum safe power dissipation for the AD8224 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 130°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the amplifiers. Exceeding a temperature of 130°C for an
extended period can result in a loss of functionality.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the LFCSP on a 4-layer
JEDEC standard board.
4.0
3.5
3.0
JA
= 48°C/W WHEN THERMAL PAD
IS SOLDERED TO BOARD
JA
= 86°C/W WHEN THERMAL PAD
IS NOT SOLDERED TO BOARD
MAX POWER (W)
2.5
2.0
1.5
Table 8.
Parameter
Supply Voltage ±18 V
Power Dissipation See Figure 2
Output Short Circuit Current Indefinite1
Input Voltage (Common Mode) ±Vs
Differential Input Voltage ±Vs
Storage Temperature −65°C to +130°C
Operating Temperature Range2 −40°C to +125°C
Lead Temperature Range (Soldering 10 sec) 300°C
Junction Temperature 130°C
Package Glass Transition Temperature 130°C
ESD (Human Body Model) 4 kV
ESD (Charge Device Model) 1 kV
ESD (Machine Model) 0.4 kV
1Assumes the load is referenced to mid-supply.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
1.0
maximum rating conditions may affect device reliability.
0.5
THERMAL RESISTANCE
0
Rating
2Temperature for specified performance is −40°C to +85°C. For performance
to +125°C, see the Typical Performance Characteristics section.
Table 9.
–60 –40 –20 0 20 40 60 80 100 120 140
06286-002
Thermal Pad θJA Unit
Soldered to Board 48 °C/W
Not Soldered to Board 86 °C/W
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation
ESD CAUTION
The θJA values in Table 9 assume a 4-layer JEDEC standard
board. If the thermal pad is soldered to the board, then it is
also assumed it is connected to a plane. θJC at the exposed pad
is 4.4°C/W.
Rev. PrB | Page 9 of 27
AD8224 Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
OUT2
12
11
10
9
–IN1 1
RG1 2
RG1 3
+IN1 4
PIN 1
INDICATOR
TOP VIEW
AD8224
–IN2
RG2
RG2
+IN2
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No Mnemonic Description
1 −IN1 Negative Input In-Amp 1.
2 RG1 Gain Resistor In-Amp 1.
3 RG1 Gain Resistor In-Amp 1.
4 +IN1 Positive Input In-Amp 1.
5 +VS Positive Supply.
6 REF1 Reference Adjust In-Amp 1.
7 REF2 Reference Adjust In-Amp 2.
8 −VS Negative Supply.
9 +IN2 Positive Input In-Amp 2.
10 RG2 Gain Resistor In-Amp 2.
11 RG2 Gain Resistor In-Amp 2.
12 −IN2 Negative Input In-Amp 2.
13 −VS Negative Supply.
14 OUT2 Output In-Amp 2.
15 OUT1 Output In-Amp 1.
16 +VS Positive Supply.
+VS 5
REF1 6
16 +VS
15 OUT1
REF2 7 14
–VS 8
06286-003
13 –VS
Rev. PrB | Page 10 of 27
Preliminary Technical Data AD8224
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Typical Distribution of CMRR (G = 1) Figure 7. Typical Distribution of Input Bias Current
Figure 5. Typical Distribution of Input Offset Voltage Figure 8. Typical Distribution of Input Offset Current
1000
GAIN = +100 BANDWIDTH ROLL-OFF
GAIN = +1
GAIN = +10
GAIN = 100/GAIN = +1000
GAIN = +1000 BANDWIDTH ROLL-OFF
(nV/ Hz)
100
10
1
1 10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 9. Voltage Spectral Density vs. Frequency
Figure 6. Typical Distribution of Output Offset Voltage
06286-009
Rev. PrB | Page 11 of 27
XX
XX
XX XX
XXX (X)
XXX (X)
XX
XX
XX XX
XXX (X)
XXX (X)
AD8224 Preliminary Technical Data
150
1s/DIV 5µV/DIV
BANDWIDTH
LIMITED
GAIN = +1
GAIN = +10
GAIN = +100
GAIN = +1000
130
110
90
70
50
30
10
06286-012 06286-011 06286-010
INPUT BIAS CURRENT (pA)
PSRR (dB) PSRR (dB)
INPUT OFFSET CURRENT (pA)
06286-014 06286-013
06286-015
1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 10. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) Figure 13. Positive PSRR vs. Frequency, RTI
150
130
1s/DIV 1µV/DIV
GAIN = +1
GAIN = +10
GAIN = +100
GAIN = +1000
110
90
70
50
30
10
1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) Figure 14. Negative PSRR vs. Frequency, RTI
8
0.1 1k
7
INPUT OFFSET
CURRENT ±5
–15.1V
–5.1V
INPUT OFFSET
CURRENT ±15
INPUT BIAS
CURRENT ±15
INPUT BIAS
CURRENT ±5
9
7
6
5
V
OSI
(µV)
5
4
–0.1
3
–0.2
3
2
–0.3
–0.4
–1 –0.5
1
1
0
–16 –12 –8 –4 0 4 8 12 16
1 10 100
COMMON-MODE VOLTAGE (V)
TIME (s)
Figure 12. Change in Input Offset Voltage vs. Warmup Time Figure 15. Input Current vs. Common-Mode Voltage
Rev. PrB | Page 12 of 27
0
0.1
0.2
0.3
Preliminary Technical Data AD8224
160
10n
140
I
BIAS
I
OS
GAIN = +1000
GAIN = +100
GAI = +10 N GAIN = +1
BANDWID
LIMITED
TH
CMRR (dB)
CURRENT (A) INPUT BIAS CURRENT (A)
1n
100p
10p
120
06286-018
06286-017 06286-016
GAIN (dB)
CMRR (V/V)
CMRR (dB)
100
80
1p
60
0.1p
40
–50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
1 10 100 1k 10k 100k
FREQUENCY (Hz)
06286-021
06286-020
06286-019
Figure 16. Input Bias Current and Offset Current Temperature, Figure 19. CMRR vs. Frequency, 1 kΩ Source Imbalance
VS = ±15 V, VREF = 0 V
10
8
10n
6
1n
4
2
–50 130
I
BIAS
I
OS
100p
0
10p
–2
–4
1p
–6
0.1p
–8
–10
–50 –25 0 25 50 75 100 125 150
–30 –10 10 30 50 70 90 110
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Input Bias Current and Offset Current vs. Temperature, Figure 20. Change in CMRR vs. Temperature, G = 1
VS = +5 V, VREF = 2.5 V
160
70
60
GAIN = +1000
GAIN = +100
GAIN = +10 BANDWIDTH
GAIN = +1
LIMITED
GAIN
GAIN
GAIN
GAIN
= +10
= +100
= +1000
+1=
140
120
100
50
40
30
20
10
0
80
–10
60
–20
–30
40
–40
10 100 1k 10k 100k
FREQUENCY (Hz)
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 18. CMRR vs. Frequency Figure 21. Gain vs. Frequency
Rev. PrB | Page 13 of 27
XXX
=
=
XXX
=
=
XXX
=
=
=
XXX
=
=
AD8224 Preliminary Technical Data
–8–10 –6 –4 –2 0 2 4 6 8 10
R
LOAD
2k
R
LOAD
= 10k
V
S
±15V
06286-022
NONLINEARITY (500ppm/DIV)
–8–10 –6 –4 –2 0 2 4 6 8 10
R
LOAD
= 2k
R
LOAD
10k
V
S
±15V
06286-025
NONLINEARITY (50ppm/DIV) NONLINEARITY (5ppm/DIV) NONLINEARITY (5ppm/DIV)
VIN (V) OUTPUT VOLTAGE (V)
Figure 22. Gain Nonlinearity, G = 1 Figure 25. Gain Nonlinearity, G = 1000
–8–10 –6 –4 –2 0 2 4 6 8 10
R
LOAD
= 2k
R
LOAD
10k
V
S
±15V
06286-023
18
+13V
±15V SUPPLIES
–14.8V, +5.5V +3V +14.9V, +5.5V
–4.8V, +0.6V +4.95V, +0.6V
–4.8V, –3.3V
±5V SUPPLIES
+4.95V, –3.3V
–14.8V, –8.3V –5.3V +14.9V, –8.3V
–15.3V
INPUT COMMON-MODE VOLTAGE (V)
12
6
0
–6
–12
–18
–16 –12 –8 –4 0 4 8 12 16
OUTPUT VOLTAGE (V)
06286-027 06286-026
VIN (V)
Figure 23. Gain Nonlinearity, G = 10 Figure 26. Input Common-Mode Voltage Range vs. Output Voltage,
G = 1, VREF = 0 V
–8–10 –6 –4 –2 0 2 4 6 8 10
R
LOAD
2k
R
LOAD
10k
V
S
±15V
06286-024
4
+3V
+0.1V,
+5V S
V
+1.7V
REF
= +2.5V
INGLE SU
+4.9V
PPLY,
, +1.7V
+0.1V, +0.5V +4.9V, +0.5V
–0.3V
INPUT COMMON-MODE VOLTAGE (V)
3
2
1
0
–1
–1 0 1 2 3 4 5 6
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 24. Gain Nonlinearity, G = 100 Figure 27. Input Common-Mode Voltage Range vs. Output Voltage,
G = 1, VS = +5 V, VREF = 2.5 V
Rev. PrB | Page 14 of 27
Preliminary Technical Data AD8224
18
V
S+
–1
12 ±15V SUPPLIES
+13V
–14.9V, +5.4V +3V +14.9V, +5.4V
–4.9V, +0.4V +4.9V, +0.5V
±5V SUPPLIES
–4.9V, –4.1V +4.9V, –4.1V
–14.8V, –9V –5.3V +14.9V, –9V
–15.3V
–40°C +25°C +85°C
+125°C
+125 +8
°C +2
5°C 5°C –40°C
INPUT COMMON-MODE VOLTAGE (V)
–2
–3
–4
+4
+3
+2
OUTPUT SWING (V)
6
0
–6
–12
+1
VS–
–18
06286-030 06286-029 06286-028
06286-031
–16 –12 –8 –4 0 4 8 12
16
OUTPUT VOLTAGE (V)
2 4 6 8 10 12 14 16 18
DUAL SUPPLY VOLTAGE (±V)
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, Figure 31. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ, G = 10,
G = 100, VREF = 0 V VREF = 0 V
4
V
S+
–0.2
+3V
+0.1V, +1.7V
+5V SINGLE SU
+4.9
PPLY,
V, +1.7V
V
REF
= +2.5V
+0.1V, –0.5V –0.3V +4.9V, –0.5V
+85°C
+125°C +25°C –40°C
–40°C
+25°C
+85°C
+125°C
INPUT COMMON-MODE VOLTAGE (V)
3
–0.4
OUTPUT SWING (V)
2
1
0
+0.4
+0.2
VS–
–1
06286-032
–1 0 1 2 3 4 5 6
OUTPUT VOLTAGE (V)
2 4 6 8 10 12 14 16 18
DUAL SUPPLY VOLTAGE (±V)
Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, Figure 32. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ, G = 10,
G = 100, VS= +5 V, VREF = 2.5 V VREF = 0 V
15
V
S
+
–40°C +125°C
NOT
1. T
T
W
H
H
ES
E AD82
E NEGATIVE S
ILL INCREASE
24 CAN
+25°
OPERA
UPPLY,
SHARPL
C +8
BUT TH
TE UP T
Y.
5°C
O A V
BE
E BIAS
BELOW
CURRENT
–40° +25C °C +85°C +125°C
+25°C
–40°C
+25°C
–40°C
+125°C
+85°C
+125°C
+85°C
–1
–2
10
VOLTAGE SWING (V)
INPUT VOLTAGE (V)
5
0
–5
+1
–10
V
S
–
–1
–15
2 4 6 8 10 12 14 16 18
VOLTAGE SUPPLY (V)
100 1k 10k
R
LOAD
()
06286-033
Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V Figure 33. Output Voltage Swing vs. Load Resistance VS = ±15 V, VREF = 0 V
Rev. PrB | Page 15 of 27
X
X
XX
XX XX
XXX (X)
XXX (X)
X
X
XX
XX XX
XXX (X)
XXX (X)
100pF
47pF
AD
AD8224 Preliminary Technical Data
5
4
3
2
1
0
–40°C
+25°C
+85°C
+125°C
+125°C
–40°C
+25°C +85°C
5µs/DIV 20mV/DIV
100pF
47pF
NO LOAD
VOLTAGE SWING (V)
06286-038 06286-037
06286-039
100 1k 10k
R
LOAD
()
06286-034
Figure 34. Output Voltage Swing vs. Load Resistance VS = +5 V, VREF = 2.5 V Figure 37. Small Signal Pulse Response for Various Capacitive Loads,
VS = ±15 V, VREF = 0 V
V
S
+
+125°C +85°C
+25°C
–40°C
+125° +85
C +25
°C
–40°C
°C
5µs/DIV 20mV/DIV
NO LO
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–1
–2
–3
–4
+4
+3
+2
+1
V
S
–
0 2 4 6 8 10 12 14
16
I
OUT
(mA)
06286-035
Figure 35. Output Voltage Swing vs. Output Current, VS = ±15 V, VREF = 0 V Figure 38. Small Signal Pulse Response for Various Capacitive Loads,
VS = +5 V, VREF = 2.5 V
V
S
+ 35
+125°C
+85°C
+25°C
+125°C
+85°C +25°C
–40°C
100 10M
GAIN = +1
GAIN = +10, +100, +1000
30
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
OUTPUT VOLTAGE SWING (V p-p)
–1
–2
+2
+1
25
20
15
10
5
V
S
– 0
0 2 4 6 8 10 12 14
16
I
OUT
(mA)
06286-036
1k 10k 100k 1M
FREQUENCY (Hz)
Figure 36. Output Voltage Swing vs. Output Current, VS = +5 V, VREF = 2.5 V Figure 39. Output Voltage Swing vs. Large Signal Frequency Response
Rev. PrB | Page 16 of 27
XX
XX
XX XX
XXX (X)
XXX (X)
XX
XX
XX XX
XXX (X)
XXX (X)
XX
XX
XX XX
XXX (X)
XXX (X)
X
X
XX
XX XX
XXX (X)
XXX (X)
XXX
XXX
XXX
XXX
Preliminary Technical Data AD8224
20µs/DIV
5µs TO 0.01%
6µs TO 0.001%
5V/DIV
0.002%/DIV
200µs/DIV
58s TO 0.01%
74s TO 0.001%
0.002%/DIV
5V/DIV
06286-042 06286-041 06286-040
06286-043
Figure 40. Large Signal Pulse Response and Settle Time, G = 1, Figure 43. Large Signal Pulse Response and Settle Time, G = 1000,
RL = 10 kΩ, VS = ±15 V, VREF = 0 V RL = 10 kΩ, VS = ±15 V, VREF = 0 V
20µs/DIV
5V/DIV
4.3s TO 0.01%
4.6s TO 0.001%
0.002%/DIV
20mV/DIV
4µs/DIV
06286-044
Figure 41. Large Signal Pulse Response and Settle Time, G = 10, Figure 44. Small Signal Pulse Response, G = 1, RL = 2 kΩ, CL = 100 pF,
RL = 10 kΩ, VS = ±15 V, VREF = 0 V VS = ±15 V, VREF = 0 V
20µs/DIV
8.1s TO 0.01%
9.6s TO 0.001%
0.002%/DIV
5V/DIV
20mV/DIV
4µs/DIV
06286-045
Figure 42. Large Signal Pulse Response and Settle Time, G = 100, Figure 45. Small Signal Pulse Response, G = 10, RL = 2 kΩ, CL = 100 pF,
RL = 10 kΩ, VS = ±15 V, VREF = 0 V VS = ±15 V, VREF = 0 V.
Rev. PrB | Page 17 of 27
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
AD8224 Preliminary Technical Data
20mV/DIV 20mV/DIV
4µs/DIV
06286-046
4µs/DIV
06286-049
Figure 46. Small Signal Pulse Response, G = 100, RL = 2 kΩ, C L= 100 pF, Figure 49. Small Signal Pulse Response, G = 10, RL = 2 kΩ, CL = 100 pF,
VS = ±15 V, VREF =0 V VS = +5 V, VREF = 2.5 V
20mV/DIV 20mV/DIV
40µs/DIV
06286-047
4µs/DIV
06286-050
Figure 47. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF, Figure 50. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF,
VS = ±15 V, VREF = 0 V VS = +5 V, VREF = 2.5 V
20mV/DIV 20mV/DIV
4µs/DIV
06286-048
40µs/DIV
06286-051
Figure 48. Small Signal Pulse Response, G = 1, RL = 2 kΩ, CL = 100 pF, Figure 51. Small Signal Pulse Response, G = 1000,RL = 2 kΩ, CL = 100 pF,
VS = +5 V, VREF = 2.5 V VS = +5 V, VREF = 2.5 V
Rev. PrB | Page 18 of 27
Preliminary Technical Data AD8224
15
60
SETTL
SETTLED T
ED TO 0.001%
O 0.01%
GAIN = +1000
+100 GAIN =
+10 GAIN =
+1GAIN =
40
10
SETTLING TIME (µs) SETTLING TIME (µs)
GAIN (dB)
20
0
5
–20
0
–40
0 5 10 15
20
OUTPUT VOLTAGE STEP SIZE (V)
Figure 52. Settling Time vs. Step Size (G = 1) ±15 V, VREF = 0 V
06286-053 06286-052
CM
R
OUT
(dB)
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 55. Differential Output Configuration: Gain vs. Frequency
06286-056
06286-055
100
100
90
80
70
.001% SETTLED TO 0
SETTLED TO 0.01%
CMR
OUT
= 20 log V
DIFF_OUT
ME
LIMITED BY
ASUREMENT
SYSTEM
V
CM_OUT
60
50
40
30
20
10
0
10
1
1 10 100 1000
GAIN (V/V)
1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 53. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V Figure 56. Differential Output Configuration:
Common-Mode Output vs. Frequency
Figure 54 Channel Separation vs. Frequency, RL = 2 kΩ, Source Channel at G = 1
Rev. PrB | Page 19 of 27
AD8224 Preliminary Technical Data
THEORY OF OPERATION
+
V
S
+
V
S
+
V
S
+
V
S
OUTPUT
+
IN REF
Q2
Q1
NODE A NODE B
NODE C NODE D
VB
C1 C2
A1 A2
+V
S
–V
S
J1
V
PINCH
+V
S
–V
S
J2 –IN
V
PINCH
–V
S
–V
S
RG
20k
20k
20k
20k
+V
S
–V
S
NODE E
–V
S
+V
S
A3
NODE F
I I
R2
24.7k
R1
24.7k
–V
S
Figure 57. Simplified Schematic
06286-057
The AD8224 is a JFET input, monolithic instrumentation amplifier
based on the classic three op amp topology (see Figure 57). Input
Transistor J1 and Input Transistor J2 are biased at a fixed current so
that any input signal forces the output voltages of A1 and A2 to
change accordingly. The input signal creates a current through RG
that flows in R1 and R2 such that the outputs of A1 and A2 provide
the correct, gained signal. Topologically, J1, A1, R1 and J2, A2, R2
can be viewed as precision current feedback amplifiers with a gain
bandwidth of 1.5 MHz. The common-mode voltage and amplified
differential signal from A1 and A2 are applied to a difference
amplifier that rejects the common-mode voltage but amplifies the
differential signal. The difference amplifier employs 20 k laser
trimmed resistors that result in an in-amp with gain error less than
0.04%. New trim techniques were developed to ensure that CMRR
exceeds 86 dB (G = 1).
Using JFET transistors, the AD8224 offers extremely high input
impedance, extremely low bias currents of 10 pA maximum,
low offset current of 0.6 pA maximum, and no input bias
current noise. In addition, input offset is less than 125 V and
drift is less than 5 V/°C. Ease of use and robustness were
considered. A common problem for instrumentation amplifiers
is that at high gains, when the input is overdriven, an excessive
milliampere input bias current can result and the output can
undergo phase reversal. Overdriving the input at high gains
refers to when the input signal is within the supply voltages but
the amplifier cannot output the gained signal. For example, at a
gain of 100, driving the amplifier with 10 V on ±15 V
constitutes overdriving the inputs since the amplifier cannot
output 100 V.
The AD8224 has none of these problems; its input bias current
is limited to less than 10 A and the output does not phase
reverse under overdrive fault conditions.
The AD8224 has extremely low load induced nonlinearity. All
amplifiers that comprise the AD8224 have rail-to-rail output
capability for enhanced dynamic range. The input of the AD8224
can amplify signals with wide common-mode voltages even
slightly lower than the negative supply rail. The AD8224 operates
over a wide supply voltage range. It can operate from either a
single +4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The
transfer function of the AD8224 is
49.4 k
Ω
G = 1 + RG
Users can easily and accurately set the gain using a single,
standard resistor. Since the input amplifiers employ a current
feedback architecture, the AD8224 gain bandwidth product
increases with gain, resulting in a system that does not experience
as much bandwidth loss as voltage feedback architectures at
higher gains.
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8224. This is calculated by referring to Table 11 or by using
the following gain equation.
49.4 k
RG = G − 1
Rev. PrB | Page 20 of 27
Preliminary Technical Data AD8224
Table 11. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω) Calculated Gain
49.9 k 1.990
12.4 k 4.984
5.49 k 9.998
2.61 k 19.93
1.00 k 50.40
499 100.0
249 199.4
100 495.0
49.9 991.0
The AD8224 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8224’s specifications to determine the total gain
accuracy of the system. When the gain resistor is not used,
gain error and gain drift are kept to a minimum.
REFERENCE TERMINAL
The output voltage of the AD8224 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF1 or REF2 pin
to level-shift the output so that the AD8224 can drive a single-
supply ADC. Pin REFx is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.5 V.
For best performance, source impedance to the REF terminal
should be kept below 1 Ω. As shown in Figure 57 the reference
terminal, REF, is at one end of a 20 k resistor. Additional
impedance at the REF terminal adds to this 20 k resistor and
results in amplification of the signal connected to the positive
input. The amplification from the additional RREF can be
computed by
2
(
20 kΩ + RREF
)
40 kΩ + RREF
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades the amplifier’s
CMRR.
INCORRECT CORRECT CORRECT
AD8224 AD8224
AD8224
+
–
AD8224
OP2177
+
–
06286-058
V
REF
V
REF
V
REF
Figure 58. Driving the Reference Pin
LAYOUT
The AD8224 is a high precision device. To ensure optimum
performance at the PC board level, care must be taken in the
design of the board layout. The AD8224 pinout is arranged in a
logical manner to aid in this task.
Package Considerations
The AD8224 is available in a 16-lead, 4 mm × 4 mm LFCSP.
Blindly copying the footprint from another 4 mm × 4 mm
LFCSP part is not recommended; it may not have the same
thermal pad size and leads. Refer to the Outline Dimensions
section to verify that the PCB symbol has the correct dimensions.
Space between the leads and thermal pad should be kept as
wide as possible for the best bias current performance.
Thermal Pad
The AD8224’s 4 mm × 4 mm LFCSP comes with a thermal pad.
This pad is connected internally to +VS. The pad can either be
left unconnected or connected to the positive supply rail.
To preserve maximum pin compatibility with future dual
instrumentation amplifiers, leave the pad unconnected. This
can be done by not soldering the paddle at all or by soldering
the part to a landing that is a not connected to any other net.
For high vibration applications, a landing is recommended.
Because the AD8224 dissipates little power, heat dissipation is
rarely an issue. If improved heat dissipation is desired (for example,
when driving heavy loads), connect the thermal pad to the
positive supply rail. For the best heat dissipation performance,
the positive supply rail should be a plane in the board. See
the section for thermal coefficients with and without the pad
soldered.
Common-Mode Rejection over Frequency
The AD8224 has a higher CMRR over frequency than typical
in-amps, which gives it greater immunity to disturbances, such
as line noise and its associated harmonics. A well-implemented
layout is required to maintain this high performance. Input
source impedances should be matched closely. Source resistance
should be placed close to the inputs so that it interacts with as
little parasitic capacitance as possible.
Parasitics at the RGx pins can also affect CMRR over frequency.
The PCB should be laid out so that the parasitic capacitances at
each pin match. Traces from the gain setting resistor to the RGx
pins should be kept short to minimize parasitic inductance.
Reference
Errors introduced at the reference terminal feed directly to the
output. Take care to tie the REFx pins to the appropriate local
ground.
Rev. PrB | Page 21 of 27
AD8224 Preliminary Technical Data
Power Supplies
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance.
The AD8224 has two positive supply pins (Pin 5 and Pin 16)
and two negative supply pins (Pin 8 and Pin 13). While the part
functions with only one pin from each supply pair connected,
both pins should be connected for specified performance and
optimum reliability.
The AD8224 should be decoupled with 0.1 µF bypass capacitors,
one for each supply. The positive supply decoupling capacitor
should be placed near Pin 16, and the negative supply
decoupling capacitor should be placed near Pin 8. Each supply
should also be decoupled with a 10 µF tantalum capacitor. The
tantalum capacitor can be placed further away from the
AD8224 and can generally be shared by other precision integrated
circuits. Figure 59 shows an example layout.
AD8224
1
2
3
4
12
11
9
5 6 7 8
13141516
0.1µF
0.1µF
R
G
R
G
10
06286-059
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8224 must have a return path
to common. When the source, such as a transformer, cannot
provide a return current path, one should be created, as shown
in Figure 60.
INPUT PROTECTION
All terminals of the AD8224 are protected against ESD. ESD
protection is guaranteed to 4 kV (human body model).In
addition, the input structure allows for dc overload conditions a
diode drop above the positive supply and a diode drop below
the negative supply. Voltages beyond a diode drop of the
supplies cause the ESD diodes to conduct and enable current to
flow through the diode. Therefore, an external resistor should
be used in series with each of the inputs to limit current for
voltages above +Vs. In either scenario, the AD8224 safely
handles a continuous 6 mA current at room temperature.
For applications where the AD8224 encounters extreme
overload voltages, as in cardiac defibrillators, external series
resistors and low leakage diode clamps, such as BAV199L,
FJH1100, or SP720, should be used.
INCORRECT CORRECT
+V
S
+V
S
REF
AD8224
–V
S
TRANSFORMER TRANSFORMER
REF
–V
S
AD8224
+V
S
+V
S
REF
C
C
–V
S
AD8224
–V
S
CAPACITIVELY COUPLED CAPACITIVELY COUPLED
Figure 60. Creating an IBIAS Path
C
1R
R
REF
AD8224
=
f
HIGH-PASS
2RC
C
0
6286-060
Figure 59. Example Layout
SOLDER WASH
The solder process can leave flux and other contaminants on
the board. When these contaminants are between the AD8224
leads and thermal pad, they can create leakage paths that are
larger than the AD8224’s bias currents. A thorough washing
process removes these contaminants and restores the device’s
excellent bias current performance.
RF INTERFERENCE
RF rectification is often a problem in applications where there are
large RF signals. The problem appears as a small dc offset voltage.
The AD8224 by its nature has a 5 pF gate capacitance (CG) at its
inputs. Matched series resistors form a natural low-pass filter that
reduces rectification at high frequency (see Figure 61). The
relationship between external, matched series resistors and the
internal gate capacitance is expressed as follows:
Rev. PrB | Page 22 of 27
Preliminary Technical Data AD8224
1
FilterFreqDIFF = 2π
RCG
1
FilterFreqCM = 2πRCG
+15
V
1
FilterFreqCM = 2πR(CC + CG )
Mismatched CC capacitors result in mismatched low-pass filters.
The imbalance causes the AD8224 to treat what would have
been a common-mode signal as a differential signal. To reduce
the effect of mismatched external CC capacitors, select a value of
CD greater than 10 times CC. This sets the differential filter
frequency lower than the common-mode frequency.
+15
V
AD8224
C
G
C
G
–V
S
REF
–V
S
R
R
+IN
–IN
0.1µF 10µF
0.1µF 10µF
+
+
R
R
AD8224
+IN
–IN
0.1µF 10µF
10µF
0.1µF
REF
V
OUT
–15V
C
D
C
C
C
C
10nF
1nF
1nF
4.02k
4.02k
06286-062
+
+
Figure 62. RFI Suppression
COMMON-MODE INPUT VOLTAGE RANGE
V
OUT
–15V
06286-061
Figure 61. RFI Filtering Without External Capacitors
To eliminate high frequency common-mode signals while using
smaller source resistors, a low-pass R-C network can be placed
at the input of the instrumentation amplifier (see Figure 62).
The filter limits the input signal bandwidth according to the
following relationship:
1
FilterFreqDIFF = 2πR(2 CD + CC + CG )
The three op amp architecture of the AD8224 applies gain and
then removes the common-mode voltage. Therefore, internal
nodes in the AD8224 experience a combination of both the
gained signal and the common-mode signal. This combined
signal can be limited by the voltage supplies even when the
individual input and output signals are not. Figure 26, Figure 27,
Figure 28, and Figure 29 show the allowable common-mode
input voltage ranges for various output voltages, supply voltages,
and gains.
Rev. PrB | Page 23 of 27
AD8224 Preliminary Technical Data
APPLICATIONS
DRIVING AN ANALOG-TO-DIGITAL CONVERTER
+IN
store and deliver necessary charge to the switched capacitor input
of the ADC. The 500 series resistor reduces the burden of the
+
–
+
–
AD8224
AD8224
REF2
An instrumentation amplifier is often used in front of an analog-to-
R
G
+OUT
+IN2
digital converter to provide CMRR and additional conditioning
20k
–IN
such as a voltage level shift and gain (see Figure 63). In this
example, a 2.7 nF capacitor and a 500 resistor create an anti-
33pF
aliasing filter for the AD7685. The 2.7 nF capacitor also serves to
06286-064
2.7 nF load from the amplifier. However, large source impedance in
–OUT
front of the ADC can degrade total harmonic distortion (THD). Figure 64. Differential Circuit Schematic
For applications where THD performance is critical, the series Setting the Common-Mode Voltage
resistor needs to be small. At worst, a small series resistor can load The output common-mode voltage is set by the average of +IN2
the AD8224, potentially causing the output to overshoot or ring. and REF2. The transfer function is
In such cases, a buffer amplifier, such as the AD8615, should be
used after the AD8224 to drive the ADC. VCM_OUT = (V+OUT + V−OUT)/2 = (V+IN2 + VREF2)/2
+5V
+IN2 and REF2 have different properties that allow the
AD8224
AD7685
ADR435
+5V
2.7nF
REF
500
1.07k
+2.5V
+IN
–IN
0.1µF 10µF +
reference voltage to be easily set for a wide variety of applications.
+IN2 has high impedance but cannot swing to the supply rails
4.7µF
of the part. REF2 must be driven with a low impedance, but can
go 300 mV beyond the supply rails.
±50mV
A common application sets the common-mode output voltage
to the midscale of a differential ADC. In this case, the ADC
reference voltage is sent to the +IN2 terminal, and ground is
connected to the REF2 terminal. This produces a common-
mode output voltage of half the ADC reference voltage.
06286-063
Figure 63. Driving an ADC in a Low Frequency Application
2-Channel Differential Output Using a Dual Op Amp
Another differential output topology is shown in Figure 65.
Instead of a second in-amp, ½ of a dual OP2177 op amp creates
the inverted output. Because the OP2177 comes in an MSOP,
this configuration allows the creation of a dual channel,
precision differential output in-amp with little board area.
Errors from the op amp are common to both outputs and are
thus common mode. Errors from mismatched resistors also
create a common-mode dc offset. Because these errors are
common mode, they are likely to be rejected by the next device
in the signal chain.
+IN
AD8224
4.99k
+
–
OP2177
4.99k
+OUT
REF V
REF
06286-065
DIFFERENTIAL OUTPUT
The differential configuration of the AD8224 has the same
excellent dc precision specifications as the single-ended output
configuration and is recommended for applications in the
frequency range of dc to 100 kHz.
The circuit configuration, outlined in Table 7, refers to the
configuration shown in Figure 64 only. The circuit includes an RC
filter that maintains the stability of the loop.
The transfer function for the differential output is:
VDIFF_OUT = V+OUT − V−OUT = (V+IN − V−IN) × G
where:
49.4 k
G = 1 +
–IN
RG
–OUT
Figure 65. Differential Output Using Op Amp
Rev. PrB | Page 24 of 27
Preliminary Technical Data AD8224
+12
V
10µF
+IN
–IN
10µF
AD8224
(DIFF OUT)
100pF
NPO
5%
100pF
NPO
5%
1000pF
0.1µF
0.1µF
–12V
1k
1k
+
+
IN+
VDD
GND REF
10µF
X5R
AD7688
IN–
0.1µF
+5V
ADR435
GND
V
IN
V
OUT
0.1µF
+12V
0.1µF
+IN2
REF2
+5V REF
+OUT
–OUT
806
2.7nF 2.7nF
806
+5V REF
06286-066
Figure 66. Driving a Differential ADC
DRIVING A DIFFERENTIAL INPUT ADC
The AD8224 can be configured in differential output mode
to drive a differential analog-to-digital converter. Figure 66
illustrates several of the concepts.
First Antialiasing Filter
The 1 kΩ resistor, 1000 pF capacitor, and 100 pF capacitors in
front of the in-amp form a 76 kHz filter. This is the first of two
antialiasing filters in the circuit and helps to reduce the noise of
the system. The 100 pF capacitors protect against common-
mode RFI signals. Note that they are 5% COG/NPO types.
These capacitors match well over time and temperature, which
keeps the system’s CMRR high over frequency.
Second Antialiasing Filter
An 806 Ω resistor and 2.7 nF capacitor are located between each
AD8224 output and ADC input. They create a 73 kHz low-pass
filter for another stage of antialiasing protection.
These four elements also isolate the ADC from loading the
AD8224. The 806 Ω resistor shields the AD8224 from the
ADC’s switched capacitor input which looks like a time varying
load. The 2.7 nF capacitor provides charge to the switched
capacitor front end of the ADC. If the application requires a
lower frequency antialiasing filter, increase the value of the
capacitor rather than the resistor.
The 1 kΩ resistors can also protect an ADC from overvoltages.
Because the AD8224 runs on wider supply voltages than a
typical ADC, there is a possibility of overdriving the ADC. This
is not an issue with a PulSAR® converter, such as the AD7688.
Its input can handle a 130 mA overdrive, which is much higher
Reference
The ADR435 supplies a reference voltage to both the ADC and
the AD8224. Because REF2 on the AD8224 is grounded, the
common-mode output voltage is precisely half the reference
voltage, exactly where it needs to be for the ADC.
DRIVING CABLING
All cables have a certain capacitance per unit length, which
varies widely with cable type. The capacitive load from the cable
may cause peaking in the AD8224 output response. To reduce
peaking, use a resistor between the AD8224 and the cable.
Because cable capacitance and desired output response vary
widely, this resistor is best determined empirically. A good
starting point is 50 Ω.
The AD8224 operates at a low enough frequency that
transmission line effects are rarely an issue; therefore, the
resistor need not match the characteristic impedance of
the cable.
AD8224
(DIFF OUT)
AD8224
(SINGLE OUT)
06286-067
than the short-circuit limit of the AD8224. However, other Figure 67. Driving a Cable
converters have less robust inputs and may need the added
protection.
Rev. PrB | Page 25 of 27
AD8224 Preliminary Technical Data
OUTLINE DIMENSIONS
0.50
0.40
4.00
BSC SQ
1
12 13 16
3.75 EXPOSED
BSC SQ PAD
4
98 5
TOP VIEW
12° MAX 0.80 MAX
0.65 TYP
0.23
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-VGGC.
Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-13)
Dimensions are shown in millimeters
ORDERING GUIDE
0.65
BSC
0.60 MAX
PIN 1
INDICATOR
1.95 BCS
0.30
0.25 MIN
SEATING
PLANE
PIN 1
INDI
C
ATOR
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.05 MAX
0.02 NOM
0.20 REF
2.65
2.50 SQ
2.35
BOTTOM VIEW
031006-A
Model Temperature Range Product Description Package Option
AD8224ACPZ-R71 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224ACPZ-RL1 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224ACPZ-WP1 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224BCPZ-R71 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224BCPZ-RL1 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224BCPZ-WP1 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13
AD8224-EVALZ Evaluation Board
1 Z = Pb-free part.
Rev. PrB | Page 26 of 27
Preliminary Technical Data AD8224
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06286-0-12/06(PrB)
Rev. PrB | Page 27 of 27
