Single Channel, 12-/16-Bit, Serial Input, Current
Source and Voltage Output DACs, HART Connectivity
Data Sheet
AD5412/AD5422
Rev. O Document Feedback
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FEATURES
12-/16-bit resolution and monotonicity
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or
0 mA to 24 mA
±0.01% FSR typical total unadjusted error (TUE)
±3 ppm FSR/°C output drift
Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V
10% overrange
±0.01% FSR typical TUE
±2 ppm FSR/°C output drift
Flexible serial digital interface
On-chip output fault detection
On-chip reference: 10 ppm/°C maximum
Optional regulated DVCC output
Asynchronous clear function
Power supply range
AVDD: 10.8 V to 40 V
AVSS: −26.4 V to −3 V/0 V
Current loop compliance voltage: AVDD – 2.5 V
Temperature range: −40°C to +105°C
TSSOP and LFCSP packages
APPLICATIONS
Process controls
Actuator controls
PLC
HART network connectivity (LFCSP package only)
GENERAL DESCRIPTION
The AD5412/AD5422 are low cost, precision, fully integrated
12-/16-bit digital-to-analog converters (DAC) offering a pro-
grammable current source and programmable voltage output
designed to meet the requirements of industrial process control
applications.
The output current range is programmable at 4 mA to 20 mA,
0 mA to 20 mA, or an overrange function of 0 mA to 24 mA.
The LFCSP version of this product has a CAP2 pin so that the
HART signals can be coupled onto the current output of the
AD5412/AD5422.
Voltage output is provided from a separate pin that can be
configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V
output ranges; an overrange of 10% is available on all ranges.
Analog outputs are short and open-circuit protected and can
drive capacitive loads of 1 µF.
The device operates with an AVDD power supply range from 10.8 V
to 40 V. Current loop compliance voltage is 0 V to AVDD − 2.5 V.
The flexible serial interface is SPI- and MICROWIRE™-compatible
and can be operated in 3-wire mode to minimize the digital
isolation required in isolated applications.
The device also includes a power-on-reset function, ensuring
that the device powers up in a known state. The part also includes
an asynchronous clear pin (CLEAR) that sets the outputs to
zero-scale/midscale voltage output or the low end of the
selected current range.
The total output error is typically ±0.01% in current mode and
±0.01% in voltage mode.
Table 1. Pin-Compatible Devices
Part No. Description
AD5410 Single channel, 12-bit, serial input current source DAC
AD5420 Single channel, 16-bit, serial input current source DAC
COMPANION PRODUCTS
HART Modem: AD5700, AD5700-1
AD5412/AD5422 Data Sheet
Rev. O | Page 2 of 44
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Companion Products ....................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications ..................................................................................... 5
AC Performance Characteristics .............................................. 10
Timing Characteristics .............................................................. 10
Absolute Maximum Ratings .......................................................... 13
ESD Caution ................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 16
General ......................................................................................... 16
Voltage Output ............................................................................ 18
Current Output ........................................................................... 23
Terminology .................................................................................... 27
Theory of Operation ...................................................................... 29
Architecture ................................................................................. 29
Serial Interface ............................................................................ 30
Power-On State ........................................................................... 31
Data Register ............................................................................... 33
Control Register .......................................................................... 33
Reset Register .............................................................................. 34
Status Register ............................................................................. 34
AD5412/AD5422 Features ............................................................ 35
Fault Alert .................................................................................... 35
Voltage Output Short Circuit Protection ................................ 35
Voltage Output Overrange ........................................................ 35
Voltage Output Force-Sense ..................................................... 35
Asynchronous Clear (CLEAR) ................................................. 35
Internal Reference ...................................................................... 35
External Current Setting Resistor ............................................ 35
Digital Power Supply .................................................................. 36
External Boost Function............................................................ 36
External Compensation Capacitor........................................... 36
HART Communication ............................................................. 36
Digital Slew Rate Control .......................................................... 36
IOUT Filtering Capacitors (LFCSP Package) ............................. 37
Applications Information .............................................................. 39
Voltage and Current Output Ranges on the Same Terminal 39
Driving Inductive Loads ............................................................ 39
Transient Voltage Protection .................................................... 39
Galvanically Isolated Interface ................................................. 39
Microprocessor Interfacing ....................................................... 39
Layout Guidelines....................................................................... 40
Thermal and Supply Considerations ....................................... 40
Industrial Analog Output Module ........................................... 41
Industrial HART Capable Analog Output Application ........ 41
Outline Dimensions ....................................................................... 43
Ordering Guide .......................................................................... 44
Data Sheet AD5412/AD5422
Rev. O | Page 3 of 44
REVISION HISTORY
10/2017—Rev. N to Rev. O
Changed CP-40-10 to CP-40-1 .................................... Throughout
Updated Outline Dimensions ........................................................ 43
Changes to Ordering Guide ........................................................... 44
3/2017—Rev. M to Rev. N
Changed CP-40-9 to CP-40-10 .................................... Throughout
Changes to Table 6 .......................................................................... 13
Changes to Figure 85 ...................................................................... 43
Updated Outline Dimensions ........................................................ 43
Changes to Ordering Guide ........................................................... 44
7/2016—Rev. L to Rev. M
Changed −40°C to +85°C to −40°C to +105°C and CP-40-1 to
CP-40-9 ........................................................................... Throughout
Changes to Table 2 ............................................................................ 5
Added Table 3; Renumbered Sequentially ..................................... 9
Changes to Figure 6......................................................................... 14
Changes to Thermal and Supply Conditions Section ................ 40
Updated Outline Dimensions ........................................................ 43
Changes to Ordering Guide ........................................................... 44
7/2015—Rev. K to Rev. L
Change to IOUT to GND Parameter, Table 5 ................................. 11
Change to Voltage and Current Output Ranges on the Same
Terminal Section ............................................................................. 37
3/2015—Rev. J to Rev. K
Changes to Table 4 ............................................................................ 9
Changes to Table 6 .......................................................................... 13
Changes to Power-On State Section ............................................. 29
10/2014—Rev. I to Rev. J
Changes to Power-On State Section ............................................. 29
Changes to Table 25 ........................................................................ 39
10/2013—Rev. H to Rev. I
Added Figure 34 and Figure 35; Renumbered Sequentially ...... 18
Changes to Figure 78 ...................................................................... 37
Changes to Industrial Analog Output Module Section ............. 39
Changes to Industrial HART Capable Analog Output
Application Section ......................................................................... 39
6/2013—Rev. G to Rev. H
Change to REFOUT Pin, Table 6 .................................................. 12
Changes to Voltage and Current Output Ranges on the Same
Terminal Section and Figure 75 .................................................... 36
3/2013—Rev. F to Rev. G
Changed TSSOP_EP θJA from 42°C/W to 35°C/W, Changed
LFCSP θJA from 28°C/W to 33°C/W, and Added Endnote 2 ..... 11
Added Figure 67 .............................................................................. 30
Changes to REXT Description; Table 15 ...................................... 31
Changes to Table 21 ........................................................................ 33
Changes to Thermal and Supply Considerations Section ......... 38
Changes to Table 25 ........................................................................ 39
7/2012—Rev. E to Rev. F
Updated Outline Dimensions........................................................ 40
Changes to Ordering Guide ........................................................... 40
5/2012—Rev. D to Rev. E
Reorganized Layout ........................................................... Universal
Changes to Product Title.................................................................. 1
Changes to Features Section, Applications Section, and General
Description Section; Added Companion Products Section ............. 1
Changes to Figure 1 .......................................................................... 3
Change to Offset Error Temperature Coefficient (TC)
Parameter, Table 1 ............................................................................. 4
Changes to Table 6 .......................................................................... 12
Changes to Power-On State Section ............................................. 29
Added HART Communication Section and Figure 68,
Renumbered Sequentially .............................................................. 33
Added Voltage and Current Output Ranges on the Same
Terminal Section and Figure 74 .................................................... 36
Added Industrial HART Capable Analog Output Application
Section .............................................................................................. 38
Added Figure 79 .............................................................................. 39
11/2011—Rev. C to Rev. D
Changes to Table 15 ........................................................................ 29
3/2010—Rev. B to Rev. C
Changes to AVSS to GND Parameter in Table 5 ......................... 10
2/2010—Rev. A to Rev. B
Changes to Thermal and Supply Considerations Section and
Table 25 ............................................................................................. 36
8/2009—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 7
Changes to Introduction to Table 4 ................................................ 8
Changes to Introduction to Table 5 and to Table 5 .................... 10
Changes to Pin Configurations and Function Descriptions
Section, Added Figure 6, Renumbered Subsequent Figures ..... 11
Changes to Theory of Operation Section .................................... 26
Changes to Architecture Section ................................................... 26
Changes to AD5412/AD5422 Features Section .......................... 31
Added IOUT Filtering Capacitors (LFCSP Package) Section,
Including Figure 69 to Figure 72 and Table 24 ............................ 33
Changes to Thermal and Supply Considerations Section ......... 36
Updated Outline Dimensions........................................................ 38
Changes to Ordering Guide ........................................................... 39
5/2009—Revision 0: Initial Version
AD5412/AD5422 Data Sheet
Rev. O | Page 4 of 44
FUNCTIONAL BLOCK DIAGRAM
INPUT SHIFT
REGISTER
AND CONTROL
LOGIC
POWER-ON
RESET VREF
AD5412/AD5422
12-/16-BIT
DAC
12/16
LATCH
SCLK
SDIN
SDO
REFOUT REFIN
RANGE
SCALING
GND C
COMP
–V
SENSE
V
OUT
+V
SENSE
R
SET
R
SET
I
OUT
BOOST
FAULT
CLEAR
CLEAR
SELECT
DV
CC
SELECT DV
CC
AV
SS
*CAP1
*PINS ONLY ON LFCSP OPTION.
*CAP2 AV
DD
R2
06996-001
R3
4.5V LDO
Figure 1.
Data Sheet AD5412/AD5422
Rev. O | Page 5 of 44
SPECIFICATIONS
AVDD = 10.8 V to 26.4 V, AV SS = −26.4 V to −3 V/0 V, AV DD + |AVSS| < 52.8 V, G N D = 0 V, R E F I N = 5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1 Min Typ Max Unit Test Conditions/Comments
VOLTAGE OUTPUT
Output Voltage Ranges 0 5 V
0 10 V
−5 +5 V
−10 +10 V
Accuracy Output unloaded
Resolution 16 Bits AD5422
12 Bits AD5412
Total Unadjusted Error (TUE)
B Version −0.1 +0.1 % FSR
−0.05
±0.01
% FSR
T
A
= 25°C
A Version −0.3 +0.3 % FSR TA = −40°C to +85°C
−0.1 ±0.05 +0.1 % FSR TA = 25°C
Relative Accuracy (INL)2 −0.008 +0.008 % FSR AD5422
−0.032 +0.032 % FSR AD5412
Differential Nonlinearity (DNL) −1 +1 LSB TA = −40°C to +85°C, guaranteed monotonic
−1 +1.3 LSB Guaranteed monotonic
Bipolar Zero Error −6 +6 mV TA = −40°C to +85°C, bipolar output range
−9 +9 mV Bipolar output range
−1.5 ±0.2 +1.5 mV TA = 25°C, bipolar output range
Bipolar Zero Error Temperature
Coefficient (TC)
3
±3 ppm FSR/°C Bipolar output range
Zero-Scale Error
−5
mV
T
A
= −40°C to +85°C
−8 +8 mV
−3.5 ±0.3 +3.5 mV TA = 25°C
Zero-Scale Error TC3 ±2 ppm FSR/°C
Offset Error −4 +4 mV TA = −40°C to +85°C, unipolar output range
−6 +6 mV Unipolar output range
−1.5 ±0.2 +1.5 mV TA = 25°C, unipolar output range
Offset Error TC3 ±2 ppm FSR/°C Unipolar output range
Gain Error −0.07 +0.07 % FSR
−0.05 ±0.004 +0.05 % FSR TA = 25°C
Gain Error TC3 ±1 ppm FSR/°C TA = −40°C to +85°C
±3 ppm FSR/°C
Full-Scale Error −0.07 +0.07 % FSR
−0.05 ±0.001 +0.05 % FSR TA = 25°C
Full-Scale Error TC3 ±1 ppm FSR/°C TA = −40°C to +85°C
±2 ppm FSR/°C
AD5412/AD5422 Data Sheet
Rev. O | Page 6 of 44
Parameter1 Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS3
Headroom 0.5 0.8 V Output unloaded
Output Voltage Drift vs. Time 90 ppm FSR Drift after 1000 hours, TA = 125°C
Short-Circuit Current 20 mA
Load
1
kΩ
Capacitive Load Stability TA = 25°C
RLOAD = ∞ 20 nF
RLOAD = 1 kΩ 5 nF
RLOAD = ∞ 1 µF External compensation capacitor of 4 nF
connected
DC Output Impedance
0.3
Ω
Power-On Time 10 µs
DC PSRR 90 130 µV/V
3 12 µV/V Output unloaded
CURRENT OUTPUT
Output Current Ranges 0 24 mA
0 20 mA
4 20 mA
Accuracy (Internal RSET)
Resolution 16 Bits AD5422
12 Bits AD5412
TUE
B Version −0.3 +0.3 % FSR
−0.13 ±0.08 +0.13 % FSR TA = 25°C
A Version
−0.5
% FSR
T
A
= −40°C to +85°C
−0.3 ±0.15 +0.3 % FSR TA = 25°C
INL4 −0.024 +0.024 % FSR AD5422
−0.032 +0.032 % FSR AD5412
DNL −1 +1 LSB TA = −40°C to +85°C, guaranteed monotonic
−1 +1.3 LSB Guaranteed monotonic
Offset Error −0.27 +0.27 % FSR TA = −40°C to +85°C
−0.40 +0.40 % FSR
−0.12 ±0.08 +0.12 % FSR TA = 25°C
Offset Error TC3 ±16 ppm FSR/°C TA = −40°C to +85°C
±28 ppm FSR/°C
Gain Error −0.18 +0.18 % FSR TA = −40°C to +85°C, AD5422
−0.20 +0.20 % FSR AD5422
−0.03 ±0.006 +0.03 % FSR AD5422, TA = 25°C
−0.22 +0.22 % FSR TA = −40°C to +85°C, AD5412
−0.24 +0.24 % FSR AD5412
−0.06 ±0.006 +0.06 % FSR AD5412, TA = 25°C
Gain TC3 ±10 ppm FSR/°C TA = −40°C to +85°C
±21 ppm FSR/°C
Full-Scale Error −0.2 +0.2 % FSR TA = −40°C to +85°C
−0.40 +0.40 % FSR
−0.1
±0.08
% FSR
T
A
= 25°C
Full-Scale TC3 ±6 ppm FSR/°C TA = −40°C to +85°C
±13 ppm FSR/°C
Data Sheet AD5412/AD5422
Rev. O | Page 7 of 44
Parameter1 Min Typ Max Unit Test Conditions/Comments
Accuracy (External RSET)
Resolution 16 Bits AD5422
12 Bits AD5412
TUE
B Version
−0.15
% FSR
−0.06 ±0.01 +0.06 % FSR TA = 25°C
A Version −0.3 +0.3 % FSR TA = −40°C to +85°C
−0.1 ±0.02 +0.1 % FSR TA = 25°C
INL4 −0.012 +0.012 % FSR AD5422
−0.032 +0.032 % FSR AD5412
DNL −1 +1 LSB TA = −40°C to +85°C, guaranteed monotonic
−1 +1.3 LSB Guaranteed monotonic
Offset Error −0.1 +0.1 % FSR TA = −40°C to +85°C
−0.12 +0.12 % FSR
−0.03 ±0.006 +0.03 TA = 25°C
Offset Error TC3 ±3 ppm FSR/°C TA = −40°C to +85°C
±5 ppm FSR/°C
Gain Error −0.08 +0.08 % FSR TA = −40°C to +85°C
−0.15 +0.15 % FSR
−0.05 ±0.003 +0.05 % FSR TA = 25°C
Gain TC3 ±4 ppm FSR/°C
Full-Scale Error
−0.15
% FSR
−0.06 ±0.01 +0.06 % FSR TA = 25°C
Full-Scale Error TC3 ±7 ppm FSR/°C TA = −40°C to +85°C
±9 ppm FSR/°C
OUTPUT CHARACTERISTICS3
Current Loop Compliance Voltage 0 AVDD − 2.5 V
Output Current Drift vs. Time Drift after 1000 hours, TA = 125°C
50 ppm FSR Internal RSET
20 ppm FSR External RSET
Resistive Load 1200 Ω
Inductive Load 50 mH TA = 25 °C
DC PSRR 1 µA/V
Output Impedance 50 MΩ
Output Current Leakage When Output
Disabled
60 pA
REFERENCE INPUT/OUTPUT
Reference Input3
Reference Input Voltage
4.95
5
V
For specified performance
DC Input Impedance 27 40 kΩ
Reference Output
Output Voltage 4.995 5 5.005 TA = 25°C
Reference TC3, 5 1.8 10 ppm/°C
Output Noise (0.1 Hz to 10 Hz)3 10 µV p-p
Noise Spectral Density3 100 nV/√Hz At 10 kHz
Output Voltage Drift vs. Time3 50 ppm Drift after 1000 hours, TA = 125°C
Capacitive Load3 600 nF
Load Current3 5 mA
Short-Circuit Current3 7 mA
Load Regulation3 95 ppm/mA
AD5412/AD5422 Data Sheet
Rev. O | Page 8 of 44
Parameter1 Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS3 JEDEC compliant
Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input Current −1 +1 µA Per pin
Pin Capacitance
10
pF
Per pin
DIGITAL OUTPUTS3
SDO
Output Low Voltage, VOL 0.4 V Sinking 200 µA
Output High Voltage, VOH DVCC − 0.5 V Sourcing 200 µA
High Impedance Leakage Current −1 +1 µA
High Impedance Output Capacitance 5 pF
FAULT
Output Low Voltage, VOL 0.4 V 10 kΩ pull-up resistor to DVCC
Output Low Voltage, VOL 0.6 V At 2.5 mA
Output High Voltage, VOH 3.6 V 10 kΩ pull-up resistor to DVCC
POWER REQUIREMENTS
AVDD 10.8 40 V
AVSS −26.4 0 V
|AVSS| + AVDD 10.8 52.8 V
DVCC
Input Voltage 2.7 5.5 V Internal supply disabled
Output Voltage
4.5
V
DV
CC
, which can be overdriven up to 5.5 V
Output Load Current3 5 mA
Short-Circuit Current3 20 mA
AIDD Outputs unloaded
2.5 3 mA Outputs disabled
3.4 4 mA Current output enabled
3.9 4.4 mA Voltage output enabled
AISS Outputs unloaded
0.24 0.3 mA Outputs disabled
0.5 0.6 mA Current output enabled
1.1 1.4 mA Voltage output enabled
DICC 1 mA VIH = DVCC, VIL = GND
Power Dissipation 128 mW AVDD = 40 V, AVSS = 0 V, outputs unloaded
120 mW AVDD = +24 V, AVSS = −24 V, outputs unloaded
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 When the AD5412/AD5422 is powered with AVSS = 0 V, INL for the 0 V to 5 V and 0 V to 10 V ranges is measured beginning from Code 256 for the AD5422 and Code 16
for the AD5412.
3 Guaranteed by design and characterization; not production tested.
4 For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412.
5 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +105°C.
Data Sheet AD5412/AD5422
Rev. O | Page 9 of 44
AVDD = 15 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. Voltage over range enabled.
Table 3.
Parameter1 Min Typ Max Unit Test Conditions/Comments
VOLTAGE OUTPUT
Output Voltage Ranges 0 5.5 V
0
11
V
−5.5 +5.5 V
−11 +11 V
Accuracy Output unloaded
Resolution 16 Bits AD5422
12 Bits AD5412
Total Unadjusted Error (TUE)
B Version −0.13 +0.13 % FSR
−0.10 ±0.01 +0.10 % FSR TA = 25°C
Relative Accuracy (INL)2 −0.008 +0.008 % FSR AD5422
−0.032 +0.032 % FSR AD5412
Differential Nonlinearity (DNL) −1 +1.3 LSB Guaranteed monotonic
Bipolar Zero Error −9 +9 mV Bipolar output range
Bipolar Zero Error Temperature Coefficient (TC)3 ±3 ppm FSR/°C Bipolar output range
Zero-Scale Error −18 +18 mV
Zero-Scale Error TC3 ±2 ppm FSR/°C
Offset Error −6 +6 mV Unipolar output range
Offset Error TC
3
±2
ppm FSR/°C
Unipolar output range
Gain Error −0.13 +0.13 % FSR
Gain Error TC3 ±3 ppm FSR/°C
Full-Scale Error −0.13 +0.13 % FSR
Full-Scale Error TC3 ±2 ppm FSR/°C
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 When the AD5412/AD5422 is powered with AVSS = 0 V, INL for the 0 V to 5.5 V and 0 V to 11 V ranges is measured beginning from Code 256 for the AD5422 and Code
16 for the AD5412.
3 Guaranteed by design and characterization; not production tested.
AD5412/AD5422 Data Sheet
Rev. O | Page 10 of 44
AC PERFORMANCE CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, AV SS = −26.4 V to −3 V/0 V, AV DD + |AVSS| < 52.8 V, G N D = 0 V, R E F I N = +5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1 Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Voltage Output
Output Voltage Settling Time 25 µs 10 V step to ±0.03 % FSR
32 µs 20 V step to ±0.03 % FSR
18 µs 5 V step to ±0.03 % FSR
8 µs 512 LSB step to ±0.03 % FSR (16-Bit LSB)
Slew Rate 0.8 V/µs
Power-On Glitch Energy 10 nV-sec
Digital-to-Analog Glitch Energy 10 nV-sec
Glitch Impulse Peak Amplitude 20 mV
Digital Feedthrough
1
nV-sec
Output Noise (0.1 Hz to 10 Hz Bandwidth) 0.1 LSB p-p 16-bit LSB
Output Noise (100 kHz Bandwidth) 200 µV rms
1/f Corner Frequency 1 kHz
Output Noise Spectral Density 150 nV/√Hz Measured at 10 kHz, midscale output, 10 V range
AC PSRR −75 dB 200 mV 50 Hz/60 Hz sine wave superimposed on power
supply voltage
Current Output
Output Current Settling Time 10 µs 16 mA step to 0.1% FSR
40 µs 16 mA step to 0.1% FSR, L = 1 mH
AC PSRR −75 dB 200 mV 50 Hz/60 Hz sine wave superimposed on power
supply voltage
1 Guaranteed by characterization, not production tested.
TIMING CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AV DD + |AV SS| < 52.8V, G N D = 0 V, R E F IN = +5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description
WRITE MODE
t1 33 ns min SCLK cycle time
t2 13 ns min SCLK low time
t3 13 ns min SCLK high time
t4 13 ns min LATCH delay time
t5 5 µs min LATCH high time
t6 5 ns min Data setup time
t7 5 ns min Data hold time
t8 40 ns min LATCH low time
t9 20 ns min CLEAR pulse width
t10 5 µs max CLEAR activation time
Data Sheet AD5412/AD5422
Rev. O | Page 11 of 44
Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description
READBACK MODE
t11 90 ns min SCLK cycle time
t12 40 ns min SCLK low time
t13 40 ns min SCLK high time
t
14
13
ns min
LATCH delay time
t15 40 ns min LATCH high time
t16 5 ns min Data setup time
t17 5 ns min Data hold time
t18 40 ns min LATCH low time
t19 35 ns max Serial output delay time (CL SDO4 = 15 pF)
t20 35 ns max LATCH rising edge to SDO tristate (CL SDO4 = 15 pF)
DAISY-CHAIN MODE
t21 90 ns min SCLK cycle time
t
22
40
ns min
SCLK low time
t23 40 ns min SCLK high time
t24 13 ns min LATCH delay time
t25 40 ns min LATCH high time
t26 5 ns min Data setup time
t
27
5
ns min
Data hold time
t28 40 ns min LATCH low time
t29 35 ns max Serial output delay time (CL SDO4 = 15 pF)
1 Guaranteed by characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 CL SDO = capacitive load on SDO output.
Timing Diagrams
DB23
SCLK
LATCH
SDIN
2421
DB0
t
2
t
3
t
1
t
4
t
8
t
7
t
6
t
9
t
10
t
5
CLEAR
I
OUT
, V
OUT
06996-002
Figure 2. Write Mode Timing Diagram
AD5412/AD5422 Data Sheet
Rev. O | Page 12 of 44
DB23
SCLK
LATCH
SDIN
24
21
DB0
SDO
DB23
SELECTED REGISTER
DATA CLOCKED OUT
NOP CONDITION
UNDEFINED DATA
INPUT WORD SPECIFIES
REGISTER TO BE READ
1 2 24
DB0
DB15 DB0
XXXX
8 9 23
22
FIRST 8 BITS ARE
DON’T CARE BITS
t
20
t
19
t
17
t
12
t
13
t
14
t
11
t
15
t
16
t
18
06996-003
Figure 3. Readback Mode Timing Diagram
DB23 DB23
SCLK
SDIN
2421
DB0 DB0
DB0
SDO DB23
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N – 1
UNDEFINED
INPUT WORD FOR DAC N
25 4826
LATCH
DB23 DB0
t
20
t
28
t
27
t
26
t
29
t
22
t
23
t
21
t
24
t
25
06996-004
Figure 4. Daisy-Chain Mode Timing Diagram
Data Sheet AD5412/AD5422
Rev. O | Page 13 of 44
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
80 mA do not cause SCR latch-up.
Table 6.
Parameter Rating
AVDD to GND −0.3 V to +48 V
AVSS to GND +0.3 V to −28 V
AVDD to AVSS −0.3 V to +60 V
DVCC to GND −0.3 V to +7 V
Digital Inputs to GND −0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
Digital Outputs to GND −0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
REFIN/REFOUT to GND −0.3 V to +7 V
VOUT to GND AVSS to AVDD
IOUT to GND AVSS to AVDD
Operating Temperature Range (T
A
)
Industrial1 −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 125°C
24-Lead TSSOP_EP Package
θJA Thermal Impedance2 35°C/W
40-Lead LFCSP Package
θJA Thermal Impedance2 33°C/W
Power Dissipation (TJ max – TA)/θJA
Lead Temperature JEDEC industry standard
Soldering J-STD-020
1 Power dissipated on chip must be derated to keep the junction temperature
below 125°C, assuming that the maximum power dissipation condition is
sourcing 24 mA into GND from IOUT with a 4 mA on-chip current.
2 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with thermal vias. See JEDEC JESD51.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD5412/AD5422 Data Sheet
Rev. O | Page 14 of 44
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
12
11
DVCC
FAULT
GND
LATCH
CLEAR
CLEAR SELECT
AVSS
SCLK
SDIN
GND
GND
SDO
20
21
22
23
24
19
18
17
16
15
14
13
–VSENSE
+VSENSE
VOUT
NC
NOTES
1. NC = NO CONNECT
2. THE PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT VOLTAGE RANGE
IS UNIPOLAR. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED
PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE AVSS PIN. IT IS
RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A
COPPER PLANE FOR ENHANCED THERM
A
L PERFORMANCE.
IOUT
BOOST
CCOMP
DVCC SELECT
RSET
REFOUT
REFIN
AVDD
AD5412/
AD5422
TOP VIEW
(Not to Scale)
06996-005
Figure 5. TSSOP Pin Configuration
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT
VOLTAGE RANGE IS UNIPOLAR. THE EXPOSED PADDLE CAN BE LEFT
ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION
IS MADE AT THE AV
SS
PIN. IT IS RECOMMENDED THAT THE PADDLE BE
THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
NC
FAULT
GND
CLEAR SELECT
CLEAR
LATCH
SCLK
SDIN
SDO
NC
DV
CC
SELECT
C
COMP
NC
I
OUT
BOOST
CAP1
CAP2
NC
NC
NC
NC
GND
GND
GND
REFOUT
R
SET
REFIN
NC
NC
AV
SS
+V
SENSE
–V
SENSE
NC
AV
DD
AV
SS
NC
DV
CC
NC
V
OUT
NC
06996-006
AD5412/
AD5422
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
Figure 6. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description TSSOP LFCSP
1 14, 37 AVSS Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be
connected to 0 V if the output voltage range is unipolar.
2 39 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. This pin can also be configured as a
4.5 V LDO output by leaving the DVCC SELECT pin floating.
3 2 FAULT Fault Alert. This pin is asserted low when an open circuit is detected in current mode or
an overtemperature is detected. Open drain output must be connected to a pull-up resistor.
4, 12 3, 15 GND These pins must be connected to 0 V.
18 1, 10, 11, 19, 20,
21, 22, 25, 30,
31, 35, 38, 40
NC No Connection. Do not connect to these pins.
5 4 CLEAR
SELECT
Selects the voltage output clear value, either zero-scale or midscale code (see Table 22).
6 5 CLEAR
Active High Input. Asserting this pin sets the current output to the bottom of the selected
range or sets the voltage output to the user selected value (zero-scale or midscale).
7 6 LATCH
Positive Edge Sensitive Latch. A rising LATCH edge parallel loads the input shift register
data into the DAC register, also updating the output.
8 7 SCLK
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This
operates at clock speeds of up to 30 MHz.
9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK.
10 9 SDO
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback
mode. Data is valid on the rising edge of SCLK (see Figure 3 and Figure 4).
11 12, 13 GND Ground Reference Pin.
13 16 RSET An external, precision, low drift 15 kΩ current setting resistor can be connected to this
pin to improve the IOUT temperature drift performance. See the AD5412/AD5422 Features
section.
14 17 REFOUT Internal Reference Voltage Output. REFOUT = 5 V ± 5 mV.
15 18 REFIN
External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for a
specified performance.
Data Sheet AD5412/AD5422
Rev. O | Page 15 of 44
Pin No.
Mnemonic Description
TSSOP LFCSP
16 23 DVCC
SELECT
When connected to GND, this pin disables the internal supply, and an external supply
must be connected to the DVCC pin. Leave this pin unconnected to enable the internal
supply. In this case, it is recommended to connect a 0.1 μF capacitor between DVCC and
GND. See the AD5412/AD5422 Features section.
17 24 CCOMP Optional compensation capacitor connection for the voltage output buffer. Connecting
a 4 nF capacitor between this pin and the VOUT pin allows the voltage output to drive up
to 1 µF. It should be noted that the addition of this capacitor reduces the bandwidth of
the output amplifier, increasing the settling time.
19 26 IOUT Current Output Pin.
20 27 BOOST Optional External Transistor Connection. Connecting an external transistor reduces the
power dissipated in the AD5412/AD5422. See the AD5412/AD5422 Features section.
N/A 28, 29 CAP1, CAP2 Connection for Optional Output Filtering Capacitor. See the AD5412/AD5422 Features
section.
21 32 VOUT Buffered Analog Output Voltage. The output amplifier is capable of directly driving a
1 kΩ, 2000 pF load.
22 33 +VSENSE Sense connection for the positive voltage output load connection.
23 34 −VSENSE Sense connection for the negative voltage output load connection.
24 36 AVDD Positive Analog Supply Pin. Voltage ranges from 10.8 V to 60 V.
25 (EPAD) 41 (EPAD) Exposed
paddle
Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This paddle can be connected
to 0 V if the output voltage range is unipolar. The paddle can be left electrically unconnected
provided that a supply connection is made at the AVSS pin. It is recommended that the
paddle be thermally connected to a copper plane for enhanced thermal performance.
AD5412/AD5422 Data Sheet
Rev. O | Page 16 of 44
TYPICAL PERFORMANCE CHARACTERISTICS
GENERAL
0
100
200
300
400
500
600
700
800
900
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DI
CC
(µA)
LOGIC VOLTAGE (V)
DV
CC
= 5V
T
A
= 25°C
DV
CC
= 3V
06996-022
Figure 7. DICC vs. Logic Input Voltage
–2
–1
0
1
2
3
4
5
10 12 14 16 18 20 22 24 26 28
AIDD/AISS (mA)
AVDD/|AVSS| (V)
AIDD
AISS
TA = 25°C
VOUT = 0V
OUTPUT UNLOADED
06996-108
Figure 8. AIDD/AISS vs. AVDD/|AVSS|
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10 15 20 25 30 35 40
AIDD (mA)
AVDD (V)
TA = 25°C
IOUT = 0mA
06996-023
Figure 9. AIDD vs. AVDD
0
1
2
3
4
5
6
7
8
9
–21 –19 –17 –15 –13 –11 –9 –7 –5 –3 –1 1
DV
CC
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
T
A
= 25°C
06996-024
Figure 10. DVCC Output Voltage vs. Load Current
CH1 2.00V
CH3 5.00V
M200µs CH3 2.1V
1
3
AV
DD
REFERENCE OUTPUT
06996-025
Figure 11. REFOUT Turn-on Transient
CH1 2µV M2.00s LINE 1.8V
1
06996-026
Figure 12. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)
Data Sheet AD5412/AD5422
Rev. O | Page 17 of 44
CH1 20µV M2.00s LINE 0V
1
0
6996-027
Figure 13. REFOUT Output Noise (100 kHz Bandwidth)
4.997
–40 –20 0 20
TEMPERATURE (°C)
40 60 80
4.998
4.999
5.000
5.001
5.002
5.003
REFERENCE OUTPUT VOLTAGE (V)
50 DEVICES SHOWN
AV
DD
= 24V
06996-029
Figure 14. Reference Voltage vs. Temperature
0
5
10
15
20
25
30
35
40
45
10 2345678910
POPULATION (%)
TEMPERATURE COEFFICIENT (ppm/°C)
AV
DD
= 24V
0
6996-030
Figure 15. Reference Temperature Coefficient Histogram
4.9955
4.9960
4.9965
4.9970
4.9975
4.9980
4.9985
4.9990
4.9995
5.0000
5.0005
0123456789
REFERENCE OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
T
A
= 25°C
AV
DD
= 24V
0
6996-031
Figure 16. Reference Voltage vs. Load Current
AD5412/AD5422 Data Sheet
Rev. O | Page 18 of 44
VOLTAGE OUTPUT
–0.0025
–0.0020
–0.0015
–0.0010
–0.0005
0.0005
0
0.0010
0.0015
0.0020
0.0025
0 10,000 20,000 30,000 40,000 50,000 60,000
INL ERROR (% FSR)
CODE
06996-117
±10V RANGE
±5V RANGE
+5V RANGE
+10V RANGE
AV
DD
= +24V
AV
SS
= –24V
T
A
= 25°C
Figure 17. Integral Nonlinearity Error vs. DAC Code, Dual Supply
–0.0025
–0.0020
–0.0015
–0.0010
–0.0005
0
0.0005
0.0010
0.0015
0.0020
0.0025
0 10,000 20,000 30,000 40,000 50,000 60,000
INL ERROR (% FSR)
CODE
+5V RANGE
+10V RANGE
AV
DD
= 24V
AV
SS
= 0V
T
A
= 25°C
06996-118
Figure 18. Integral Nonlinearity Error vs. DAC Code, Single Supply
–1.0
–0.8
–0.6
–0.4
–0.2
0.2
0
0.4
0.6
0.8
1.0
0 10,000 20,000 30,000 40,000 50,000 60,000
DNL ERROR (LSB)
CODE
06996-119
±10V RANGE
±5V RANGE
+10V RANGE
+5V RANGE
AV
DD
= +24V
AV
SS
= –24V
T
A
= 25°C
Figure 19. Differential Nonlinearity Error vs. DAC Code, Dual Supply
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 10,000 20,000 30,000 40,000 50,000 60,000
DNL ERROR (LSB)
CODE
AV
DD
= 24V
AV
SS
= 0V
T
A
= 25°C
06996-120
+5V RANGE
+10V RANGE
Figure 20. Differential Nonlinearity Error vs. DAC Code, Single Supply
–0.009
–0.007
–0.003
–0.005
–0.001
0.001
0.003
0.005
0 10,000 20,000 30,000 40,000 50,000 60,000
TOTAL UNADJSUTED ERROR (% FSR)
CODE
06996-221
±10V RANGE
±5V RANGE
+5V RANGE
+10V RANGE
AV
DD
= +24V
AV
SS
= –24V
T
A
= 25°C
Figure 21. Total Unadjusted Error vs. DAC Code, Dual Supply
–0.010
–0.005
0
0.005
0.010
0.015
0.020
0.025
0.030
0 10,000 20,000 30,000 40,000 50,000 60,000
TOTAL UNADJUSTED ERROR (% FSR)
CODE
AV
DD
= 24V
AV
SS
= 0V
T
A
= 25°C
06996-122
+5V RANGE
+10V RANGE
Figure 22. Total Unadjusted Error vs. DAC Code, Single Supply
Data Sheet AD5412/AD5422
Rev. O | Page 19 of 44
–0.0015
–0.0010
–0.0005
0.0005
0
0.0010
0.0015
–40 –20 020 40 60 80
INL ERROR (% FSR)
TEMPERATURE (°C)
+5V RANGE MAX INL +10V RANGE MAX INL
±5V RANGE MAX INL ±10V RANGE MAX INL
+5V RANGE MIN INL +10V RANGE MIN INL
±5V RANGE MIN INL ±10V RANGE MIN INL
06996-121
AV
DD
= +24V
AV
SS
= –24V
Figure 23. Integral Nonlinearity Error vs. Temperature
–1.0
–0.8
–0.6
–0.4
–0.2
0.2
0
0.4
0.6
0.8
1.0
–40 –20 020 40 60 80
DNL ERROR (LSB)
TEMPERATURE (°C)
AVDD = +24V
AVSS = –24V
ALL RANGES
06996-124
Figure 24. Differential Nonlinearity Error vs. Temperature
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
–40 –20 020 40 60 80
TOTAL UNADJSUTED ERROR (% FSR)
TEMPERATURE (°C)
AV
DD
=+24V
AV
SS
= –24V
OUTPUT UNLOADED
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
06996-101
Figure 25. Total Unadjusted Error vs. Temperature
–0.008
–0.006
–0.004
–0.002
0.002
0
0.004
0.006
0.008
0.010
0.012
–40 –20 020 40 60 80
FULL-SCALE ERROR (% FSR)
TEMPERATURE (°C)
AV
DD
= +24V
AV
SS
= –24V
OUTPUT UNLOADED
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
06996-100
Figure 26. Full-Scale Error vs. Temperature
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–40–20 0 20 40 60 80
OFFSET ERROR (mV)
TEMPERATURE (°C)
+5V RANGE
+10V RANGE
AVDD =+24V
AVSS = –24V
OUTPUT UNLOADED
06996-129
Figure 27. Offset Error vs. Temperature
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–40–20 0 20 40 60 80
BIPOLAR ZERO ERROR (mV)
TEMPERATURE (°C)
+5V RANGE
+10V RANGE
AV
DD
=+24V
AV
SS
= –24V
OUTPUT UNLOADED
06996-130
Figure 28. Bipolar Zero Error vs. Temperature
AD5412/AD5422 Data Sheet
Rev. O | Page 20 of 44
–0.008
–0.006
–0.004
–0.002
0.002
0
0.004
0.006
0.008
0.010
0.012
0.014
–40 –20 0 20 40 60 80
GAIN ERROR (% FSR)
TEMPERATURE (°C)
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
AVDD = +24V
AVSS = –24V
OUTPUT UNLOADED
0
6996-131
Figure 29. Gain Error vs. Temperature
–1.2
–0.7
–0.2
0.3
0.8
1.3
–40 –20 0 20 40 60 80
ZERO-SCALE ERROR (mV)
TEMPERATURE (°C)
AV
DD
= +24V
AV
SS
= –24V
OUTPUT UNLOADED
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
06996-102
Figure 30. Zero-Scale Error vs. Temperature
–0.0015
–0.0010
–0.0005
0
0.0005
0.0010
0.0015
10 12 14 16 18 20 22 24 26 28
INL ERROR (% FSR)
AV
DD
/|AV
SS
| (V)
T
A
=25°C
±10V RANGE
06996-231
Figure 31. Integral Nonlinearity Error vs. AVDD/|AVSS|
–1.0
–0.8
–0.6
–0.4
–0.2
0.2
0
0.4
0.6
0.8
1.0
10 12 14 16 18 20 22 24 26 28
DNL ERROR (LSB)
AV
DD
/|AV
SS
| (V)
T
A
= 25°C
±10V RANGE
06996-232
Figure 32. Differential Nonlinearity Error vs. AVDD/|AVSS|
0
0.0005
0.0010
0.0015
0.0020
0.0025
0.0030
0.0035
0.0040
0.0045
0.0050
10 12 14 16 18 20 22 24 26 28
TOTAL UNADJUSTED ERRO
R
(% FSR)
AV
DD
/|AV
SS
|(V)
T
A
= 25°C
±10V RANGE
06996-033
Figure 33. Total Unadjusted Error vs. AVDD/|AVSS|
2.5
0
0.5
1.0
1.5
2.0
0 5 10 15 20 25 30 35
06996-301
HEADROOM VOLTAGE (V)
R
LOAD
(kΩ)
T
A
= 25°C
0V TO 10V RANGE
Figure 34.VOUT Headroom
Data Sheet AD5412/AD5422
Rev. O | Page 21 of 44
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
0510 15 20 25 30 35
06996-302
FOOTROOM VOLTAGE (V)
R
LOAD
(kΩ)
T
A
= 25°C
0V TO 10V RANGE
Figure 35.VOUT Footroom
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
0.04
0.05
–20–15–10–5 0 5 10 15 20
CHANGE IN OUTPUT VOLTAGE (V)
SOURCE/SINK CURRENT (mA)
AV
DD
=+15V
T
A
=25°C
±10V RANGE
AV
SS
= –15V
06996-132
Figure 36. Source and Sink Capability of Output Amplifier,
Full-Scale Code Loaded
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
0.04
0.05
–20 –15 –10 –5 0 5 10 15 20
CHANGE IN OUTPUT VOLTAGE (V)
SOURCE/SINK CURRENT (mA)
AV
DD
= +15V
AV
SS
= –15V
T
A
= 25°C
±10V RANGE
06996-035
Figure 37. Source and Sink Capability of Output Amplifier,
Zero-Scale Loaded
–12
–8
–4
0
4
8
12
–10 –5 0 5 10 15 20 25 30
OUTPUT VOLTAGE (V)
TIME (µs)
±10V RANGE
TA = 25°C
OUTPUT UNLOADED
06996-136
AVSS = –24V
AVDD = +24V
Figure 38. Full-Scale Positive Step
–12
–8
–4
0
4
8
12
–10 –5 0510 15 20 25 30
OUTPUT VOLTAGE (V)
TIME (µs)
AV
SS
= –24V
±10V RANGE
T
A
= 25°C
OUTPUT UNLOADED
AV
DD
= +24V
06996-137
Figure 39. Full-Scale Negative Step
–16
–14
–12
–10
–8
–6
–4
–2
0
2
4
–1 1357 9 11 13 15
OUTPUT VOLTAGE (mV)
TIME (µs)
0x8000 TO 0x7FFF
0x7FFF TO 0x8000
AV
DD
= +24V
T
A
= 25°C
±10V RANGE
AV
SS
= –24V
06996-036
Figure 40. Digital-to-Analog Glitch
AD5412/AD5422 Data Sheet
Rev. O | Page 22 of 44
06996-037
CH1 5.0µV M 5.00ms LINE 1.8V
1
AV
DD
= +24V
AV
SS
= –24V
T
A
= 25°C
Figure 41. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
06996-038
CH1 50.0µV M 5.00ms LINE 0V
1
AV
DD
= +24V
AV
SS
= –24V
T
A
= 25°C
Figure 42. Peak-to-Peak Noise (100 kHz Bandwidth)
0
5
10
15
20
25
30
35
0 2 4 6 8 10 12 14 16 18 20
V
OUT
(mV)
TIME (µs)
AV
DD
=+15V
T
A
=25°C
AV
SS
= –15V
06996-039
Figure 43. VOUT vs. Time on Power-Up
Data Sheet AD5412/AD5422
Rev. O | Page 23 of 44
CURRENT OUTPUT
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0 10,000 20,000 30,000 40,000 50,000 60,000
INL ERROR (% FSR)
CODE
AV
DD
= 24V
AV
SS
= –24V/0V
T
A
= 25°C
R
LOAD
= 250Ω
06996-106
EXTERNAL R
SET
INTERNAL R
SET
EXTERNAL R
SET
, BOOST TRANSISTOR
INTERNAL R
SET
, BOOST TRANSISTOR
Figure 44. Integral Nonlinearity vs. Code
–1.0
–0.8
–0.6
–0.2
–0.4
0
0.2
0.4
0.6
0.8
1.0
0 10,000 20,000 30,000 40,000 50,000 60,000
DNL ERROR (LSB)
CODE
06996-007
AVDD = 24V
AVSS = –24V/0V
TA= 25°C
RLOAD = 250Ω
EXTERNAL RSET
INTERNAL RSET
EXTERNAL RSET, BOOST TRANSISTOR
INTERNAL RSET, BOOST TRANSISTOR
Figure 45. Differential Nonlinearity vs. Code
–0.15
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
0.01
0.05
–0.01
0.03
0 10,000 20,000 30,000 40,000 50,000 60,000
TOTAL UNADJUSTED ERROR (% FSR)
CODE
EXTERNAL R
SET
INTERNAL R
SET
EXTERNAL R
SET
, BOOST TRANSISTOR
INTERNAL R
SET
, BOOST TRANSISTOR
06996-008
AV
DD
= 24V
AV
SS
= –24V/0V
T
A
= 25°C
R
LOAD
= 250Ω
Figure 46. Total Unadjusted Error vs. Code
–0.010
–0.008
–0.006
–0.004
0
–0.002
0.002
0.004
–40 –20 0 20 40 60 80
INL ERROR (% FSR)
TEMPERATURE (°C)
0mA TO 24mA RANGE
AV
DD
= 24V
AV
SS
= –24V/0V
0
6996-009
Figure 47. Integral Nonlinearity vs. Temperature, Internal RSET
–0.003
–0.002
–0.001
0
0.002
0.001
0.003
–40–20020406080
INL ERROR (% FSR)
TEMPERATURE (°C)
0mA TO 24mA RANGE
AV
DD
= 24V
AV
SS
= –24V/0V
0
6996-109
Figure 48. Integral Nonlinearity vs. Temperature, External RSET
–1.0
–0.8
–0.6
–0.4
0
–0.2
0.4
0.8
0.2
0.6
1.0
–40 –20 0 20 40 60 80
DNL ERROR (LSB)
TEMPERATURE (°C)
AV
DD
= 24V
AV
SS
= –24V/0V
ALL RANGES
INTERNAL AND EXTERNAL R
SET
0
6996-010
Figure 49. Differential Nonlinearity vs. Temperature
AD5412/AD5422 Data Sheet
Rev. O | Page 24 of 44
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
–40 –20 0 20 40 60 80
TOTAL UNADJUSTED ERROR (% FSR)
TEMPERATURE (°C)
AV
DD
= 24V
AV
SS
= –24V/0V
4mA TO 20mA INTERNAL R
SET
0mA TO 20mA INTERNAL R
SET
0mA TO 24mA INTERNAL R
SET
4mA TO 20mA EXTERNAL R
SET
0mA TO 20mA EXTERNAL R
SET
0mA TO 24mA EXTERNAL R
SET
06996-013
Figure 50. Total Unadjusted Error vs. Temperature
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
–40–20 0 20406080
OFFSET ERROR (% FSR)
TEMPERATURE (°C)
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
AVDD = 24V
AVSS = –24V/0V
06996-017
Figure 51. Offset Error vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
–40–20 0 20406080
GAIN ERROR (% FSR)
TEMPERATURE (°C)
AV
DD
= 24V
AV
SS
= –24V/0V
4mA TO 20mA INTERNAL R
SET
0mA TO 20mA INTERNAL R
SET
0mA TO 24mA INTERNAL R
SET
4mA TO 20mA EXTERNAL R
SET
0mA TO 20mA EXTERNAL R
SET
0mA TO 24mA EXTERNAL R
SET
06996-018
Figure 52. Gain Error vs. Temperature
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
10 15 20 25 30 35 40
INL ERROR (% FSR)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
0
6996-011
Figure 53. Integral Nonlinearity Error vs. AVDD, External RSET
–0.015
–0.020
–0.010
–0.005
0.005
0.015
0
0.010
0.020
10 15 20 25 30 35 40
INL ERROR (% FSR)
AV
DD
(V)
T
A
= 25°C
0mA TO 24mA RANGE
AV
SS
= 0V
06996-014
Figure 54. Integral Nonlinearity Error vs. AVDD, Internal RSET
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
10 15 20 25 30 35 40
DNL ERRO
R
(LSB)
AV
DD
(V)
T
A
= 25°C
0mA TO 24mA RANGE
AV
SS
= 0V
0
6996-012
Figure 55. Differential Nonlinearity Error vs. AVDD, External RSET
Data Sheet AD5412/AD5422
Rev. O | Page 25 of 44
–0.8
–1.0
–0.6
–0.4
0
0.8
–0.2
0.4
0.6
0.2
1.0
10 15 20 25 30 35 40
DNL ERROR (LSB)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
06996-015
Figure 56. Differential Nonlinearity Error vs. AVDD, Internal RSET
–0.010
–0.015
–0.005
0
0.010
0.005
0.020
0.015
0.025
10 15 20 25 30 35 40
TOTAL UNADJUSTED ERROR (% FSR)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
06996-016
Figure 57. Total Unadjusted Error vs. AVDD, External RSET
–0.15
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
–0.01
0.01
0.03
0.05
10 15 20 25 30 35 40
TOTAL UNADJUSTED ERROR (% FSR)
AVDD (V)
06996-032
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
Figure 58. Total Unadjusted Error vs. AVDD, Internal RSET
0
0.5
1.0
1.5
2.0
2.5
–40 –20 020 40 60 80
HEADROOM VOLTAGE (V)
TEMPERATURE (°C)
AVDD = 15V
AVSS = 0V
IOUT = 24mA
RLOAD = 500Ω
06996-019
Figure 59. Compliance Voltage Headroom vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0100 200 300 400 500 600
OUTPUT CURRENT (µA)
TIME (µs)
AVDD = 24V
AVSS = 0V
TA = 25°C
RLOAD = 250Ω
06996-020
Figure 60. Output Current vs. Time on Power-Up
–50
–40
–30
–20
–10
0
10
20
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT CURRENT (µA)
TIME (µs)
AVDD = 24V
AVSS = 0V
TA = 25°C
RLOAD = 250Ω
06996-021
Figure 61. Output Current vs. Time on Output Enable
AD5412/AD5422 Data Sheet
Rev. O | Page 26 of 44
–10
0
10
20
30
40
50
60
70
0 5 10 15 20 25 30 35 40 45
LEAKAGE CURRENT (pA)
COMPLIANCE VOLTAGE (V)
TA = 25°C
AVDD = 40V
AVSS = 0V
OUTPUT DISABLED
06996-028
Figure 62. Output Leakage Current vs. Compliance Voltage
–30
–20
–10
0
10
20
30
02468101214161820
OUTPUT CURRENT (µA)
TIME (µs)
AV
DD
= 24V
AV
SS
= 0V
T
A
= 25°C
R
LOAD
= 250Ω
0x8000 TO 0x7FFF
0x7FFF TO 0x8000
06996-049
Figure 63. Digital to Analog Glitch
0
5
10
15
20
25
–1012345678
OUTPUT CURRENT (mA)
TIME (µs)
T
A
= 25°C
AV
DD
= 24V
AV
SS
= 0V
R
LOAD
= 300Ω
06996-134
Figure 64. 4 mA to 20 mA Output Current Step
Data Sheet AD5412/AD5422
Rev. O | Page 27 of 44
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy, or INL, is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL vs. code plot can be seen in Figure 17.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures monoton-
icity. This DAC is guaranteed monotonic by design. A typical
DNL vs. code plot can be seen in Figure 19.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5412/AD5422
are monotonic over their full operating temperature range.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding) or 0x0000 (twos complement
coding). A plot of bipolar zero error vs. temperature can be seen
in Figure 28.
Bipolar Zero Temperature Coefficient (TC)
Bipolar zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in ppm FSR/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output should be
full-scale − 1 LSB. Full-scale error is expressed in percent of
full-scale range (% FSR).
Negative Full-Scale Error/Zero-Scale Error
Negative full-scale error is the error in the DAC output voltage
when 0x0000 (straight binary coding) or 0x8000 (twos complement
coding) is loaded to the DAC register. Ideally, the output voltage
should be negative full-scale − 1 LSB. A plot of zero-scale error
vs. temperature can be seen in Figure 30.
Zero-Scale Temperature Coefficient (TC)
Zero-scale TC is a measure of the change in zero-scale error
with a change in temperature. Zero-scale error TC is expressed
in ppm FSR/°C.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for the
output to settle to a specified level for a full-scale input change.
Slew Rate
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage-output
DAC is usually limited by the slew rate of the amplifier used at
its output. Slew rate is measured from 10% to 90% of the output
signal and is expressed in V/µs.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed in % FSR. A plot of gain error vs. temperature
can be seen in Figure 29.
Gain Error Temperature Coefficient (TC)
Gain error TC is a measure of the change in gain error with
changes in temperature. Gain error TC is expressed in ppm
FSR/°C.
Total Unadjusted Error (TUE)
TUE is a measure of the output error taking all the various
errors into account, namely INL error, offset error, gain error,
and output drift over supplies, temperature, and time. TUE is
expressed in % FSR.
Current Loop Voltage Compliance
The maximum voltage at the IOUT pin for which the output
current is equal to the programmed value.
Power-On Glitch Energy
Power-on glitch energy is the impulse injected into the analog
output when the AD5412/AD5422 is powered on. It is specified
as the area of the glitch in nV-sec. See Figure 43 and Figure 60.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state, but the output voltage remains constant. It is normally
specified as the area of the glitch in nV-sec and is measured
when the digital input code is changed by 1 LSB at the major
carry transition (0x7FFF to 0x8000). See Figure 40 and
Figure 63.
Glitch Impulse Peak Amplitude
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in millivolt and is measured when the digital input
code is changed by 1 LSB at the major carry transition (0x7FFF
to 0x8000). See Figure 40 and Figure 63.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus.
AD5412/AD5422 Data Sheet
Rev. O | Page 28 of 44
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the power supply voltage.
Voltage Reference TC
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given temperature
range expressed in ppm/°C, as follows:
6
10×
×
−
=TempRangeV
VV
TC
REFnom
REFminREFmax
where:
VREFmax is the maximum reference output measured over the
total temperature range.
VREFmin is the minimum reference output measured over the total
temperature range.
VREFnom is the nominal reference output voltage, 5 V.
TempRange is the specified temperature range, −40°C to
+105°C.
Load Regulation
Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/mA.
Data Sheet AD5412/AD5422
Rev. O | Page 29 of 44
THEORY OF OPERATION
The AD5412/AD5422 are precision digital-to-current loop and
voltage output converters designed to meet the requirements of
industrial process control applications. They provide a high
precision, fully integrated, low cost single-chip solution for
generating current loop and unipolar/bipolar voltage outputs.
Current ranges are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA
to 20 mA; the voltage ranges available are 0 V to 5 V, ± 5 V, 0 V
to 10 V, and ±10 V; a 10% overrange is available on all voltage
output ranges. The current and voltage outputs are available on
separate pins, and only one is active at any time. The desired
output configuration is user selectable via the control register.
ARCHITECTURE
The DAC core architecture of the AD5412/AD5422 consists
of two matched DAC sections. A simplified circuit diagram is
shown in Figure 65. The four MSBs of the 12-/16-bit data-word
are decoded to drive 15 switches, E1 to E15. Each of these switches
connects one of 15 matched resistors to either ground or the
reference buffer output. The remaining 8/12 bits of the data-
word drive the S0 to S7/S11 switches of an 8-/12-bit voltage
mode R-2R ladder network.
8-12 BIT R-2R LADDER FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
2R 2R
S0 S1 S7/S11 E1 E2 E15
V
OUT
2R 2R 2R 2R 2R
06996-057
Figure 65. DAC Ladder Structure
The voltage output from the DAC core is either converted to
a current (see Figure 66) which is then mirrored to the supply
rail so that the application simply sees a current source output
with respect to ground or it is buffered and scaled to output a
software selectable unipolar or bipolar voltage range (see
Figure 67). The current and voltage are output on separate
pins and cannot be output simultaneously.
12-/16-BIT
DAC A1
AV
DD
I
OUT
A2
T1
T2
R
SET
R2 R3
06996-058
Figure 66. Voltage-to-Current Conversion Circuitry
06996-059
12-/16-BIT
DAC
RANGE
SCALING
VCM
REFIN
+VSENSE
VOUT
–VSENSE
R1
RLOAD
–1V TO +3V
AD5412/AD5422
Figure 67. Voltage Output
Voltage Output Amplifier
The voltage output amplifier is capable of generating both unipolar
and bipolar output voltages. It is capable of driving a load of
1 kΩ in parallel with 1 µF (with an external compensation
capacitor) to GND. The source and sink capabilities of the
output amplifier can be seen in Figure 37. The slew rate is
1 V/µs with a full-scale settling time of 25 µs maximum (10 V
step). Figure 67 shows the voltage output driving a load, RLOAD,
on top of a common-mode voltage (VCM) of −1 V to +3 V. In
output module applications where a cable could possibly
become disconnected from +VSENSE, resulting in the amplifier
loop being broken and possibly resulting in large destructive
voltages on VOUT, include an optional resistor (R1) between
+VSENSE and VOUT, as shown in Figure 67, of a value between
2 kΩ and 5 kΩ to ensure the amplifier loop is kept closed. If
remote sensing of the load is not required, connect +VSENSE
directly to VOUT and connect −VSENSE directly to GND. When
changing ranges on the voltage output, a glitch may occur. For
this reason, it is recommended that the output be disabled by
setting the OUTEN bit of the control register to logic low before
changing the output voltage range; this prevents a glitch from
occurring.
Driving Large Capacitive Loads
The voltage output amplifier is capable of driving capacitive
loads of up to 1 µF with the addition of a nonpolarized 4 nF
compensation capacitor between the CCOMP and VOUT pins.
Without the compensation capacitor, up to 20 nF capacitive
loads can be driven.
AD5412/AD5422 Data Sheet
Rev. O | Page 30 of 44
SERIAL INTERFACE
The AD5412/AD5422 are controlled over a versatile 3-wire
serial interface that operates at clock rates of up to 30 MHz. It is
compatible with SPI, QSPI™, MICROWIRE, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the rising edge of SCLK.
The input register consists of eight address bits and 16 data bits,
as shown in Table 8. The 24-bit word is unconditionally latched
on the rising edge of the LATCH pin. Data continues to be clocked
in irrespective of the state of LATCH. On the rising edge of
LATCH, the data that is present in the input register is latched;
in other words, the last 24 bits to be clocked in before the rising
edge of LATCH is the data that is latched. The timing diagram
for this operation is shown in Figure 2.
Table 8. Input Shift Register Format
MSB LSB
D23 to D16 D15 to D0
Address byte Data-word
Table 9. Address Byte Functions
Address Word Function
00000000 No operation (NOP)
00000001 Data register
00000010 Readback register value as per read address
(see Table 10)
01010101 Control register
01010110 Reset register
Standalone Operation
The serial interface works with both a continuous and non-
continuous serial clock. A continuous SCLK source can be used
only if LATCH is taken high after the correct number of data
bits have been clocked in. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used, and
LATCH must be taken high after the final clock to latch the
data. The rising edge of SCLK that clocks in the MSB of the
data-word marks the beginning of the write cycle. Exactly 24
rising clock edges must be applied to SCLK before LATCH is
brought high. If LATCH is brought high before the 24th rising
SCLK edge, the data written is invalid. If more than 24 rising
SCLK edges are applied before LATCH is brought high, the
input data is also invalid.
CONTROLLER
DATA IN
DATA OUT
SERIAL CLOCK
CONTROL OUT
AD5412/
AD5422
1
SDO
SDIN
SCLK
LATCH
AD5412/
AD5422
1
SDO
SDIN
SCLK
LATCH
AD5412/
AD5422
1
SDO
SDIN
SCLK
LATCH
1
ADDITIONAL PINS OMITTED FOR CLARITY.
06996-060
Figure 68. Daisy Chaining the AD5412/AD5422
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain the devices together as shown in Figure 68.
This daisy-chain mode can be useful in system diagnostics and
in reducing the number of serial interface lines. Daisy-chain
mode is enabled by setting the DCEN bit of the control register
to 1. The first rising edge of SCLK that clocks in the MSB of the
data-word marks the beginning of the write cycle. SCLK is
continuously applied to the input shift register. If more than
24 clock pulses are applied, the data ripples out of the shift
register and appears on the SDO line. This data is valid on the
rising edge of SCLK, having been clocked out on the previous
falling SCLK edge. By connecting the SDO of the first device to
the SDIN input of the next device in the chain, a multidevice
interface is constructed. Each device in the system requires
24 clock pulses. Therefore, the total number of clock cycles
must equal 24 × n, where n is the total number of AD5412/
AD5422 devices in the chain. When the serial transfer to all
devices is complete, LATCH is taken high. This latches the
input data in each device in the daisy chain. The serial clock
can be a continuous or a gated clock.
A continuous SCLK source can be used only if LATCH is taken
high after the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used, and LATCH must be taken high after the final
clock to latch the data (see Figure 4 for a timing diagram).
Data Sheet AD5412/AD5422
Rev. O | Page 31 of 44
Readback Operation
Readback mode is invoked by setting the address byte and read
address when writing to the input register (see Table 10 and
Table 12). The next write to the AD5412/AD5422 should be a
NOP command, which clocks out the data from the previously
addressed register as shown in Figure 3.
By default the SDO pin is disabled after having addressed the
AD5412/AD5422 for a read operation; a rising edge on LATCH
enables the SDO pin in anticipation of data being clocked out.
After the data has been clocked out on SDO, a rising edge on
LATCH disables (tristate) the SDO pin. To read back the data
register, for example, implement the following sequence:
1. Write 0x020001 to the input register. This configures the
part for read mode with the data register selected.
2. Follow this with a second write: a NOP condition, which is
0x000000. During this write, the data from the register is
clocked out on the SDO line.
Table 10. Read Address Decoding
Read Address
Function
00 Read status register
01 Read data register
10 Read control register
POWER-ON STATE
During power-on of the AD5412/AD5422, the power-on-reset
circuit ensures that all registers are loaded with zero-code. As
such, both outputs are disabled; that is, the VOUT and IOUT pins
are in tristate. The +VSENSE pin is internally connected to ground
through a 30 kΩ resistor. Therefore, if the VOUT and +VSENSE pins
are connected together, VOUT is effectively clamped to ground
through a 30 kΩ resistor. Also upon power-on, internal calibration
registers are read, and the data is applied to internal calibration
circuitry. For a reliable read operation, there must be sufficient
voltage on the AVDD supply when the read event is triggered by
the DVCC power supply powering up. Powering up the DVCC
supply after the AVDD supply has reached at least 5 V ensures this. If
DVCC and AVDD are powered up simultaneously, then the
supplies should be powered up at a rate greater than, typically,
5000 V/sec. If the internal DVCC is enabled, the supplies should
be powered up at a rate greater than, typically, 2000 V/sec. If
this cannot be achieved, issue a reset command to the AD5412/
AD5422 after power-on; this performs a power-on-reset event,
reading the calibration registers and ensures specified operation
of the AD5412/AD5422. To ensure correct calibration and to
allow the internal reference to settle to its correct trim value,
40 µs should be allowed after a successful power on reset.
Voltage Output
For a unipolar voltage output range, the output voltage can be
expressed as
×= N
REFIN
OUT
D
GainVV
2
For a bipolar voltage output range, the output voltage can be
expressed as
22
REFIN
N
REFIN
OUT
VGain
D
Gain
VV ×
−
×
=
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
VREFIN is the reference voltage applied at the REFIN pin.
Gain is an internal gain whose value depends on the output
range selected by the user as shown in Table 11.
Table 11. Internal Gain Value
Output Range Gain Value
+5 V 1
+10 V 2
±5 V 2
±10 V 4
Current Output
For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA
current output ranges, the output current is respectively
expressed as
D
IN
OUT ×
=2
mA20
DI N
OUT ×
=2
mA24
mA
4
2
mA
16 +
×
=DI N
OUT
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
Table 12. Input Shift Register Contents for a Read Operation
MSB LSB
D23 D22 D21 D20 D19 D18 D17 D16 D15 to D2 D1 D0
0 0 0 0 0 0 1 0 X1 Read address
1 X = don’t care.
AD5412/AD5422 Data Sheet
Rev. O | Page 32 of 44
06996-300
POWER-ON
SOFTWARE RESET
CONTROL REGISTER WRITE (ONE WRITE COMMAND)
• SELECT R
SET
EXTERNAL/INTERNAL
• SET THE REQUIRED RANGE
• CONFIGURE THE SLEW RATE CONTROL (IF REQUIRED)
• CONFIGURE DAISY CHAIN MODE (IF REQUIRED)
• ENABLE THE OUTPUT
DATA REGISTER WRITE
• WRITE REQUIRED CODE TO DATA REGISTER
CONTROL REGISTER WRITE
• DISABLE OUTPUT
R
SET
CONFIGURATION CHANGE RANGE CHANGE
Figure 69. Programming Sequence to Write/Enable the Output Correctly
Data Sheet AD5412/AD5422
Rev. O | Page 33 of 44
DATA REGISTER
The data register is addressed by setting the address word of the input shift register to 0x01. The data to be written to the data register is
entered in the D15 to D4 positions for the AD5412 and the D15 to D0 positions for the AD5422, as shown in Table 13 and Table 14.
Table 13. Programming the AD5412 Data Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
12-bit data-word X X X X
Table 14. Programming the AD5422 Data Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
16-bit data-word
CONTROL REGISTER
The control register is addressed by setting the address word of the input shift register to 0x55. The data to be written to the control
register is entered in the D15 to D0 positions, as shown in Table 15. The control register functions are shown in Table 16.
Table 15. Programming the Control Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CLRSEL OVRRNG REXT OUTEN SR clock SR step SREN DCEN R2 R1 R0
Table 16. Control Register Functions
Option
Description
CLRSEL See Table 22 for a description of the CLRSEL operation.
OVRRNG Setting this bit increases the voltage output range by 10% (see the AD5412/AD5422 Features section).
REXT Setting this bit selects the external current setting resistor (see the AD5412/AD5422 Features section). When using an
external current setting resistor, it is recommended to only set REXT when also setting the OUTEN bit. Alternately, REXT can
be set before the OUTEN bit is set, but the range (see Table 17) must be changed on the write in which the output is enabled.
See Figure 69 for best practice.
OUTEN Output enable. This bit must be set to enable the outputs. The range bits select which output is functional.
SR clock
Digital slew rate control (see the AD5412/AD5422 Features section).
SR step Digital slew rate control (see the AD5412/AD5422 Features section).
SREN Digital slew rate control enable.
DCEN Daisy chain enable.
R2, R1, R0 Output range select (see Table 17).
Table 17. Output Range Options
R2 R1 R0 Output Range Selected
0
0
0
0 V to 5 V voltage range
0 0 1 0 V to 10 V voltage range
0 1 0 ±5 V voltage range
0 1 1 ±10 V voltage range
1 0 1 4 mA to 20 mA current range
1 1 0 0 mA to 20 mA current range
1 1 1 0 mA to 24 mA current range
AD5412/AD5422 Data Sheet
Rev. O | Page 34 of 44
RESET REGISTER
The reset register is addressed by setting the address word of the input shift register to 0x56. The data to be written to the reset register is
entered in the D0 position as shown in Table 18. The reset register options are shown in Table 18 and Table 19.
Table 18. Programming the Reset Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Reserved Reset
Table 19. Reset Register Functions
Option Description
Reset Setting this bit performs a reset operation, restoring the AD5412/AD5422 to its power-on state.
STATUS REGISTER
The status register is a read-only register. The status register functionality is shown in Table 20 and Table 21.
Table 20. Decoding the Status Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Reserved IOUT fault Slew active Over temp
Table 21. Status Register Functions
Option Description
I
OUT
Fault
This bit is set if a fault is detected on the I
OUT
pin.
Slew Active This bit is set while the output value is slewing (slew rate control enabled).
Over Temp This bit is set if the AD5412/AD5422 core temperature exceeds ~150°C.
Data Sheet AD5412/AD5422
Rev. O | Page 35 of 44
AD5412/AD5422 FEATURES
FAULT ALERT
The AD5412/AD5422 are equipped with a FAULT pin, which
is an open-drain output allowing several AD5412/AD5422
devices to be connected together to one pull-up resistor for
global fault detection. The FAULT pin is forced active by one of
the following fault scenarios:
• The voltage at IOUT attempts to rise above the compliance
range, due to an open-loop circuit or insufficient power
supply voltage. The IOUT current is controlled by a PMOS
transistor and internal amplifier, as shown in Figure 66.
The internal circuitry that develops the fault output avoids
using a comparator with window limits because this would
require an actual output error before the FAULT output
becomes active. Instead, the signal is generated when the
internal amplifier in the output stage has less than ~1 V
of remaining drive capability (when the gate of the output
PMOS transistor nearly reaches ground). Thus, the FAULT
output activates slightly before the compliance limit is
reached. Because the comparison is made within the
feedback loop of the output amplifier, the output accuracy
is maintained by its open-loop gain, and an output error
does not occur before the FAULT output becomes active.
• If the core temperature of the AD5412/AD5422 exceeds
approximately 150°C.
The IOUT fault and over temp bits of the status register are used
in conjunction with the FAULT pin to inform the user which
one of the fault conditions caused the FAULT pin to be asserted
(see Table 20 and Table 21).
VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION
Under normal operation, the voltage output sinks/sources
10 mA. The maximum current that the voltage output delivers
is ~20 mA; this is the short-circuit current.
VOLTAGE OUTPUT OVERRANGE
An overrange facility is provided on the voltage output. When
enabled via the control register, the selected output range is
overranged by, typically, 10%.
VOLTAGE OUTPUT FORCE-SENSE
The +VSENSE and −VSENSE pins are provided to facilitate remote
sensing of the load connected to the voltage output. If the load
is connected at the end of a long or high impedance cable,
sensing the voltage at the load allows the output amplifier to
compensate and ensure that the correct voltage is applied across
the load. This function is limited only by the available power
supply headroom.
ASYNCHRONOUS CLEAR (CLEAR)
The CLEAR pin is an active high clear that allows the voltage
output to be cleared to either zero-scale code or midscale code,
user selectable via the CLEAR SELECT pin, or the CLRSEL bit
of the control register, as described in Table 22. (The clear select
feature is a logical OR function of the CLEAR SELECT pin and
the CLRSEL bit.) The current output clears to the bottom of its
programmed range. It is necessary for CLEAR to be high for a
minimum amount of time to complete the operation (see Figure 2).
When the CLEAR signal is returned low, the output remains at
the cleared value. The preclear value can be restored by pulsing
the LATCH signal low without clocking any data. A new value
cannot be programmed until the CLEAR pin is returned low.
Table 22. CLRSEL Options
CLRSEL
Output Value
Unipolar Output Range Bipolar Output Range
0 0 V 0 V
1
Midscale
Zero scale
In addition to defining the output value for a clear operation,
the CLRSEL bit and CLEAR SELECT pin also define the default
output value. During selection of a new voltage range, the
output value is as defined in Table 22. To avoid glitches on the
output, it is recommended that, before changing voltage ranges,
the user disable the output by setting the OUTEN bit of the
control register to logic low. When OUTEN is set to logic high,
the output goes to the default value as defined by CLRSEL and
CLEAR SELECT.
INTERNAL REFERENCE
The AD5412/AD5422 contain an integrated 5 V voltage
reference with initial accuracy of ±5 mV maximum and a
temperature drift coefficient of ±10 ppm/°C maximum. The
reference voltage is buffered and externally available for use
elsewhere within the system. See Figure 16 for a load regulation
graph of the integrated reference.
EXTERNAL CURRENT SETTING RESISTOR
RSET is an internal sense resistor as part of the voltage-to-current
conversion circuitry (see Figure 66). The stability of the output
current over temperature is dependent on the stability of the
value of RSET. As a method of improving the stability of the
output current over temperature, an external precision 15 kΩ
low drift resistor can be connected to the RSET pin of the
AD5412/AD5422 to be used instead of the internal resistor
(RSET). The external resistor is selected via the control register
(see Table 15).
AD5412/AD5422 Data Sheet
Rev. O | Page 36 of 44
DIGITAL POWER SUPPLY
By default, the DVCC pin accepts a power supply of 2.7 V to
5.5 V. Alternatively, via the DVCC SELECT pin, an internal 4.5 V
power supply can be output on the DVCC pin for use as a digital
power supply for other devices in the system or as a termination
for pull-up resistors. This facility offers the advantage of not
having to bring a digital supply across an isolation barrier. The
internal power supply is enabled by leaving the DVCC SELECT
pin unconnected. To disable the internal supply, tie DVCC
SELECT to 0 V. D V CC is capable of supplying up to 5 mA of
current (for a load regulation graph, see Figure 10).
EXTERNAL BOOST FUNCTION
The addition of an external boost transistor, as shown in
Figure 70, reduces the power dissipated in the AD5412/AD5422
by reducing the current flowing in the on-chip output transistor
(dividing it by the current gain of the external circuit). A discrete
NPN transistor with a breakdown voltage, BVCEO, greater than
40 V can be used. The external boost capability has been developed
for users who may wish to use the AD5412/AD5422 at the
extremes of the supply voltage, load current, and temperature
range. The boost transistor can also be used to reduce the
amount of temperature-induced drift in the part. This minimizes
the temperature-induced drift of the on-chip voltage reference,
which improves on drift and linearity.
BOOST MJD31C
OR
PBSS8110Z
R
LOAD
0.022µF
1kΩ
AD5412/
AD5422
I
OUT
06996-061
Figure 70. External Boost Configuration
EXTERNAL COMPENSATION CAPACITOR
The voltage output can ordinarily drive capacitive loads of up to
20 nF; if there is a requirement to drive greater capacitive loads,
of up to 1 µF, an external compensation capacitor can be con-
nected between the CCOMP and VOUT pins. The addition of the
capacitor keeps the output voltage stable but also reduces the
bandwidth and increases the settling time of the voltage output.
HART COMMUNICATION
The AD5412/AD5422 (LFCSP version only) contain a CAP2
pin, into which a HART signal can be coupled. The HART
signal appears on the current output if the output is enabled. To
achieve a 1 mA peak-to-peak current, the signal amplitude at
the CAP2 pin must be 48 mV peak-to-peak. Assuming that the
modem output amplitude is 500 mV peak-to-peak, its output
must be attenuated by 500/48 = 10.42. If this voltage is used, the
current output should meet the HART amplitude specifications.
Figure 71 shows the recommended circuit for attenuating and
coupling in the HART signal.
HART MODEM
OUTPUT
C1
C2
CAP2
AVDD
06996-051
Figure 71. Coupling HART Signal
In determining the absolute values of the capacitors, ensure that
the FSK output from the modem is passed undistorted. Thus,
the bandwidth presented to the modem output signal must pass
1200 Hz and 2200 Hz frequencies. The recommended values
are C1 = 2.2 nF and C2 = 22 nF. Digitally controlling the slew
rate of the output is necessary to meet the analog rate of change
requirements for HART.
DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5412/AD5422 allows the
user to control the rate at which the output voltage or current
changes. With the slew rate control feature disabled, the output
changes at a rate limited by the output drive circuitry and the
attached load. See Figure 64 for current output step and
Figure 38 for voltage output step. To reduce the slew rate, enable
the slew rate control feature. With the feature enabled via the
SREN bit of the control register (see Table 15), the output, instead
of slewing directly between two values, steps digitally at a rate
defined by two parameters accessible via the control register, as
shown in Table 15. The parameters are set by the SR clock and
SR step bits. SR clock defines the rate at which the digital slew is
updated; SR step defines by how much the output value changes
at each update. Both parameters together define the rate of
change of the output voltage or current. Table 23 and Table 24
outline the range of values for both the SR clock and SR step
parameters. Figure 72 shows the output current changing for
ramp times of 10 ms, 50 ms, and 100 ms.
Table 23. Slew Rate Step Size Options
SR Step
AD5412 Step Size (LSB)
AD5422 Step Size (LSB)
000 1/16 1
001 1/8 2
010 1/4 4
011 1/2 8
100 1 16
101 2 32
110 4 64
111 8 128
Data Sheet AD5412/AD5422
Rev. O | Page 37 of 44
Table 24. Slew Rate Update Clock Options
SR Clock Update Clock Frequency (Hz)
0000 257,730
0001 198,410
0010 152,440
0011 131,580
0100 115,740
0101 69,440
0110 37,590
0111 25,770
1000 20,160
1001 16,030
1010 10,290
1011 8280
1100 6900
1101 5530
1110 4240
1111
3300
The time it takes for the output to slew over a given output
range can be expressed as follows:
Size
LSBFrequencyClockUpdate
Size
Step
ChangeOutput
Time
Slew
××
=
(1)
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps for IOUT or volts for VOUT.
When the slew rate control feature is enabled, all output
changes change at the programmed slew rate; if the CLEAR
pin is asserted, the output slews to the zero-scale value at the
programmed slew rate. The output can be halted at its current
value with a write to the control register. To avoid halting the
output slew, the slew active bit (see Table 20) can be read to
check that the slew has completed before writing to any of the
AD5410/AD5420 registers. The update clock frequency for any
given value is the same for all output ranges. The step size,
however, varies across output ranges for a given value of step
size because the LSB size is different for each output range.
Table 25 shows the range of programmable slew times for a full-
scale change on any of the output ranges. The values in Table 25
were obtained using Equation 1.
The digital slew rate control feature results in a staircase
formation on the current output, as shown in Figure 76. This
figure also shows how the staircase can be removed by
connecting capacitors to the CAP1 and CAP2 pins, as described
in the IOUT Filtering Capacitors (LFCSP Package) section.
0
5
10
15
20
25
–10 010 20 30 40 50 60 70 80 90 100 110
OUTPUT CURRENT (mA)
TIME (ms)
T
A
= 25°C
AV
DD
= 24V
R
LOAD
= 300Ω
06996-139
10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5
50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7
100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5
Figure 72. Output Current Slewing Under Control of the Digital Slew Rate
Control Feature
IOUT FILTERING CAPACITORS (LFCSP PACKAGE)
Capacitors can be placed between CAP1 and AVDD, and CAP2
and AVDD, as shown in Figure 73.
CAP1
AV
DD
C1 C2
AV
DD
AD5412/
AD5422
CAP2
GND
06996-062
I
OUT
Figure 73. IOUT Filtering Capacitors
The CAP1 and CAP2 pins are available only on the LFCSP
package. The capacitors form a filter on the current output
circuitry, as shown in Figure 74, reducing the bandwidth and
the slew rate of the output current. Figure 75 shows the effect
the capacitors have on the slew rate of the output current. To
achieve significant reductions in the rate of change, very large
capacitor values are required, which may not be suitable in
some applications. In this case, the digital slew rate control
feature can be used. The capacitors can be used in conjunction
with the digital slew rate control feature as a means of
smoothing out the steps caused by the digital code increments,
as shown in Figure 76.
AD5412/AD5422 Data Sheet
Rev. O | Page 38 of 44
DAC
I
OUT
BOOST
CAP1CAP2
C1
R1
C2
AV
DD
4kΩ
12.5kΩ
40Ω
06996-063
Figure 74. IOUT Filter Circuitry
0
5
–0.5 00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
10
15
20
25
OUTPUT CURRENT (mA)
TIME (ms)
T
A
=25°C
AV
DD
=24V
R
LOAD
=300Ω
06996-142
NO CAPACITOR
10nF ON CAP1
10nF ON CAP2
47nF ON CAP1
47nF ON CAP2
Figure 75. Slew Controlled 4 mA to 20 mA Output Current Step Using
External Capacitors on the CAP1 and CAP2 Pins
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
–1 0123 4 56 7 8
OUTPUT CURRENT (mA)
TIME (ms)
T
A
= 25°C
AV
DD
= 24V
R
LOAD
= 300Ω
NO EXTERNAL CAPS
10nF ON CAP1
10nF ON CAP2
06996-043
Figure 76. Smoothing Out the Steps Caused by the Digital Slew
Rate Control Feature
Table 25. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range
Update Clock Frequency (Hz)
Step Size (LSB)
1 2 4 8 16 32 64 128
257,730 0.25 0.13 0.06 0.03 0.016 0.008 0.004 0.0020
198,410 0.33 0.17 0.08 0.04 0.021 0.010 0.005 0.0026
152,440 0.43 0.21 0.11 0.05 0.027 0.013 0.007 0.0034
131,580 0.50 0.25 0.12 0.06 0.031 0.016 0.008 0.0039
115,740 0.57 0.28 0.14 0.07 0.035 0.018 0.009 0.0044
69,440 0.9 0.47 0.24 0.12 0.06 0.03 0.015 0.007
37,590 1.7 0.87 0.44 0.22 0.11 0.05 0.03 0.014
25,770
2.5
1.3
0.64
0.32
0.16
0.08
0.04
0.020
20,160 3.3 1.6 0.81 0.41 0.20 0.10 0.05 0.025
16,030 4.1 2.0 1.0 0.51 0.26 0.13 0.06 0.03
10,290 6.4 3.2 1.6 0.80 0.40 0.20 0.10 0.05
8280 7.9 4.0 2.0 1.0 0.49 0.25 0.12 0.06
6900 9.5 4.8 2.4 1.2 0.59 0.30 0.15 0.07
5530 12 5.9 3.0 1.5 0.74 0.37 0.19 0.09
4240 15 7.7 3.9 1.9 0.97 0.48 0.24 0.12
3300 20 9.9 5.0 2.5 1.24 0.62 0.31 0.16
Data Sheet AD5412/AD5422
Rev. O | Page 39 of 44
APPLICATIONS INFORMATION
VOLTAGE AND CURRENT OUTPUT RANGES ON
THE SAME TERMINAL
The current and voltage output pins can be connected together.
A buffer amplifier is required, however, to prevent a current
leakage path through an internal 30 kΩ resistor on the +VSENSE pin
when the device is in current output mode. In current mode,
the VOUT pin is high impedance; whereas in voltage output
mode, the IOUT pin is high impedance and does not affect the
voltage output. It is important that the external RSET be used in
this configuration, as depicted in Figure 77.
IOUT
AD5412/
AD5422
IOUT/VOUT
+VSENSE
–VSENSE
VOUT
RSET
OP07/OP184
06996-071
Figure 77. IOUT and VOUT Connected Together
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, connect a
0.01 µF capacitor between IOUT and GND. This ensures stability
with loads above 50 mH. There is no maximum capacitance
limit. The capacitive component of the load may cause slower
settling. The digital slew rate control feature may also prove
useful in this situation.
TRANSIENT VOLTAGE PROTECTION
The AD5412/AD5422 contain ESD protection diodes that
prevent damage from normal handling. The industrial control
environment can, however, subject I/O circuits to much higher
transients. To protect the AD5412/AD5422 from excessively
high voltage transients, external power diodes and a surge
current limiting resistor are required, as shown in Figure 78.
The constraint on the resistor value is that, during normal
operation, the output level at IOUT must remain within its voltage
compliance limit of AVDD – 2.5 V, and the two protection diodes
and resistor must have appropriate power ratings. Further
protection can be provided with transient voltage suppressors or
transorbs; these are available as both unidirectional suppressors
(protect against positive high voltage transients) and bidirectional
suppressors (protect against both positive and negative high
voltage transients) and are available in a wide range of standoff
and breakdown voltage ratings. It is recommended that all field
connected nodes be protected.
AV
DD
I
OUT
R
LOAD
R
P
AV
DD
AD5412/
AD5422
GND AV
SS
AV
SS
06996-064
Figure 78. Output Transient Voltage Protection
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® products from Analog Devices, Inc., provide voltage
isolation in excess of 2.5 kV. The serial loading structure of the
AD5412/AD5422 makes the parts ideal for isolated interfaces
because the number of interface lines is kept to a minimum.
Figure 79 shows a 4-channel isolated interface to the AD5412/
AD5422 using an ADuM1400. For further information, visit
www.analog.com/isolators.
ENCODE
SERIAL
CLOCK IN
CONTROLLER
ADuM1400
1
SERIAL
DATA OUT
SYNC OUT
CONTROL
OUT
DECODE TO
SCLK
TO
SDIN
TO
LATCH
TO
CLEAR
V
IA
V
OA
ENCODE DECODE
V
IB
V
OB
ENCODE DECODE
V
IC
V
OC
ENCODE DECODE
V
ID
V
OD
06996-065
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 79. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5412/AD5422 is via a serial
bus that uses a protocol compatible with microcontrollers and
DSP processors. The communications channel is a 3-wire
minimum interface consisting of a clock signal, a data signal,
and a latch signal. The AD5412/AD5422 require a 24-bit data-
word with data valid on the rising edge of SCLK.
For all interfaces, the DAC output update is initiated on the rising
edge of LATCH. The contents of the registers can be read using
the readback function.
AD5412/AD5422 Data Sheet
Rev. O | Page 40 of 44
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. Design the printed circuit board (PCB) on
which the AD5412/AD5422 is mounted so that the analog and
digital sections are separated and confined to certain areas of the
board. If the AD5412/AD5422 is in a system where multiple
devices require an analog ground-to-digital ground connection,
make the connection at one point only. Establish the star ground
point as close as possible to the device.
The AD5412/AD5422 should have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types,
which provide a low impedance path to ground at high frequencies
to handle transient currents due to internal logic switching.
The power supply lines of the AD5412/AD5422 should use as
large a trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with a digital ground
to avoid radiating noise to other parts of the board. Never run these
near the reference inputs. A ground line routed between the SDIN
and SCLK lines helps reduce crosstalk between them (this is not
required on a multilayer board that has a separate ground plane,
but separating the lines helps). It is essential to minimize noise
on the REFIN line because it couples through to the DAC output.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the PCB should run at right angles to each
other. This reduces the effects of feed through the board. A
microstrip technique is by far the best but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane, and signal
traces are placed on the solder side.
THERMAL AND SUPPLY CONSIDERATIONS
The AD5412/AD5422 are designed to operate at a maximum
junction temperature of 125°C. It is important that the devices
not be operated under conditions that cause the junction
temperature to exceed this value. Excessive junction tempera-
ture can occur if the AD5412/AD5422 are operated from the
maximum AVDD while driving the maximum current (24 mA)
directly to ground. In this case, control the ambient temperature
or reduce AVDD. The conditions depend on the device package.
At the ambient temperature of 85°C, the 24-lead TSSOP package
can dissipate 1.14 mW, and the 40-lead LFCSP package can
dissipate 1.21 W.
To ensure that the junction temperature does not exceed 125°C
while driving the maximum current of 24 mA directly into ground
(also adding an on-chip current of 3 mA), reduce AVDD from the
maximum rating to ensure that the package is not required to
dissipate more power than previously stated (see Table 26,
Figure 80, and Figure 81).
0
0.5
1.0
1.5
2.0
2.5
40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
LFCSP
TSSOP
06996-066
Figure 80. Maximum Power Dissipation vs. Ambient Temperature
25
27
29
31
33
35
37
39
41
43
45
25 35 45 55 65 75 85
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
06996-067
TSSOP
LFCSP
Figure 81. Maximum Supply Voltage vs. Ambient Temperature
Data Sheet AD5412/AD5422
Rev. O | Page 41 of 44
Table 26. Thermal and Supply Considerations for Each Package
Considerations TSSOP LFCSP
Maximum Allowed Power Dissipation When Operating at an
Ambient Temperature of 85°C
W14.1
35
85
125 =
−
=
θ
−
JA
A
JT
maxT
W21.1
33
85125 =
−
=
θ
−
JA
A
J
TmaxT
Maximum Allowed Ambient Temperature When Operating from
a Supply of 40 V and Driving 24 mA Directly to Ground
C8635)028.040(125 °=××−
=θ×−
JA
DJ
PmaxT
C8833)028.040(125 °=××−
=θ×−
JA
DJ
PmaxT
Maximum Allowed Supply Voltage When Operating at an Ambient
Temperature of 85°C and Driving 24 mA Directly to Ground
V40
35028.0
85125 =
×
−
=
×
−
JA
DD
A
J
AI
TmaxT
θ
V43
33028.0
85125 =
×
−
=
×
−
JA
DD
A
J
AI
TmaxT
θ
INDUSTRIAL ANALOG OUTPUT MODULE
Many industrial control applications have requirements for
accurately controlled current and voltage output signals. The
AD5412/AD5422 are ideal for such applications. Figure 83 shows
the AD5412/AD5422 in a circuit design for an output module,
specifically for use in an industrial control application. The design
provides for a current or voltage output. The module is powered
from a field supply of 24 V. This supplies AVDD directly. An inverting
buck regulator generates the negative supply for AVSS. For transient
overvoltage protection, transient voltage suppressors (TVS) are
placed on all field accessible connections. A 24 V volt TVS is placed
on each IOUT, VOUT, +VSENSE, and −VSENSE connection, and a 36 V TVS
is placed on the field supply input. For added protection, clamping
diodes are connected from the IOUT, VOUT, +VSENSE, and −VSENSE
pins to the AVDD and AVSS power supply pins. If remote voltage load
sensing is not required, the +VSENSE pin can be directly connected to
the VOUT pin and the –VSENSE pin can be connected to GND.
Isolation between the AD5412/AD5422 and the backplane
circuitry is provided with ADuM1400 and ADuM1200 iCoupler
digital isolators; further information on iCoupler products is
available at www.analog.com/isolators. The internally generated
digital power supply of the AD5412/AD5422 powers the field
side of the digital isolaters, removing the need to generate a digital
power supply on the field side of the isolation barrier. The AD5412/
AD5422 digital supply output supplies up to 5 mA, which is more
than enough to supply the 2.8 mA requirements of the ADuM1400
and ADuM1200 operating at a logic signal frequency of up to
1 MHz. To reduce the number of isolators required, nonessential
signals such as CLEAR can be connected to GND. FAULT and
SDO can be left unconnected, reducing the isolation requirements
to just three signals. See Circuit Note CN0321 for an example of
a built and tested circuit of a fully isolated, single channel voltage
and 4 mA to 20 mA output with HART.
INDUSTRIAL HART CAPABLE ANALOG OUTPUT
APPLICATION
Many industrial control applications have requirements for
accurately controlled current output signals, and the AD5412/
AD5422 are ideal for such applications. Figure 82 shows the
AD5412/AD5422 in a circuit design for a HART-enabled output
module, specifically for use in an industrial control application in
which both the voltage output and current output are available—
one at a time—on one pin, thus reducing the number of screw
connections required. There is no conflict with tying the two output
pins together because only the voltage output or the current output
can be enabled at any one time. For further information on this
circuit, see Circuit Note CN0278, Complete 4 mA to 20 mA
HART Solution with Additional Voltage Output Capability.
The design provides for a HART-enabled current output, with
the HART capability provided by the AD5700/AD5700-1 HART
modem, the industry’s lowest power and smallest footprint HART-
compliant IC modem. For additional space-savings, the AD5700-1
offers a 0.5% precision internal oscillator. The HART_OUT signal
from the AD5700 is attenuated and ac-coupled into the RSET pin
of the AD5412/AD5422. Because the RSET pin is used to couple
the HART signal into the AD5412/AD5422, either the TSSOP or
LFCSP package option can be used for this configuration. It should
be noted however, that since the TSSOP package does not have
a CAP1 pin, C1 (see Figure 82) cannot be inserted in this case.
While the TSSOP equivalent circuit (as in Figure 82 but without
C1 in place) still passes the HART Communication Foundation
physical layer specs, the results with C1 in place are superior to
those without C1 in place. Further information on an alternative
configuration, whereby the HART signal is coupled into the CAP2
pin can be found in Application Note AN-1065. This is based
on the AD5410/AD5420 but can also be applied to the AD5412/
AD5422. Use of either configuration results in the AD5700 HART
modem output modulating the 4 mA to 20 mA analog current
without affecting the dc level of the current. This circuit adheres
to the HART physical layer specifications as defined by the
HART Communication Foundation.
The module is powered from a field supply of ±10.8 V to ±26.4 V.
This supplies AVDD/AVSS directly. For transient overvoltage
protection, transient voltage suppressors (TVS) are placed on
both the IOUT and field supply connections. A 24 V TVS is placed
on the IOUT connection, and a 36 V TVS is placed on the field
supply input(s). For added protection, clamping diodes are
connected from the IOUT pin to the AVDD and GND power
supply pins. A 10 kΩ current limiting resistor is also placed in
series with the positive terminal of the +VSENSE buffer input. This is
to limit the current to an acceptable level during a transient event.
AD5412/AD5422 Data Sheet
Rev. O | Page 42 of 44
I
OUT
LATCH
SCLK
SDIN
SDO
GND
CLEAR
FAULT
REFOUT
0.1µF
10µF
2.7V
TO
5.5V
DGND
TXD
RXD
RTS
CD
V
CC
ADC_IP
REF
1µF
10kΩ
1.2MΩ
1.2MΩ
300pF 150kΩ
C3
R
SET
DV
CC
AV
DD
CAP2
CAP1
R
L
500Ω
AGND
0.1µF
10µF
150pF
V
OUT
+V
SENSE
–V
SENSE
OP1177
10µF
0.1µF
0.1µF
0.1µF
AV
SS
10kΩ
R
P
R
P
C2
22nF
C1
2.2nF
D1
D2
D3
D4
AV
SS
DIGITAL
INTERFACE
UART
INTERFACE
AD5412/
AD5422
REFIN
0V
TO
–26.4V
10.8V
TO
26.4V
AV
DD
HART_OUT
AD5700
4mA TO 20mA
CURRENTLOOP
06996-079
Figure 82. AD5412/AD5422 in HART Configuration
LATCH
SCLK
SDIN
SDO
DVCC
AVSS
AVDD
+VSENSE
–VSENSE
IOUT
VOUT
+VSENSE
–VSENSE
IOUT
+VOUT
CCOMP
GND
CLEAR
FAULT
REFOUT REFIN
CLEAR SELECT
DVCC
S ELECT
AD5412/
AD5422
1
24V
SMAJ24CA
4nF
24V FIELD SUPPLY
36V
10µF
0.1µF
0.1µF
10µF
0.1µF
–15V
INVERTING
BUCK
REGULATOR
–15V
VDD2
VDD2
GND
1
GND
1
V
IA
V
IA
NC
GND
1
V
IC
V
ID
V
IB
V
IB
V
OA
V
OA
V
OC
V
OD
V
OB
V
OB
GND
2
V
E2
GND
2
GND
2
ADuM1400
10kΩ
FIELD GROUND
ADuM1200
V
DD1
V
DD1
MICROCONTROLLER
DIGITAL
OUTPUTS
DIGITAL
INPUTS
0.1µF
0.1µF
BACKPLANE INTERFACE
BACKPLANE
SUPPLY
SMAJ36CA
4.7kΩ
18Ω
100Ω
+
+
06996-068
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 83. AD5412/AD5422 in an Industrial Analog Output Module Application
Data Sheet AD5412/AD5422
Rev. O | Page 43 of 44
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-ADT
061708-A
24 13
121
6.40 BSC
0.15
0.05
0.10 COPLANARITY
TOP VIEW
EXPOSED
PAD
(Pins Up)
BOTTOM VIEW
4.50
4.40
4.30
7.90
7.80
7.70
1.20 MAX 1.05
1.00
0.80
0.65
BSC
0.30
0.19
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
5.02
5.00
4.95
3.25
3.20
3.15
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 84. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]
(RE-24)
Dimensions shown in millimeters
1
40
10
11
31
30
21
20
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
06-01-2012-D
0.50
BSC
PIN 1
INDICATOR
4.50 REF
0.20 MIN
0.50
0.40
0.30
TOP VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
4.25
4.10 SQ
3.95
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
5.85
5.75 SQ
5.65
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
(BOTTOM VIEW)
Figure 85. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.85 mm Package Height
(CP-40-1)
Dimensions shown in millimeters
AD5412/AD5422 Data Sheet
Rev. O | Page 44 of 44
ORDERING GUIDE
Model1
Resolution
(Bits)
I
OUT
TUE
(% FSR max)
V
OUT
TUE
(% FSR max) Temperature Range Package Description
Package
Option
AD5412AREZ 12 0.5 0.3 −40°C to +105°C 24-Lead TSSOP_EP RE-24
AD5412AREZ-REEL7 12 0.5 0.3 −40°C to +105°C 24-Lead TSSOP_EP RE-24
AD5412ACPZ-REEL 12 0.5 0.3 −40°C to +105°C 40-Lead LFCSP CP-40-1
AD5412ACPZ-REEL7 12 0.5 0.3 −40°C to +105°C 40-Lead LFCSP CP-40-1
AD5422AREZ 16 0.5 0.3 −40°C to +105°C 24-Lead TSSOP_EP RE-24
AD5422AREZ-REEL 16 0.5 0.3 −40°C to +105°C 24-Lead TSSOP_EP RE-24
AD5422BREZ 16 0.3 0.1 −40°C to +105°C 24-Lead TSSOP_EP RE-24
AD5422BREZ-REEL 16 0.3 0.1 −40°C to +105°C 24-Lead TSSOP_EP RE-24
AD5422ACPZ-REEL 16 0.5 0.3 −40°C to +105°C 40-Lead LFCSP CP-40-1
AD5422ACPZ-REEL7 16 0.5 0.3 −40°C to +105°C 40-Lead LFCSP CP-40-1
AD5422BCPZ-REEL 16 0.3 0.1 −40°C to +105°C 40-Lead LFCSP CP-40-1
AD5422BCPZ-REEL7 16 0.3 0.1 −40°C to +105°C 40-Lead LFCSP CP-40-1
EVAL-AD5422EBZ AD5422 Evaluation Board
EVAL-AD5422LFEBZ AD5422 LFCSP Evaluation Board
1 Z = RoHS Compliant Part.
©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06996-0-10/17(O)