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FEATURES
DESCRIPTION/ORDERING INFORMATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
SN74LVC16373A16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005
•Member of the Texas Instruments Widebus™Family
•Operates From 1.65 V to 3.6 V•Inputs Accept Voltages to 5.5 V•Max t
pd
of 4.2 ns at 3.3 V•Typical V
OLP
(Output Ground Bounce) <0.8 Vat V
CC
= 3.3 V, T
A
= 25 °C•Typical V
OHV
(Output V
OH
Undershoot) >2 Vat V
CC
= 3.3 V, T
A
= 25 °C•I
off
Supports Partial-Power-Down ModeOperation
•Supports Mixed-Mode Signal Operation (5-VInput and Output Voltages With 3.3-V V
CC
)•Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 1000-V Charged-Device Model (C101)
This 16-bit transparent D-type latch is designed for1.65-V to 3.6-V V
CC
operation.
The SN74LVC16373A is particularly suitable forimplementing buffer registers, I/O ports, bidirectionalbus drivers, and working registers. The device can beused as two 8-bit latches or one 16-bit latch. Whenthe latch-enable (LE) input is high, the Q outputsfollow the data (D) inputs. When LE is taken low, theQ outputs are latched at the levels set up at the Dinputs.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
FBGA – GRD SN74LVC16373AGRDR
Tape and reel LD373AFBGA – ZRD (Pb-free) SN74LVC16373AZRDR
Tube SN74LVC16373ADLSSOP – DL LVC16373ATape and reel SN74LVC16373ADLR
SN74LVC16373ADGGR–40 °C to 85 °C TSSOP – DGG Tape and reel LVC16373A74LVC16373ADGGRG4
SN74LVC16373ADGVRTVSOP – DGV Tape and reel LD373A74LVC16373ADGVRE4VFBGA – GQL SN74LVC16373AGQLR
Tape and reel LD373AVFBGA – ZQL (Pb-free) SN74LVC16373AZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
K
ABC
GRD OR ZRD PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
SN74LVC16373A
16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005
A buffered output-enable ( OE) input can be used to place the eight outputs in either a normal logic state (high orlow logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive thebus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lineswithout interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered whilethe outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator ina mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
TERMINAL ASSIGNMENTS
(1)
(56-Ball GQL/ZQL Package)
1 2 3 4 5 6
A1 OE NC NC NC NC 1LE
B1Q2 1Q1 GND GND 1D1 1D2
C1Q4 1Q3 V
CC
V
CC
1D3 1D4
D1Q6 1Q5 GND GND 1D5 1D6
E1Q8 1Q7 1D7 1D8
F2Q1 2Q2 2D2 2D1
G2Q3 2Q4 GND GND 2D4 2D3
H2Q5 2Q6 V
CC
V
CC
2D6 2D5
J2Q7 2Q8 GND GND 2D8 2D7
K2 OE NC NC NC NC 2LE
ABC (1) NC – No internal connection
TERMINAL ASSIGNMENTS
(1)
(54-Ball GRD/ZRD Package)
1 2 3 4 5 6
A1Q1 NC 1 OE 1LE NC 1D1
B1Q3 1Q2 NC NC 1D2 1D3
C1Q5 1Q4 V
CC
V
CC
1D4 1D5
D1Q7 1Q6 GND GND 1D6 1D7
E2Q1 1Q8 GND GND 1D8 2D1
F2Q3 2Q2 GND GND 2D2 2D3
G2Q5 2Q4 V
CC
V
CC
2D4 2D5
H2Q7 2Q6 NC NC 2D6 2D7
J2Q8 NC 2 OE 2LE NC 2D8
(1) NC – No internal connection
2
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1OE
1LE
1D1
To Seven Other Channels
1Q1
C1
1D
1
48
47 2
2OE
2LE
2D1
To Seven Other Channels
2Q1
C1
1D
24
25
36 13
Pin numbers shown are for the DGG, DGV, and DL packages.
Absolute Maximum Ratings
(1)
SN74LVC16373A16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005
FUNCTION TABLE
INPUTS
OUTPUT
QOE LE D
L H H HL H L LL L X Q
0
H X X Z
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 VV
I
Input voltage range
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high or low state
(2) (3)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through each V
CC
or GND ±100 mADGG package 70DGV package 58θ
JA
Package thermal impedance
(4)
DL package 63 °C/WGQL/ZQL package 42GRD/ZRD package 36T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of V
CC
is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
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Recommended Operating Conditions
(1)
SN74LVC16373A
16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005
MIN MAX UNIT
Operating 1.65 3.6V
CC
Supply voltage VData retention only 1.5V
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 VV
CC
= 2.7 V to 3.6 V 2V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 VV
CC
= 2.7 V to 3.6 V 0.8V
I
Input voltage 0 5.5 VHigh or low state 0 V
CCV
O
Output voltage VHigh-impedance state 0 5.5V
CC
= 1.65 V –4V
CC
= 2.3 V –8I
OH
High-level output current mAV
CC
= 2.7 V –12V
CC
= 3 V –24V
CC
= 1.65 V 4V
CC
= 2.3 V 8I
OL
Low-level output current mAV
CC
= 2.7 V 12V
CC
= 3 V 24∆t/ ∆v Input transition rise or fall rate 10 ns/VT
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Electrical Characteristics
Timing Requirements
Switching Characteristics
SN74LVC16373A16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= –100 µA 1.65 V to 3.6 V V
CC
– 0.2I
OH
= –4 mA 1.65 V 1.2I
OH
= –8 mA 2.3 V 1.7V
OH
V2.7 V 2.2I
OH
= –12 mA
3 V 2.4I
OH
= –24 mA 3 V 2.2I
OL
= 100 µA 1.65 V to 3.6 V 0.2I
OL
= 4 mA 1.65 V 0.45V
OL
I
OL
= 8 mA 2.3 V 0.7 VI
OL
= 12 mA 2.7 V 0.4I
OL
= 24 mA 3 V 0.55I
I
V
I
= 0 to 5.5 V 3.6 V ±5µAI
off
V
I
or V
O
= 5.5 V 0 ±10 µAI
OZ
V
O
= 0 to 5.5 V 3.6 V ±10 µAV
I
= V
CC
or GND 20I
CC
I
O
= 0 3.6 V µA3.6 V ≤V
I
≤5.5 V
(2)
20∆I
CC
One input at V
CC
– 0.6 V, Other inputs at V
CC
or GND 2.7 V to 3.6 V 500 µAC
i
V
I
= V
CC
or GND 3.3 V 5 pFC
o
V
O
= V
CC
or GND 3.3 V 6.5 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.(2) This applies in the disabled state only.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 2.7 V±0.15 V ±0.2 V ±0.3 V
UNITMIN MAX MIN MAX MIN MAX MIN MAX
t
w
Pulse duration, LE high 3.3 3.3 3.3 3.3 nst
su
Setup time, data before LE ↓1.6 1.2 1.7 1.7 nst
h
Hold time, data after LE ↓1 1.1 1.2 1.2 ns
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 2.7 VFROM TO
±0.15 V ±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
D 1.5 6.4 1 4.2 1 4.9 1.6 4.2t
pd
Q nsLE 1.5 7.1 1 4.8 1 5.3 2.1 4.6t
en
OE Q 1.5 6.7 1 4.7 1 5.7 1.3 4.7 nst
dis
OE Q 1.5 8.4 1 5 1 6.3 2.5 5.9 ns
5
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Operating Characteristics
SN74LVC16373A
16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005
T
A
= 25 °C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VTESTPARAMETER UNITCONDITIONS
TYP TYP TYP
Outputs enabled 32 35 39Power dissipation capacitanceC
pd
f = 10 MHz pFper latch
Outputs disabled 4 4 6
6
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WA VEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH − V∆≈0 V
VI
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
SN74LVC16373A16-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com 3-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
74LVC16373ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVC16373ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVC16373ADGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC16373ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC16373ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC16373ADL ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC16373ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC16373ADLR ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC16373ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC16373AGQLR LIFEBUY BGA
MICROSTAR
JUNIOR
GQL 56 1000 TBD SNPB Level-1-240C-UNLIM
SN74LVC16373AZQLR ACTIVE BGA
MICROSTAR
JUNIOR
ZQL 56 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
SN74LVC16373AZRDR ACTIVE BGA
MICROSTAR
JUNIOR
ZRD 54 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 3-May-2012
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC16373A :
•Enhanced Product: SN74LVC16373A-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC16373ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
SN74LVC16373ADGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1
SN74LVC16373ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
SN74LVC16373AGQLR BGA MI
CROSTA
R JUNI
OR
GQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1
SN74LVC16373AZQLR BGA MI
CROSTA
R JUNI
OR
ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1
SN74LVC16373AZRDR BGA MI
CROSTA
R JUNI
OR
ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC16373ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0
SN74LVC16373ADGVR TVSOP DGV 48 2000 367.0 367.0 38.0
SN74LVC16373ADLR SSOP DL 48 1000 367.0 367.0 55.0
SN74LVC16373AGQLR BGA MICROSTAR
JUNIOR GQL 56 1000 333.2 345.9 28.6
SN74LVC16373AZQLR BGA MICROSTAR
JUNIOR ZQL 56 1000 333.2 345.9 28.6
SN74LVC16373AZRDR BGA MICROSTAR
JUNIOR ZRD 54 1000 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
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of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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