PIC18F4431-E/PT - Microchip Technology

PIC18F2331/2431/4331/4431

The PIC18F2331/2431/4331/4431 parts you have

received conform functionally to the Device Data Sheet

(DS39616), except for the anomalies described below.

Any Data Sheet Clarification issues related to the

PIC18F2331/2431/4331/4431 will be reported in a

separate Data Sheet errata. Please check the

Microchip web site for any existing issues.

All the issues listed here will be addressed in future

revisions of the PIC18F2331/2431/4331/4431 silicon.

The following silicon errata apply only to

PIC18F2331/2431/4331/4431 devices with these

Device/Revision IDs:

1. Module: Timer5

In Debug mode (using the MPLAB® ICD 2), if

“Freeze on Halt” is selected (an option in the

MPLAB ICD 2 settings under the Program tab),

TMR5L will not increment properly when single

stepping if the prescaler is not set to 1:1.

Work around

None. Use in Debug mode only with the 1:1

prescaler.

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: In-Circuit Serial Programming™

(ICSP™)

A small number of parts may be dif ficult to program

succes sfully at cert ain voltage s using the MPLAB®

ICD 2.

Work around

If such a part is encountered, attempt to program

several times. If unsuccessful, adjust VDD up or

down slightly, within the operating range of the

device . If thi s is n ot pos sible , then try ano the r pa rt.

Date Codes that pertain to this issue:

All engineering and production devices.

3. Module: PCPWM

When the PCPWM is operated in Complementary

mode with a non-zero dead-time value and the

duty cy cle re sults in an act ive-lo w time of less tha n

CY, the PWM ge nerator will miss th e rising edge

for a new PWM period and the PWM output will

alternate between one PWM period high and one

PWM period low.

Work around

When in Complementary mode with a non-zero

dead-time value, ensure that the active-low time

will always be greater than 1TCY. In other words,

when dead-time is not equal to zero, ensure that:

PDCH:PDCL < (4 * PTPERH:PTPERL)

PDCH:PDCL > (4 * (PTPERH:PTPERL + 1))

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F2331 00 1000 111 00001

PIC18F2431 00 1000 110 00001

PIC18F4331 00 1000 101 00001

PIC18F4431 00 1000 100 00001

The Devic e IDs (DEVID1 an d DEVID2 ) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

PIC18F2331/2431/4331/4431 Rev. A2 Silicon Errata

PIC18F2331/2431/4331/4431

4. Module: PCPWM

When the PCPWM is operated in Center-Aligned

mode with double updates and the duty cycle

alternates on each update between a zero and

non-zero value, an incorrect waveform is gener-

ated (the PWM output will alternate between one

PWM period high and one PWM period low). If in

Complementary mode, dead time will not be

inserted properly.

Work around

Do not use zero duty c ycle when in Center-Aligned

mode with do uble updates. Instead of zero, set the

duty cycle to a small, non-zero value.

Date Codes that pertain to this issue:

All engineering and production devices.

5. Module: PCPWM

When the PCPWM is operated in Center-Aligned

mode with double updates and the duty cycle

alte rnates on ea ch up dat e be tween a gr eat er tha n

100% duty cycle and a non-zero value, an incorrect

waveform is generated.

Work around

Do not use equal to or greater than 100% duty cycle

when in Center-Aligned m ode with double updates.

Ensure that the maximum duty cycle value is

always smaller than or equal to the PWM period,

i.e., PDCH:PDCL ≤ (4 * (PTPERH:PTPERL)).

Date Codes that pertain to this issue:

All engineering and production devices.

6. Module: PCPWM

If dead-time insertion is enabled and it is a non-

zero value, glitches in the PWM output will occur

under the following conditions:

1. When the PWM Timer is stopped by clearing

the PTEN bit.

2. When the duty cycle is changed to zero.

Work around

1. Before disabling the PWM timer, ensure that

PORTB is set up to maintain a safe state of

external hardware and that TRISB is set up to

define the pins as outputs.

2. Do not use zero duty cycle when dead-time

insertion is enabled. Instead of zero, set the

duty cycle to a small, non-zero value (such as

‘1’).

Date Codes that pertain to this issue:

All engineering and production devices.

7. Module: PCPWM

The PTMRH register will read as ‘00’ or the last

value written to it, even though the upper four bits

of the PWM timer may be different. Writing to

PTMRH will effect the upper four bits of the PWM

timer when PTMRL is subsequently written.

Although the PWM timer operates correctly, the

double-buffer circuit does not transfer data to the

PTMRH register from the upper four bits of the

PWM timer.

Work around

PWM operation is not affected. Do not attempt to

read PTMRH.

Date Codes that pertain to this issue:

All engineering and production devices.

8. Module: PCPWM

In Complementary mode with dead-time insertion,

when using OVDCOND and OVDCONS to

override the PWM outputs, dead time is not

inserted corre ctl y whe n the de ad-time pres ca le r is

FOSC/4, FOSC/8 or FOSC/16.

Work around

None. Us e dead-ti me pres caler of FOSC/2 in th ese

circumstances.

Date Codes that pertain to this issue:

All engineering and production devices.

9. Module: Data EEPROM

When writi ng to the dat a EEPROM, the cont ents of

the data EEPROM memory may not be written as

expected if the internal voltage reference is not

enabled.

Work around

Either of two work arounds can be used:

1. Before beginning any writes to the data

EEPROM, enable the LVD (any voltage) and

wait for the internal voltage reference to

become st ab le. LVD interrupt re qu ests may be

ignored. Once the LVD voltage reference is

stable, perform all EEPROM writes normally.

When writes have been completed, the LVD

may be disabled.

2. Configure the BOR as enabled (any voltage).

Select a threshold below VDD to allow normal

operation. If VDD is below the BOR threshold,

the device will be held in Brown-out Reset.

PIC18F2331/2431/4331/4431

10. Module: Program Memory

When wri ting to the program memory, the c ontents

of the program memory may not be written as

expected if the internal voltage reference is not

enabled.

Work around

Either of two workarounds can be used:

1. Before beginning any writes to the program

memory, enable the LVD (any voltage) and

wait for the internal voltage reference to

become st able. LVD interrupt request s may be

ignored. Once the LVD voltage reference is

stab le, perform a ll program mem ory writes n or-

mally. When writes have been completed, the

LVD may be disabled.

2. Configure the BOR as enabled (any voltage).

Select a threshold below VDD to allow normal

operation. If VDD is below the BOR threshold,

the device will be held in BOR Reset.

Date Codes that pertain to this issue:

All engineering and production devices.

11. Module: Cor e (DAW Instruction)

The DAW instruction may improperly clear the

Carry bit (Status<0>) when executed.

Work around

Test the Carry bit state before executing the DAW

instruction. If the Carry bit is set, increment the

nex t highe r by te to be adde d, usi ng an inst ruct ion

such as INCFSZ (this instruction does not affect

any Status flags and will not overflow a BCD

nibble). After the DAW instruction has been

executed, process the Carry bit normally (see

Example 1).

EXAMP LE 1: PROCESSING T HE CARRY

BIT DURING BCD A DDITIONS

Date Codes that pertain to this issue:

All engineering and production devices.

12. Module: EUSART

Bit SENDB in the TXSTA register is not automati-

cally cleared by hardware upon completion of

transmission of a Sync Break.

Work around

Check the TRMT bit in TXSTA. If the TRMT bit is

set, Break transmission is said to be complete.

13. Module: EUSART

If the transm itter is left enab led while the modu le is

performing an auto-baud operation, an arbitrary

data byte may get transmitted.

Work around

Clear TXEN (TXSTA<5>) before any auto-baud

operation and set it after auto-baud is complete.

Enable TXEN only when a data byte is to be

transmitted . Care m ust be t aken to ensu re that th e

TX pin is pulled high, either through an external

resistor, or by making the TX pin an output and

writing ‘1’ to it to not disturb the transmit line.

14. Module: EUSART

This module may perform incorrect auto-baud

calculation if the ABDEN (BAUDCON<0>) bit was

set while the receive pin was at a low level.

Work around

Wait for the RX pin to go high and then set the

ABDEN bit.

15. Module: EUSART

In Asynchronous Receiver mode, the EUSART

does no t load the SPBRGH val ue afte r com pletion

of auto-baud.

Work around

Do not enable the BRG16 (BAUDCON<3>) bit.

If the BRG16 is in use, ensure that the auto-baud

SPBRG value does not exceed the 8-bit value.

16. Module: EUSART

The CREN (RCSTA<4>) bit is cleared after every

auto-baud operation.

Work around

Upon completion of auto-baud, manually set the

CREN bit.

MOVLW 0x80 ; .80 (BCD)

ADDLW 0x80 ; .80 (BCD)

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

DAW

BTFSC STATUS, C ; test C

INCFSZ byte2 ; inc next higher LSB

This is repeated for each DAW instruction.

PIC18F2331/2431/4331/4431

17. Module: EUSART

Writing to the USART/EUSART TXREG register

faster than the baud rate in Synchronous mode

will overwrite the previous value instead of

double-bufferi ng as in Asynchronous mode.

Work around

Load the firs t cha rac ter int o TXR EG an d then wa it

for a TX interrupt, or check the TXIF bit before

writing each additional character to TXREG.

18. Module: EUSART

The EUSART ca nnot receive asynchronous dat a at

the four fastest baud rates (BRGH = 1, BRG16 = 1

and SPBRG < 4).

Work around

Use a slower baud rate or a faster system clock

speed.

19. Module: HSADC

A ΔIAD (parameter D026) of greater than 300 μA

(for VDD = 3V) is observed when the device is

put into Sleep mode with the HSADC enabled

(ADON = 1) without setting the GO/DONE bit so

that at least one conversio n is p erformed.

Observed ΔIAD will increase in proportion to VDD.

Work around

If no conv ers io n wil l be don e whil e in Sleep m od e,

disabl e th e H SADC m odu le by cle ari ng the ADON

bit before entering Sleep mode.

If power consumption is an issue for the applica-

tion, do not put the part into Sleep mode with the

HSADC enabled if no conversion is to be

performed.

PIC18F2331/2431/4331/4431

REVISION HISTORY

Rev A Document (1/2004)

First revi sion of this doc ument. Silico n issues 1 (T imer5),

2 (In-Circuit Serial Programming), 3-8 (PCPWM),

9 (Data EEPROM), 10 (Program Memory), 11 (Core –

DAW In struction) and 12-18 (EUSART) and Data Sheet

Clarification issue 1 (P ower-on Reset).

Rev B Document (2/2004)

Modifications to the Work Around for Silicon issue 3

(PCPWM).

Rev C Document (05/2005)

Added silicon issue 19 (HSADC). All Data Sheet Clarifi-

cation issu es w ere r emov ed an d pl aced into a separ ate

Data Sh ee t Err at a .

PIC18F2331/2431/4331/4431

NOTES:

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applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

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