74ABT245PW - NXP Semiconductors - searchdatasheet.com

September 1991

Revised November 1999

74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs

74ABT245

Octal Bi-Directi onal Transceiver with 3-STATE Outputs

General Description

The ABT245 contains eight non-inverting bidirectional buff-

ers with 3-STATE outp uts and is intend ed for bus-ori ented

applications. Current sinking capability is 64 mA on both

the A and B ports. The Transmit/Receive (T/R) input deter-

mines the direction of data flow through the bidirectional

transceiver. Transmit (active HIGH) enables data from A

Ports to B Ports; Re ceive (a ctive LOW) enables d ata from

B Ports to A Ports. The Output Enab le input, wh en HIGH,

disables both A and B po rts by placing them in a HIGH Z

condition.

Features

■Bidirectional non-inverting buffers

■A and B output sink capability of 64 mA, source

capability of 32 mA

■Guaranteed output skew

■Guaranteed multiple output switching specifications

■Output switching specified for both 50 pF and 250 pF

loads

■Guaranteed simultaneous switching, noise level and

dynamic thresh ol d per for man ce

■Guaranteed latchup protection

■High impedance glitch-free bus loading during entire

power up and power down cycle

■Non-destructive hot insertion capability

■Disable time is less than enable time to avoid bus

contention

Ordering Code:

Device a ls o av ailable in Tape and Reel. Specify by a ppending s uffix let te r “X” to the or dering co de.

Connection Diagram Pin Descriptions

Order Number Package Number Package Description

74ABT245CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

74ABT245CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ABT245CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

74ABT245CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ABT245CPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Descri ption

OE Output Enable Input (Active LOW)

T/R Transmit/Receive Input

A0–A7 Side A Inputs or 3-STATE Outputs

B0–B7 Side B Inputs or 3-STATE Outputs

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74ABT245

Logic Symbol Truth Table

H = HIGH Voltage Lev el

L = LOW Voltage Level

X = Immaterial

Logic Diagram

Inputs Output

OE T/R

L L Bus B Data to Bus A

L H Bus A Data to Bus B

H X HIGH Z State

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74ABT245

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: Eith er v oltage lim it or c urrent limit is sufficie nt to protect inputs

DC Electrical Characteristics

Storage Temperature −65°C to +150°C

Ambient Temperature under Bias −55°C to +125°C

Junction Temperature under Bias −55°C to +150°C

VCC Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 2) −0.5V to +7.0V

Input Current (Note 2) −30 mA to +5.0 mA

Voltage Applied to Any Output

in the Disabled or

Power-off State −0.5V to 5.5V

in the HIGH State −0.5V to VCC

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

DC Latchup Source Current −500 mA

Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature −40°C to +85°C

Supply Voltage +4.5V to +5.5V

Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns

Enable Input 20 mV/ns

Symbol Parameter Min Typ Max Units VCC Conditions

VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized LOW Signal

VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (OE, T/R)

VOH Output HIGH Voltage 2.5 V Min IOH = −3 mA (An, Bn)

2.0 V Min IOH = −32 mA (An, Bn)

VOL Output LOW Voltage 0.55 V Min IOL = 64 mA (An, Bn)

IIH Input HIGH Current 1 µAMax

VIN = 2.7V (OE, T/R)

1VIN = VCC (O E, T/R)

IBVI Input HIGH Current Breakdown Test 7 µAMax

VIN = 7.0V (OE, T/R)

IBVIT Input HIGH Current Breakdown Test (I/O) 100 µAMaxV

IN = 5.5 V (An, Bn)

IIL Input LOW Current −1µAMax

VIN = 0.5V (OE, T/R)

−1VIN = 0.0V (OE, T/R)

VID Input Leakage Test 4.75 V 0.0 IID = 1.9 µA (OE, T/R)

All Other Pins Grounded

IIH + IOZH Output Leakage Current 10 µA0 − 5.5V VOUT = 2.7V (An, Bn); OE = 2.0V

IIL + I OZL Output Leakage Current −10 µA0 − 5.5V VOUT = 0.5V (An, Bn); OE = 2.0V

IOS Output Short-Circuit Current −100 −275 mA Max VOUT = 0.0V (An, Bn)

ICEX Output HIGH Leakage Current 50 µAMaxV

OUT = V CC (An, Bn)

IZZ Bus Drainage Test 100 µA0.0V

OUT = 5.5V (An, Bn);

All Others GND

ICCH Power Supply Current 50 µA Max All Outputs HIGH

ICCL Power Supply Current 30 mA Max All Outputs LOW

ICCZ Power Supply Current 50 µAMax

OE = VCC, T/R = GND or VCC;

All Other GND or VCC

ICCT Additional Outputs Enabled 2.5 mA VI = V CC − 2.1V

I CC/Input Outputs 3-STATE 2.5 mA Max OE, T/R VI = VCC − 2.1V

Outputs 3-STATE 50 µA Data Input VI = VCC − 2.1V

All Others at VCC or GND.

ICCD Dynamic ICC No Load 0.1 mA/ Max Outputs Open

MHz OE = GND, T/R = GND or VCC

One Bit Toggling, 50% Duty Cycle

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74ABT245

DC Electrical Characteristi cs

(SOIC package)

Note 3: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.

Note 4: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).

Guaranteed, but not tested.

Note 5: Max num ber of outputs defined as (n). n − 1 data input s are drive n 0V to 3V. One outp ut H I GH . Guaranteed, but not te s te d.

AC Electrical Characteristi cs

(SOIC and SSOP package)

Extended AC Electrical Characteristics

(SOIC package)

Note 6: This specif ic ation is guaranteed but not t es t ed. The limit s apply to pro pagati on delays for all paths des c ribed sw it ch ing in phase

(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 7: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-

itors in t he standard AC load. This s pec ification pertains t o s ingle out put switching only.

Note 8: This specif ic ation is guaranteed but not t es t ed. The limit s represent propagation delays for all paths desc ribed sw it ch ing in phase

(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.

Note 9: The 3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and have been excluded from the datasheet.

Symbol Parameter Min Typ Max Units VCC Conditions

CL = 50 pF, RL = 500Ω

VOLP Quiet Output Maximum Dynamic VOL 0.7 1.0 V 5.0 TA = 25°C (Note 3)

VOLV Quiet Output Minimum Dynamic VOL −1.3 −1.0 V 5.0 TA = 25°C (Note 3)

VOHV Minimum HIGH Level Dynamic Output Voltage 2.7 3.1 V 5.0 TA = 25°C (Note 5)

VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.7 V 5.0 TA = 25°C (Note 4)

VILD Maximum LOW Level Dynamic Input Voltage 0.9 0.6 V 5.0 TA = 25°C (Note 4)

TA = +25°CT

A = −55°C to +125°CT

A = −40°C to +85°C

Symbol Parameter VCC = +5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V Units

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

tPLH Propagation Delay 1.0 2.1 3.6 1.0 4.8 1.0 3.6 ns

tPHL Data to Outputs 1.0 2.4 3.6 1.0 4.8 1.0 3.6

tPZH Output Enable 1.5 3.2 6.0 1.0 6.7 1.5 6.0 ns

tPZL Time 1.5 3.7 6.0 2.0 7.5 1.5 6.0

tPHZ Output Disable 1.0 3.6 6.1 1.7 7.4 1.0 6.1 ns

tPLZ Time 1.0 3.3 5.6 1.7 6.5 1.0 5.6

Symbol Parameter

−40°C to +85°C TA = −40°C to +85°C T

A = −40°C to +85°C

Units

VCC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V

CL = 50 pF CL = 250 pF CL = 250 pF

8 Outputs Switching 1 Output Switching 8 Outputs Switching

(Note 6) (Note 7) (Note 8)

Min Typ Max Min Max Min Max

fTOGGLE Max Toggle Frequency 100 MHz

tPLH Propagation Delay 1.5 5.0 1.5 6.0 2.5 8.5 ns

tPHL Data to Outputs 1.5 5.0 1.5 6.0 2.5 8.5

tPZH Output Enable Time 1.5 6.5 2.5 7.5 2.5 9.5 ns

tPZL 1.5 6.5 2.5 7.5 2.5 11.0

tPHZ Output Disable Time 1.0 6.5 (Note 9) (Note 9) ns

tPLZ 1.0 5.6

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74ABT245

Skew

(SOIC package)

Note 10: S kew is de fined a s the ab solute v alue of t he differen ce betwe en the a ctual p ropagat ion delay s for any two se parate o utputs o f the same de vice.

The spec if ic at ion applies to any outputs s w it c hing HIGH-to-LO W (t OSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or

HIGH-to-LOW (tOST). The sp ec if ic ation is guaranteed but not tested .

Note 11: Propagation delay variation for a giv en set o f condit ions (i.e., te m perature and VCC) from device to device. This specification is guaranteed but not

tested.

Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase

(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)

Note 13: The se specif ications g uaranteed but not tes ted. The limits repr esent pro pagation delays with 250 pF lo ad capac itors in pla ce of the 50 pF load

capacitors in the standard AC load.

Note 14: Th is d esc ribes th e differe nce b etwee n th e delay of the LOW- to-HI GH and the HIG H-to -LO W trans itio n on the sam e p in. I t i s mea sure d acros s all

the output s (driver s) on t he same chip, the worst (large s t delt a) numb er is the gua ranteed s pecificat ion. This sp ec if ic at ion is guaranteed but not tested.

Capacitance

Note 15: CI/O is measured at f reque nc y f = 1 MHz, per MI L-STD-8 83, Method 3012.

Symbol Parameter

TA = −40°C to +85°CT

A = −40°C to +85°C

Units

VCC = 4.5V–5.5V VCC = 4.5V–5.5V

CL = 50 pF CL = 250 pF

8 Outputs Switching 8 Outputs Switching

(Note 12) (Note 13)

Max Max

tOSHL Pin to Pin Skew 1.3 2.3 ns

(Note 10) HL Transitions

tOSLH Pin to Pin Skew 1.0 1.8 ns

(Note 10) LH Transitions

tPS Duty Cycle 2.0 3.5 ns

(Note 14) LH–HL Skew

tOST Pin to Pin Skew 2.0 3.5 ns

(Note 10) LH/HL Transitions

tPV Device to Device Skew 2.0 3.5 ns

(Note 11) LH/HL Transitions

Symbol Parameter Typ Units Conditions

TA = 25°C

CIN Input Capacitance 5.0 pF VCC = 0V (OE , T/R)

CI/O (Note 15) I/O Capacitance 11.0 pF VCC = 5.0V (An, Bn)

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74ABT245

AC Loading

*Inclu des jig an d probe capacitan c e

FIGURE 1. Standard AC Test Load FIGURE 2. Test Input Signal Levels

FIGURE 3. Test Input Signal Requirements

AC W aveforms

FIGURE 4. Propagation Delay Waveforms

for Inverting and Non-Inverting Functions

FIGURE 5. Propagation Delay,

Pulse Width Waveforms

FIGURE 6. 3-STATE Output HIGH

and LOW Enable and Disable Times

FIGURE 7. Setup Time, Hold Time

and Recovery Time Waveforms

Amplitude Rep. Rate tW tr tf

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

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74ABT245

Physical Dim ensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

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74ABT245

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Sma ll Outline Pac kage (SOP), EI AJ TYPE II, 5.3mm Wide

Package Number M20D

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74ABT245

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Number MSA20

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74ABT245

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

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74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

20-L ead Plastic Dual-In-Line Pa ckage (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A

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Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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