| Dual Wideband, Low-Noise, Comlinear Voltage-Feedback Op Amp CLC428 APPLICATIONS: FEATURES: e General purpose dual op amp e Wide unity-gain bandwidth: 160MHz e Low noise integrators e Ultra-low noise: 2.0nV/VHz Low noise active filters e Low distortion: -78dBc 2nd (2MHz) Diff-in/diff-out instrumentation amp -62/-72dBe (10MHz) Driver/receiver for transmission systems Settling time: 16ns to 0.1% e High-speed detectors e Supply voltage range: +2.5 to +5 or e 1/Q channel! amplifiers single supply e High output current: +80mA DESCRIPTION Channel Matching The CLC428 is a very high-speed dual op amp that offers a traditional voltage-feedback topology featuring unity-gain stability and slew-enhanced circuitry. The CLC428s ultra low noise and very low harmonic distortion combine to form a very wide dynamic- range op amp that operates from a single (5 to 12V) or dual (+5V) power supply. Gain Channel 1 \ (Alp/oSp) aSBYd ph a Magnitude (1dB/div) Each of the CLC428s closely matched channels provides a 160MHz unity-gain bandwidth with an ultra low input voltage noise density (2nV/VHz). Very low 2nd/3rd harmonic distortion (-62/-72dBc) as well as high channel-to-channelisolation (-62dB) make the CLC428 a perfect wide dynamic-range amplifier for matched 1/Q channels. { 300 Frequency (MHz) a hannel 2 a wo a -180 -270 With its fast and accurate settling (16ns to 0.1%), the CLC428 is also a excellent choice for wide-dynamic range, anti-aliasing filters PINOUT to buffer the inputs of hi-resolution analog-to-digital converters. DIP & SOIC Combining the CLC428s two tightly-matched amplifiers in a single yg eight-pin SOIC reduces cost and board space for many composite Vout [4 . 8 | +Vec amplifier applications such as active filters, differential line drivers/ receivers, fast peak detectors and instrumentation amplifiers. Vinv1 [2 7 Vout2 Vnon-inv1 | 3 6} Vinv2 To reduce design times and assist in board layout, the CLC428 nonin! [3 | [8 | View is supported by an evaluation board and a SPICE simulation Vee [4 15} Vnon-inv2 model! available from Comlinear. TYPICAL APPLICATION Frequency & Phase Response 5-Decade Integrator = 00 360pF va " Vout Vin o Magnitude (20dB/div) (Aip/oSP) BS2Ud 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Comlinear Corporation 4800 Wheaton Drive Fort Collins, CO.80525 + (800) 776-0500 FAX (303) 226-6761 Internet: clc_apps@cc.com DS428.02 . J 1995 M@ 2279101 0001877 TOL ameC428 Electrical Characteristics (v,.= +5v; Ay= +2V/V; R,=100Q; R,=1002; R, = 1002; uniess notea) PARAMETERS CONDITIONS TYP GUARANTEED MIN/MAX UNITS || NOTES Ambient Temperature CLC428 +25C +25C Oto +70C |-40 to +85C FREQUENCY DOMAIN RESPONSE gain bandwidth product Vou < 0.5V op 135 100 80 70 MHz -30B bandwidth, Av=+1 Vou < 0.5V op 160 120 90 80 MHz Av=+2 Vout < 0.5Vo0 80 50 40 35 MHz B,1 Vout < 5.0Vop 40 25 22 20 MHz gain flatness Vou < 0.5Vop peaking DC to 200MHz 0.0 0.6 0.8 1.0 dB B,1 rolloff DC to 20MHz 0.05 0.5 0.7 0.7 dB B,1 linear phase deviation DC to 20MHz 0.2 1.0 1.5 1.5 TIME DOMAIN RESPONSE rise and fall! time 1V step 5.5 7.5 9.0 10.0 ns settling time 2V step to 0.1% 16 20 24 24 ns overshoot 1V step 1 5 10 10 % slew rate 5V step 500 300 275 250 Vius DISTORTION AND NOISE RESPONSE 2 harmonic distortion 1V 59,1 0MHz - 62 - 50 - 45 - 43 dBc B 3 harmonic distortion 1V,,,10MHz -72 - 60 - 56 - 56 dBc B equivalent input noise voltage 1MHz to 100MHz 2.0 2.5 2.8 2.8 nV/VHz current 1MHz to 100MHz 2.0 3.0 3.6 4.6 pA/VHz crosstalk input referred, 10MHz || - 62 - 58 - 58 - 58 dB STATIC DC PERFORMANCE open-loop gain 60 56 50 50 dB input offset voltage 1.0 2.0 3.0 3.5 mV A average drift 5 - 15 20 pVvieC input bias current 1.5 25 40 65 pA A average drift 150 oo 600 700 nArG input offset current 0.3 3 5 5 pA average drift 5 --- 25 50 nA/C power supply rejection ratio 66 60 55 55 dB B common-mode rejection ratio 63 57 52 52 dB supply current per channel, R.= 2 11 12 13 15 mA A MISCELLANEOUS PERFORMANCE input resistance common-mode 500 250 125 4125 kQ differential-mode 200 50 25 25 kQ input capacitance common-mode 2.0 3.0 3.0 3.0 pF differential-mode 2.0 3.0 3.0 3.0 pF output resistance closed loop 0.05 0.1 0.2 0.2 Q output voltage range Ri= 2 +3.8 +3.5 + 3.3 + 3.3 Vv R,=1000 +3.5 3.2 +2.6 13 Vv input voltage range common mode +3.7 + 3.5 +3.3 3.3 Vv output current + 80 + 50 +40 +20 mA Absolute Maximum Ratings supply voltage +7V short circuit current (note 2) common-mode input voltage Voc differential input voltage +10V maximum junction temperature +200C storage temperature -65C to+ 150C lead temperature (soldering 10 sec) +300C A) J-level: spec is 100% tested at +25C, sample tested at +85C. L-level: spec is 100% wafer probed at 25C. B) J-level: spec is sample tested at 25C. 1) Spec is guaranteed at 0.5Vpp but tested at 0.1Vpp. 2) Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 200mA. ad Ordering Information Model Temperature Range Description CLC428AJP -40C to +85C 8-pin PDIP CLC428AJE -40C to +85C 8-pin SOIC CLC428ALC -40C to +85C dice CLC428A8B* -55C to +125C 8-pin CerDIP, MIL-STD-883 CLC428AMC* -55C to +125C dice, MIL-STD-883 CLC428AIB* -40C to +85C 8-pin CerDIP 5962-9470801MPA* -55C to +125C DESC SMD *See CLC428 MIL-883 Data Sheet for Specifications Package Thermal Resistance Package 6. Oia Plastic (AJP) 75W 90/W Surface Mount (AJE) 90/W 105/wW Comlinear reserves the right to change specifications without notice. 2279101 0001878 46Non-Inverting Frequency Response CLC428 Typical Performance (1q=+25C, Ay=+2, Voc=+5V, Ri=1000, RL=1000, unless noted) Inverting Frequency Response Frequency Response vs. Load Resistance Ava =1kQ zu uv a Gain > Galn za a = a = = = = 3 g & g 3 g = 2 = g 0 3 0 3 0 2 4 = 4 = 45 e e Ay=-5 S = 4 = -90 = -$0 135 Ae-t0 135 135 Vout=100MV pp 480 Vow =100MV pp 180 Vout=100mVpp 120 1M 10M 100M 1M 10M 100M 1M 10M 100M Frequency (Hz) Frequency (Hz) Frequency (Hz) Frequency Response vs. Output Amplitude Response vs. Capacitive Load 4 Gain Flatness & Linear Phase Deviation 020 =100pF = , , an a o Gain Vout=200mV ~ 1.02 =< N\ 0.12 > 2 _ PN 3 a ma 1) NX a 3 = 0.04 0.04 a s 3g WA 3 2 & -0.06 0.04 -0.08 LPD 0.12 0.10 0.20 1M 10M 400M 1M 10M 400M 0M 5M 10M 15M 20M Frequency (Hz) Frequency (Hz) Frequency (Hz) rn Maximum Output Voltage vs. Load Channel-to-Channel Crosstalk 80 Open-Loop Gain & Phase | | AEN Oy 70 2 ae ~ a* A a 60 g 2 Va S 3 3 g 5 6 / S50 8 a a a 3 30 L 3 2 40 0 = 60 lV S40 8 Wa 2 Channel 1] | | Y 2 0 S 29 Va 6 20 / V) | /| \channel 2 0 135 20 20 | | | 0 180 25 50 75 100 1M 10M 100M 10k 100k 1M 10M 100M Loads? Frequency (Hz) Frequency (Hz) 2nd and 3rd Harmonic Distortion 2nd Harmonic Distortion vs. P 3rd Harmonic Distortion vs. Poy -40 -20 ~20 45 -30 _ -30 20MHz zo -50 Ri=100Q4 3rd ss o 8 55 F 8 49 3 4p ss" B 2 = 60 & 6 2 9 s g s 3* 5 60 2 0 a -70 5 a -70 -70 75 Vout=1Vpp -80 -80 -60 4M 10M 50M 0 1 3 4 5 6 8 0 1 3 4 5 6 7 8 Frequency (Hz) Output (Vp,) Output (Vpp) Closed-Loop Output Resistance 0 Noise 0 2-Tone, 3rd Order Intermodulation Intercept 10 48 = _ 46 3 - 3 eu > urrent o 2 | s & Fa Ce 2 gS < & 5 = 3 40 = 2 0.10 2 = 8 = & 2% et 2 Voltage -. = e x N 34 0.01 4 1 32 100 tk 10k 100k = 1M 10M 100M 1 10 1000 iM 10M 100M Frequency (Hz) Frequency (kHz) Frequency (Hz) 2 mm 2279101 0001879 484 2 (soasBep)ad)0.10 0.08 0.06 0.04 0.02 -0.00 0.02 Oo 0.04 0.06 0.08 0.10 utput Voltage 0.2 0.15 = =a 2 ol e & _ oO 0.15 0.2 Vout (% final value) o Pulse Response (Vout=100mV) CLC428 Typical Performance (Tq=+25 C, Ay=+#2, Vec= + 5V, Ri=1000), RL=10002, unless noted) Pulse Response (Vout=2V) Settling Time vs. Capacitive Load | Ay=+2 [I re * v= Av=+2 0 a / o a N Ts to 0.05% g < N | s 3 * = E INQ / 3 i 3 22 M4 20 3 Rs N 10 10 Ave Cc. a SL Av=-1 J r 0 Ti 0 Time (5ns/div) Time (Sns/div) 10 100 1000 we Ci (pF) Short-Term Settling Time CMRR and PSRR Typical DC Errors vs. Temperature 80 1.2 7 5 Vout=2Vstep YL 70 PSRR a z I Ves ~ 60 o \ 08 3 a 50 $ lb 5 06 SZ 2 g 3 at 39 04 | PS ' a los h~ 20 02 | 40 0 10 20 3 40 50 6 70 8 90 100 10k 400k 10M 100M 40-20 80 400 Time (ns) Frequency (Hz) 0 20 40 oO Temperature (C) Application Discussion Low Noise Design Ultimate low noise performance from circuit designs using the CLC428 requires the proper selection of external resistors. By selecting appropriate low-valued resistors for Ryand Rg, amplifier circuits using the CLC428 can achieve output noise that is approximately the equivalent voltage input noise of 2.0 nV/VHz multiplied by the desired gain (Av). Each amplifier in the CLC428 has an equivalent input noise resistance which is optimum for matching source impedances of approximately 1k. Using a transformer, any source can be matched to achieve the lowest noise design. For even lower noise performance than the CLC428, consider the CLC425 or CLC426 at 1.05 and 1.6 nV/VHz, respectively. DC Bias Currents and Offset Voltages Cancellation of the output offset voltage due to input bias currents is possible with the CLC428. This is done by making the resistance seen from the inverting and non- inverting inputs equal. Once done, the residual output offset voltage will be the input offset voltage (Vos) multiplied by the desired gain (Av). Comlinear Applica- tion Note OA-7 offers several solutions to further reduce the output offset. Me 2279101 002860 STb Output and Supply Considerations With +5V supplies, the CLC428 is capable of a typical output swing of +3.8V under a no-load condition. Additional output swing is possible with slightly higher supply voltages. For loads of less than 50Q, the output swing will be limited by the CLC428s output current capability, typically 80mA. Output settling time when driving capacitive loads can be improved by the use of a series output resistor. See the plot labeled "Settling Time vs. Capacitive Load" in the Typical Performance section. Layout Proper power supply bypassing is critical to insure good high frequency performance and low noise. De-coupling capacitors of 0.1F should be place as close as possible to the power supply pins. The use of surface mounted capaci- tors is recommended due to their low series inductance. Agood high frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic Capacitance from these nodes to ground causes frequency response peaking and possible circuit oscillation. See OA-15 for more information. Comlinear suggests the 730036 (through-hole) or the 730027 (SOIC) dual op amp evaluation board as a guide for high frequency layout and as an aid in device evaluation. Y (u) Sy popuewuiacey (vil) juauing Jesyo 2 seg ynduyAnalog Delay Circuit (All-Pass Network) The circuit in Figure 1 implements an all-pass network using the CLC428. A wide bandwidth buffer (CLC111) drives the circuit and provides a high input impedence for the source. As shown in Figure 2, the circuit provides a | 4oee Vin 4990 nid CLC vi ~- 4992 AAA YeCL.0428 wv - Vout a yeCLCa2g >+$-~0 ; jp + Cc R Delay Circuit Response to 0.5V Pulse Figure 1 Vin, Vout (100mV/div.} Time (10ns/div) Figure 2 13.1ns delay (with R =40.2Q, C=47pF). Rr and Rg should be of equal and low value for parasitic insensitive opera- tion. The circuit gain is +1 and the delay is determined by the following equations. Tdelay = 2(2RC + Ty) Eq. 1 1 do Ty=-; Eq. 2 4" 360 df q where Tg is the delay of the op amp at Ay=+1. The CLC428 provides a typical delay of 2.8ns at its -3dB point. Full Duplex Digital or Analog Transmission Simultaneous transmission and reception of analog or digital signals over a single coaxial cable or twisted-pair line can reduce cabling requirements. The CLC428's wide bandwidth and high common-mode rejection in a differential amplifier configuration allows full duplex trans- mission of video, telephone, control and audio signals. In the circuit shown in Figure 3, one of the CLC428's amps is used as a "driver" and the other as a difference "receiver" amplifier. The output impedance of the driver" is essentially zero. The two R's are chosen to match the characteristic impedance of the transmission line. The "driver" op amp gain can be selected for unity or greater. Receiver amplifier Ao (Bz) is connected across R and forms differential amplifier for the signals transmitted by driver Aj (B1). If the coax cable is lossiess and Ry equals Rg, receiver Ag (Bz) will then reject the signals from driver Vin A B1 Vin + Coax Cable + Rin YeCLC428 R / %CLC428 Rin > g Ri Re = $Me Rr WA AA Vout Vout VeCLC428 o A Ba Figure 3 A; (B1) and pass the signals from driver By (Ai). The output of the receiver amplifier will be: _1 R; 1 R; Voutaia) = Minne, Boy, [1-2 Eq. 3 Care must be given to layout and component placement to maintain a high frequency common-mode rejection. The plot of Figure 4 shows the simultaneous reception of signals transmitted at 1MHz and 10MHz. Th TAOMOnAn el owl U UU UU UU UT +0.5V - | -0.5V L 0 0.2 0.4 0.6 0.8 1.0 Time (0.2418/div) Figure 4 Five Decade Integrator A composite integrator, as shown in Figure 5, uses the CLC428 dual op amp to increase the circuits' usable frequency range of operation. The transfer function of this circuit is: 1 Vo = ac! Vide Eq. 4 o > Vout Figure 5 A resistive divider made from the 1430 and 60.4Q resistors was chosen to reduce the loop-gain and stabi- lize the network. The CLC428 composite integrator provides integration over five decades of operation. R and C set the integrator's gain. Figure 6 shows the frequency and phase response of the circuit in Figure 5 with R=44.2Q and C=360pF. MH 2279101 0001881) 432 DOFrequency & Phase Response _ 00 Magnitude (20dB/div) (Alp/oGp) aSPYd 10 100 ik 10k 100k 1M 10M 100M Frequency (Hz) Figure 6 Positive Peak Detector The CLC428's duai amplifiers can be used to inplement a unity-gain peak detector circuit as shown in Figure 7. Figure 7 The acquisition speed of this circuit is limited by the dynamic resistance of the diode when charging Choid. A plot of the of the circuit's performance is shown in Figure 8 with a 1MHz sinusoidal input. 2 yl Output \ 7 \ | NEA ~ - y Input 2 0 0.5 1.0 1.5 2.0 25 3.0 Time (us) es, Input, Output (Volts) ~ o - Figure 8 A current source, built around Q,, provides the neces- sary bias current for the second amplifier and prevents saturation when power is applied. The resistor, R, closes the loop while diode D2 prevents negative saturation when Vin is less than Vc. AMOS-type switch (not shown) can be used to reset the capacitor's voltage. The maximum speed of detection is limited by the delay of the op amps and the diodes. The use of Schottky diodes will provide faster response. Adjustable or Bandpass Equalizer A "boost" equalizer can be made with the CLC428 by summing a bandpass response with the input signal, as shown in Figure 9. c It 1 Vin c Ra iB 7 +_| v Ra J * KR Vout oO V R Figure 9 The overall transfer function is shown in Eq. 5. R, s2Qa, = K(R, +R,) - 1 Vin c R, +R, niet Eq. 5 To build a boost circuit, use the design equations Eq. 6 and Eq. 7. 2 Q 1 =, 2C(R,IIR,)= Q, ( a ) Qo, Eq. 6,7 Select Re and C using Eq. 6. Use reasonable values for high frequency circuits - Re between 10 and 5kQ, C between 10pF and 2000pF. Use Eq. 7 to determine the parallel combination of Ra and Rp. Select Ra and Rp by either the 102 to 5kQ criteria or by other requirements based on the impedance Vin is capable of driving. Finish the design by determining the value of K from Eq. 8. V, R Peak Gain = (w, ) = # V, okR, In 1 Eg. 8 Figure 10 shows an example of the response of the circuit of Figure 9, where fp is 2.3MHz. The component values are as follows: Ra =2.1kQ, Rp =68.50, Re =4.22kQ, R =5002, KR =502, C =120pF. 20 mal {o=2.3MHz77| = on | JN = So on Pall Magnitude (5dB/div) Oo 10k 100k 1M 10M Frequency (Hz) Figure 10 5CC3C DS428.02 BH 2279) o1 000 1482 3745 i. Comlinear Corporation 1995