19-3174; Rev 0; 1/04 KIT ATION EVALU E L B AVAILA Low-Cost Linear-Regulator LCD Panel Power Supplies The MAX8710/MAX8711/MAX8712 offer complete linear-regulator power-supply solutions for thin-film transistor (TFT) liquid-crystal-display (LCD) panels used in LCD monitors and LCD TVs. All three devices include a high-performance AVDD linear regulator, a positive charge-pump regulator, a negative charge-pump regulator, and built-in power-up sequence control. The MAX8710 and MAX8711 also include a high-current operational amplifier. Additionally, the MAX8710 provides logic-controlled high-voltage switches to control the positive charge-pump output. The linear regulator directly steps down the input voltage to generate the supply voltage for the source-driver ICs (AVDD). The two built-in charge-pump regulators are used to generate the TFT gate-on and gate-off supplies. The high-current operational amplifier is typically used to drive the LCD backplane (VCOM) and features high output current (150mA), fast slew rate (12V/s), and wide bandwidth (12MHz). Its Rail-to-Rail(R) inputs and output maximize flexibility. The MAX8710 is available in a 24-pin thin QFN package, the MAX8711 is available in a 16-pin thin QFN package, and the MAX8712 is available in a 12-pin thin QFN package. All three packages are 4mm x 4mm with a maximum thickness of 0.8mm for ultra-thin LCD panel design. They operate over the -40C to +100C temperature range. Applications Features High-Performance Linear Regulator 1.6% Output Accuracy Works with Small Ceramic Output Capacitors Fast Transient Response Foldback Current Limit 50mA Negative Regulated Charge Pump 20mA Positive Regulated Charge Pump with Adjustable Delay Built-In Power-Up Sequence High-Current Operational Amplifier (MAX8710/MAX8711) 150mA Output Short-Circuit Current 12V/s Slew Rate 12MHz, -3dB Bandwidth Rail-to-Rail Inputs/Output Dual-ModeTM High-Voltage Switches (MAX8710) Thermal Protection Latched Fault Protection with Timer Ordering Information PART TEMP RANGE MAX8710ETG -40C to +100C 24 Thin QFN 4mm x 4mm MAX8711ETE -40C to +100C 16 Thin QFN 4mm x 4mm MAX8712ETC -40C to +100C 12 Thin QFN 4mm x 4mm LCD Monitor Panel Modules LCD TV Panel Modules Minimum Operating Circuit IN CTL FBL MODE DLP FBN Pin Configurations SRC PIN-PACKAGE IN REF GND INL REF OUTL AVDD 19 20 21 22 24 23 FBL TOP VIEW FBN MAX8710 VIN GON 1 18 SHDN DRN 2 17 FBP 16 THR 15 SUPB VGOFF REF 3 POSB 4 INL 5 14 OUTB NEGB 6 13 GND SHDN DRVN DRVP DLP POSB AVDD MAX8710 SUPCP AVDD VCOM VP SUPB FBP OUTB NEGB SRC MODE 12 11 9 10 8 7 GON N.C. DRVP DRVN SUPCP IN OUTL CTL CTL DRN VGON REF THR THIN QFN 4mm x 4mm Pin Configurations continued at end of data sheet. Rail-to-Rail is a registered trademark of Motorola, Ltd. Dual Mode is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX8710/MAX8711/MAX8712 General Description MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies ABSOLUTE MAXIMUM RATINGS CTL, FBL, FBP, FBN, SHDN, REF, THR to GND ......-0.3V to +6V MODE, DLP to GND ....................................-0.3V to VREF + 0.3V IN, INL, OUTL (MAX8710) to GND .........................-0.3V to +28V SUPCP, SUPB , OUTL (MAX8711, MAX8712) to GND................................................................-0.3V to +14V POSB, OUTB, NEGB to GND ....................-0.3V to VSUPB + 0.3V DRVN, DRVP to GND ..............................-0.3V to VSUPCP + 0.3V SRC to GND ...........................................................-0.3V to +30V GON, DRN to GND......................................-0.3V to VSRC + 0.3V DRN to GON............................................................-30V to +30V OUTB Maximum Continuous Output Current....................75mA DRVP RMS Output Current .................................................90mA DRVN RMS Output Current..............................................-150mA Continuous Power Dissipation (TA = +70C) 24-, 16-, and 12-Pin Thin QFN 4mm x 4mm (derate 16.9mW/C above +70C) .............................1349mW Operating Temperature Range .........................-40C to +100C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.) PARAMETER CONDITIONS IN Operating Supply Range IN Quiescent Current TYP MAX UNITS 28 V 0.2 0.4 8 SHDN = GND SHDN = 3.3V Duration to Trigger Fault Condition 216 oscillator clock cycles REF Output Voltage -10A < IREF < 1mA (excluding internal load) SUPCP Input Supply Range 2.5 44 4.9 5.0 2.7 Charge-Pump Regulators Operating Frequency Thermal Shutdown MIN 1275 Rising temperature, 15C hysteresis 1500 mA ms 5.1 V 13.2 V 1725 kHz C +160 LINEAR REGULATOR INL Operation Supply Range VOUTL < VINL Dropout Voltage IOUTL = 50mA FBL Regulation Voltage IOUTL = 50mA FBL Input Bias Current VFBL = 2.5V FBL Fault Trip Level Falling edge FBL Line-Regulation Error VINL = VIN = 10.8V~13.2V, VOUTL = 10V, IOUTL = 50mA 7 28 V 150 300 mV 2.46 2.50 2.54 V 50 nA 1.92 2.00 2.08 V 15 VINL = VIN = 10V~28V, VOUTL = 9V, IOUTL = 50mA mV 10 Bandwidth Guaranteed by design 1000 Maximum OUTL Current VFBL = 2.4V 300 OUTL Soft-Start Period 212 oscillator clock cycles in a 7-bit DAC OUTL Load Regulation VIN = 12V, 5mA < IOUTL < 300mA kHz mA 3 ms 2 % OPERATIONAL AMPLIFIER SUPB Supply Operating Range SUPB Supply Current 4.5 Buffer configuration, VPOSB = 4V, no load Input Offset Voltage (VNEGB, VPOSB) = VSUPB / 2, TA = +25C Input Bias Current (VNEGB, VPOSB) = VSUPB / 2 2 13.2 V 1.0 mA 0 12 mV +1 +50 nA 0.7 -50 _______________________________________________________________________________________ Low-Cost Linear-Regulator LCD Panel Power Supplies (Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.) PARAMETER CONDITIONS MIN Common-Mode Input Range VNEGB, VPOSB 0 Common-Mode Rejection Ratio 0 (VNEGB, VPOSB) < VSUPB 50 Open-Loop Gain TYP MAX VSUPB Short-Circuit Current V 90 dB 125 dB IOUTB = 100A VSUPB 15 VSUPB -2 IOUTB = 5mA VSUPB 150 VSUPB - 80 Output Voltage Swing High Output Voltage Swing Low UNITS mV IOUTB = -100A 2 15 IOUTB = -5mA 80 150 Short to VSUPB / 2, sourcing 50 150 Short to VSUPB / 2, sinking 50 140 Output Current Buffer configuration, VPOSB = 4V, VOUTB error < 10mV Power-Supply Rejection Ratio 6V VSUPB 13.2V, DC (VNEGB, VPOSB) = VSUPB / 2 mA 40 60 Slew Rate mV mA 100 dB 12 V/s -3dB Bandwidth Buffer configuration, RL = 10k, CL = 10pF 12 MHz Gain-Bandwidth Product Buffer configuration, RL = 10k, CL = 10pF 8 MHz POSITIVE CHARGE-PUMP REGULATOR FBP Regulation Voltage IGON = 10mA FBP Line-Regulation Error VOUTL (VSUPCP, MAX8710) = 10.8V~13.2V, VGON = 27V, IGON = 20mA FBP Input Bias Current VFBP = 2.5V 2.425 2.575 V 25 mV +50 nA 15 30 6 12 -50 DRVP P-Channel On-Resistance DRVP N-Channel On-Resistance 2.500 VFBP = 2.4V VFBP = 2.6V 20 FBP Fault Trip Level Falling edge 1.92 Positive Charge-Pump Soft-Start Period 212 oscillator clock cycles in a 7-bit DAC k 2.00 2.08 2.73 V ms NEGATIVE CHARGE-PUMP REGULATOR FBN Regulation Voltage IGOFF = 10mA 200 FBN Input Bias Current VFBN = 250mV -50 FBN Line Regulation VOUTL (VSUPCP, MAX8710) = 10.8V~13.2V, VVGOFF = -6V, IGOFF = -50mA DRVN P-Channel On-Resistance DRVN N-Channel On-Resistance VFBN = 350mV VFBN = 150mV 250 300 mV +50 nA 25 mV 7.5 15 3 6 20 k FBN Fault Trip Level Rising edge 700 mV Negative Charge-Pump Soft-Start Period 212 oscillator clock cycles in a 7-bit DAC 2.73 ms _______________________________________________________________________________________ 3 MAX8710/MAX8711/MAX8712 ELECTRICAL CHARACTERISTICS (continued) MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS 0.6 V 1 A A SEQUENCE CONTROL SHDN Input Low Voltage SHDN Input High Voltage 2.0 V SHDN Input Current DLP Capacitor Charge Current During startup, VDLP = 1.0V DLP Turn-On Threshold 4 5 6 2.375 2.5 2.625 SHDN = low or fault tripped; DLP, FBP, FBN to GND Pin Discharge Switch On-Resistance SHDN = low or fault tripped; MODE, OUTL, GON, OUTB to GND V 10 1 k POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES CTL Input Low Voltage CTL Input High Voltage 2.0 CTL Input Leakage Current -1 0.6 V +1 A V CTL to GON Rising Propagation Delay VMODE = VREF, 1.5nF from GON to GND, VCTL = 0V to 3V step, no load on GON, measured from VCTL = 1.5V to GON = 20% 100 ns CTL to GON Falling Propagation Delay VMODE = VREF, 1.5nF from GON to GND, VCTL = 3V to 0V step, DRN falling, no load on DRN and GON, measured from VCTL = 1.5V to GON = 80% 100 ns SRC Input Voltage Range 28 V SRC Input Current DRN Input Current VMODE = VREF, VDLP = 3V, CTL = high 150 250 A VMODE = VREF, VDRN = 8V, VDLP = 3V, VCTL = 0V 26 40 A SRC Switch On-Resistance VMODE = VREF, VDLP = 3V, CTL = high 15 30 DRN Switch On-Resistance VMODE = VREF, VDLP = 3V, VCTL = 0V 30 1 k MODE Switch On-Resistance Mode 2 MODE Capacitor Charge Current VMODE < MODE current-source stop voltage threshold MODE Voltage Threshold for Enabling DRN Switch Control in Mode 2 MODE Current-Source Stop Voltage Threshold THR to GON Voltage Gain GON Falling Slew Rate 4 VMODE rising edge 42 50 64 A 2.3 2.5 2.7 V 3.3 3.5 3.7 V 9.4 10 10.6 V/V 13.5 _______________________________________________________________________________________ V/s Low-Cost Linear-Regulator LCD Panel Power Supplies (Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = -40C to +100C, unless otherwise noted.) (Note 1) PARAMETER REF Output Voltage CONDITIONS -10A < IREF < 1mA (excluding internal load) SUPCP Input Supply Range Charge-Pump Regulators Operating Frequency MIN MAX UNITS 4.9 TYP 5.1 V 2.7 13.2 V 1200 1850 kHz LINEAR REGULATOR Dropout Voltage IOUTL = 50mA 300 mV FBL Regulation Voltage IOUTL = 50mA 2.455 2.545 V FBL Fault Trip Level Falling edge 1.96 2.04 V FBL Line-Regulation Error VINL = VIN = 10.8V~13.2V, VOUTL = 10V, IOUTL = 50mA 15 mV Maximum OUTL Current VFBL = 2.4V OUTL Load Regulation VIN = 12V, 5mA < IOUTL < 300mA 300 mA 2 % OPERATIONAL AMPLIFIER SUPB Supply Current Buffer configuration, VPOSB = 4V, no load 1.0 mA Input Offset Voltage (VNEGB, VPOSB) = VSUPB / 2 14 mV IOUTB = 100A VSUPB 15 IOUTB = 5mA VSUPB 150 Output Voltage Swing High Output Voltage Swing Low Short-Circuit Current mV IOUTB = -100A 15 IOUTB = -5mA 150 Short to VSUPB / 2, sourcing 50 Short to VSUPB / 2, sinking 50 mV mA POSITIVE CHARGE-PUMP REGULATOR FBP Regulation Voltage IGON = 10mA FBP Line-Regulation Error VOUTL (VSUPCP, MAX8710) = 10.8V~13.2V, VGON = 27V, IGON = 20mA FBP Input Bias Current VFBP = 3V 2.425 -50 DRVP P-Channel On-Resistance DRVP N-Channel On-Resistance VFBP = 2.4V VFBP = 2.6V 2.575 V 25 mV +50 nA 30 12 20 k NEGATIVE CHARGE-PUMP REGULATOR FBN Regulation Voltage IGOFF = 10mA FBN Line Regulation VOUTL (VSUPCP, MAX8710) = 10.8V~13.2V, VGOFF = -6V, IGOFF = -50mA 200 DRVN P-Channel On-Resistance DRVN N-Channel On-Resistance VFBN = 350mV VFBN = 150mV 20 300 mV 25 mV 15 6 k _______________________________________________________________________________________ 5 MAX8710/MAX8711/MAX8712 ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = -40C to +100C, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 0.6 V 4 6 A 2.375 2.625 V SEQUENCE CONTROL SHDN Input Low Voltage SHDN Input High Voltage 2.0 DLP Capacitor Charge Current During startup, VDLP = 1.0V DLP Turn-On Threshold V POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES SRC Input Current VMODE = VREF, VDLP = 3V, CTL = high 250 A DRN Input Current VMODE = VREF, VDRN = 8V, VDLP = 3V, VCTL = 0V 40 A SRC Switch On-Resistance VMODE=VREF, VDLP = 3V, CTL = high 30 Mode 2 MODE Capacitor Charge Current VMODE < MODE current-source stop voltage threshold 42 64 A 2.3 2.7 V MODE Voltage Threshold for Enabling DRN Switch Control in Mode 2 Note 1: Specifications to -40C and +100C are guaranteed by design, not production tested. Typical Operating Characteristics (Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 10V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.) LINEAR-REGULATOR LINE REGULATION IOUTL = 300mA -2 -3 -4 0 10V A -0.5 VOUTL = 10V VINL = 12V -1.0 B 0mA VOUTL = 10V -1.5 -5 10 12 14 16 18 20 22 INPUT VOLTAGE (V) 6 MAX8710/11/12 toc02 IOUTL = 50mA -1 MAX8710/11/12 toc03 0.5 OUTPUT VOLTAGE ERROR (%) 0 LINEAR-REGULATOR LOAD-TRANSIENT RESPONSE LINEAR-REGULATOR LOAD REGULATION MAX8710/11/12 toc01 1 OUTPUT VOLTAGE ERROR (%) MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies 24 26 28 1 10 100 LOAD CURRENT (mA) 1000 20s/div A: VOUTL, 50mV/div, AC-COUPLED B: IOUTL, 200mA/div _______________________________________________________________________________________ Low-Cost Linear-Regulator LCD Panel Power Supplies CHARGE-PUMP NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE LINEAR-REGULATOR OVERCURRENT PROTECTION MAX8710/11/12 toc04 MAX8710/11/12 toc05 2.0 MAX8710/11/12 toc06 LINEAR-REGULATOR PULSED LOAD-TRANSIENT RESPONSE A A 0V B SUPPLY CURRENT (mA) 1.9 10V 1.8 1.7 1.6 B 0mA 0mA POSITIVE CHARGE-PUMP LOAD REGULATION -1.0 -1.5 11 12 13 14 MAX8710/11/12 toc08 0 -0.2 -0.4 -0.6 0.25 OUTPUT VOLTAGE ERROR (%) -0.5 10 NEGATIVE CHARGE-PUMP LOAD REGULATION 0.2 OUTPUT VOLTAGE ERROR (%) 0 VGOFF = -5V INPUT = 12V 0 -0.25 -0.50 -0.75 -1.00 -0.8 INPUT = 12V 20mA LOAD CURRENT -2.0 -1.25 -1.0 10 9 SUPPLY VOLTAGE (V) POSITIVE CHARGE-PUMP LINE REGULATION MAX8710/11/12 toc07 OUTPUT VOLTAGE ERROR (%) 0.5 20 30 50 40 LOAD CURRENT (mA) 10 11 12 13 14 0 20 40 60 POWER-UP SEQUENCE MAX8710/11/12 toc10 0 MAX8710/11/12 toc12 A 0V -0.2 100 SWITCH CONTROL FUNCTION (MODE 1) MAX8710/11/12 toc11 0.2 80 LOAD CURRENT (mA) INPUT VOLTAGE (V) NEGATIVE CHARGE-PUMP LINE REGULATION OUTPUT VOLTAGE ERROR (%) 8 A: VOUTL, 5V/div B: IOUTL, 500mA/div A: VOUTL, 100mV/div, AC-COUPLED B: IOUTL, 500mA/div 0 1.5 10ms/div MAX8710/11/12 toc09 4s/div A 0V B -0.4 0V -0.6 B 0V CGON = 1.5nF -0.8 C VGOFF = -5V IGOFF = 50mA 7 8 9 10 11 12 INPUT VOLTAGE (V) 13 C 0V 0V -1.0 10ms/div 14 A: VOUTL, 10V/div B: VGOFF, 5V/div C: VGON, 10V/div 20s/div A: VGON, 10V/div B: VMODE, 5V/div C: VCTL, 5V/div _______________________________________________________________________________________ 7 MAX8710/MAX8711/MAX8712 Typical Operating Characteristics (continued) (Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 10V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 10V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.) REFERENCE LOAD REGULATION REFERENCE vs. TEMPERATURE A 0V CGON = 1.5nF B 0V MAX8710/11/12 toc14 REF VOLTAGE ERROR (%) 0 -0.02 -0.04 -0.06 -0.08 C 0V -0.10 0 -0.2 -0.4 -0.6 0 20s/div 0.2 MAX8710/11/12 toc15 MAX8710/11/12 toc13 REF VOLTAGE ERROR (%) SWITCH CONTROL FUNCTION (MODE 2) 0.2 0.4 0.6 1.0 0.8 -40 -20 REF LOAD CURRENT (mA) A: VGON, 10V/div B: VMODE, 5V/div C: VCTL, 5V/div 0 20 MAX8710/11/12 toc16 0.8 60 MAX8710/11/12 toc18 A A 0V 0V 0.6 0.4 B B 0V 0.2 0V BUFFER CONFIGURATION VOUTB = 0.5 x VPOSB 0 4 6 8 10 12 400ns/div 14 A: VPOSB, 50mV/div, AC-COUPLED B: VOUTB, 50mV/div, AC-COUPLED SUPB VOLTAGE (V) OPERATIONAL-AMPLIFIER LOAD-TRANSIENT RESPONSE (BUFFER CONFIGURATION) 400ns/div A: VPOSB, 5V/div B: VOUTB, 5V/div OPERATIONAL-AMPLIFIER RAIL-TO-RAIL I/O MAX8710/11/12 toc19 MAX8710/11/12 toc20 A A 5V 0V B 0V B 0mA 1s/div A: VOUTB, 2V/div B: IOUTB, 50mA/div 8 100 80 OPERATIONAL-AMPLIFIER LARGE-SIGNAL STEP RESPONSE (BUFFER CONFIGURATION) MAX8710/11/12 toc17 1.0 40 TEMPERATURE (C) OPERATIONAL-AMPLIFIER SMALL-SIGNAL STEP RESPONSE (BUFFER CONFIGURATION) SUPB SUPPLY CURRENT vs. SUPB VOLTAGE SUPB SUPPLY CURRENT (mA) MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies 40s/div A: VPOSB, 5V/div B: VOUTB, 5V/div _______________________________________________________________________________________ Low-Cost Linear-Regulator LCD Panel Power Supplies NAME PIN FUNCTION MAX8710 MAX8711 MAX8712 GON 1 -- -- Internal High-Voltage MOSFET Switch Common Terminal. GON is the output of the high-voltage switch-control block. GON is internally pulled to GND by a 1k resistor in shutdown. DRN 2 -- -- Switch Input. Drain of the internal high-voltage back-to-back P-channel MOSFETs connected to GON. REF 3 1 1 Reference Output. Connect a 0.22F capacitor from REF to GND. REF remains on in shutdown. POSB 4 2 -- Operational-Amplifier Noninverting Input INL 5 3 2 Linear-Regulator Supply Input NEGB 6 4 -- Operational-Amplifier Inverting Input IN 7 5 3 IC Supply Input. Bypass IN to GND with a 0.1F capacitor. OUTL 8 6 4 Linear-Regulator Output. OUTL is internally pulled to GND by a 1k resistor in shutdown. For the MAX8711/MAX8712, OUTL is also the supply input for the charge-pump regulators. SUPCP 9 -- -- Supply Input for the Charge-Pump Regulators. Connect a 0.1F capacitor from SUPCP to GND. DRVN 10 7 5 Negative Charge-Pump Driver Output. Output high level is VSUPCP, and output low level is GND. DRVN is internally pulled high to SUPCP when the negative charge pump is disabled. DRVP 11 8 6 Positive Charge-Pump Driver Output. Output high level is VSUPCP, and output low level is GND. DRVP is internally pulled low in shutdown. N. C. 12 -- -- No Connect. Not internally connected. GND 13 9 7 Ground OUTB 14 10 -- Operational-Amplifier Output. OUTB is internally pulled to GND by a 1k resistor in shutdown. SUPB 15 11 -- Operational-Amplifier Supply Input. Bypass SUPB to GND with a 0.1F capacitor. THR 16 -- -- GON Low-Level Regulation Set-Point Input. Connect THR to the center of a resistive voltage-divider between REF and GND to set the VGON regulation level. The actual level is 10 x VTHR. See the Switch Control section for details. _______________________________________________________________________________________ 9 MAX8710/MAX8711/MAX8712 Pin Description MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies Pin Description (continued) NAME PIN MAX8710 MAX8711 FUNCTION MAX8712 FBP 17 12 8 Positive Charge-Pump Feedback Input. Connect FBP to the center of a resistive voltage-divider between the positive charge-pump regulator output and GND to set the regulator output voltage. Place the divider within 5mm of FBP. FBP is internally pulled to GND by a 10 resistor in shutdown. SHDN 18 13 9 Active-Low Shutdown Control Input. Pull SHDN low to turn off all sections of the device except REF. Pull SHDN high to enable the device. Cycle SHDN to reset the device after a fault. CTL 19 -- -- High-Voltage Switch-Control Block Timing Control Input. See the Switch Control section for details. FBL 20 14 10 Linear-Regulator Feedback Input. Connect FBL to the center of a resistive voltage-divider between the linear-regulator output and GND to set the linearregulator output voltage. Place the divider within 5mm of FBL. MODE 21 -- -- High-Voltage Switch-Control Block-Mode Selection Input and Timing-Adjustment Input. See the Switch Control section for details. MODE is high impedance when it is connected to REF. MODE is internally pulled to GND by a 1k resistor during REF UVLO, when VDLP < 2.5V, or in shutdown. DLP 22 15 11 Positive Charge-Pump Startup Delay and High-Voltage Switch Delay Input. Connect a capacitor from DLP to GND to set the delay time. A 5A current source charges CDLP. DLP is internally pulled to GND by a 10 resistor in shutdown. FBN 23 16 12 Negative Charge-Pump Feedback Input. Connect FBN to the center of a resistive voltage-divider between the negative output and REF to set the output voltage. Place the divider within 5mm of FBN. FBN is internally pulled to GND through a 10 resistor in shutdown. SRC 24 -- -- Switch Input. Source of the internal high-voltage P-channel MOSFET connected to GON. Typical Operating Circuit Figures 1, 2, and 3 are the Typical Operating Circuits of the MAX8710, MAX8711, and MAX8712 for generating power rails in TFT LCD panels. The input voltage range is from 10.8V to 13.2V. The AVDD output is 10V at 300mA, the V GON output is 27V at 20mA, and the VGOFF output is -5V at 50mA. Detailed Description The MAX8710/MAX8711/MAX8712 include a high-performance linear regulator, a positive charge-pump regulator, a negative charge-pump regulator, and built-in power-up sequence control. The MAX8710 and MAX8711 also include a high-current operational amplifier. Additionally, the MAX8710 provides logic-controlled high-voltage switches to control the positive chargepump output. The linear regulator directly steps down the 10 input voltage to generate the source-driver ICs' supply voltage. The two built-in charge-pump regulators are used to generate the TFT gate-on and gate-off supplies. The high-current operational amplifier is typically used to drive the LCD backplane (VCOM) and features high output current (150mA), fast slew rate (12V/s), and wide bandwidth (12MHz). Its rail-to-rail inputs and output maximize flexibility. Linear Regulator MAX8710/MAX8711/MAX8712 contain a linear regulator that uses an internal PNP pass transistor to supply load currents up to 300mA. Connect an external resistive voltage-divider between the regulator output and GND with the midpoint connected to FBL to adjust the linear-regulator output. An error amplifier compares the FBL voltage with the 2.5V internal reference voltage and amplifies the difference. If the feedback voltage is higher than the ______________________________________________________________________________________ Low-Cost Linear-Regulator LCD Panel Power Supplies MAX8710/MAX8711/MAX8712 IN 10.8V TO 13.2V GND 10F 0.1F GND IN N.C. INL OUTL C1 47pF AVDD 4.7F SUPB 0.1F AVDD 10V/300mA FBL 120k POSB R1 100k 1% R2 33.2k 1% MAX8710 IN 100k SUPCP 0.1F NEGB 0.1F OUTB OUTB DRVP 0.1F MMBD4148SE (FAIRCHILD) 0.1F 0.22F R5 110k 1% MMBD4148SE (FAIRCHILD) VP 27V/20mA FBP FBN R4 33.2k 1% R6 100k 1% 0.47F R3 325k 1% SRC REF REF 5V/1mA 0.1F DRVN 1F GOFF -5V/mA MMBD4148SE (FAIRCHILD) 1F 51.1k THR GON 20k 20k GON DRN MODE SHDN SHDN CTL DLP 0.1F 100k CTL Figure 1. Typical Operating Circuit of the MAX8710 ______________________________________________________________________________________ 11 MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies IN 10.8V TO 13.2V GND 10F 0.1F GND IN INL OUTL C1 47pF AVDD 4.7F SUPB 120k 0.1F AVDD 10V/300mA FBL POSB R1 100k 1% R2 33.2k 1% MAX8711 100k NEGB OUTB OUTB DRVP 0.22F 0.1F DRVN 1F GOFF -5V/50mA MMBD4148 0.1F MMBD4148SE (FAIRCHILD) 0.1F 2x MMBD4148SE (FAIRCHILD) R5 110k 1% 1F FBN FBP R4 33.2k 1% R6 100k 1% REF REF 5V/1mA R3 325k 1% DLP 0.1F 0.47F SHDN SHDN Figure 2. Typical Operating Circuit of the MAX8711 12 1F ______________________________________________________________________________________ GON 27V/20mA Low-Cost Linear-Regulator LCD Panel Power Supplies 10F 0.1F GND IN INL OUTL MMBD4148SE (FAIRCHILD) C1 47pF 0.22F DRVN 1F GOFF -5V/50mA FBN R6 100k 1% 4.7F AVDD 10V/300mA FBL R5 110k 1% MAX8712 0.47F R1 100k 1% R2 33.2k 1% MMBD4148 REF REF 5V/1mA MAX8710/MAX8711/MAX8712 IN 10.8V TO 13.2V GND 0.1F DRVP 0.1F 0.1F DLP 1F 2x MMBD4148SE (FAIRCHILD) 0.1F 1F SHDN SHDN GON 27V/20mA FBP R4 33.2k 1% R3 325k 1% Figure 3. Typical Operating Circuit of the MAX8712 reference voltage, the controller lowers the base current of the PNP transistor, which reduces the amount of current delivered to the output. If the feedback voltage is too low, the device increases the PNP transistor's base current, which allows more current to pass to the output and raises the output voltage. The linear regulator also includes an output current limit that protects the internal pass transistor against short circuits. The input voltage range of the linear regulator is from 8V to 28V. The Typical Operating Circuits shown use a 12V input. The output voltage range of the linear regulator (OUTL) is up to 28V (MAX8710) or up to 14V (MAX8711/MAX8712). The linear-regulator output is used to generate the AVDD voltage, which is the analog supply rail for source-driver ICs in TFT LCD panels. The typical load of the AVDD supply is a periodic pulsed load, with a peak current of approximately 1A and pulse width of approximately 2s. The period of the pulse load is between 8.9s and 31.7s. The excellent transient performance of the linear regulator can easily meet this transient-response requirement. The linear regulator can deliver at least 300mA output current continuously with a 4.7F output capacitor. Do not allow the device power dissipation to exceed the package-dissipation limit listed in the Absolute Maximum Ratings section. The power dissipation can be estimated by multiplying the voltage difference between the input and the output with the required maximum continuous output current. For applications where the power dissipation exceeds the package limit, see the External Transistor for Higher Current or Power Dissipation section for more information. The linear regulator is enabled whenever REF is in regulation and SHDN is logic high. Each time it is enabled, the ______________________________________________________________________________________ 13 MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies IN IN INL GND REF REF MAX8710 REF LINEAR REG OUTL AVDD FBL FBN VIN SUPCP OSC SHDN DRVN VGOFF DLP DRVP SEQ POSB AVDD AVDD VP SUPB FBP OUTB VCOM NEGB MODE SRC SWITCH CONTROL CTL GON REF DRN THR Figure 4. MAX8710 Functional Diagram 14 VGON CTL ______________________________________________________________________________________ Low-Cost Linear-Regulator LCD Panel Power Supplies Positive Charge-Pump Regulator The positive charge-pump regulator is typically used to generate the positive supply rail for the TFT LCD gate-driver ICs. The output voltage is set with an external resistive voltage-divider from its output to GND with the midpoint connected to FBP. The number of charge-pump stages and the setting of the feedback divider determine the output voltage of the positive charge-pump regulator. The charge pump includes a high-side P-channel MOSFET (P1) and a low-side N-channel MOSFET (N1) to control the power transfer as shown in Figure 5. The MOSFETs switch at a constant frequency of 1.5MHz. During the first half-cycle, N1 turns on and allows VINPUT (VSUPCP, MAX8710 or VOUTL, MAX8711/MAX8712) to charge up the flying capacitor CX(POS) through diode D1. The amount of charge transferred from VINPUT to CX(POS) is determined by the on-resistance of N1, which varies according to the output of the feedback error amplifier. The error amplifier compares the feedback signal (FBP) with a 2.5V internal reference and amplifies the difference. If the feedback signal is below the reference, the error-amplifier output increases the supply voltage of N1's gate driver, lowering the on-resistance. Similarly, if the feedback signal is above the reference, the erroramplifier output reduces the driver supply voltage, increasing the on-resistance. During the second halfcycle, N1 turns off and P1 turns on, level shifting CX(POS) by VINPUT volts. This connects CX(POS) in parallel with the reservoir capacitor C OUT(POS) . If the voltage across COUT(POS) plus a diode drop (VPOS + VDIODE) is smaller than the level-shifted flying-capacitor voltage REF FBN MAX8710 SUPCP VSUPCP D4 P2 VNEG DRVN D1 P1 0.5 x VREF VSUPCP DRVP COUT(NEG) CX(NEG) D3 N2 250mV CX(POS) N1 D2 VPOS COUT(POS) OSCILLATOR FBP SEQUENCE Figure 5. Charge-Pump Regulator Functional Diagram ______________________________________________________________________________________ 15 MAX8710/MAX8711/MAX8712 linear regulator goes through a soft-start routine by ramping up its internal reference voltage from 0 to 2.5V in 128 steps. The soft-start period is 2.73ms (typ), and FBL fault detection is disabled during this period. This soft-start feature effectively limits the inrush current during startup. The linear-regulator current-limit circuitry monitors the current flowing through the internal pass transistor. The internal current limit is approximately 800mA. The linearregulator output declines when it is not able to supply the load current. If the FBL voltage drops below 0.75V, the current limit folds back to approximately 100mA. The MAX8710/MAX8711/MAX8712 monitor the FBL voltage for undervoltage conditions. If VFBL is continuously below 2V (typ) for approximately 44ms, the device latches off. The foldback current-limit circuit, in conjunction with the output undervoltage fault latch and thermal-overload protection, protects the output load and the internal pass transistor against short circuits or overloads. MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies (V CX(POS) + V INPUT ), charge flows from CX(POS) to COUT(POS) until diode D2 turns off. The positive charge-pump regulator's startup can be delayed by connecting an external capacitor from DLP to GND. An internal constant current source begins charging the DLP capacitor when SHDN is logic high and REF reaches regulation. When the DLP voltage exceeds VREF / 2, the positive charge-pump regulator is enabled. Each time it is enabled, the positive chargepump regulator goes through a soft-start routine by ramping up its internal reference voltage from 0 to 2.5V in 128 steps. The soft-start period is 2.73ms (typ), and FBP fault detection is disabled during this period. The soft-start feature effectively limits the inrush current during startup. The MAX8710/MAX8711/MAX8712 also monitor the FBP voltage for undervoltage conditions. If VFBP is continuously below 2V (typ) for approximately 44ms, the device latches off. Negative Charge-Pump Regulator The negative charge-pump regulator is typically used to generate the negative supply rail for the TFT LCD gatedriver ICs. The output voltage is set with an external resistive voltage-divider from its output to REF with the midpoint connected to FBN. The number of charge-pump stages and the setting of the feedback divider determine the output of the negative charge-pump regulator. The charge-pump controller includes a high-side P-channel MOSFET (P2) and a low-side N-channel MOSFET (N2) to control the power transfer as shown in Figure 5. The MOSFETs switch a constant frequency of 1.5MHz. During the first half-cycle, P2 turns on and allows V INPUT to charge up the flying capacitor C X(NEG) through diode D3. During the second half-cycle, P2 turns off and N2 turns on, level shifting CX(NEG) by VINPUT volts. This connects CX(NEG) in parallel with reservoir capacitor C OUT(NEG) . If the voltage across COUT(NEG) minus a diode drop is greater than the voltage across CX(NEG), charge flows from COUT(NEG) to CX(NEG) until the diode D4 turns off. The amount of charge transferred to the output is controlled by the onresistance of N2, which varies according to the output of the feedback error amplifier. The error amplifier compares the feedback signal (FBN) with a 250mV internal reference and amplifies the difference. If the feedback signal is above the reference, the error-amplifier output increases the supply voltage of N2's gate driver, lowering the on-resistance. Similarly, if the feedback signal is below the reference, the error-amplifier output reduces the driver supply voltage, increasing the on-resistance. time it is enabled, the negative charge-pump regulator goes through a soft-start routine by ramping down its internal reference voltage from 5V to 250mV in 128 steps. The soft-start period is 2.73ms (typ), and FBN fault detection is disabled during this period. The softstart feature effectively limits the inrush current during startup. The MAX8710/MAX8711/MAX8712 also monitor the FBN voltage for undervoltage conditions. If VFBN is continuously above 700mV (typ) for approximately 44ms, the device latches off. Operational Amplifier (MAX8710/MAX8711) The MAX8710/MAX8711s' operational amplifier features high output current (150mA), fast slew rate (7.5V/s), and wide bandwidth (12MHz). The operational amplifier is enabled when REF is in regulation and SHDN is logic high. The output of the amplifier (OUTB) is internally pulled to ground through a 1k resistor in shutdown. The amplifier is typically used to drive the backplane (VCOM) of TFT LCD panels. The LCD backplane consists of a distributed series capacitance and resistance, a load that can be easily driven by this operational amplifier. However, if the operational amplifier is used in an application with a pure capacitive load, steps must be taken to ensure stable operation. As the operational amplifier's capacitive load increases, the amplifier's bandwidth decreases and its gain peaking increases. To ensure stable operation, a 5 to 50 resistor can be placed between OUTB and the capacitive load to reduce gain peaking. The operational amplifier limits short-circuit current to approximately 150mA if the output is directly shorted to SUPB or to GND. If the short-circuit condition persists, the junction temperature of the IC rises until it trips the IC's thermal-overload protection. Reference Voltage (REF) The reference output is nominally 5V and can source up to 1mA (see the Typical Operating Characteristics). Bypass REF with a 0.22F ceramic capacitor connected between REF and GND. The reference remains enabled in shutdown. Power-Up Sequence and Shutdown Control When the MAX8710/MAX8711/MAX8712 are powered up, REF rises with the voltage on IN. After REF reaches regulation and if SHDN is logic high, the linear regulator, operational amplifier, and negative charge-pump regulator are enabled and begin their respective softstart routines. After the soft-start routines are complet- The negative charge-pump regulator is enabled when SHDN is logic high and REF reaches regulation. Each 16 ______________________________________________________________________________________ Low-Cost Linear-Regulator LCD Panel Power Supplies Thermal-Overload Protection The thermal-overload protection prevents excessive power dissipation from overheating the IC. When the junction temperature exceeds +160C, a thermal sensor immediately activates the fault protection, which shuts down all the outputs except the reference, allowing the device to cool down. Once the device cools down by approximately 15C, the IC restarts automatically. Switch Control (MAX8710) Output Fault Protection The MAX8710's switch-control block (Figure 6) consists of a high-voltage P-channel MOSFET Q1 between SRC and GON, and a common-source-connected P-channel MOSFET pair Q2 between GON and DRN. The switchcontrol block is enabled when VDLP goes above VREF / 2. Q1 and Q2 are controlled by CTL and MODE. There are two different modes of operation. Activate the first mode by connecting MODE to REF. When CTL is logic high, Q1 turns on and Q2 turns off, connecting GON to SRC. When CTL is logic low, Q1 turns off and Q2 turns on, connecting GON to DRN. GON can then be discharged through a resistor connected between DRN and GND or OUTL. Q2 turns off and stops discharging GON when VGON reaches 10 times the voltage on THR. During steady-state operation, if the output of the linear regulator or any of the charge-pump regulator outputs does not exceed its respective fault-detection threshold, the MAX8710/MAX8711/MAX8712 activate an internal fault timer. If any condition or the combination of conditions indicates a continuous fault for the faulttimer duration (44ms typ), the MAX8710/MAX8711/ MAX8712 set the fault latch, shutting down all the outputs except the reference. Once the fault condition is removed, cycle the input voltage or toggle SHDN to clear the fault latch and reactivate the device. Each regulator's fault-detection circuit is disabled during the regulator's soft-start time. When VMODE is less than 0.9 x VREF, the switch-control block works in the second mode. The rising edge of VCTL turns on Q1 and turns off Q2, connecting GON to SRC. An internal N-channel MOSFET Q5 between MODE and GND is also turned on to discharge an external capacitor between MODE and GND. The falling edge of VCTL turns off Q5, and an internal 50A current source starts charging the MODE capacitor. Once VMODE exceeds 0.5 x VREF, the switch-control block turns off Q1 and turns on Q2, connecting GON to DRN. GON can then be discharged through a resistor connected between DRN and GND or OUTL. Q2 turns off and stops discharging GON when VGON reaches 10 times the voltage on THR. ______________________________________________________________________________________ 17 MAX8710/MAX8711/MAX8712 ed, the fault-protection circuits for the linear regulator and the negative charge-pump regulator are activated. When the linear regulator is enabled, the positive charge-pump-regulator delay block is enabled. An internal current source starts charging the DLP capacitor. The voltage on DLP linearly rises because of the constant charging current. When V DLP goes above VREF / 2, the switch control block is enabled, and the positive charge-pump regulator begins its soft-start. After the positive charge-pump regulator's soft-start is completed, the fault protection of the positive chargepump regulator is also enabled. The MAX8710/MAX8711/MAX8712 enter into shutdown when SHDN is pulled low or REF falls below 4.5V. In shutdown, OUTL, GON and OUTB are all internally pulled to ground with 1k resistors. FBN, FBP, and DLP are all internally pulled to ground with 10 resistors in shutdown. The DLP current source is disabled in shutdown and a switch discharges CDLP to ground. REF remains on in shutdown. Pulling SHDN high when REF is above 4.5V reactivates the IC. Output fault protection and thermal-overload protection can also turn off the IC's outputs. See the respective sections for details. MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies REF MAX8710 5A DLP Q4 FAULT SHDN REF OK SRC 0.5 x VREF Q1 GON 9R 1k Q3 R Q2 REF 50A R 4R MODE 1k 5R Q5 CTL Figure 6. MAX8710 High-Voltage Switch Control 18 ______________________________________________________________________________________ DRN THR Low-Cost Linear-Regulator LCD Panel Power Supplies Linear Regulator Output-Voltage Selection Adjust the linear-regulator output voltage by connecting a resistive voltage-divider from the linear-regulator output AVDD to GND with the center tap connected to FBL (Figure 1). Select the lower resistor of the divider R2 in the range of 10k to 50k. Calculate the upper resistor R1 with the following equation: V R1 = R2 x AVDD - 1 VFBL where VFBL = 2.5V (typ) is the regulation point of the linear regulator. Input-Capacitor Selection The linear regulator's output stage consists of a PNP pass transistor. Rapid movements of the input voltage must be avoided since the movement can be coupled into the base of the transistor through the base-to-emitter junction capacitance. The input capacitor reduces the current peaks drawn from the input supply and slows down the input voltage movement. One 10F ceramic capacitor is used in the Typical Operating Circuits (Figure 1, 2, and 3) because of the high source impedance seen in typical lab setups. Actual applications usually have much lower source impedance, since the linear regulator typically runs directly from the output of another regulated supply and can operate with less input capacitance. Output-Capacitor Selection The output capacitor and its equivalent series resistance (ESR) affect the linear regulator's stability and transient response. The regulator can deliver at least 300mA output current continuously with a 4.7F output capacitor. The typical load on the linear regulator for source-driver applications is a large pulsed load, with a peak current of approximately 1A and pulse width of approximately 2s. The shape of the pulse is close to a triangle, so it is equivalent to a square pulse with 1A height and 1s pulse width. The total voltage dip during the pulsed load transient also has two components: the ohmic dip due to the output capacitor's ESR, and the capacitive dip caused by discharging the output capacitance: VDIP = VDIP(ESR) + VDIP(C) VDIP(ESR) = IPULSE x RESR I x tPULSE VDIP(C) PULSE COUT where IPULSE is the height of the pulse load, and tPULSE is the pulse width. Higher capacitance and lower ESR result in less voltage dip. The ESR dip can be ignored when using ceramic output capacitors. Calculate the minimum required capacitance for the maximum allowed dip using: I x tPULSE COUT(MIN) PULSE VDIP(MAX) The above equations are "worst-case" and assume that the linear regulator does not react to correct the output voltage during the load pulse. In fact, the regulator is fast enough to partially correct the output voltage, so the actual dip may be smaller, or a smaller capacitor may be acceptable. For the typical load pulse described above, assuming the voltage dip must be limited to 150mV, the minimum output capacitor is: COUT(MIN) 1A x 1s = 6.7F 0.15V Because the regulator is able to limit the dip somewhat, the circuit of Figure 1 uses a 4.7F output capacitor. The voltage rating and temperature characteristics of the output capacitor must also be considered. Feed-Forward Compensation The output capacitance and equivalent load resistance determine the dominant pole. An internal parasitic capacitance of the regulator creates a second pole. This pole typically occurs at 100kHz, but can vary between 60kHz and 140kHz depending on the process variation. Since the pole occurs after the loop gain crossover, it does not affect the loop stability. However, canceling this pole with an additional zero can improve the load-transient response. A zero can be added by connecting a feed-forward capacitor (C1) between OUTL and FBL as shown in Figure 1. The frequency of the zero can be calculated with the following equation: fZERO = 1 2 x R1 x C1 where R1 is the upper resistor of the feedback divider. To cancel the second pole, the zero should be placed at or below the frequency of the second pole. Because the frequency of the second pole varies between 60kHz and 140kHz, the zero can be placed between 40kHz and 60kHz. ______________________________________________________________________________________ 19 MAX8710/MAX8711/MAX8712 Design Procedure MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies Charge-Pump Regulators Number of Charge-Pump Stages For highest efficiency, always choose the lowest number of charge-pump stages that meets the output requirement. The number of positive charge-pump stages is given by: nPOS = VP + VSWITCH VINPUT - VSUPCP 2 x VDIODE - where nPOS is the number of positive charge-pump stages, VP is the positive charge-pump regulator output, VINPUT is the supply voltage for the charge-pump regulators (V SUPCP, MAX8710 or V OUTL, MAX8711/ MAX8712), VDIODE is the forward-voltage drop of the charge-pump diode, and VSWITCH is the voltage drop of the internal switches. Use VSWITCH = 0.3V. The number of negative charge-pump stages is given by: nNEG = - VGOFF VINPUT + VSWITCH - 2 x VDIODE Output Voltage Selection Adjust the positive charge-pump-regulator output voltage by connecting a resistive voltage-divider from the regulator output VP to GND with the center tap connected to FBP (Figure 1). Select the lower resistor of divider R4 in the range of 10k to 50k. Calculate upper resistor R3 with the following equation: V R3 = R4 x P - 1 V FBP where VFBP = 2.5V (typ) is the regulation point of the positive charge-pump regulator. Adjust the negative charge-pump-regulator output voltage by connecting a resistive voltage-divider from the negative charge-pump output VGOFF to REF with the center tap connected to FBN (Figure 1). Select R6 in the 20k to 100k range. Calculate R5 with the following equation: R5 = R6 x VFBN - VGOFF VREF - VFBN where nNEG is the number of negative charge-pump stages and VGOFF is the negative charge-pump regulator output. where VREF = 5V and VFBN = 250mV is the regulation point of the negative charge-pump regulator. The above equations are derived based on the assumption that the first stage of the positive charge pump is connected to VMAIN and the first stage of the negative charge pump is connected to ground. Sometimes fractional stages are more desirable for better efficiency. This can be done by connecting the first stage to another available supply, such as a 5V supply. If the first charge-pump stage is powered from 5V, then the above equations become: Flying Capacitor Increasing the flying-capacitor (CX) value lowers the effective source impedance and increases the outputcurrent capability of the charge pump. Increasing the capacitance indefinitely has a negligible effect on output-current capability because the internal switch resistance and the diode impedance place a lower limit on the source impedance. A 0.1F ceramic capacitor works well in most low-current applications. The flying capacitor's voltage rating must exceed the following: VCX > n x VINPUT where n is the stage number in which the flying capacitor is used, and VINPUT is the supply voltage for the charge-pump regulators (VSUPCP, MAX8710 or VOUTL, MAX8711/MAX8712). nPOS = nNEG = VP + VSWITCH - 5V VINPUT - 2 x VDIODE - VGOFF + VSWITCH + 5V VINPUT - 2 x VDIODE Charge-Pump Input Capacitor Use an input capacitor with a value equal to or greater than the flying capacitor. Place the capacitor as close to the IC as possible. Connect the capacitor directly to PGND. 20 ______________________________________________________________________________________ Low-Cost Linear-Regulator LCD Panel Power Supplies COUT _ CP MAX8710/MAX8711/MAX8712 Charge-Pump Output Capacitor Increasing the output capacitance or decreasing the ESR reduces the output ripple voltage and the peak-topeak transient voltage. With ceramic capacitors, the output voltage ripple is dominated by the capacitance value. Use the following equation to approximate the required capacitor value: VIN = 19V 51 INL ILOAD _ CP LINEAR REGULATOR 2 fOSC VRIPPLE _ CP 4.7F KSB834W (FAIRCHILD) AVDD = 10V OUTL 140k 4.7F FBL where COUT_CP is the output capacitor of the charge pump, I LOAD_CP is the load current of the charge pump, and V RIPPLE_CP is the desired peak-to-peak value of the output ripple. Charge-Pump Rectifier Diode Use low-cost silicon switching diodes with a current rating equal to or greater than two times the average charge-pump input current. If it helps avoid an extra stage, some or all of the diodes can be replaced with Schottky diodes with an equivalent current rating. 20k MAX8710 MAX8711 MAX8712 Figure 7. High-Power Linear Regulator REF 0.47F Applications Information The load current and the voltage difference between the input and output determine the linear regulator's power dissipation as shown in the following equation: PDISSIPATION = (VINL - VOUTL) x IOUTL For some applications, the input voltage to the linear regulator is from a 19V adapter. To make a 10V output, the voltage across the pass transistor is 9V. In this case, the regulator's power dissipation may exceed the dissipation limit that the package can handle. In some other applications, the load current may be much higher than the regulator's guaranteed 300mA output current. The solution for such applications is to connect an external PNP transistor with the internal PNP transistor in a Darlington configuration as shown in Figure 7. The external pass transistor must be able to handle most of the power dissipation since most of the load current flows through it. On the other hand, the power dissipated in the internal pass transistor is very low. The currentlimit circuit will not work if an external pass transistor is used because the linear regulator only senses the current of the internal pass transistor. MAX8710 VDD External Transistor for Higher Current or Power Dissipation OUTL MAX8711 4.7F MAX1512 CE SUPB AVDD 20k POSB OUT 100k CTL 0.1F TO OUTB VCOM NEGB SET GND 25k Figure 8. Using the MAX1512 to Adjust the VCOM Buffer Output Using the MAX1512 VCOM Calibrator to Adjust the Buffer Output The operational amplifier is typically used as the VCOM buffer in TFT LCD panels. The output voltage of the VCOM buffer can be adjusted using the MAX1512, which is an EEPROM-programmable VCOM calibrator, using the circuit shown in Figure 8. Refer to the MAX1512 data sheet for details. ______________________________________________________________________________________ 21 22 POSB 2 DLP FBL SHDN 15 14 13 12 FBP 11 SUPB MAX8711 INL 3 10 OUTB NEGB 4 9 6 8 DRVN OUTL 7 DRVP 5 GND REF 1 INL 2 IN 3 DLP FBL THIN QFN 4mm x 4mm 12 11 10 MAX8712 4 5 9 SHDN 8 FBP 7 GND 6 DRVP 3) Place IN, INL, SUPB, SUPCP, and REF pin bypass capacitors close to the IC. The ground connection of the IN bypass capacitor should be connected directly to the GND pin with a wide trace. 4) Minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. 5) Minimize the size of the switching nodes (DRVP and DRVN). Keep the switching nodes away from feedback nodes (FBL, FBP, and FBN) and the analog ground. Use DC traces as a shield if necessary. Refer to the MAX8710 evaluation kit for an example of proper board layout. 1 16 DRVN 2) Place all feedback voltage-divider resistors as close to their respective feedback pins as possible. The divider's center trace should be kept short. Placing the resistors far away causes their FB traces to become antennas that can pick up noise from the switching nodes of the charge pumps. Avoid running any feedback trace near these switching nodes. REF FBN 1) Create a power ground island consisting of the linear-regulator input and output-capacitor ground connections, the GND pin, and the capacitor ground connections for the charge-pump regulators. Connect all these together with short, wide traces or a small ground plane. Maximizing the width of the power ground traces improves efficiency. Create an analog ground island consisting of all the feedback-divider ground connections, the operational-amplifier divider ground connection, the REF capacitor ground connection, the MODE capacitor ground connection, the DLP capacitor ground connection, and the device's exposed backside pad. Connect the analog ground island and the power ground island by connecting the GND pin directly to the exposed backside pad. Make no other connections between these separate ground islands. TOP VIEW IN Careful PC board layout is important for proper operation. Use the following guidelines for good PC board layout: Pin Configurations (continued) FBN PC Board Layout Guidelines OUTL MAX8710/MAX8711/MAX8712 Low-Cost Linear-Regulator LCD Panel Power Supplies THIN QFN 4mm x 4mm Chip Information TRANSISTOR COUNT: 3946 PROCESS: BiCMOS ______________________________________________________________________________________ Low-Cost Linear-Regulator LCD Panel Power Supplies 24L QFN THIN.EPS PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 B 1 2 PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 B 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX8710/MAX8711/MAX8712 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)