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1
FEATURES APPLICATIONS
DESCRIPTION
OFF ON
OFF ON
OFF ON
VBAT
LBI
SKIPEN
EN
LDOEN
SWN
VOUT
FB
PGOOD
LBO
LDOIN
LDOOUT
LDOSENSE
GND PGND
Control
Inputs
Control
Outputs
VOut1
VOut2
TPS61130
SWP
22 mH
22 mH
100 mF
e.g. 3.3 V
up to 300 mA
2.2 mF
e.g. 1.5 V
up to 300 mA
10 mF
1.8 V up to 6 V
Input 10 mF
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008www.ti.com
SYNCHRONOUS SEPIC / FLYBACK CONVERTER WITH 1.1A SWITCHAND INTEGRATED LDO
•All Single Cell Li, Dual or Triple Cell Battery or2
•Synchronous, Up To 90% Efficient, SEPIC
USB Powered Products as MP-3 Player, PDAs,Converter With 300-mA Output Current From
and Other Portable Equipment2.5-V Input
•Dual Input or Dual Output Mode•Integrated 200-mA Reverse Voltage Protected
•High Efficient Li-Ion to 3.3-V ConversionLDO for DC/DC Output Voltage PostRegulation or Second Output Voltage•40- µA (Typical) Quiescent Current
The TPS6113x devices provide a complete power•Input Voltage Range: 1.8-V to 5.5-V
supply solution for products powered by either a•Fixed and Adjustable Output Voltage Options
one-cell Li-Ion or Li-Polymer, or two- to four-cellup to 5.5-V
Alkaline, NiCd, or NiMH batteries. The devices can•Power Save Mode for Improved Efficiency at
generate two regulated output voltages. It provides asimple and efficient buck-boost solution forLow Output Power
generating 3.3 V out of an input voltage that can be•Low Battery Comparator
both higher and lower than the output voltage. The•Power Good Output
converter provides a maximum output current of at•Low EMI-Converter (Integrated Antiringing
least 300 mA with supply voltages down to 1.8 V. Theimplemented SEPIC converter is based on a fixedSwitch)
frequency, pulse-width-modulation (PWM) controller•Load Disconnect During Shutdown
using a synchronous rectifier to obtain maximum•Overtemperature Protection
efficiency. The maximum peak current in the SEPIC•Available in a Small 4mm x 4mm QFN-16 or in
switch is limited to a value of 1600 mA.a TSSOP-16 Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
Description (continued)
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
The converter can be disabled to minimize battery drain. During shutdown, the load is completely disconnectedfrom the battery. A low-EMI mode is implemented to reduce ringing, and in effect, lower radiated electromagneticenergy when the converter enters the discontinuous conduction mode. A power good output at the SEPIC stageprovides additional control of any connected circuits like cascaded power supply stages, or microprocessors.
The built-in LDO can be used for a second output voltage derived either from the SEPIC output or directly fromthe battery. The output voltage of this LDO can be programmed by an external resistor divider or is fixedinternally on the chip. The LDO can be enabled separately, i.e., using the power good of the SEPIC stage. Thedevice is packaged in a 16-pin QFN package measuring 4 mm x 4 mm (RSA) or in a 16-pin TSSOP (PW)package.
AVAILABLE OUTPUT VOLTAGE OPTIONS
(1)
OUTPUT VOLTAGET
A
OUTPUT VOLTAGE LDO PACKAGE PART NUMBER
(2)DC/DC
Adjustable Adjustable TPS61130PW3.3 V 3.3 V 16-Pin TSSOP TPS61131PW40 °C to 85 °C 3.3 V 1.5 V TPS61132PWAdjustable Adjustable TPS61130RSA16-Pin QFN3.3 V 1.5 V TPS61132RSA
(1) Contact the factory to check availability of other fixed output voltage versions.(2) The packages are available taped and reeled. Add R suffix to device type (e.g., TPS61130PWR or TPS61130RSAR) to order quantitiesof 2000 devices per reel for the TSSOP (PW) package and 3000 devices per reel for the QFN (RSA) package.
over operating free-air temperature range (unless otherwise noted)
(1)
TPS61130
TPS61131
TPS61132
Input voltage range on FB – 0.3 V to 3.6 VInput voltage range on SWN – 0.3 V to 12 VInput voltage range on SWP – 7.0 V to 7.0 VMaximum voltage between SWP and VOUT – 12 VInput voltage range on VOUT, LDOIN, LDOOUT, LDOEN, LDOSENSE, PGOOD, LBO, VBAT, LBI, SKIPEN, EN – 0.3 V to 7 VOperating virtual junction temperature T
J
– 40 °C to 150 °CStorage temperature range T
stg
– 65 °C to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN NOM MAX UNIT
Supply voltage at VBAT 1.8 6.5 VOperating free air temperature range, T
A
– 40 85 °COperating virtual junction temperature, T
J
– 40 125 °C
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ELECTRICAL CHARACTERISTICS
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperaturerange of 25 °C) (unless otherwise noted)
DC/DC
PARAMETER TEST CONDITIONS MIN TYP MAX UNITSTAGE
V
I
Input voltage range 1.8 6.5 VAdjustable output voltageV
O
2.5 5.5 Vrange (TPS61130)V
ref
Reference voltage 485 500 515 mVf Oscillator frequency 400 500 600 kHzI
SW
Switch current limit VOUT= 3.3 V 1100 1300 1600 mAStartup current limit 0.4 x I
SW
mASWN switch on resistance VOUT= 3.3 V 200 350 m Ω
SWP switch on resistance VOUT= 3.3 V 250 500 m Ω
Total accuracy (including line
± 3 %and load regulation)
into I
O
= 0 mA, V
EN
= VBAT = 1.8 V,
10 25 µAVBAT VOUT = 3.3 V, ENLDO = 0 VDC/DC
quiescent current
into I
O
= 0 mA, V
EN
= VBAT = 1.8 V,
10 25 µAVOUT VOUT = 3.3 V, ENLDO = 0 VDC/DC shutdown
V
EN
= 0 V 0.2 1 µAcurrent
LDO
PARAMETER TEST CONDITIONS MIN TYP MAX UNITSTAGE
V
I(LDO)
Input voltage range 1.8 7 VAdjustable output voltageV
O(LDO)
0.9 5.5 Vrange (TPS61130)I
O(max)
Output current 200 320 mALDO short circuit current limit 500 mAMinimum voltage drop I
O
=200 mA 300 mVTotal accuracy (including
I
O
≥1 mA ± 3%line and load regulation)
LDOIN change from 1.8 V toLine regulation 2.6 V at 100 mA, 0.6%LDOOUT = 1.5 VLoad change from 10% to 90%,Load regulation 0.6%LDOIN = 3.3 VLDOIN = 7 V, VBAT = 1.8 V,LDO quiescent current 20 30 µAEN = VBATLDO shutdown current LDOEN = 0 V, LDOIN = 7 V 0.1 1 µA
CONTROL PARAMETER TEST CONDITIONS MIN TYP MAX UNITSTAGE
V
IL
LBI voltage threshold V
LBI
voltage decreasing 490 500 510 mVLBI input hysteresis 10 mVLBI input current EN = VBAT or GND 0.01 0.1 µALBO output low voltage V
O
= 3.3 V, I
OI
= 100 µA 0.04 0.4 VLBO output low current 100 µALBO output leakage current V
LBO
= 7 V 0.01 0.1 µAV
IL
EN, SKIPEN input low 0.2 ×Vvoltage VBATV
IH
EN, SKIPEN input high 0.8 ×VBAT Vvoltage
0.2 ×V
IL
LDOEN input low voltage VV
LDOIN
V
IH
LDOEN input high voltage 0.8 ×V
LDOIN
V
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PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SWP
SWN
PGND
VBAT
LBI
SKIPEN
EN
LDOEN
VOUT
FB
PGOOD
LBO
GND
LDOSENSE
LDOOUT
LDOIN
PW PACKAGE
(TOP VIEW)
VBAT
LBI
SKIPEN LDOSENSE
PGOOD
PGND
GND
LBO
EN
LDOEN
LDOIN
LDOOUT
SWN
SWP
VOUT
FB
RSA PACKAGE
(TOP VIEW)
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
ELECTRICAL CHARACTERISTICS (continued)over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperaturerange of 25 °C) (unless otherwise noted)
CONTROL
STAGE (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EN, SKIPEN input current Clamped on GND or VBAT 0.01 0.1 µAPower-Good threshold V
O
= 3.3 V 0.9 ×V
o
0.92 ×V
o
0.95 ×V
o
VPower-Good delay 30 µsPower-Good output low V
O
= 3.3 V, I
OI
= 100 µA 0.04 0.4 Vvoltage
Power-Good output low 100 µAcurrent
Power-Good output leakage V
PG
= 7 V 0.01 0.1 µAcurrent
Over-Temperature protection 140 °COver-Temperature hysteresis 20 °C
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TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
Terminal Functions
TERMINAL
NO. I/O DESCRIPTIONNAME
PW RSA
EN 7 5 I DC/DC-enable input. (1/VBAT enabled, 0/GND disabled)FB 15 13 I DC/DC voltage feedback of adjustable versionsGND 12 10 Control/logic groundLBI 5 3 I Low battery comparator input (comparator enabled with EN)LBO 13 11 O Low battery comparator output (open drain)LDOEN 8 6 I LDO-enable input (1/LDOIN enabled, 0/GND disabled)LDOOUT 10 8 O LDO outputLDOIN 9 7 I LDO inputLDOSENSE 11 9 I LDO feedback for voltage adjustment, must be connected to LDOOUT at fixedoutput voltage versionsPGND 3 1 Power groundPGOOD 14 12 O DC/DC output power good (1 : good, 0 : failure) (open drain)SKIPEN 6 4 I Enable/disable power save mode (1/VBAT enabled, 0/GND disabled)SWN 2 16 I DC/DC switch inputSWP 1 15 I DC/DC rectifying switch inputVBAT 4 2 I Supply pinVOUT 16 14 O DC/DC outputPowerPAD™ Must be soldered to achieve appropriate power dissipation. Should be connectedto PGND.
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Functional Block Diagram
Anti-
Ringing
Gate
Control
PGND
Regulator
Error
Amplifier
PGND
Control Logic Oscillator
Temperature
Control
VOUT
PGND
FB
LDOIN
LDOOUT
SWN
VBAT
EN
PGOOD
ENLDO
SKIPEN
GND
LBI
LBO
SWP
_
+
_
+
Backgate
Control
Vmax
Control
VOUT 100 kΩ
20 pF
_
+
Vref = 0.5 V
GND
Backgate
Control
Error
Amplifier LDOSENSE
_
+
_
+
Vref = 0.5 V
GND
Low Battery
Comparator
_
+Vref = 0.5 V
GND
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
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PARAMETER MEASUREMENT INFORMATION
SWN
C3
10 µF
Power
Supply
L1−A
22 µH
R1
R2
VBAT VOUT
FB
R3
R6
LDOIN
R5
R4
LDOSENSE
LDOOUT
R7
R9
C6
2.2 µF
C4
100 µF
U1
LBO
PGOOD
PGND
LBI
SKIPEN
EN
LDOEN
GND
TPS6113xPW
ListofComponents:
U1= TPS6113xPW
L1=CoiltronicsDRQ74−220
C3,C5,C6,C7=X7R/X5RCeramic
C4=LowESR Tantalum
VCC1
SEPICOutput
VCC2
LDOOutput
Control
Outputs
C5
2.2 µF
SWP
C7
L1−B
22 µH
10 µF
TYPICAL CHARACTERISTICS
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
Table of Graphs
SEPIC Converter Figure
Maximum output current vs Input voltage (TPS61130) (V
O
= 3.3 V, 5.0V, 2.5V) 1, 2vs Output current (TPS61130) (V
O
= 2.5 V, V
I
= 1.8 V) 3vs Output current (TPS61132) (V
O
= 3.3 V, V
I
= 1.8 V, 3.8 V) 4Efficiency
vs Output current (TPS61130) (V
O
= 5.0 V, V
I
= 3.6 V, 6.0 V) 5vs Input voltage (TPS61132) 6Output voltage vs Output current (TPS61132) 7No-load supply current into VBAT vs Input voltage (TPS61132) 8No-load supply current into VOUT vs Input voltage (TPS61132) 9Output voltage in continuous mode (TPS61132) 10Output voltage in power save mode (TPS61132) 11Waveforms Load transient response (TPS61132) 12Line transient response (TPS61132) 13Start-up after enable (TPS61132) 14
LDO
vs Input voltage (V
O
= 2.5 V, 3.3 V) 15Maximum output current
vs Input voltage (V
O
= 1.5 V, 1.8 V) 16Output voltage vs Output current (TPS61131) 17Dropout voltage vs Output current (TPS61131, TPS61132) 18Supply current into LDOIN vs LDOIN input voltage (TPS61132) 19PSRR vs Frequency (TPS61132) 20Load transient response 21Waveforms Line transient response 22Start-up after enable 23
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0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
234567
1.8
VO = 3.3 V
VO = 5 V
Maximum Output CURRENT − A
VI − Input Voltage − V
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 5.4 5.8 6.2 6.6 7
VI− Input Voltage − V
Maximum Output Current − A
VO = 2.5 V
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
VBAT = 3.8 V
VBAT = 1.8 V
TPS61132
Efficiency − %
IO − Output Current − mA
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
TPS61130 TPS61130MAXIMUM SEPIC CONVERTER OUTPUT CURRENT MAXIMUM SEPIC CONVERTER OUTPUT CURRENTvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 1. Figure 2.
TPS61130
TPS61132SEPIC CONVERTER EFFICIENCY
SEPIC CONVERTER EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 3. Figure 4.
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60
65
70
75
80
85
90
95
100
3 5 7
Efficiency − %
VI − Input Voltage − V
IO = 10 mA
IO = 100 mA IO = 200 mA
1.8
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
VBAT = 6 V
VBAT = 3.6 V
TPS61130
Efficiency − %
IO − Output Current − mA
3.20
3.22
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3.38
3.40
0 100 200 300 400
− Output Voltage − V
IO − Output Current − mA
VO
VI = 2.4 V
0
2
4
6
8
10
12
14
1.8 2 2.2 2.4 2.6 2.8 3 3.2
85°C
25°C
−40°C
VI − Input Voltage − V
No-Load Supply Current Into VBAT − Aµ
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
TPS61130
TPS61132SEPIC CONVERTER EFFICIENCY
SEPIC CONVERTER EFFICIENCYvs
vsOUTPUT CURRENT INPUT VOLTAGE
Figure 5. Figure 6.
TPS61132 TPS61132SEPIC CONVERTER OUTPUT VOLTAGE NO-LOAD SUPPLY CURRENT INTO VBATvs vsOUTPUT CURRENT INPUT VOLTAGE
Figure 7. Figure 8.
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Inductor Current
100 mA/Div, DC
Output Voltage
20 mV/Div, AC
Timebase − 1 µs/Div
VI = 3.3 V, RL = 33 W
VO = 3.3 V
0
2
4
6
8
10
12
14
1.8 2 2.2 2.4 2.6 2.8 3 3.2
VI − Input Voltage − V
−40°C
85°C
25°C
No-Load Supply Current Into VOUT − Aµ
Inductor Current
100 mA/Div, DC
Output Voltage
50 mV/Div, AC
Timebase − 200 µs/Div
VI = 3.3 V, RL = 330 W
VO = 3.3 V
Output Voltage
20 mV/Div, AC
Current
100 mA/Div, DC
Timebase − 500 µs/Div
VI = 3.3 V
IL = 60 mA to 140 mA
VO = 3.3 V
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
TPS61132
TPS61132NO-LOAD SUPPLY CURRENT INTO VOUT
SEPIC CONVERTER OUTPUT VOLTAGEvsINPUT VOLTAGE IN CONTINUOUS MODE
Figure 9. Figure 10.
TPS61132SEPIC CONVERTER OUTPUT VOLTAGE TPS61132IN POWER SAVE MODE SEPIC CONVERTER LOAD TRANSIENT RESPONSE
Figure 11. Figure 12.
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Output Voltage
2 V/Div, DC
Input Current
200 mA/Div, DC
Enable
5 V/Div, DC
Voltage at SW
5 V/Div, DC
Timebase − 400 µs/Div
VI = 3.6 V, RL = 66 W
VO = 3.3 V
Output Voltage
50 mV/Div, AC
Input Voltage
1 V/Div, DC
Timebase − 200 µs/Div
VI = 3.0 V to 4.2 V
RL = 33 W
VO = 3.3 V
150
200
250
300
350
400
2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
VO = 3.3 V
Maximum LDO Output Current − mA
LDO Input Voltage − V
100
50
0
VO = 2.5 V
0
200
250
300
350
400
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VO = 1.8 V
VO = 1.5 V
LDO Input Voltage − V
Maximum LDO Output Current − mA
150
100
50
6.5 7
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
TPS61132 TPS61132SEPIC CONVERTER LINE TRANSIENT RESPONSE SEPIC CONVERTER START-UP AFTER ENABLE
Figure 13. Figure 14.
TPS61130MAXIMUM LDO OUTPUT CURRENTMAXIMUM LDO OUTPUT CURRENT
vsvsLDO INPUT VOLTAGE LDO INPUT VOLTAGE
Figure 15. Figure 16.
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0
0.5
1
1.5
2
2.5
3
3.5
10 60 110 160 210 260 310
TPS61131
(LDO OUTPUT
VOLTAGE 1.5 V)
TPS61132
(LDO OUTPUT
VOLTAGE 3.3 V)
LDO Dropout Voltage − V
LDO Output Current − mA
3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
0 50 100 150 200 250 300 350 400
LDO Output Voltage − V
LDO Output Current − mA
PSRR − dB
f − Frequency − Hz
LDOIN = 3.3 V
1k 10k 100k 1M 10M
0
10
20
30
40
70
60
50
80
LDO Output Current 10 mA
LDO Output Current 200 mA
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
TPS61131
LDO DROPOUT VOLTAGELDO OUTPUT VOLTAGE
vsvsLDO OUTPUT CURRENT LDO OUTPUT CURRENT
Figure 17. Figure 18.
TPS61132TPS61132
PSRRSUPPLY CURRENT INTO LDOIN
vsvsLDOIN INPUT VOLTAGE FREQUENCY
Figure 19. Figure 20.
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Input Voltage
1 V/Div, DC
Output Voltage
10 mV/Div, AC
Timebase − 2 ms/Div
VI = 1.8 V to 2.6 V
RL = 15 W
VO = 1.5 V
Output Current
100 mA/Div, DC
Output Voltage
20 mV/Div, AC
Timebase − 500 µs/Div
VI = 3.3 V
IL = 20 mA to 180 mA
VO = 1.5 V
LDO-Enable
5 V/Div, DC
LDO-Output Voltage
1 V/Div, DC
Input Current
200 mA/Div, DC
Timebase − 20 µs/Div
VI = 3.3 V
RL = 15 W
VO = 1.5 V
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
TPS61132 TPS61132LDO LOAD TRANSIENT RESPONSE LDO LINE TRANSIENT RESPONSE
Figure 21. Figure 22.
TPS61132LDO START-UP AFTER ENABLE
Figure 23.
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DETAILED DESCRIPTION
Controller Circuit
Synchronous Rectifier
Device Enable
Undervoltage Lockout
Softstart
Power Good
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Inputvoltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. Sochanges in the operating conditions of the converter directly affect the duty cycle and must not take the indirectand slow way through the control loop and the error amplifier. The control loop, determined by the error amplifier,only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed outputvoltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage togenerate an accurate and stable output voltage.
The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch andthe inductor. The typical peak current limit is set to 1300 mA. An internal temperature sensor prevents the devicefrom getting overheated in case of excessive power dissipation.
The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier.Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the powerconversion efficiency reaches 90%. To avoid ground shift due to the high currents in the NMOS switch, twoseparate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOSswitch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GNDpin. Due to the nature of the SEPIC topology, there is no dc path from the battery to the output. No additionalcomponents must be added in a SEPIC or Flyback topology to make sure the battery is disconnected from theoutput of the converter.
Nevertheless, the backgate diode of the high-side PMOS which is forward biased in standard operation, is turnedoff in shutdown. This is done by a special circuit which takes the cathode of the backgate diode of the high-sidePMOS and disconnects it from the source when the regulator is not enabled (EN = low).
The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. Inshutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator isswitched off, and the backgate diode of the rectifying switch is turned off (as described in the SynchronousRectifier Section). This also means that the output voltage can drop below the input voltage during shutdown.During start-up of the converter, the duty cycle and the peak current are limited in order to avoid high peakcurrents drawn from the battery.
An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower thanapproximately 1.6 V. When in operation and the battery is being discharged, the device automatically enters theshutdown mode if the voltage on VBAT drops below approximately 1.6 V. This undervoltage lockout function isimplemented in order to prevent the malfunctioning of the converter.
When the SEPIC section is enabled, the internal startup cycle starts with switching at a duty cycle of 50%. Afterthe output voltage has reached approximately 1.4V the device continues switching with a variable duty cycle.Until the programmed output voltage is reached, the main switch current limit is set to 40% of its nominal value toavoid high peak inrush currents at the battery during startup. Also the maximum output power during output shortcircuit conditions is reduced. When the programmed output voltage is reached, the regulator takes control andthe switch current limit is set back to 100%.
The PGOOD pin stays high impedance when the dc/dc converter delivers an output voltage within a definedvoltage window. So it can be used to enable any connected circuitry such as cascaded converters (LDO) ormicroprocessor circuits.
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Power Save Mode
Low Battery Detector Circuit — LBI/LBO
Low-EMI Switch
LDO
LDO Enable
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
The SKIPEN pin can be used to select different operation modes. To enable the power save mode, SKIPENmust be set high. Power save mode is used to improve efficiency at light loads. In power save mode, theconverter only operates when the output voltage trips below a set threshold voltage. It ramps up the outputvoltage with several pulses, and goes again into power save mode once the output voltage exceeds the setthreshold voltage. The power save mode can be disabled by setting the SKIPEN to GND.
The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flagwhen the battery voltage drops below a user-set threshold voltage. The function is active only when the device isenabled. When the device is disabled, the LBO pin is high-impedance. The switching threshold is 500 mV at LBI.During normal operation, LBO stays at high impedance when the voltage, applied at LBI, is above the threshold.It is active low when the voltage at LBI goes below 500 mV.
The battery voltage, at which the detection circuit switches, can be programmed with a resistive dividerconnected to the LBI pin. The resistive divider scales down the battery voltage to a voltage level of 500 mV,which is then compared to the LBI threshold voltage. The LBI pin has a built-in hysteresis of 10 mV. See theapplication section for more details about the programming of the LBI threshold. If the low-battery detectioncircuit is not used, the LBI pin should be connected to GND (or to VBAT) and the LBO pin can be leftunconnected. Do not let the LBI pin float.
The device integrates a circuit that removes the ringing that typically appears on the SW node when theconverter enters discontinuous current mode. In this case, the current through the inductor ramps to zero and therectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to thebattery. Due to the remaining energy that is stored in parasitic components of the semiconductor and theinductor, a ringing on the SW pin is induced. The integrated antiringing switch clamps this voltage to VBAT andtherefore dampens ringing.
The built-in LDO can be used to generate a second output voltage derived from the dc/dc converter output, fromthe battery, or from another power source like an ac adapter or a USB power rail. The LDO is capable of beingback biased. This allows the user just to connect the outputs of dc/dc converter and LDO. So the device is ableto supply the load via dc/dc converter when the energy comes from the battery and efficiency is most importantand from another external power source via the LDO when lower efficiency is not critical. The LDO must bedisabled if the LDOIN voltage drops below LDOOUT to block reverse current flowing. The status of the dc/dcstage (enabled or disabled) does not matter.
The LDO can be separately enabled and disabled by using the LDOEN pin in the same way as the EN pin at thedc/dc converter stage described above. This is completely independent of the status of the EN pin. The voltagelevels of the logic signals which need to be applied at LDOEN are related to LDOIN.
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
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APPLICATION INFORMATION
DESIGN PROCEDURE
Programming the Output Voltage
DC/DC Converter
R3 +R6 ǒVO
VFB *1Ǔ+180 kW ǒVO
500 mV *1Ǔ
(1)
CparR3 +20 pF ǒ200 kW
R6 *1Ǔ
(2)
SWN
C3
10 µF
Power
Supply
R1
R2
VBAT VOUT
FB
R3
R6
LDOIN
R5
R4
LDOSENSE
LDOOUT
R7 R9
C6
2.2 µF
C4
100 µF
U1
LBO
PGOOD
PGND
LBI
SKIPEN
EN
LDOEN
GND
TPS6113xPW
VCC1
SEPICOutput
VCC2
LDOOutput
Control
Outputs
C5
2.2 µF
L1−A
22 µH SWP
C7
L1−B
22 µH
10 µF
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
The TPS6113x dc/dc converters are intended for systems powered by a dual up to 4 cell NiCd or NiMH batterywith a typical terminal voltage between 1.8 V and 6.5 V. They can also be used in systems powered by one-cellLi-Ion with a typical stack voltage between 2.5 V and 4.2 V. Additionally, two up to four primary alkaline batterycells can be the power source in systems where the TPS6113x is used.
The output voltage of the TPS61130 dc/dc converter section can be adjusted with an external resistor divider.The typical value of the voltage on the FB pin is 500 mV. The maximum recommended value for the outputvoltage is 5.5 V. The current through the resistive divider should be about 100 times greater than the current intothe FB pin. The typical current into the FB pin is 0.01 µA and the voltage across R6 is typically 500 mV. Basedon those two values, the recommended value for R6 should be lower than 500 k Ω, in order to set the dividercurrent at 1 µA or higher. Because of internal compensation circuitry the value for this resistor should be in therange of 200 k Ω. From that, the value of resistor R3, depending on the needed output voltage (V
O
), can becalculated using Equation 1 :
If as an example, an output voltage of 3.3 V is needed, a 1-M Ωresistor should be chosen for R3. If for anyreason the value for R6 is chosen significantly lower than 200 k Ωadditional capacitance in parallel to R3 isrecommended. The required capacitance value can be easily calculated using Equation 2 .
Figure 24. Typical Application Circuit for Adjustable Output Voltage Option
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LDO
R5 +R4 ǒVO
VFB–1Ǔ+180 kW ǒVO
500 mV–1Ǔ
(3)
Programming the LBI/LBO Threshold Voltage
R1 +R2 ǒVBAT
VLBI*threshold *1Ǔ+390 kW ǒVBAT
500 mV *1Ǔ
(4)
Inductor Selection
IL1*A+IL1*B+IOUT VOUT
VBAT 0.8
(5)
L1 *A+L1 *B+VBAT VOUT
DIL ƒ ǒVOUT)VBATǓ
(6)
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
Programming the output voltage of the LDO follows almost the same rules as at the dc/dc converter section. Themaximum recommended output voltage of the LDO is 5.5 V. Since reference and internal feedback circuitry aresimilar, as they are at the dc/dc converter section, R4 also should be in the 200-k Ωrange. The calculation of thevalue of R5 can be done using the following Equation 3 :
If as an example, an output voltage of 1.5 V is needed, a 360 k Ω-resistor should be chosen for R5.
The current through the resistive divider should be about 100 times greater than the current into the LBI pin. Thetypical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that isgenerated on-chip, which has a value of 500 mV. The recommended value for R2 is therefore in the range of 500kΩ. From that, the value of resistor R1, depending on the desired minimum battery voltage V
BAT,
can becalculated using Equation 4 .
The output of the low battery supervisor is a simple open-drain output that goes active low if the dedicatedbattery voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor witha recommended value of 1 M Ω. The maximum voltage which is used to pull up the LBO outputs should notexceed the output voltage of the dc/dc converter. If not used, the LBO pin can be left floating or tied to GND.
A SEPIC converter normally requires three main passive components for storing energy during the conversion.Two inductors, a flying capacitor, and a storage capacitor at the output are required. To select the two inductors,it is recommended to keep the possible peak inductor current below the current limit threshold of the powerswitch in the chosen configuration. For example, the typical current limit threshold of the TPS6113x's switch is1300 mA at an output voltage of 3.3 V. The highest peak current through the switch is the sum of the twoinductor currents and depends on the output load, the input (V
BAT
), and the output voltage (V
OUT
). Estimation ofthe maximum average inductor current of each inductor can be done using Equation 5 :
For example, for an output current of 300 mA at 3.3 V, at least 680 mA of average current flows through each ofthe the inductors at a minimum input voltage of 1.8 V.
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it isadvisable to work with a ripple of around ± 20% of the average inductor current. A smaller ripple reduces themagnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way,regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With thoseparameters, it is possible to calculate the value for the inductor by using Equation 6 :
Parameter fis the switching frequency and ΔI
L
is the ripple current in the inductor, i.e., 40% ΔI
L
. In this example,the desired inductance is in the range of 20 µH. With this calculated value and the calculated currents, it ispossible to choose a suitable inductor. In typical applications a 22 µH inductance is recommended. The device
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
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Capacitor Selection
Input Capacitor
Flying Capacitor DC/DC Converter
Cmin +100
4p2ƒ2L
(7)
Output Capacitor DC/DC Converter
Cmin +IOUT VOUT
ƒ DV ǒVOUT )VBATǓ
(8)
DVESR +IOUT RESR
(9)
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
has been optimized to operate with inductance values between 10 µH and 47 µH. Nevertheless operation withhigher inductance values may be possible in some applications. Detailed stability analysis is recommended. Carehas to be taken that load transients and losses in the circuit can lead to higher currents as estimated inEquation 6 . Also, the losses in the inductor caused by magnetic hysteresis losses and copper losses are a majorparameter for total circuit efficiency.
The following inductor series from different suppliers have been used with the TPS6113X converters:
List of Inductors
VENDOR RECOMMENDED INDUCTOR SERIES COUPLED INDUCTOR SERIES
LPS4012 LPD4012Coilcraft
LPS3015Cooper Electronics Technologies DR73 DRQ73DR74 DRQ74EPCOS B82462GSumida CDRH5D18
7447789___ 744878220Wurth Electronik
7447779___ 744877220
At least a 10- µF input capacitor is recommended to improve transient behavior of the regulator and EMI behaviorof the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor inparallel, placed close to the IC, is recommended.
In the normal operating mode, the flying capacitor (C7) must be large enough so that the voltage across thecapacitor is small. This means the resonance frequency formed by the flying capacitor and the inductors must beat least ten times lower than the switching frequency (see Equation 7 ).
Where L is the inductance of L1-A or L1-B.
To optimize efficiency, capacitors with very low ESR such as ceramic capacitors are recommended. The voltagerating of the flying capacitor must be higher than the input voltage V
BAT
.
The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple ofthe converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It ispossible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, byusing Equation 8 :
Parameter fis the switching frequency and ΔV is the maximum allowed ripple.
With a chosen ripple voltage of 15 mV, a minimum capacitance of 26 µF is needed. The total ripple is larger dueto the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 9 :
An additional ripple of 24 mV is the result of using a tantalum capacitor with a low ESR of 80 m Ω. The total rippleis the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In thisexample, the total ripple is 39 mV. Additional ripple is caused by load transients. This means that the output
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Small Signal Stability
AREG +d
VFB +10 (R3 )R6)
R6 (1 )i w 1.6 ms)
(10)
Output Capacitor LDO
Layout Considerations
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
capacitance needs to be larger than calculated above to meet the total ripple requirements. The output capacitorhas to completely supply the load during the charging phase of the inductor. A reasonable value of the outputcapacitance depends on the speed of the load transients and the load current during the load change. With thecalculated minimum value of 26 µFand load transient considerations the recommended output capacitance valueis in a 100 µF range. For economical reasons this usually is a tantalum capacitor. Because of this the controlloop has been optimized for using output capacitors with an ESR of above 30 m Ω. The minimum value for theoutput capacitor is 22 µF.
When using output capacitors with lower ESR, like ceramics, it is recommended to use the adjustable voltageversion. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in therange of 10 pF in parallel with R3 helps to obtain small signal stability, with the lowest ESR output capacitors.For more detailed analysis the small signal transfer function of the error amplifier and regulator, which is given inEquation 10 , can be used.
To ensure stable output regulation, it is required to use an output capacitor at the LDO output. Ceramiccapacitors in the range from 1 µF up to 4.7 µF are recommend. At 4.7 µF and above it is recommended to usestandard ESR tantalum. There is no maximum capacitance value.
For all switching power supplies, the layout is an important step in the design, especially at high peak currentsand high switching frequencies. If the layout is not carefully done, the regulator could show stability problems aswell as EMI problems. Therefore, use wide and short traces for the main current path and for the power groundtracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.Use a common ground node for power ground and a different one for control ground to minimize the effects ofground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out thecontrol ground, it is recommended to use short traces as well, separated from the power ground traces. Thisavoids ground shift problems, which can occur due to superimposition of power ground current and controlground current.
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
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APPLICATION EXAMPLES
SWN
C3
10 µF
L1−A
22 µH
R1
R2
VBAT
LDOIN
LDOSENSE
LDOOUT
R7 R9
C6
2.2 µFC4
100 µF
U1
LBO
PGOOD
PGND
LBI
SKIPEN
EN
LDOEN
GND
TPS61132PW
List of Components:
U1 = TPS61132PW
L1 = Coiltronics DRQ74−220
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
3.3 V,
>250 mA
C5
2.2 µF
1.5 V,
>120 mA
LBO
PGOOD
SWP
C7
VOUT
22 µH
L1−B
10 µF
SWP
C7
SWN
C3
10 µF
L1
22 µH
R1
R2
VBAT VOUT
LDOIN
LDOSENSE
LDOOUT
R7 R9
C6
2.2 µFC4
100 µF
U1
LBO
PGOOD
PGND
LBI
SKIPEN
EN
LDOEN
GND
TPS61132PW
List of Components:
U1 = TPS61132PW
L1 , L2 = Sumida 5D18−220
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR, Low Profile Tantalum
3.3 V
C5
2.2 µF
1.5 V
LBO
PGOOD
L2
22 µH
10 µF
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
Figure 25. Solution for Maximum Output Power
Figure 26. Low Profile Solution, Maximum Height 1,8 mm
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SWN
C3
10 µF
L1−A
22 µH
R1
R2
VBAT VOUT
FB R3
R6
LDOIN
R5
R4
LDOSENSE
LDOOUT
R7 R9
C6
22 µF
C5
2.2 µF
U1
LBO
PGOOD
PGND
LBI
SKIPEN
EN
LDOEN
GND
TPS61130PW
List of Components:
U1 = TPS61130PW
L1 = Coiltronics DRQ74−220
C3, C5, C7 = X7R/X5R Ceramic
C6 = X7R/X5R Ceramic or Low
ESR Tantalum
3.3 V
LBO
PGOOD
C7
SWP L1−B
22 µH
10 µF
SWN
C3
10 µF
L1−A
22 µH
R1
R2
VBAT VOUT
LDOIN
LDOSENSE
LDOOUT
R7 R8
C6
2.2 µFC4
100 µF
U1
LBO
PGOOD
PGND
LBI
SYNC
EN
LDOEN
GND
TPS61130PW
List of Components:
U1 = TPS61130PW
L1 = Coiltronics DRQ74−220
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
D1 = On-Semiconductor MBR0520
VCC
Control
Outputs
D1
USB Input
4.2 V...5.5 V
FB
3.3 V System Supply
R5
R4
1.022 MΩ
180 kΩ
R3
1 MΩ
180 kΩ
R6
C7
SWP L1−B
22 µH
10 µF
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
Figure 27. Single Output Using LDO as Filter
Figure 28. Dual Input Power Supply Solution
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THERMAL INFORMATION
PD(MAX) +TJ(MAX) *TA
RqJA +150°C*85°C
155°CńW+420 mW
(11)
TPS61130
TPS61131
TPS61132
SLVS431B – JUNE 2002 – REVISED JANUARY 2008
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requiresspecial attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, addedheat sinks and convection surfaces, and the presence of other heat-generating components affect thepower-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.•Improving the power dissipation capability of the PCB design.•Improving the thermal coupling of the component to the PCB.•Introducing airflow in the system.
The maximum recommended junction temperature (T
J
) of the TPS6113x devices is 150 °C. The thermalresistance of the 16-pin TSSOP package (PW) is R
ΘJA
= 155 °C/W. The 16-pin QFN PowerPAD package (RSA)has a thermal resistance of R
ΘJA
= 38.1 °C/W, if the PowerPAD is soldered and the board layout is optimized.Specified regulator operation is assured to a maximum ambient temperature T
A
of 85 °C. Therefore, themaximum power dissipation is about 420 mW for the TSSOP (PW) package and 1700 mW for the QFN (RSA)package. More power can be dissipated if the maximum ambient temperature of the application is lower (seeEquation 11 ).
If designing for a lower junction temperature of 125 °C, which is recommended, maximum heat dissipation islower. Using the above Equation 11 results in 1050 mW power dissipation for the RSA package and 260 mW forthe PW package.
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Product Folder Link(s): TPS61130 TPS61131 TPS61132
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS61130PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS61130RSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
TPS61131PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS61132RSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS61130PWR TSSOP PW 16 2000 367.0 367.0 35.0
TPS61130RSAR QFN RSA 16 3000 338.1 338.1 20.6
TPS61131PWR TSSOP PW 16 2000 367.0 367.0 35.0
TPS61132RSAR QFN RSA 16 3000 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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