74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0
February 2008
74LCX08
Low Voltage Quad 2-Input AND Gate with 5V
Tolerant Inputs
Features
5V tolerant inputs
2.3V–3.6V V
CC
specifications provided
5.5ns t
PD
max. (V
CC
=
3.3V), 10µA I
CC
max.
Power down high impedance inputs and outputs
±24mA output drive (V
CC
=
3.0V)
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
– Human body model
>
2000V
– Machine model
>
150V
Leadless DQFN package
General Description
The LCX08 contains four 2-input AND gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V
systems to 3V systems.
The 74LVX08 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Information
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74LCX08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX08BQX
(1)
MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Implements proprietary noise/EMI reduction circuitry
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 2
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Pad Assignments for DQFN
(Top View)
Pin Description
Logic Symbol
IEEE/IEC
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 3
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Note:
2. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +7.0V
V
I
DC Input Voltage –0.5V to +7.0V
V
O
DC Output Voltage, Output in HIGH or LOW State
(2)
–0.5V to V
CC
+ 0.5V
I
IK
DC Input Diode Current, V
I
<
GND –50mA
I
OK
DC Output Diode Current
V
O
<
GND –50mA
V
O
>
V
CC
+50mA
I
O
DC Output Source/Sink Current ±50mA
I
CC
DC Supply Current per Supply Pin ±100mA
I
GND
DC Ground Current per Ground Pin ±100mA
T
STG
Storage Temperature –65°C to +150°C
Symbol Parameter Min. Max. Units
V
CC
Supply Voltage
Operating 2.0 3.6 V
Data Retention 1.5 3.6
V
I
Input Voltage 0 5.5 V
V
O
Output Voltage, HIGH or LOW State 0 V
CC
V
I
OH
/
I
OL
Output Current
V
CC
=
3.0V–3.6V ±24 mA
V
CC
=
2.7V–3.0V ±12
V
CC
=
2.3V–2.7V ±8
T
A
Free-Air Operating Temperature –40 85 °C
t
/
V Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V 0 10 ns
/
V
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 4
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
DC Electrical Characteristics
AC Electrical Characteristics
Note:
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Symbol Parameter V
CC
(V) Conditions
T
A
=
–40°C to +85°C
UnitsMin. Max.
V
IH
HIGH Level Input Voltage 2.3–2.7 1.7 V
2.7–3.6 2.0
V
IL
LOW Level Input Voltage 2.3–2.7 0.7 V
2.7–3.6 0.8
V
OH
HIGH Level Output Voltage 2.3–3.6 I
OH
=
–100µA V
CC
– 0.2 V
2.3 I
OH
=
–8mA 1.8
2.7 I
OH
=
–12mA 2.2
3.0 I
OH
=
–18mA 2.4
I
OH
=
–24mA 2.2
V
OL
LOW Level Output Voltage 2.3–3.6 I
OL
=
100µA 0.2 V
2.3 I
OL
=
8mA 0.6
2.7 I
OL
=
12mA 0.4
3.0 I
OL
=
16mA 0.4
I
OL
=
24mA 0.55
I
I
Input Leakage Current 2.3–3.6 0
V
I
5.5V ±5.0 µA
I
OFF
Power-Off Leakage Current 0 V
I
or V
O
=
5.5V 10 µA
I
CC
Quiescent Supply Current 2.3–3.6 V
I
=
V
CC
or GND 10 µA
3.6V
V
I
5.5V ±10
I
CC
Increase in I
CC
per Input 2.3–3.6 VIH = VCC – 0.6V 500 µA
Symbol Parameter
TA = –40°C to +85°C, RL = 500
Units
VCC = 3.3V ± 0.3V,
CL = 50pF
VCC = 2.7V,
CL = 50pF
VCC = 2.5V ± 0.2V,
CL = 30pF
Min. Max. Min. Max. Min. Max.
tPHL, tPLH Propagation Delay 1.5 5.5 1.5 6.2 1.5 6.6 ns
tOSHL, tOSLH Output to Output Skew(4) 1.0 ns
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 5
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
Dynamic Switching Characteristics
Capacitance
Symbol Parameter VCC (V) Conditions
TA = 25°C
UnitTypical
VOLP Quiet Output Dynamic Peak VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V
2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6
VOLV Quiet Output Dynamic Valley VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 V
2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6
Symbol Parameter Conditions Typical Units
CIN Input Capacitance VCC = Open, VI = 0V or VCC 7pF
COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8pF
CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10MHz 25 pF
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 6
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
AC Loading and Waveforms (Generic for LCX Family)
Figure 1. AC Test Circuit (CL includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay. Pulse Width and trec Waveforms
3-STATE Output Low Enable and
Disable Times for Logic
3-STATE Output High Enable and
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)
Test Switch
tPLH, tPHL Open
tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH, tPHZ GND
Symbol
VCC
3.3V ± 0.3V 2.7V 2.5V ± 0.2V
Vmi 1.5V 1.5V VCC / 2
Vmo 1.5V 1.5V VCC / 2
VxVOL + 0.3V VOL + 0.3V VOL + 0.15V
VyVOH – 0.3V VOH – 0.3V VOH – 0.15V
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 7
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
Schematic Diagram (Generic for LCX Family)
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 8
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
Tape and Reel Specification
Tape Format for DQFN
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status
BQX Leader (Start End) 125 (Typ.) Empty Sealed
Carrier 3000 Filled Sealed
Trailer (Hub End) 75 (Typ.) Empty Sealed
Tape Size A B C D N W1 W2
12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4)
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 9
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
Physical Dimensions
Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8°
0°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X45°
1
0.10
C
C
BC A
7
M
14 B
A
8
SEE DETAIL A
5.60
0.65
1.70 1.27
8.75
8.50
7.62
6.00 4.00
3.80
(0.33)
1.27 0.51
0.35
1.75 MAX
1.50
1.25 0.25
0.10 0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
R0.10
0.50
0.25
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 10
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
Physical Dimensions (Continued)
Figure 4. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 11
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
Physical Dimensions (Continued)
Figure 5. 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 12
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
Physical Dimensions (Continued)
Figure 6. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00°TOP & BOTTO
M
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LCX08 Rev. 1.5.0 13
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when properly used in accordance with instructions for use
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Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
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This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs