MC74HC30ADTR2G - ON Semiconductor

January, 2010 − Rev. 0

1Publication Order Number:

MC74HC30A/D

MC74HC30A

8-Input NAND Gate

High−Performance Silicon−Gate CMOS

The MC74HC30 is identical in pinout to the LS30. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 mA

•High Noise Immunity Characteristic of CMOS Devices

•These are Pb−Free Devices

Figure 1. Logic Diagram

8Y = ABCDEFGH

PIN 14 = VCC

PIN 7 = GND

PINS 9, 10, 13 = NO CONNECTION

MARKING

DIAGRAMS

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or  = Pb−Free Package

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

http://onsemi.com

TSSOP−14

DT SUFFIX

CASE 948G

SOIC−14

D SUFFIX

CASE 751A

HC30AG

AWLYWW

30A

ALYW



(Note: Microdot may be in either location)

PIN ASSIGNMENT

105

VCC

GND

NC = NO CONNECTION

FUNCTION TABLE

Inputs A through H

Output

All inputs H

One or more inputs L

MC74HC30A

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

−0.5 to +7.0

ÎÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎ

−1.5 to VCC + 1.5

ÎÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎ

−0.5 to VCC + 0.5

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎ

±20

ÎÎÎ

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±50

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air SOIC Package

TSSOP Package

ÎÎÎÎÎ

500

TBD

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

−65 to +150

ÎÎÎ

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not implied.

Extended exposure to stresses above the Recommended Operating Conditions may affect device

reliability.

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

ÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

−55

ÎÎ

+125

ÎÎÎ

°C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 2) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

ÎÎ

1000

500

400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

− 55 to

25°C

ÎÎÎÎ

v 85°C

ÎÎÎÎ

v 125°C

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎÎ

Minimum High−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC − 0.1 V

|Iout| v 20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC − 0.1 V

|Iout| v 20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎ

0.3

0.9

1.2

ÎÎÎÎ

0.3

0.9

1.2

ÎÎÎÎ

0.3

0.9

1.2

ÎÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎÎ

Minimum High−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout| v 4.0 mA

|Iout| v 5.2 mA

ÎÎÎ

4.5

6.0

ÎÎÎÎ

3.98

5.48

ÎÎÎÎ

3.84

5.34

ÎÎÎÎ

3.70

5.20

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout| v 4.0 mA

|Iout| v 5.2 mA

ÎÎÎ

4.5

6.0

ÎÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎ

0.40

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

6.0

ÎÎÎÎ

±0.1

ÎÎÎÎ

±1.0

ÎÎÎÎ

±1.0

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0 mA

ÎÎÎ

6.0

ÎÎÎÎ

ÎÎÎ

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HC30A

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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

− 55 to

25°C

ÎÎÎÎ

v 85°C

ÎÎÎÎ

v 125°C

ÎÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Any Input to Output Y

(Figures 2 and 3)

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎ

175

ÎÎÎÎ

220

ÎÎÎÎ

265

ÎÎÎ

ÎÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 2 and 3)

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎ

110

ÎÎÎ

ÎÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎ

−

ÎÎÎÎ

ÎÎÎ

CPD Power Dissipation Capacitance (Per Gate)

Typical @ 25°C, VCC = 5.0 V

Figure 2. Switching Waveforms

VCC

GND

90%

50%

10%

90%

50%

10%

ANY INPUT

OUTPUT Y

tPHL tPLH

tTHL tTLH

*Includes all probe and jig capacitance

Figure 3. Test Circuit

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 4. Expanded Logic Diagram

ORDERING INFORMATION

Device Package Shipping†

MC74HC30ADG SOIC−14

(Pb−Free) 55 Units/Rail

MC74HC30ADR2G SOIC−14

(Pb−Free) 2500/Tape & Reel

MC74HC30ADTR2G TSSOP−14*

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC74HC30A

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PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE J NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−A−

−B−

P7 PL

14 8

0.25 (0.010) B M

0.25 (0.010) A S

−T−

RX 45

SEATING

PLANE D14 PL K

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

 

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC30A

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PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.



U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

ÉÉÉ

DETAIL E

−W−

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

−V−

14X REFK

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC30A

http://onsemi.com

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MC74HC30A/D

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