74LVT573
3.3V Octal D-type transparent latch
(3-State)
Product specification
Supersedes data of 1995 Nov 14
IC23 Data Handbook
1998 Feb 19
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
2
1998 Feb 19 853–1750 18988
FEATURES
•Inputs and outputs on opposite side of package allow easy
interface to microprocessors
•3-State output buffers
•Common output enable
•TTL input and output switching levels
•Input and output interface capability to systems at 5V supply
•Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
•Live insertion/extraction permitted
•No bus current loading when output is tied to 5V bus
•Latch-up protection exceeds 500mA per JEDEC Std 17
•Power-up 3-State
•Power-up reset
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The LVT573 is a high-performance BiCMOS product designed for
VCC operation at 3.3V. This device is an octal transparent latch
coupled to eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (E) and Output
Enable (OE) control gates. The 74LVT573 has a broadside pinout
configuration to facilitate PC board layout and allow easy interface
with microprocessors.
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation.
When OE is Low , the latched or transparent data appears at the
outputs. When OE is High, the outputs are in the High-impedance
“OFF” state, which means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS
Tamb = 25°C; GND = 0V TYPICAL UNIT
tPLH
tPHL Propagation delay
Dn to Qn CL = 50pF; VCC = 3.3V 2.5
2.7 ns
CIN Input capacitance VI = 0V or 3.0V 4 pF
COUT Output capacitance Outputs disabled; VO = 0V or 3.0V 8 pF
ICCZ Total supply current Outputs disabled; VCC = 3.6V .13 mA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
20-Pin Plastic SOL –40°C to +85°C74LVT573 D 74LVT573 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C74LVT573 DB 74LVT573 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C74LVT573 PW 74LVT573PW DH SOT360-1
PIN CONFIGURATION
10
9
8
7
6
5
4
3
2
120
19
18
17
16
15
14
13
12
11
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
E
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
SV00031
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enable input
(active-Low)
2, 3, 4, 5, 6, 7, 8, 9 D0-D7 Data inputs
19, 18, 17, 16, 15,
14, 13, 12 Q0-Q7 Data outputs
11 EEnable input
(active-High)
10 GND Ground (0V)
20 VCC Positive supply voltage
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
1998 Feb 19 3
LOGIC SYMBOL
23456789
11
1
E
OE
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19 18 17 16 15 14 13 12
SV00032
LOGIC SYMBOL (IEEE/IEC)
EN
C1
1D
SV00033
12
13
14
15
16
17
18
19
9
8
7
6
5
4
3
2
11
1
FUNCTION TABLE
INPUTS INTERNAL OUTPUTS
OPERATING MODE
OE E Dn
INTERNAL
REGISTER Q0 – Q7
OPERATING
MODE
L
LH
HL
HL
HL
HEnable and read register
L
L↓
↓I
hL
HL
HLatch and read register
L L X NC NC Hold
H X X NC Z Disable outputs
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “of f” state
↓= High-to-Low E transition
LOGIC DIAGRAM
E Q
D
2
D0
Q0
EQ
D
3
D1
EQ
D
4
D2
EQ
D
5
D3
EQ
D
6
D4
EQ
D
7
D5
EQ
D
8
D6
EQ
D
9
D7
19
Q1
18
Q2
17
Q3
16
Q4
15
Q5
14
Q6
13
Q7
12
11
E
1
OE
SV00034
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
1998 Feb 19 4
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +4.6 V
IIK DC input diode current VI < 0 –50 mA
VIDC input voltage3–0.5 to +7.0 V
IOK DC output diode current VO < 0 –50 mA
VOUT DC output voltage3Output in Off or High state –0.5 to +7.0 V
IO
DC out
p
ut current
Output in Low state 128
mA
I
OUT
DC
o
u
tp
u
t
c
u
rrent
Output in High state –64
mA
Tstg Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN MAX
UNIT
VCC DC supply voltage 2.7 3.6 V
VIInput voltage 0 5.5 V
VIH High-level input voltage 2.0 V
VIL Input voltage 0.8 V
IOH High-level output current –32 mA
IO
Low-level output current 32
mA
I
OL Low-level output current; current duty cycle ≤ 50%, f ≥ 1kHz 64
mA
∆t/∆vInput transition rise or fall rate; outputs enabled 10 ns/V
Tamb Operating free-air temperature range –40 +85 °C
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
1998 Feb 19 5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
VIK Input clamp voltage VCC = 2.7V ; IIK = –18mA –0.9 –1.2 V
VCC = 2.7 to 3.6V ; IOH = –100µA VCC-0.2 VCC-0.1
VOH High-level output voltage VCC = 2.7V ; IOH = –8mA 2.4 2.5 V
VCC = 3.0V ; IOH = –32mA 2.0 2.2
VCC = 2.7V ; IOL = 100µA 0.1 0.2
VCC = 2.7V ; IOL = 24mA 0.3 0.5
VOL Low-level output voltage VCC = 3.0V ; IOL = 16mA 0.25 0.4 V
VCC = 3.0V ; IOL = 32mA 0.3 0.5
VCC = 3.0V ; IOL = 64mA 0.4 0.55
VRST Power-up output low voltage5VCC = 3.6V; IO = 1mA; VI = GND or VCC 0.13 0.55 V
VCC = 0 or 3.6V ; V I = 5.5V 1 10
I
Itlk t
VCC = 3.6V ; V I = VCC or GND Control pins ±0.1 ±1
A
IIInput leakage current VCC = 3.6V ; V I = VCC
Data
p
ins4
0.1 1 µA
VCC = 3.6V ; V I = 0
Data
pins4
–1 -5
IOFF Output off current VCC = 0V; VI or VO = 0 to 4.5V 1±100 µA
7
VCC = 3V ; VI = 0.8V 75 150
IHOLD Bus Hold current A inputs
7
VCC = 3V ; VI = 2.0V –75 –150 µA
VCC = 0V to 3.6V ; V CC = 3.6V ±500
IEX Current into an output in the
High state when VO > VCC VO = 5.5V ; V CC = 3.0V 60 125 µA
IPU/PD Power up/down 3-State output
current3VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC;
OE/OE = Don’t care 1±100 µA
IOZH 3-State output High current VCC= 3.6V; VO = 3V; VI = VIL or VIH 1 5
µA
IOZL 3-State output Low current VCC= 3.6V ; VO = 0.5V; VI = VIL or VIH –1 –5 µ
A
ICCH VCC = 3.6V ; Outputs High, VI = GND or VCC, IO = 0 0.13 0.19
ICCL Quiescent supply current VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 3 12 mA
ICCZ VCC = 3.6V ; Outputs Disabled; VI = GND or VCC, IO = 050.13 0.19
∆ICC Additional supply current per
input pin2VCC = 3V to 3.6V ; One input at V CC-0.6V,
Other inputs at VCC or GND 0.1 0.2 mA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ±0.3V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only
4. Unused pins at VCC or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
6. ICCZ is measured with outputs pulled to VCC or GND.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
1998 Feb 19 6
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; Tamb = –40°C to +85°C. LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT
MIN TYP1MAX MAX
tPLH
tPHL Propagation delay
Dn to Qn 21.0
1.0 2.5
2.7 4.2
4.3 4.7
5.2 ns
tPLH
tPHL Propagation delay
E to Qn 11.6
2.5 3.5
4.3 5.6
6.5 6.3
7.2 ns
tPZH
tPZL Output enable time
to High and Low level 4
51.0
1.3 2.8
3.3 5.1
5.5 6.2
6.6 ns
tPHZ
tPLZ Output disable time
from High and Low level 4
52.0
1.5 3.7
3.0 5.7
4.6 6.7
5.1 ns
NOTE:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; Tamb = –40°C to +85°C. LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT
MIN MAX MIN
tS(H)
tS(L) Setup time, High or Low, Dn to E 30.7
0.7 0.6
0.6 ns
TH(H)
TH(L) Hold time, High or Low, Dn to E 31.6
1.6 1.8
1.8 ns
TW(H) E pulse width High 1 3.3 3.3 ns
AC WAVEFORMS
VM = 1.5V, VIN = GND to 2.7V
tPHL
tw(H)
tPLH
E
Qn
1.5V
2.7V
0V
1.5V1.5V
1.5V1.5V
VOH
VOL
SV00035
W aveform 1. Propagation Delay, Enable to Output, and Enable
Pulse Width
Dn
tPLH tPHL
Qn
1.5V 1.5V
1.5V 1.5V
2.7V
0V
VOL
VOH
SV00117
W aveform 2. Propagation Delay for Data to Outputs
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
Dn
E
ts(H) th(H) ts(L) th(L)
1.5V 1.5V 1.5V 1.5V
1.5V1.5V
2.7V
2.7V
0V
0V
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SV00118
W aveform 3. Data Setup and Hold Times
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
1998 Feb 19 7
OE
tPZH tPHZ
0V
VOH –0.3V
Qn
1.5V 1.5V
1.5V
2.7V
0V
VOH
SV00119
W aveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
OE
tPZL tPLZ
VOL +0.3V
Qn
1.5V 1.5V
1.5V
2.7V
0V
VOL
3V
SV00120
W aveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
VMVM
tWAMP (V)
NEGATIVE
PULSE 10% 10%
90% 90%
0V
VMVM
tW
AMP (V)
POSITIVE
PULSE
90% 90%
10% 10% 0V
tTHL (tF)
tTLH (tR)t
THL (tF)
tTLH (tR)
VM = 1.5V
Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
74LVT
PULSE
GENERATOR
VIN
D.U.T.
VOUT
CL
VCC
RL
Test Circuit for 3-State Outputs
6.0V
RTRL
SV00092
Open
GND
SWITCH POSITION
TEST SWITCH
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Amplitude Rep. Rate tWtRtF
2.7V 10MHz 500ns 2.5ns 2.5ns
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
1998 Feb 19 8
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
1998 Feb 19 9
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
1998 Feb 19 10
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
1998 Feb 19 11
NOTES
Philips Semiconductors Product specification
74LVT573
3.3V Octal D-type transparent latch
(3-State)
yyyy mmm dd 12
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-03538
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
