LT1815/LT1816/LT1817
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Layout and Passive Components
As with all high speed amplifi ers, the LT1815/LT1816/
LT1817 require some attention to board layout. A ground
plane is recommended and trace lengths should be mini-
mized, especially on the negative input lead.
Low ESL/ESR bypass capacitors should be placed directly
at the positive and negative supply (0.01μF ceramics are
recommended). For high drive current applications, ad-
ditional 1μF to 10μF tantalums should be added.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input combine with the
input capacitance to form a pole that can cause peaking
or even oscillations. If feedback resistors greater than 1k
are used, a parallel capacitor of value:
C
F > RG • CIN/RF
should be used to cancel the input pole and optimize dy-
namic performance. For applications where the DC noise
gain is 1 and a large feedback resistor is used, CF should
be greater than or equal to CIN. An example would be an
I-to-V converter.
Input Considerations
The inputs of the LT1815/LT1816/LT1817 amplifi ers are
connected to the base of an NPN and PNP bipolar transis-
tor in parallel. The base currents are of opposite polarity
and provide fi rst-order bias current cancellation. Due to
variation in the matching of NPN and PNP beta, the polar-
ity of the input bias current can be positive or negative.
The offset current, however, does not depend on beta
matching and is tightly controlled. Therefore, the use of
balanced source resistance at each input is recommended
for applications where DC accuracy must be maximized.
For example, with a 100Ω source resistance at each input,
the 800nA maximum offset current results in only 80μV of
extra offset, while without balance the 8μA maximum input
bias current could result in a 0.8mV offset contribution.
The inputs can withstand differential input voltages of
up to 6V without damage and without needing clamping
or series resistance for protection. This differential input
voltage generates a large internal current (up to 80mA),
which results in the high slew rate. In normal transient
APPLICATIONS INFORMATION
closed-loop operation, this does not increase power dis-
sipation signifi cantly because of the low duty cycle of the
transient inputs. Sustained differential inputs, however,
will result in excessive power dissipation and therefore
this device should not be used as a comparator.
Capacitive Loading
The LT1815/LT1816/LT1817 are optimized for high band-
width and low distortion applications. They can drive a
capacitive load of 10pF in a unity-gain confi guration and
more with higher gain. When driving a larger capacitive
load, a resistor of 10Ω to 50Ω should be connected be-
tween the output and the capacitive load to avoid ringing
or oscillation. The feedback should still be taken from the
output so that the resistor will isolate the capacitive load
to ensure stability.
Slew Rate
The slew rate of the LT1815/LT1816/LT1817 is propor-
tional to the differential input voltage. Therefore, highest
slew rates are seen in the lowest gain confi gurations.
For example, a 5V output step in a gain of 10 has a 0.5V
input step, whereas in unity gain there is a 5V input step.
The LT1815/LT1816/LT1817 are tested for a slew rate
in a gain of –1. Lower slew rates occur in higher gain
confi gurations.
Programmable Supply Current
(LT1815/LT1816A)
In order to operate the LT1815S6 or LT1816A at full speed
(and full supply current), connect the ISET pin to the nega-
tive supply through a resistance of 75Ω or less.
To adjust or program the supply current and speed of the
LT1815S6 or LT1816A, connect an external resistor (RSET)
between the ISET pin and the negative supply, as shown in
Figure 1. The amplifi ers are fully functional with 0 ≤ RSET
≤ 40k. Figures 2 and 3 show how the gain bandwidth and
supply current vary with the value of the programming
resistor RSET. In addition, the Electrical Characteristics sec-
tion of the data sheet specifi es maximum supply current
and offset voltage, as well as minimum gain bandwidth
and output current at the maximum RSET value of 40k.