3. Current Sense Application
In the driver circuit presented below, the Si8920 is used to amplify the voltage across the sense resistor, RSENSE, and transmit the
analog signal to the low-voltage domain across an isolation barrier. Isolation is needed because the voltage of RSENSE with respect to
ground will swing between 0 V and the high voltage rail connected to the drain of Q1.
C4
0.1uF
C2
0.1uF
C3
0.1uF
R3
1.82K
Si8234
PWM
GNDI
DISABLE
VOB
VDDI
GNDB
VDDB
VDDI
DT
GNDA
VOA
VDDA
Si8920
VDDA
AIP
GNDA
AOP 7
GNDB 5
VDDB 8
AIN AON 6
Q1
Q2
C5
0.1uF
R6
C6
R4
R5
C1
10nF
R1 20
R2 20
RSENSE
D1
5.6V
Q3
Load
ADC
To
Controller
3.3 to 5V
Supply
Low Side
Gate Driver
Supply
Floating
Gate Driver
24V Supply
High
Voltage Bus
1
2
3
4
+
_
Figure 3.1. Current Sense Application
The load in this application can be a motor winding or a similar inductive winding. In a three-phase motor drive application, this circuit
would be repeated three times, one for each phase. RSENSE should be a small resistor value to reduce power loss. However, an ex-
cessively low resistance will reduce the signal-to-noise ratio of the measurement. Si8920 offers two specified full-scale input options,
±100 mV (Si8920A) and ±200 mV (Si8920B), for optimizing the value of RSENSE.
AIP and AIN connections to the RSENSE resistor should be made as close as possible to each end of the RSENSE resistor as trace
resistance will add error to the measurement. The input to the Si8920 is differential, and the PCB traces back to the input pins should
run in parallel. This ensures that any large noise transients that occur on the high-voltage side are coupled equally to the AIP and AIN
pins and will be rejected by the Si8920 as a common-mode signal.
The amplifier bandwidth of the Si8920 is approximately 950 kHz. If further input filtering is required, a passive, differential RC low-pass
filter can be placed between RSENSE and the input pins. Values of R1 = R2 = 20 Ω and C1 = 10 nF, as shown in Figure 4.8 Step
Response Low to High on page 11, provides a cutoff at approximately 400 kHz. For the lowest gain error, R1 and R2 should always
be less than 33 Ω to keep the source impedance sufficiently low compared to the Si8920 input impedance.
The common-mode voltage of AIN and AIP must be greater than –0.2 V but less than 1 V with respect to GNDA. To meet this require-
ment, connect GNDA of the Si8920 to one side of the RSENSE resistor. In this example, GNDA, RSENSE, the source of Q1, and the
drain of Q2 are connected. The ground of the gate driver (Silicon Labs’ Si8234 in this circuit) is also commonly connected to the same
node.
The Q1 gate driver has a floating supply, 24 V in this example. Since the input and output of the Si8920 are galvanically isolated from
each other, separate power supplies are necessary on each side. Q3, R3, C3, and D1 make a regulator circuit for powering the input
side of the Si8920 from this floating supply. D1 establishes a voltage of 5.6 V at the base of Q3. R3 is selected to provide a Zener
current of 10 mA for D1. C3 provides filtering at the base of Q3, and the emitter output of Q3 provides approximately 5 V to VDDA. C2
is a bypass capacitor for the supply and should be placed at the VDDA pin with its return trace connecting to the GNDA connection at
RSENSE.
C4, the local bypass capacitor for the B-side of Si8920, should be placed closed to VDDB supply pin with its return close to GNDB. The
output signal at AOP and AON is differential with a nominal gain of 8.1 (Si8920B) or 16.2 (Si8920A) and common mode of 1.1 V. The
outputs are sampled by a differential input ADC. Depending on the sample rate of the ADC, an anti-aliasing filter may be required. A
simple anti-aliasing filter can be made from the passive components, R4, C6, and R5. The characteristics of this filter are dictated by
the input topology and sampling frequency of the ADC. However, to ensure the Si8920 outputs are not overloaded, R4 = R5 > 5 kΩ and
C6 can be calculated by the following equation:
C6 = 1
2 × π×
(
R4 + R5
)
×f3dB
Si8920 Data Sheet
Current Sense Application
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