Am26LS32 e AmM26LS33 Quad Differential Line Receivers DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION Input voltage range of 15V (differential or common mode) The Am26LS32 is a quad line receiver designed to meet the on Am26LS33; 7V (differential or common mode) on requirements of RS-422 and RS-423, and Federal Standards Am26LS32 1020 and 1030 for balanced and unbalanced digital data @ +0.2V sensitivity over the input voltage range on AM26LS32; transmission. +0.5V sensitivity on Am26LS33 ; o. The Am26LS32 meets all the requirements of RS-422 and The Am26LS32 features an input sensitivity of 200mV over RS-423 the input voltage range of +7V. 6k minimum input impedance The Am26LS33 features an input sensitivity of 500mV over @ 30mV input hysteresis the input voltage range of 15V. e i i + . . Operation from single +5V supply The Am26LS32 and Am26LS33 provide an enable and disable @ 16-pin hermetic and molded DIP package . i . : 7 : function common to all four receivers. Both parts feature 3- Fail safe input-output relationship. Output always high ith : ae . . when inputs are open. state outputs wit 8mA sink capability and incorporate a fail Three-state drive, with choice of complementary output safe input-output relationship which keeps the outputs high enables, for receiving directly onto a data bus. when the inputs are open. @ Propagation delay 17ns typical The Am26LS32 and Am26LS33 are constructed using Ad- Available in military and commercial temperature range vanced Low-Power Schottky processing. @ Advanced low-power Schottky processing @ 100% reliability assurance screening to MIL-STD-883 requirements LOGIC DIAGRAM ENABLE ENABLE IND IND. Wer INCL INg+ INg_ INae Na GND Voc OUTPUT D OUTPUT C OUTPUT B OUTPUT 4 BLI-024 ORDERING INFORMATION CONNECTION DIAGRAM Top View Am26L$32 Am26L533 ] vec INPUTS A Package Temperature Order Order O a | NPUT: Type Range Number Number outeuta FJ 7 | INPUTS B Hermetic DIP 55C to+125C AM26LS32DM AM26LS33DM o 4 output a Flat Pak 55C to +125C }~=AM26LS32FM AM26LS33FM ENABLE Dice BBC to +125C AM26LS32XM AM26LS33XM output [J 5 [} ENABLE Hermetic DIP OC to +70C AM26LS32DC AM26LS33DC O 0 output b Molded DIP OC to+70C AM26LS32PC AM26LS33PC NPUTSC Dice OC to +70C AM26LS32XC AM26LS33XC Oo \ 7 INPUTS D eno TJ Note: Pin 1 is marked for orientatian. LiC-360Am26LS32 e Am26LS33 ABSOLUTE MAXIMUM RATINGS (Above which the useful life may be impaired) Supply Voltage 7.0V Common Mode Range - +25V Differential Input Voltage +25V Enable Voltage 7.0V Output Sink Current 7 50mA Storage Temperature Range ~65 C to +165C ELECTRICAL CHARACTERISTICS Over the operating temperature range The following conditions apply unless otherwise specified: Am26LS32XM, AM26LS33XM (MIL) Am26LS32XC, AM26LS33XC (COML) Ta = 55C to +125C Tas Veco = 5.0V + 10% c to +70C Vec = 5.0V + 5% Typ. Parameters Description Test Conditions Min. (Note 1) Max. Units / ; Am26LS32, 7V < Vom < +7V 0.2 0.06 0.2 VTH Differential Input Voltage Vout = You or Vou Volts Am26LS33, 15V < Voy < +15V 0.5 0.12 0.5 Rin input Resistance 15V < Vom < +15V (One input AC ground) 6.0k 8.5k 2 HN input Current (Under Test} Vin = +15V, Other Input -15V < Vin < +15V 2.3 mA lin Input Current (Under Test) Vin = 15V, Other Input 15V < Vin < +15V 2.8 mA Vcc = Min., AVipqy = +1.0V COM'L 2.7 3.4 Vou Output HIGH Voltage Volts VENABLE = 0.8V, IOH * 440uA MIL 25 3.4 Vec =Min., AVin = -1.0V lo = 4.0mA 0.4 VOL Output LOW Voltage ce 'N Volts VENABLE = 0.8V loL =8.0mA 0.45 VIL Enable LOW Voltage 0.8 Volts Vin Enable HIGH Voltage 2.0 Volts | vy Enable Clamp Voltage Vec = Min., ty = 18mA -1.5 | Volts ; ; Vo =2.4v 20 lo : Off-State (High Impedance) Voc = Max. oO LA Output Current Vo =04v 20 He Enable LOW Current VIN =0.4V 0.2 0.36 mA IH Enable HIGH Current Vin =2.7V 05 20 uA lay Enable Input High Current Vin = 5.5V 1 100 uA Isc Output Short Cireuit Current Vo = OV, Voc = Max., AViny = +1.0V -15 -50 85 mA lec Power Supply Current Vec = Max., All Viqy = GND, Outputs Disabled 52 70 mA VuyYst Input Hysteresis Ta = 28C, Voc = 5.0V, Vom = OV 30 mV | tly Input to Output Ta= 25C, Vec =5.0V,C_ = 15pF, see test cond. below 17 25 ns tPHL Input to Output Ta = 25C, Voc =5.0V, CL = 15pF, see test cond. below 17 25 ns tLz Enable to Output Ta= 25C, Voc =5.0V,C, = 5SpF, see test cond. below 20 30 ns tHz Enable to Output Tat 25C, Vec =5.0V,C_ = SpF, see test cond. below 15 22 ns tz Enable to Output Ta = 25C, Voc = 5.0V, CL = 15pF, see test cond. below 15 22 ns t2H Enable to Output Ta = 28C, Voc = 5.0V, CL = 15pF, see test cond. below 15 22 ns Note: 1. All typical values are Vag = 5.0V, Ta = 25C. LOAD TEST CIRCUIT PROPAGATION DELAY ENABLE AND DISABLE TIMES FOR THREE-STATE OUTPUTS (Notes 1 and 3) (Notes 2 and 3) TEST Vou -- 30v POINT vec - _ ENABLE _ _ v 3 5, vous ouTPuT f-*- ae INPUT J \ 13 FROM OUTPUT A Ly aon . ty yl ov UNDER TEST PLH PHL ZL "LZ OPPOSITE I +2.5V output ~a5y : asy OL INCLUDES be ALL DIODES INPUT 7 KO? ov NORMALLY ay - ~15V PROBE AND WIG 2 1 IN9IGGR TRANSITION fi. -25v LOW 59 OPEN Po gy CAPACITANCE 5.0K2 1*43064 | {tas tz =| | T V LIC-362 ouTPuT ie oo on RMA V3V ~1be sz xo hGH S,OPEN/| nov cay 8 = = LIC-363 LIC-361 Notas: 1. Diagram shawn for Enable LOW. 2. $1 and Sz of Laad Circuit are closed except where shown. 3. Pulse Generator for All Pulses: Rate < 1.0MHz; Zo = 500; t; < 150s; te S 6.0ns. 4-41Am26LS32 e Am26LS33 N EQUIVALENT CIRCUIT (1/4 Am26LS32 OR Am26LS33) Ry v F209 16 A ; Oo Sr, Ss jf Re a $85 $F Ala Rig Ria - 4 D J a1 , Ra RS a4 a3 L. 2 Og Q3 Ong Rat < >R > Or4 __ any a, on a2 at By Z 3 a oFis oO os Ea | on < Og an awl D Ris > < Ry Rig $ Fa R2g 3 16 8 O TO OTHER 3 CIRCUITS Note: Ag and Rg value for AM26LS32 is 2 times AM26LS33 value. BLI-025 DaTa INPUT TYPICAL APPLICATION W4 Am26LS231 14 4m26L532 DATA Out CATA QUT OATA OUT SHIELD GR COMMON GROUND RETURN LIC-364 4-42Am26LS32 e Am26LS33 ERGBLE Oats 14 am28L531 t4 4rr 26L529 Two Wire Balanced System. D4T4 OUTPUT DATA | | Ls | L [ Single Wire With Common Ground Unbalanced System. LIC-365 |~ 2 DATA OUTPUT 14 | Am26LS32 I 1 GROUNG PETURN COMMON T VERAL SIGKAL\, O SEVERAL SIGRGL WIRES. LIC-366 LINE TERMINATION It is important in a digital communication system to have the minimum amount of noise generated by undesired reflections at the driver and receiver. There are numerous ways of match- ing to the line. The line can be matched at the driver, at the receiver or both, each method has advantages and disadvan- tages. Generally for any but the longest lines it is sufficient to match at one place, and only when there are discontinuities in the line, party line operation, or lack of a reasonable match at the opposite end of the line is the extra hardware of match- ing at both ends justified. The majority of transmission lines have fairly low characteristic impedances {in the range of 50 to 200 ohms) and the currents involved for a reasonable voltage swing are quite large. It is more difficult to couple noise into this low impedance, but it is also more difficult to drive, and line drivers must have the ability to supply large currents. Various matching techniques that can be employed are shown in Figure 1. These impedance charts are useful in showing what happens to wave fronts traveling down a tine, when the line delay is longer than the wave front transition. The DC input characteristic of the receiver, including any external compo- nents, is plotted on the V-I graph together with the output characteristic of the driver, including any external components used at the driving end. There are always quiescent points points where the driver and receiver characteristics cross. These points represent the DC voltage/current conditions, which must eventually be satisfied. To determine the effect of switching from one quiescent point to the other, a line with a slope equal to the characteristic impedance of the transmission line is plotted, starting at the initial quiescent point and ending at the applicable output impedance characteristic. The point of intersection gives the voltage and current at the output of the driver (and the input of the transmission line immediately after the driver switched states). From this point a line having an equal but opposite slope is drawn to the input characteristic and, at the intersection shows the voltage/current conditions of the wave front at the input of the receiver. This procedure is repeated to the output characteristic and so on at each intersection of the characteristic, the voltage/current relation- ship for a particular reflection is given. The resulting time/ 4-43 voltage relationships for the traveling wavefront at the two ends of the transmission line are shown alongside. From the graphs several important features can be seen. If the line is not matched at either end considerable transient voltage swings can occur. In fact if the input and output character- istics are at right angles to one another, the reflections con- tinue for an infinite time if the line is assumed to have zero loss. Most lines have extremely low losses, and, therefore, a very undesirable situation exists if the line is not matched at either end. lf the line is matched at the receiver, a voltage wave of con- stant amplitude travels down the line and is absorbed at the termination. Note whether the line is terminated to ground or to the power supply the system consumes DC power, either in the HIGH lagic level or in the LOW logic level. In arder to reduce the power dissipation, a blocking capacitor can be used in series with the receiver termination. The capacitor can be chosen to look like a short circuit to the voltage wavefront but stop DC (current) flow. Since the capacitor must be charged and discharged through the line, the data rate is reduced, when this technique is employed. If the line is matched with a series resistor at the driver, then the line input initially rises to one half the final voltage. This wave front travels down the line and is reflected at the receiver. When the reflection reaches the driver the valtage at the driver rises to its final amplitude. The receiver, however, sees one transition from the initial to the final amplitude. When the driver switches from HIGH to LOW a similar situation occurs, in which the input of the line sees at first a step to one half the final value and, two line detays tater, the final LOW condition. This back matching mode of operation consumes no DC power if the input impedance of the receiver is infinite. The advantage of the method is that if the input impedance of the receiver is high, very little power is dissipated and current only flows during the transition time, which is twice the line delay time. If back matching is used in a balanced system the terminating series resistance must be divided into two equal resistances with resistors inserted in series with each wire in order to maintain a balanced system.Am26LS32 Am26LS33 SWITCHING FROM LOW TO HIGH SWITCHING FROM HIGH TO Low VOLTAGE VERSUS TIME t Zout L Zout 1 Zour ZoutH > P>- " INPUT Zo Uf. OF LINE t = NO MATCHING a > Zin ~ v v Zo # Zo * ZoH * Zin ff OUTPUT c4 OF LINE | = ' Zout kh ZoutH ' ZoutL ZoutH v 2 Zin + + INPUT OF LINE Zin Zin MATCHING AT RECEIVER TO GROUND * v v v 29 * Zin * ZoL * ZoH ouTPuT OF LINE vt 1 Zouth ZoutH Zout Zout H 2 1 v in Zo - + Zn INPUT S OF LINE _ . MATCHING AT SSS RECEIVER TO SUPPLY v v v Zo* Zin # Zo # Zon OUTPUT OF LINE ' Zout L Zout H ' ZoutL Zout v | > > INPUT * OF LINE MATCHING AT DRIVER Zin Zin v 2g * Zon = 20 * Zin OUTPUT OF LINE t (MPEDANCE PLOTS Figure 1. Line Matching Methods LIC-367 Metallization and Pad Layout | 1 vec 6 \ ANPUTS & 16 | INPUTS B l2 OUTPLT A 3 OUTPUT B ENABLE 4 ENABLE OUTPUT C 5 ouTPUT D INPUTS C a weutso CD'S SIZE GND 0.087" xX 0.059" ~ ry