24-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
●24 BITS NO MISSING CODES
●SIMULTANEOUS 50Hz AND 60Hz REJECTION
(–90dB MINIMUM)
●0.0015% INL
●21 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
●PGA GAINS FROM 1 TO 128
●SINGLE CYCLE SETTLING
●PROGRAMMABLE DATA OUTPUT RATES
●EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 5V
●ON-CHIP CALIBRATION
●SPI™ COMPATIBLE
●2.7V TO 5.25V SUPPLY RANGE
●600µW POWER CONSUMPTION
●UP TO EIGHT INPUT CHANNELS
●UP TO EIGHT DATA I/O
DESCRIPTION
The ADS1240 and ADS1241 are precision, wide dynamic range,
delta-sigma, Analog-to-Digital (A/D) converters with 24-bit resolution
operating from 2.7V to 5.25V power supplies. The delta-sigma A/D
converter provides up to 24 bits of no missing code performance and
effective resolution of 21 bits.
The input channels are multiplexed. Internal buffering can be
selected to provide very high input impedance for direct connection
to transducers or low-level voltage signals. Burnout current sources
are provided that allow for detection of an open or shorted sensor.
An 8-bit Digital-to-Analog (D/A) converter provides an offset cor-
rection with a range of 50% of the Full-Scale Range (FSR).
The Programmable Gain Amplifier (PGA) provides selectable gains of
1 to 128, with an effective resolution of 19 bits at a gain of 128. The
A/D conversion is accomplished with a 2nd-order delta-sigma modu-
lator and programmable Finite-Impulse Response (FIR) filter that
provides a simultaneous 50Hz and 60Hz notch. The reference input
is differential and can be used for ratiometric conversion.
The serial interface is SPI compatible. Up to eight bits of data
I/O are also provided that can be used for input or output. The
ADS1240 and ADS1241 are designed for high-resolution measure-
ment applications in smart transmitters, industrial process control,
weigh scales, chromatography, and portable instrumentation.
APPLICATIONS
●INDUSTRIAL PROCESS CONTROL
●WEIGH SCALES
●LIQUID/ GAS CHROMATOGRAPHY
●BLOOD ANALYSIS
●SMART TRANSMITTERS
●PORTABLE INSTRUMENTATION
BUF PGA
A = 1:128
+
Clock Generator
Serial Interface
2nd-Order
Modulator
AGNDAV
DD
V
REF+
V
REF–
X
IN
X
OUT
DSYNCPDWN RESET DRDYBUFEN DGNDDV
DD
SCLK
POL
D
IN
D
OUT
CS
MUX
A
IN
0/D0
A
IN
1/D1
A
IN
2/D2
A
IN
3/D3
A
IN
4/D4
A
IN
5/D5
A
IN
6/D6
A
IN
7/D7
A
INCOM
Controller Registers
Digital
Filter
2µA
AV
DD
Offset
DAC
AGND
2µA
ADS1241
Only
ADS1241
ADS1240
ADS1240
ADS1241
SBAS173E – JUNE 2001 – REVISED AUGUST 2006
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2006, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks property of their respective owners.
ADS1240, 1241
2SBAS173E
www.ti.com
DIGITAL CHARACTERISTICS: –40°C to +85°C, DVDD 2.7V to 5.25V
PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Input/Output
Logic Family CMOS
Logic Level: VIH 0.8 • DVDD DVDD V
VIL DGND 0.2 • DVDD V
VOH IOH = 1mA DVDD – 0.4 V
VOL IOL = 1mA DGND DGND + 0.4 V
Input Leakage: IIH VI = DVDD 10 µA
IIL VI = 0 –10 µA
Master Clock Rate: fOSC 15MHz
Master Clock Period: tOSC 1/fOSC 200 1000 ns
AVDD to DGND ...................................................................... –0.3V to +6V
DVDD to DGND...................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary
DGND to AGND ....................................................................–0.3V to 0.3V
Input Current ................................................................. 10mA, Continuous
AIN .................................................................AGND –0.5V to AVDD + 0.5V
Digital Input Voltage to DGND .................................–0.3V to DVDD + 0.3V
Digital Output Voltage to DGND ..............................–0.3V to DVDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +150°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
For the most current package and ordering information, see
the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.
PACKAGE/ORDERING INFORMATION
ADS1240, 1241 3
SBAS173E www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +2.5V, unless otherwise specified.
ADS1240
ADS1241
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
(AIN0 – AIN7, AINCOM)
Analog Input Range Buffer OFF AGND – 0.1 AVDD + 0.1 V
Buffer ON AGND + 0.05 AVDD – 1.5 V
Full-Scale Input Range
(In+) – (In–), See Block Diagram, RANGE = 0
±VREF/PGA V
RANGE = 1
±V
REF
/(2 • PGA)
V
Differential Input Impedance Buffer OFF 5/PGA MΩ
Buffer ON 5 GΩ
Bandwidth
fDATA = 3.75Hz –3dB 1.65 Hz
fDATA = 7.50Hz –3dB 3.44 Hz
fDATA = 15.00Hz –3dB 14.6 Hz
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance 9pF
Input Leakage Current Modulator OFF, T = 25°C5 pA
Burnout Current Sources 2µA
OFFSET DAC
Offset DAC Range RANGE = 0 ±VREF/(2 • PGA) V
RANGE = 1 ±VREF/(4 • PGA) V
Offset Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 1 ppm/°C
SYSTEM PERFORMANCE
Resolution No Missing Codes 24 Bits
Integral Nonlinearity End Point Fit ±0.0015 % of FS
Offset Error (1) 7.5 ppm of FS
Offset Drift(1) 0.02 ppm of FS/°C
Gain Error 0.005 %
Gain Error Drift(1) 0.5 ppm/°C
Common-Mode Rejection at DC 100 dB
fCM = 60Hz, fDATA = 15Hz 130 dB
fCM = 50Hz, fDATA = 15Hz 120 dB
Normal-Mode Rejection fSIG = 50Hz, fDATA = 15Hz 100 dB
fSIG = 60Hz, fDATA = 15Hz 100 dB
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆VOUT/∆VDD)(2) 80 95 dB
VOLTAGE REFERENCE INPUT
VREF
VREF ≡ (REF IN+) – (REF IN–), RANGE = 0
0.1 2.5 2.6 V
Reference Input Range REF IN+, REF IN– 0 AVDD V
RANGE = 1 0.1 AVDD V
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection fVREFCM = 60Hz, fDATA = 15Hz 120 dB
Bias Current(3) VREF = 2.5V 1.3 µA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AVDD 4.75 5.25 V
Analog Current PDWN = 0, or SLEEP 1 nA
PGA = 1, Buffer OFF 120 250 µA
PGA = 128, Buffer OFF 400 675 µA
PGA = 1, Buffer ON 160 300 µA
PGA = 128, Buffer ON 760 1275 µA
Digital Current Normal Mode, DVDD = 5V 80 125 µA
SLEEP Mode, DVDD = 5V 60 µA
Read Data Continuous Mode, DVDD = 5V
230 µA
PDWN 0.5 nA
Power Dissipation PGA = 1, Buffer OFF, DVDD = 5V 1.1 1.9 mW
NOTES: (1) Calibration can minimize these errors to the level of the noise.
(2) ∆VOUT is a change in digital result.
(3) 12pF switched capacitor at fSAMP clock frequency.
ADS1240, 1241
4SBAS173E
www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +1.25V, unless otherwise specified.
ADS1240
ADS1241
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
(AIN0 – AIN7, AINCOM)
Analog Input Range Buffer OFF AGND – 0.1 AVDD + 0.1 V
Buffer ON AGND + 0.05 AVDD – 1.5 V
Full-Scale Input Voltage Range
(In+) – (In–) See Block Diagram, RANGE = 0
±VREF/PGA V
RANGE = 1
±V
REF
/(2 • PGA)
V
Input Impedance Buffer OFF 5/PGA MΩ
Differential Buffer ON 5 GΩ
Bandwidth
fDATA = 3.75Hz –3dB 1.65 Hz
fDATA = 7.50Hz –3dB 3.44 Hz
fDATA = 15.00Hz –3dB 14.6 Hz
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance 9pF
Input Leakage Current Modulator OFF, T = 25°C5 pA
Burnout Current Sources 2µA
OFFSET DAC
Offset DAC Range RANGE = 0 ±VREF/(2 • PGA) V
RANGE = 1 ±VREF/(4 • PGA) V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 2 ppm/°C
SYSTEM PERFORMANCE
Resolution No Missing Codes 24 Bits
Integral Nonlinearity End Point Fit ±0.0015 % of FS
Offset Error(1) 15 ppm of FS
Offset Drift(1) 0.04 ppm of FS/°C
Gain Error 0.01 %
Gain Error Drift(1) 1.0 ppm/°C
Common-Mode Rejection at DC 100 dB
fCM = 60Hz, fDATA = 15Hz 130 dB
fCM = 50Hz, fDATA = 15Hz 120 dB
Normal-Mode Rejection fSIG = 50Hz, fDATA = 15Hz 100 dB
fSIG = 60Hz, fDATA = 15Hz 100 dB
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log(∆VOUT/∆VDD)(2) 75 90 dB
VOLTAGE REFERENCE INPUT
VREF
VREF ≡ (REF IN+) – (REF IN–), RANGE = 0
0.1 1.25 1.30 V
Reference Input Range REF IN+, REF IN– 0 AVDD V
RANGE = 1 0.1 2.5 2.6 V
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection fVREFCM = 60Hz, fDATA = 15Hz 120 dB
Bias Current(3) VREF = 1.25 0.65 µA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AVDD 2.7 3.3 V
Analog Current PDWN = 0, or SLEEP 1 nA
PGA = 1, Buffer OFF 107 225 µA
PGA = 128, Buffer OFF 355 600 µA
PGA = 1, Buffer ON 118 275 µA
PGA = 128, Buffer ON 483 1225 µA
Digital Current Normal Mode, DVDD = 3V 50 100 µA
SLEEP Mode, DVDD = 3V 40 µA
Read Data Continuous Mode, DVDD = 3V
113 µA
PDWN = 0 0.5 nA
Power Dissipation PGA = 1, Buffer OFF, DVDD = 3V 0.6 1.2 mW
NOTES: (1) Calibration can minimize these errors to the level of the noise.
(2) ∆VOUT is a change in digital result.
(3) 12pF switched capacitor at fSAMP clock frequency.
ADS1240, 1241 5
SBAS173E www.ti.com
PIN CONFIGURATION (ADS1240)
PIN
NUMBER NAME DESCRIPTION
1DV
DD Digital Power Supply
2 DGND Digital Ground
3X
IN Clock Input
4X
OUT Clock Output, used with external crystals.
5 RESET Active LOW, resets the entire device.
6 DSYNC Active LOW, Synchronization Control
7 PDWN Active LOW, Power Down. The power down func-
tion shuts down the analog and digital circuits.
8 DGND Digital Ground
9V
REF+ Positive Differential Reference Input
10 VREF– Negative Differential Reference Input
11 AIN0/D0 Analog Input 0 / Data I/O 0
12 AIN1/D1 Analog Input 1 / Data I/O 1
13 AIN2/D2 Analog Input 2 / Data I/O 2
14 AIN3/D3 Analog Input 3 / Data I/O 3
15 AINCOM
Analog Input Common, connect to AGND if unused.
16 AGND Analog Ground
17 AVDD Analog Power Supply
18 POL Serial Clock Polarity
19 CS Active LOW, Chip Select
20 DIN Serial Data Input, Schmitt Trigger
21 DOUT Serial Data Output
22 SCLK Serial Clock, Schmitt Trigger
23 DRDY Active LOW, Data Ready
24 BUFEN Buffer Enable
PIN DESCRIPTIONS (ADS1240)
ADS1240
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DVDD
DGND
XIN
XOUT
RESET
DSYNC
PDWN
DGND
VREF+
VREF–
AIN0/D0
AIN1/D1
BUFEN
DRDY
SCLK
DOUT
DIN
CS
POL
AVDD
AGND
AINCOM
AIN3/D3
AIN2/D2
PIN CONFIGURATION (ADS1241)
ADS1241
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DVDD
DGND
XIN
XOUT
RESET
DSYNC
PDWN
DGND
VREF+
VREF–
AIN0/D0
AIN1/D1
AIN4/D4
AIN5/D5
BUFEN
DRDY
SCLK
DOUT
DIN
CS
POL
AVDD
AGND
AINCOM
AIN3/D3
AIN2/D2
AIN7/D7
AIN6/D6
PIN
NUMBER NAME DESCRIPTION
1DV
DD Digital Power Supply
2 DGND Digital Ground
3X
IN Clock Input
4X
OUT Clock Output, used with external crystals.
5 RESET Active LOW, resets the entire device.
6 DSYNC Active LOW, Synchronization Control
7 PDWN Active LOW, Power Down. The power down func-
tion shuts down the analog and digital circuits.
8 DGND Digital Ground
9V
REF+ Positive Differential Reference Input
10 VREF–Negative Differential Reference Input
11 AIN0/D0 Analog Input 0 / Data I/O 0
12 AIN1/D1 Analog Input 1 / Data I/O 1
13 AIN4/D4 Analog Input 4 / Data I/O 4
14 AIN5/D5 Analog Input 5 / Data I/O 5
15 AIN6/D6 Analog Input 6 / Data I/O 6
16 AIN7/D7 Analog Input 7 / Data I/O 7
17 AIN2/D2 Analog Input 2 / Data I/O 2
18 AIN3/D3 Analog Input 3 / Data I/O 3
19 AINCOM
Analog Input Common, connect to AGND if unused.
20 AGND Analog Ground
21 AVDD Analog Power Supply
22 POL Serial Clock Polarity
23 CS Active LOW, Chip Select
24 DIN Serial Data Input, Schmitt Trigger
25 DOUT Serial Data Output
26 SCLK Serial Clock, Schmitt Trigger
27 DRDY Active LOW, Data Ready
28 BUFEN Buffer Enable
PIN DESCRIPTIONS (ADS1241)
Top View SSOP Top View SSOP
ADS1240, 1241
6SBAS173E
www.ti.com
SPEC DESCRIPTION MIN MAX UNITS
t1SCLK Period 4t
OSC Periods
3 DRDY Periods
t2SCLK Pulse Width, HIGH and LOW 200 ns
t3CS low to first SCLK Edge; Setup Time(2) 0ns
t4DIN Valid to SCLK Edge; Setup Time 50 ns
t5Valid DIN to SCLK Edge; Hold Time 50 ns
t6Delay between last SCLK edge for DIN and first SCLK edge for DOUT:
RDATA, RDATAC, RREG, WREG 50 tOSC Periods
t7(1) SCLK Edge to Valid New DOUT 50 ns
t8(1) SCLK Edge to DOUT, Hold Time 0 ns
t9Last SCLK Edge to DOUT Tri-State 6 10 tOSC Periods
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
t10 CS LOW time after final SCLK edge.
Read from the device 0 tOSC Periods
Write to the device 8 tOSC Periods
t11 Final SCLK edge of one command until first edge SCLK
of next command:
RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC
4t
OSC Periods
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 2 DRDY Periods
SELFCAL 4 DRDY Periods
RESET (also SCLK Reset or RESET Pin) 16 tOSC Periods
t16 Pulse Width 4t
OSC Periods
t17 Allowed analog input change for next valid conversion. 5000 tOSC Periods
t18 DOR update, DOR data not valid. 4 tOSC Periods
t19 First SCLK after DRDY goes LOW:
RDATAC Mode 10 tOSC Periods
Any other mode 0 tOSC Periods
NOTES: (1) Load = 20pF10kΩ to DGND.
(2) CS may be tied LOW.
TIMING DIAGRAMS
TIMING CHARACTERISTICS TABLE
t
4
MSB
(Command or Command and Data)
LSB
t
5
t
1
t
3
CS
SCLK
(POL = 0)
D
IN
D
OUT
NOTE: (1) Bit order = 0.
SCLK Reset Waveform
t
7
MSB
(1)
LSB
(1)
t
8
t
10
t
2
t
2
t
11
t
6
t
9
SCLK
(POL = 1)
t
12
t
14
t
15
t
13
t
13
SCLK
ADS1240 or ADS1241
Resets On
Falling Edge 300 • t
OSC
< t
12
< 500 • t
OSC
t
13
: > 5 • t
OSC
550 • t
OSC
< t
14
< 750 • t
OSC
1050 • t
OSC
< t
15
< 1250 • t
OSC
DIAGRAM 1.
DIAGRAM 2.
t
17
t
18
DRDY
SCLK
t
DATA
t
16
RESET, DSYNC, PDWN
t
19
ADS1240, 1241 7
SBAS173E www.ti.com
TYPICAL CHARACTERISTICS
All specifications AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
22
21
20
19
18
17
16
15
EFFECTIVE NUMBER OF BITS vs PGA SETTING
PGA Setting
ENOB (rms)
1 2 4 8 16 1286432
DR = 10
DR = 00
DR = 01
Buffer ON
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
EFFECTIVE NUMBER OF BITS vs PGA SETTING
PGA Setting
1 2 4 8 16 1286432
ENOB (rms)
Buffer OFF
DR = 10
DR = 01
DR = 00
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
EFFECTIVE NUMBER OF BITS vs PGA SETTING
PGA Setting
1 2 4 8 16 64 12832
ENOB (rms)
Buffer OFF, VREF = 1.25V
DR = 10
DR = 00
DR = 01
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
NOISE vs INPUT SIGNAL
V
IN
(V)
–2.5 –1.5 0.5–0.5 1.5 2.5
Noise (rms, ppm of FS)
140
120
100
80
60
40
20
0
COMMON-MODE REJECTION RATIO
vs FREQUENCY
Frequency of Power Supply (Hz)
1 10 100 1k 10k 100k
CMRR (dB)
Buffer ON
POWER SUPPLY REJECTION RATIO
vs FREQUENCY
Frequency of Power Supply (Hz)
110 1k100 10k 100k
PSRR (dB)
140
120
100
80
60
40
20
0Buffer ON
ADS1240, 1241
8SBAS173E
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
All specifications AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
900
800
700
600
500
400
300
200
100
0
ANALOG CURRENT vs PGA
PGA Setting
IANALOG (µA)
1 2 4 8 16 1286432
AVDD = 5V, Buffer = ON
AVDD = 3V, Buffer = ON
Buffer = OFF
Buffer = OFF
1.00010
1.00006
1.00002
0.99998
0.99994
0.99990
0.99986
GAIN vs TEMPERATURE
(Cal at 25°C)
Temperature (°C)
–50 –30 10–10 30 50 70 90
Gain (Normalized)
50
0
–50
–100
–150
–200
OFFSET vs TEMPERATURE
(Cal at 25°C)
Offset (ppm of FS)
PGA1
PGA128
PGA64
Temperature (°C)
–50 –30 10–10 30 50 70 90
PGA16
10
8
6
4
2
0
–2
–4
–6
–8
–10
INTEGRAL NONLINEARITY vs INPUT SIGNAL
V
IN
(V)
–2.5 –2.0 –1.0 –0.5–1.5 0 0.5 1.0 1.5 2.0 2.5
INL (ppm of FS)
–40°C
+25°C
+85°C
150
140
130
120
110
100
90
80
70
60
50
ANALOG CURRENT vs TEMPERATURE
Current (µA)
Temperature (°C)
–50 –30 10–10 30 50 70 90
AVDD = 5
AVDD = 3
Buffer OFF
300
250
200
150
100
50
0
DIGITAL CURRENT vs SUPPLY
V
DD
(V)
3.0 3.5 4.0 4.5 5.0
I
DIGITAL
(µA)
Normal
4.91MHz Normal
2.45MHz
SLEEP
2.45MHz
Power Down
SLEEP
4.91MHz
ADS1240, 1241 9
SBAS173E www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
All specifications AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
OFFSET DAC
NOISE vs SETTING
Offset DAC Setting
Noise (rms, ppm of FS)
–128 –96 –64 –32 0 32 64 96 128
200
170
140
110
80
50
20
–10
–40
–70
–100
OFFSET DAC
OFFSET vs TEMPERATURE
(Cal at 25°C)
Offset (ppm of FSR)
Temperature (°C)
–50 –30 10–10 30 50 70 90
3500
3000
2500
2000
1500
1000
500
0
NOISE HISTOGRAM
10k Readings
VIN = 0V
ppm of FS
–3.5 –3.0
Number of Occurrences
–2.5 –2.0 –1.5 –1–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
1.00020
1.00016
1.00012
1.00008
1.00004
1.00000
0.99996
0.99992
0.99988
0.99984
0.99980
0.99976
OFFSET DAC
GAIN vs TEMPERATURE
(Cal at 25°C)
Gain (Normalized)
Temperature (°C)
–50 –30 10–10 30 50 70 90
ADS1240, 1241
10 SBAS173E
www.ti.com
channel. With this method, it is possible to have up to eight
single-ended input channels or four independent differential
input channels for the ADS1241, and four single-ended input
channels or two independent differential input channels for
the ADS1240. Note that AINCOM can be treated as an input
channel.
The ADS1240 and ADS1241 feature a single-cycle settling
digital filter that provides valid data on the first conversion
after a new channel selection. In order to minimize the
settling error, synchronize MUX changes to the conversion
beginning, which is indicated by the falling edge of
DRDY
. In
other words, issuing a MUX change through the WREG
command immediately after
DRDY
goes LOW minimizes the
settling error. Increasing the time between the conversion
beginning (
DRDY
goes LOW) and the MUX change com-
mand (tDELAY) results in a settling error in the conversion
data, as shown in Figure 2.
BURNOUT CURRENT SOURCES
The Burnout Current Sources can be used to detect sensor
short-circuit or open-circuit conditions. Setting the Burnout
Current Sources (BOCS) bit in the SETUP register activates
two 2µA current sources called burnout current sources. One
of the current sources is connected to the converter’s nega-
tive input and the other is connected to the converter’s
positive input.
Figure 3 shows the situation for an open-circuit sensor. This
is a potential failure mode for many kinds of remotely con-
nected sensors. The current source on the positive input acts
as a pull-up, causing the positive input to go to the positive
analog supply, and the current source on the negative input
acts as a pull-down, causing the negative input to go to
ground. The ADS1240/41 therefore outputs full-scale (7FFFFF
Hex).
OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differ-
ential inputs to be selected on any of the input channels, as
shown in Figure 1. For example, if AIN0 is selected as the
positive differential input channel, any other channel can be
selected as the negative terminal for the differential input
A
IN
3/D3
A
IN
4/D4
A
IN
5/D5
A
IN
6/D6
A
IN
0/D0
A
IN
1/D1
A
IN
2/D2
A
IN
7/D7
A
INCOM
Burnout Current Source
Burnout Current Source
AGND
AV
DD
ADS1241
Only
Input
Buffer
FIGURE 1. Input Multiplexer Configuration.
FIGURE 2. Input Multiplexer Configuration.
SETTLING ERROR vs DELAY TIME
fCLK = 2.4576MHz
Delay Time, tDELAY (ms)
Settling Error (%)
2 4 6 8 10 12 14 160
10.000000
1.000000
0.100000
0.010000
0.001000
0.000100
0.000010
0.000001
New Conversion Begins,
Complete Previous Conversion New Conversion Complete
tDELAY
MSB LSB
DRDY
DIN
SCLK
(POL = 0)
Previous Conversion Data
ADS1240, 1241 11
SBAS173E www.ti.com
Figure 4 shows a short-circuited sensor. Since the inputs are
shorted and at the same potential, the ADS1240/41 signal
outputs are approximately zero. (Note that the code for
shorted inputs is not exactly zero due to internal series
resistance, low-level noise and other error sources.)
The buffer draws additional current when activated. The
current required by the buffer depends on the PGA setting.
When the PGA is set to 1, the buffer uses approximately
50µA; when the PGA is set to 128, the buffer uses approxi-
mately 500µA.
PGA
The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the
effective resolution of the A/D converter. For instance, with a
PGA of 1 on a 5V full-scale signal, the A/D converter can
resolve down to 1µV. With a PGA of 128 and a full-scale signal
of 39mV, the A/D converter can resolve down to 75nV. AVDD
current increases with PGA settings higher than 4.
OFFSET DAC
The input to the PGA can be shifted by half the full-scale input
range of the PGA using the Offset DAC (ODAC) register. The
ODAC register is an 8-bit value; the MSB is the sign and the
seven LSBs provide the magnitude of the offset. Using the
offset DAC does not reduce the performance of the A/D
converter. For more details on the ODAC, please refer to TI
application report SBAA077.
MODULATOR
The modulator is a single-loop second-order system. The
modulator runs at a clock speed (fMOD) that is derived from
the external clock (fOSC). The frequency division is deter-
mined by the SPEED bit in the SETUP register, as shown in
Table I.
OPEN CIRCUIT
AV
DD
AV
DD
0V
2µA
2µA
CODE = 0x7FFFFF
H
ADC
FIGURE 3. Burnout detection while sensor is open-circuited.
SHORT
CIRCUIT
AV
DD
AV
DD
/2
AV
DD
/2
2µA
2µA
CODE ≅ 0
ADC
FIGURE 4. Burnout detection while sensor is short-circuited.
INPUT BUFFER
The input impedance of the ADS1240/41 without the buffer
enabled is approximately 5MΩ/PGA. For systems requiring
very high input impedance, the ADS1240/41 provides a
chopper-stabilized differential FET-input voltage buffer. When
activated, the buffer raises the ADS1240/41 input impedance
to approximately 5GΩ.
The buffer’s input range is approximately 50mV to AVDD –
1.5V. The buffer’s linearity will degrade beyond this range.
Differential signals should be adjusted so that both signals
are within the buffer’s input range.
The buffer can be enabled using the BUFEN pin or the
BUFEN bit in the ACR register. The buffer is on when the
BUFEN pin is high and the BUFEN bit is set to one. If the
BUFEN pin is low, the buffer is disabled. If the BUFEN bit is
set to zero, the buffer is also disabled.
SPEED DR BITS 1st NOTCH
fOSC BIT fMOD 00 01 10 FREQ.
2.4576MHz 0 19,200Hz 15Hz 7.5Hz 3.75Hz 50/60Hz
1 9,600Hz 7.5Hz 3.75Hz 1.875Hz 25/30Hz
4.9152MHz 0 38,400Hz 30Hz 15Hz 7.5Hz 100/120Hz
1 19,200Hz 15Hz 7.5Hz 3.75Hz 50/60Hz
TABLE I. Output Configuration.
CALIBRATION
The offset and gain errors can be minimized with calibration.
The ADS1240 and ADS1241 support both self and system
calibration.
Self-calibration of the ADS1240 and ADS1241 corrects inter-
nal offset and gain errors and is handled by three commands:
SELFCAL, SELFGAL, and SLEFOCAL. The SELFCAL com-
mand performs both an offset and gain calibration. SELFGCAL
performs a gain calibration and SELFOCAL performs an
offset calibration, each of which takes two tDATA periods to
complete. During self-calibration, the ADC inputs are discon-
nected internally from the input pins. The PGA must be set to
1 prior to issuing a SELFCAL or SELFGCAL command. Any
PGA is allowed when issuing a SELFOCAL command. For
example, if using PGA = 64, first set PGA = 1 and issue
ADS1240, 1241
12 SBAS173E
www.ti.com
SELFGCAL. Afterwards set PGA = 64 and issue SELFOCAL.
For operation with a reference voltage greater than (AVDD –
1.5) volts, the buffer must also be turned off during gain self-
calibration to avoid exceeding the buffer input range.
System calibration corrects both internal and external offset
and gain errors. While performing system calibration, the
appropriate signal must be applied to the inputs. The system
offset calibration command (SYSOCAL) requires a zero input
differential signal (see Table IV, page 18). It then computes
the offset that nullifies the offset in the system. The system
gain calibration command (SYSGCAL) requires a positive
full-scale input signal. It then computes a value to nullify the
gain error in the system. Each of these calibrations takes two
tDATA periods to complete. System gain calibration is recom-
mended for the best gain calibration at higher PGAs.
Calibration should be performed after power on, a change in
temperature, or a change of the PGA. The RANGE bit (ACR bit
2) must be zero during calibration.
Calibration removes the effects of the ODAC; therefore, dis-
able the ODAC during calibration, and enable again after
calibration is complete.
At the completion of calibration, the
DRDY
signal goes low,
indicating the calibration is finished. The first data after
calibration should be discarded since it may be corrupt from
calibration data remaining in the filter. The second data is
always valid.
EXTERNAL VOLTAGE REFERENCE
The ADS1240 and ADS1241 require an external voltage
reference. The selection for the voltage reference value is
made through the ACR register.
The external voltage reference is differential and is repre-
sented by the voltage difference between the pins: +VREF
and –VREF. The absolute voltage on either pin, +VREF or
–VREF, can range from AGND to AVDD. However, the follow-
ing limitations apply:
For AVDD = 5.0V and RANGE = 0 in the ACR, the differential
VREF must not exceed 2.5V.
For AVDD = 5.0V and RANGE = 1 in the ACR, the differential
VREF must not exceed 5V.
For AVDD = 3.0V and RANGE = 0 in the ACR, the differential
VREF must not exceed 1.25V.
For AVDD = 3.0V and RANGE = 1 in the ACR, the differential
VREF must not exceed 2.5V.
CLOCK GENERATOR
The clock source for the ADS1240 and ADS1241 can be
provided from a crystal, oscillator, or external clock. When the
clock source is a crystal, external capacitors must be provided
to ensure start-up and stable clock frequency. This is shown in
both Figure 5 and Table II. XOUT is only for use with external
crystals and it should not be used as a clock driver for external
circuitry.
FIGURE 5. Crystal Connection.
CLOCK PART
SOURCE FREQUENCY C1C2NUMBER
Crystal 2.4576 0-20pF 0-20pF ECS, ECSD 2.45 - 32
Crystal 4.9152 0-20pF 0-20pF ECS, ECSL 4.91
Crystal 4.9152 0-20pF 0-20pF ECS, ECSD 4.91
Crystal 4.9152 0-20pF 0-20pF CTS, MP 042 4M9182
TABLE II. Recommended Crystals.
DIGITAL FILTER
The ADS1240 and ADS1241 have a 1279 tap linear phase
Finite Impulse Response (FIR) digital filter that a user can
configure for various output data rates. When a 2.4576MHz
crystal is used, the device can be programmed for an output
data rate of 15Hz, 7.5Hz, or 3.75Hz. Under these conditions,
the digital filter rejects both 50Hz and 60Hz interference. Figure
6 shows the digital filter frequency response for data output
rates of 15Hz, 7.5Hz, and 3.75Hz.
If a different data output rate is desired, a different crystal
frequency can be used. However, the rejection frequencies
shift accordingly. For example, a 3.6864MHz master clock with
the default register condition has:
(3.6864MHz/2.4576MHz) • 15Hz = 22.5Hz data output rate
and the first and second notch is:
1.5 • (50Hz and 60Hz) = 75Hz and 90Hz
DATA I/O INTERFACE
The ADS1240 has four pins and the ADS1241 has eight pins
that serve a dual purpose as both analog inputs and data
I/O. These pins are powered from AVDD and are configured
through the IOCON, DIR, and DIO registers. These pins
can be individually configured as either analog inputs or data
I/O. See Figure 7 (page 14) for the equivalent schematic of
an Analog/Data I/O pin.
The IOCON register defines the pin as either an analog input
or data I/O. The power-up state is an analog input. If the pin
is configured as an analog input in the IOCON register, the
DIR and DIO registers have no effect on the state of the pin.
If the pin is configured as data I/O in the IOCON register,
then DIR and DIO are used to control the state of the pin.
The DIR register controls the direction of the data pin, either
as an input or output. If the pin is configured as an input in
the DIR register, then the corresponding DIO register bit
reflects the state of the pin. Make sure the pin is driven to a
C
1
Crystal
X
IN
X
OUT
C
2
ADS1240, 1241 13
SBAS173E www.ti.com
FIGURE 6. Filter Frequency Responses.
DATA –3dB
OUTPUT RATE BANDWIDTH fIN = 50 ± 0.3Hz fIN = 60 ± 0.3Hz fIN = 50 ± 1Hz fIN = 60 ± 1Hz
15Hz 14.6Hz –80.8dB –87.3dB –68.5dB –76.1dB
7.5Hz 3.44Hz –85.9dB –87.4dB –71.5dB –76.2dB
3.75Hz 1.65Hz –93.8dB –88.6dB –86.8dB –77.3dB
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN f
DATA
= 15Hz
Frequency (Hz)
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
Magnitude (dB)
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN f
DATA
= 7.5Hz
Frequency (Hz)
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
Magnitude (dB)
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN f
DATA
= 3.75Hz
Frequency (Hz)
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
Magnitude (dB)
ADS1240 AND ADS1241
FILTER RESPONSE WHEN f
DATA
= 15Hz
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
–140
–160
–180 020 8040 60 100 120 140 160 180 200
Gain (dB)
45 50 55 60 65
45 50 55 60 65
45 50 55 60 65
ADS1240 AND ADS1241
FILTER RESPONSE WHEN f
DATA
= 7.5Hz
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
–140
–160
–180 020 8040 60 100 120 140 160 180 200
Gain (dB)
ADS1240 AND ADS1241
FILTER RESPONSE WHEN f
DATA
= 3.75Hz
Frequency (Hz)
f
OSC
= 2.4576MHz, SPEED = 0 or f
OSC
= 4.9152MHz, SPEED = 1
0
–20
–40
–60
–80
–100
–120
–140
–160
–180 020 8040 60 100 120 140 160 180 200
Gain (dB)
ATTENUATION
ADS1240, 1241
14 SBAS173E
www.ti.com
Data Continuous Mode (RDATAC) command should not be
issued when DIN and DOUT are connected. While in RDATAC
mode, DIN looks for the STOPC or RESET command. If
either of these 8-bit bytes appear on DOUT (which is con-
nected to DIN), the RDATAC mode ends.
DATA READY
DRDY
PIN
The
DRDY
line is used as a status signal to indicate when
data is ready to be read from the internal data register.
DRDY
goes LOW when a new data word is available in the
DOR register. It is reset HIGH when a read operation from
the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
The status of
DRDY
can also be obtained by interrogating bit
7 of the ACR register (address 2H). The serial interface can
operate in 3-wire mode by tying the
CS
input LOW. In this
case, the SCLK, DIN, and DOUT lines are used to communi-
cate with the ADS1240 and ADS1241. This scheme is
suitable for interfacing to microcontrollers. If
CS
is required
as a decoding signal, it can be generated from a port bit of
the microcontroller.
DSYNC OPERATION
Synchronization can be achieved either through the
DSYNC
pin or the DSYNC command. When the
DSYNC
pin is used,
the digital circuitry is reset on the falling edge of
DSYNC
.
While
DSYNC
is LOW, the serial interface is deactivated.
Reset is released when
DSYNC
is taken HIGH. Synchroni-
zation occurs on the next rising edge of the system clock
after
DSYNC
is taken HIGH.
When the DSYNC command is sent, the digital filter is reset
on the edge of the last SCLK of the DSYNC command. The
modulator is held in RESET until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK following the DSYNC
command.
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotoni-
cally.
RESET
The user can reset the registers to their default values in
three different ways: by asserting the
RESET
pin; by issuing
the RESET command; or by applying a special waveform on
the SCLK (the
SCLK Reset Waveform
, as shown in the
Timing Diagram). Note: if both POL and SCLK pins are held
high, applying the SCLK Reset Waveform to the
CS
pin also
resets the part.
logic one or zero when configured as an input to prevent
excess current dissipation. If the pin is configured as an
output in the DIR register, then the corresponding DIO
register bit value determines the state of the output pin
(0 = AGND, 1 = AVDD).
It is still possible to perform A/D conversions on a pin
configured as data I/O. This may be useful as a test mode,
where the data I/O pin is driven and an A/D conversion is
done on the pin.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1240 and ADS1241.
The ADS1240 and ADS1241 operate in slave-only mode.
The serial interface is a standard four-wire SPI (
CS
, SCLK,
DIN and DOUT) interface that supports both serial clock
polarities (POL pin).
Chip Select (
CS
)
The chip select (
CS
) input must be externally asserted
before communicating with the ADS1240 or ADS1241.
CS
must stay LOW for the duration of the communication.
Whenever
CS
goes HIGH, the serial interface is reset.
CS
may be hard-wired LOW.
Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input
and is used to clock DIN and DOUT data. Make sure to have
a clean SCLK to prevent accidental double-shifting of the
data. If SCLK is not toggled within 3
DRDY
pulses, the serial
interface resets on the next SCLK pulse and starts a new
communication cycle. A special pattern on SCLK resets the
entire chip; see the RESET section for additional information.
Clock Polarity (POL)
The clock polarity input (POL) controls the polarity of SCLK.
When POL is LOW, data is clocked on the falling edge of
SCLK and SCLK should be idled LOW. Likewise, when POL
is HIGH, the data is clocked on the rising edge of SCLK and
SCLK should be idled HIGH.
Data Input (DIN) and Data Output (DOUT)
The data input (DIN) and data output (DOUT) receive and send
data from the ADS1240 and ADS1241. DOUT is high imped-
ance when not in use to allow DIN and DOUT to be connected
together and driven by a bidirectional bus. Note: the Read
FIGURE 7. Analog/Data Interface Pin.
IOCON
A
IN
x/Dx To Analog Mux
DIO WRITE
DIR
DIO READ
ADS1240, 1241 15
SBAS173E www.ti.com
DETAILED REGISTER DEFINITIONS
SETUP (Address 00H) Setup Register
Reset Value = iiii0000
bit 7-4 Factory Programmed Bits
bit 3 BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ID ID ID ID BOCS PGA2 PGA1 PGA0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00HSETUP ID ID ID ID BOCS PGA2 PGA1 PGA0
01HMUX PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
02HACR DRDY U/B SPEED BUFEN BIT ORDER RANGE DR1 DR0
03HODAC SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0
04HDIO DIO_7 DIO_6 DIO_5 DIO_4 DIO_3 DIO_2 DIO_1 DIO_0
05HDIR DIR_7 DIR_6 DIR_5 DIR_4 DIR_3 DIR_2 DIR_1 DIR_0
06HIOCON IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
07HOCR0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00
08HOCR1 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08
09HOCR2 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
0AHFSR0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00
0BHFSR1 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08
0CHFSR2 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16
0DHDOR2 DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16
0EHDOR1 DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR09 DOR08
0FHDOR0 DOR07 DOR16 FSR21 DOR04 DOR03 DOR02 DOR01 DOR00
TABLE III. Registers.
ADS1240 AND ADS1241
REGISTER
The operation of the device is set up through individual
registers. Collectively, the registers contain all the informa-
tion needed to configure the part, such as data format,
multiplexer settings, calibration settings, data rate, etc. The
set of the 16 registers are shown in Table III.
MUX (Address 01H) Multiplexer Control Register
Reset Value = 01H
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when xxx = 111)
1111 = Reserved
bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when xxx = 111)
1111 = Reserved
ADS1240, 1241
16 SBAS173E
www.ti.com
ACR (Address 02H) Analog Control Register
Reset Value = X0H
bit 7
DRDY
: Data Ready (Read Only)
This bit duplicates the state of the
DRDY
pin.
bit 6 U/
B
: Data Format
0 = Bipolar (default)
1 = Unipolar
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DRDY U/B SPEED BUFEN
BIT ORDER
RANGE DR1 DR0
U/B ANALOG INPUT DIGITAL OUTPUT (Hex)
+FSR 0x7FFFFF
0 Zero 0x000000
–FSR 0x800000
+FSR 0xFFFFFF
1 Zero 0x000000
–FSR 0x000000
bit 5 SPEED: Modulator Clock Speed
0 = fMOD = fOSC/128 (default)
1 = fMOD = fOSC/256
bit 4 BUFEN: Buffer Enable
0 = Buffer Disabled (default)
1 = Buffer Enabled
bit 3 BIT ORDER: Data Output Bit Order
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
This configuration bit controls only the bit order
within the byte of data that is shifted out. Data is
always shifted out of the part most significant byte
first. Data is always shifted into the part most
significant bit first.
bit 2 RANGE: Range Select
0 = Full-Scale Input Range equal to ±VREF
(default).
1 = Full-Scale Input Range equal to ±1/2 VREF
NOTE: This allows reference voltages as high as
AVDD, but even with a 5V reference voltage the
calibration must be performed with this bit set to 0.
bit 1-0 DR1: DR0: Data Rate
(fOSC = 2.4576MHz, SPEED = 0)
00 = 15Hz (default)
01 = 7.5Hz
10 = 3.75Hz
11 = Reserved
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DIO 7 DIO 6 DIO 5 DIO 4 DIO 3 DIO 2 DIO 1 DIO 0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00
ODAC (Address 03 ) Offset DAC
Reset Value = 00H
bit 7 Sign
0 = Positive
1 = Negative
Offset V
2 PGA OSET[6: 0]
127 RANGE 0
REF
=••
=
Offset VPGA OSET RANGE
REF
=••
=
460
127 1
[:]
NOTE: The offset DAC must be enabled after calibration or the calibration
nullifies the effects.
DIO (Address 04H) Data I/O
Reset Value = 00H
If the IOCON register is configured for data, a value written
to this register appears on the data I/O pins if the pin is
configured as an output in the DIR register. Reading this
register returns the value of the data I/O pins.
Bit 4 to bit 7 is not used in ADS1240.
DIR (Address 05H) Direction Control for Data I/O
Reset Value = FFH
Each bit controls whether the corresponding data I/O pin is
an output (= 0) or input (= 1). The default power-up state is
as inputs.
Bit 4 to bit 7 is not used in ADS1240.
IOCON (Address 06H) I/O Configuration Register
Reset Value = 00H
bit 7-0 IO7: IO0: Data I/O Configuration
0 = Analog (default)
1 = Data
Configuring the pin as a data I/O pin allows it to be controlled
through the DIO and DIR registers.
Bit 4 to bit 7 is not used in ADS1240.
OCR0 (Address 07H) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00H
ADS1240, 1241 17
SBAS173E www.ti.com
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR09 DOR08
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DOR07 DOR06 DOR05 DOR04 DOR03 DOR02 DOR01 DOR00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
OCR1 (Address 08H) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00H
OCR2 (Address 09H) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00H
FSR0 (Address 0AH) Full-Scale Register
(Least Significant Byte)
Reset Value = 59H
FSR1 (Address 0BH) Full-Scale Register
(Middle Byte)
Reset Value = 55H
FSR2 (Address 0CH) Full-Scale Register
(Most Significant Byte)
Reset Value = 55H
DOR2 (Address 0DH) Data Output Register
(Most Significant Byte) (Read Only)
Reset Value = 00H
DOR1 (Address 0EH) Data Output Register
(Middle Byte) (Read Only)
Reset Value = 00H
DOR0 (Address 0FH) Data Output Register
(Least Significant Byte) (Read Only)
Reset Value = 00H
ADS1240, 1241
18 SBAS173E
www.ti.com
RDATA–Read Data
Description: Read the most recent conversion result from the
Data Output Register (DOR). This is a 24-bit value.
Operands: None
Bytes: 1
Encoding: 0000 0001
Data Transfer Sequence:
RDATAC–Read Data Continuous
Description: Read Data Continuous mode enables the con-
tinuous output of new data on each
DRDY
. This command
eliminates the need to send the Read Data Command on each
DRDY
. This mode may be terminated by either the STOPC
command or the RESET command. Wait at least 10 fOSC after
DRDY
falls before reading.
Operands: None
Bytes: 1
Encoding: 0000 0011
Data Transfer Sequence:
Command terminated when “uuuu uuuu” equals STOPC or
RESET.
D
IN
0000 0001 • • •
(1)
xxxx xxxx xxxx xxxx xxxx xxxx
D
OUT
NOTE: (1) For wait time, refer to timing specification.
MSB Mid-Byte LSB
DIN
• • •
0000 0011 • • •(1)
uuuu uuuu uuuu uuuu uuuu uuuu
DOUT MSB Mid-Byte LSB
DOUT MSB Mid-Byte LSB
DRDY
DRDY
• • •
NOTE: (1) For wait time, refer to timing specification.
COMMANDS DESCRIPTION OP CODE 2nd COMMAND BYTE
RDATA Read Data 0000 0001 (01H)—
RDATAC Read Data Continuously 0000 0011 (03H)—
STOPC Stop Read Data Continuously 0000 1111 (0FH)—
RREG Read from REG “rrrr”0001 rrrr(1x
H) xxxx_nnnn (# of regs-1)
WREG Write to REG “rrrr”0101 rrrr(5x
H) xxxx_nnnn (# of regs-1)
SELFCAL Offset and Gain Self Cal 1111 0000 (F0H)—
SELFOCAL Self Offset Cal 1111 0001 (F1H)—
SELFGCAL Self Gain Cal 1111 0010 (F2H)—
SYSOCAL Sys Offset Cal 1111 0011 (F3H)—
SYSGCAL Sys GainCal 1111 0100 (F4H)—
WAKEUP Wakup from SLEEP Mode 1111 1011 (FBH)—
DSYNC Sync DRDY 1111 1100 (FCH)—
SLEEP Put in SLEEP Mode 1111 1101 (FDH)—
RESET Reset to Power-Up Values 1111 1110 (FEH)—
NOTE: The received data format is always MSB First; the data out format is set by the BIT ORDER bit in the ACR register.
TABLE IV. Command Summary.
The commands listed in Table IV control the operations of
the ADS1240 and ADS1241. Some of the commands are
stand-alone commands (e.g., RESET) while others require
additional bytes (e.g., WREG requires the count and data
bytes).
Operands:
n = count (0 to 127)
r = register (0 to 15)
x = don’t care
ADS1240 AND ADS1241 CONTROL COMMAND DEFINITIONS
ADS1240, 1241 19
SBAS173E www.ti.com
STOPC–Stop Continuous
Description: Ends the continuous data output mode. Issue
after
DRDY
goes LOW.
Operands: None
Bytes: 1
Encoding: 0000 1111
Data Transfer Sequence:
DIN 0000 1111xxx
DRDY
RREG–Read from Registers
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte
count. If the count exceeds the remaining registers, the ad-
dresses wrap back to the beginning.
Operands: r, n
Bytes: 2
Encoding: 0001 rrrr xxxx nnnn
Data Transfer Sequence:
Read Two Registers Starting from Register 01H (MUX)
WREG–Write to Registers
Description: Write to the registers starting with the register
address specified as part of the instruction. The number of
registers that will be written is one plus the value of the second
byte.
Operands: r, n
Bytes: 2
Encoding: 0101 rrrr xxxx nnnn
Data Transfer Sequence:
Write Two Registers Starting from 04H (DIO)
D
IN
0001 0001 0000 0001 xxxx xxxx xxxx xxxx
D
OUT
MUX ACR
• • •
(1)
NOTE: (1) For wait time, refer to timing specification.
SELFCAL–Offset and Gain Self Calibration
Description: Starts the process of self calibration. The Offset
Calibration Register (OCR) and the Full-Scale Register (FSR)
are updated with new values after this operation.
Operands: None
Bytes: 1
Encoding: 1111 0000
Data Transfer Sequence:
D
IN
1111 0000
0101 0100 xxxx 0001
Data for DIO Data for DIR
DIN
SELFOCAL–Offset Self Calibration
Description: Starts the process of self-calibration for offset.
The Offset Calibration Register (OCR) is updated after this
operation.
Operands: None
Bytes: 1
Encoding: 1111 0001
Data Transfer Sequence:
SELFGCAL–Gain Self Calibration
Description: Starts the process of self-calibration for gain.
The Full-Scale Register (FSR) is updated with new values after
this operation.
Operands: None
Bytes: 1
Encoding: 1111 0010
Data Transfer Sequence:
DIN 1111 0001
D
IN
1111 0010
ADS1240, 1241
20 SBAS173E
www.ti.com
SYSOCAL–System Offset Calibration
Description: Initiates a system offset calibration. The input
should be set to 0V, and the ADS1240 and ADS1241 compute
the OCR value that compensates for offset errors. The Offset
Calibration Register (OCR) is updated after this operation. The
user must apply a zero input signal to the appropriate analog
inputs. The OCR register is automatically updated afterwards.
Operands: None
Bytes: 1
Encoding: 1111 0011
Data Transfer Sequence:
SYSGCAL–System Gain Calibration
Description: Starts the system gain calibration process. For
a system gain calibration, the input should be set to the
reference voltage and the ADS1240 and ADS1241 compute
the FSR value that will compensate for gain errors. The FSR
is updated after this operation. To initiate a system gain
calibration, the user must apply a full-scale input signal to the
appropriate analog inputs. FCR register is updated automati-
cally.
Operands: None
Bytes: 1
Encoding: 1111 0100
Data Transfer Sequence:
DSYNC–Sync
DRDY
Description: Synchronizes the ADS1240 and ADS1241 to an
external event.
Operands: None
Bytes: 1
Encoding: 1111 1100
Data Transfer Sequence:
SLEEP–Sleep Mode
Description: Puts the ADS1240 and ADS1241 into a low
power sleep mode. To exit sleep mode, issue the WAKEUP
command.
Operands: None
Bytes: 1
Encoding: 1111 1101
Data Transfer Sequence:
RESET–Reset to Default Values
Description: Restore the registers to their power-up values.
This command stops the Read Continuous mode.
Operands: None
Bytes: 1
Encoding: 1111 1110
Data Transfer Sequence:
D
IN
1111 0011
D
IN
1111 0100
DIN 1111 1100
DIN 1111 1101
D
IN
1111 1110
WAKEUP
Description: Wakes the ADS1240 and ADS1241 from SLEEP
mode.
Operands: None
Bytes: 1
Encoding: 1111 1011
Data Transfer Sequence:
D
IN
1111 1011
ADS1240, 1241 21
SBAS173E www.ti.com
APPLICATION EXAMPLES
GENERAL-PURPOSE WEIGH SCALE
Figure 8 shows a typical schematic of a general-purpose
weigh scale application using the ADS1240. In this example,
the internal PGA is set to either 64 or 128 (depending on the
maximum output voltage of the load cell) so that the load cell
ADS1240
V
REF+
AV
DD
DRDY
SCLK
D
OUT
D
OUT
CS
X
IN
DV
DD
AGND DGND
A
IN
0
V
DD
2.7V ~ 5.25V
GND
MCLK
A
IN
1
EMI Filter
Load Cell
MSP430x4xx
or other µP
V
REF–
SPI
X
OUT
2.7V ~ 5.25V
EMI Filter
EMI Filter
EMI Filter
output can be directly applied to the differential inputs of
ADS1240.
HIGH PRECISION WEIGH SCALE
Figure 9 shows the typical schematic of a high-precision
weigh scale application using the ADS1240. The front-end
differential amplifier helps maximize the dynamic range.
ADS1240
ADS1241
V
REF+
AV
DD
DRDY
SCLK
D
OUT
D
IN
CS
X
IN
DV
DD
AGND DGND
A
IN
0
V
DD
2.7V ~ 5.25V
GND
MCLK
A
IN
1
EMI Filter
EMI Filter
Load Cell
OPA2335
G = 1 + 2 • R
F
/R
G
MSP430x4xx
or other µP
V
REF–
SPI
X
OUT
2.7V ~ 5.25V
EMI Filter
EMI Filter
OPA2335
R
F
C
I
R
G
R
F
R
I
R
I
FIGURE 8. Schematic of a General-Purpose Weigh Scale.
FIGURE 9. Block Diagram for a High-Precision Weigh Scale.
ADS1240, 1241
22 SBAS173E
www.ti.com
DEFINITION OF TERMS
An attempt has been made to be consistent with the termi-
nology used in this data sheet. In that regard, the definition
of each term is given as follows:
Analog Input Voltage—the voltage at any one analog input
relative to AGND.
Analog Input Differential Voltage—given by the following
equation: (IN+) – (IN–). Thus, a positive digital output is
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced whenever
the differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differen-
tial is 2.5V. The negative full-scale output is produced when
the differential is –2.5V. In each case, the actual input
voltages must remain within the AGND to AVDD range.
Conversion Cycle—the term
conversion cycle
usually refers
to a discrete A/D conversion operation, such as that per-
formed by a successive approximation converter. As used
here, a conversion cycle refers to the tDATA time period.
Data Rate—The rate at which conversions are completed.
See definition for fDATA.
ff
DATA OSC
SPEED DR
=128 2 1280 2•••
SPEED = 0, 1
DR = 0, 1, 2
fOSC—the frequency of the crystal oscillator or CMOS com-
patible input signal at the XIN input of the ADS1240 and
ADS1241.
fMOD—the frequency or speed at which the modulator of the
ADS1240 and ADS1241 is running. This depends on the
SPEED bit as given by the following equation:
ff
mfactor
SAMP OSC
=•8
ff
mfactor
SAMP OSC
=•4
ff
mfactor
SAMP OSC
=•2
ff
mfactor
SAMP OSC
=
PGA SETTING SAMPLING FREQUENCY
1, 2, 4, 8
16
32
64, 128
SPEED = 0 SPEED = 1
mfactor 128 256
pling capacitor. The value is given by one of the following
equations:
fDATA—the frequency of the digital output data produced by
the ADS1240 and ADS1241, fDATA is also referred to as the
Data Rate.
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1240 and ADS1241 is defined as
the input, that produces the positive full-scale digital output
minus the input, that produces the negative full-scale digital
output.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [1.25V (positive full-scale) minus –1.25V (negative
full-scale)] = 2.5V.
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input has to change in order to observe a change in the
output data of one least significant bit. It is computed as
follows:
LSB Weight Full Scale Range
N
=−21–
where N is the number of bits in the digital output.
tDATA—the inverse of fDATA, or the period between each data
output.
5V SUPPLY ANALOG INPUT(1) GENERAL EQUATIONS
DIFFERENTIAL PGA OFFSET FULL-SCALE DIFFERENTIAL PGA SHIFT
GAIN SETTING FULL-SCALE RANGE INPUT VOLTAGES(2) RANGE RANGE INPUT VOLTAGES(2) RANGE
15V±2.5V ±1.25V
22.5V±1.25V ±0.625V
4 1.25V ±0.625V ±312.5mV
8 0.625V ±312.5mV ±156.25mV
16 312.5mV ±156.25mV ±78.125mV
32 156.25mV ±78.125mV ±39.0625mV
64 78.125mV ±39.0625mV ±19.531mV
128 39.0625mV ±19.531mV ±9.766mV
NOTES: (1) With a 2.5V reference. (2) Refer to electrical specification for analog input voltage range.
TABLE VI. Full-Scale Range versus PGA Setting.
2•V
PGA
REF ±V
PGA
REF
±•
V
PGA
REF
2
RANGE = 0
RANGE = 1
V
PGA
REF
±•
VPGA
REF
2
±•
VPGA
REF
4
ff
mfactor f
MOD OSC OSC
SPEED
==
128 2•
fSAMP—the frequency, or switching speed, of the input sam-
ADS1240, 1241 23
SBAS173E www.ti.com
DATE REVISION PAGE SECTION DESCRIPTION
6 Timing Characteristics Table Clarified t10 specification.
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
8/06 E
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS1240E ACTIVE SSOP DB 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1240E/1K ACTIVE SSOP DB 24 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1240E/1KG4 ACTIVE SSOP DB 24 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1240EG4 ACTIVE SSOP DB 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1241E ACTIVE SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1241E/1K ACTIVE SSOP DB 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1241E/1KG4 ACTIVE SSOP DB 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1241EG4 ACTIVE SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Apr-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS1240E/1K SSOP DB 24 1000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
ADS1241E/1K SSOP DB 28 1000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jan-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1240E/1K SSOP DB 24 1000 346.0 346.0 33.0
ADS1241E/1K SSOP DB 28 1000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jan-2009
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids allexpress and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is notresponsible or liable for any such statements.TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonablybe expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governingsuch use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, andacknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their productsand any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may beprovided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products insuch safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products arespecifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet militaryspecifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely atthe Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products aredesignated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designatedproducts in automotive applications, TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers amplifier.ti.com Audio www.ti.com/audioData Converters dataconverter.ti.com Automotive www.ti.com/automotiveDLP® Products www.dlp.com Broadband www.ti.com/broadbandDSP dsp.ti.com Digital Control www.ti.com/digitalcontrolClocks and Timers www.ti.com/clocks Medical www.ti.com/medicalInterface interface.ti.com Military www.ti.com/militaryLogic logic.ti.com Optical Networking www.ti.com/opticalnetworkPower Mgmt power.ti.com Security www.ti.com/securityMicrocontrollers microcontroller.ti.com Telephony www.ti.com/telephonyRFID www.ti-rfid.com Video & Imaging www.ti.com/videoRF/IF and ZigBee® Solutions www.ti.com/lprf Wireless www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2009, Texas Instruments Incorporated