CY37032 - Cypress Semiconductor - searchdatasheet.com

PRELIMINARY

UltraLogicTM 32-Macrocell ISRTM CPLD

CY37032

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA95134 • 408-943-2600

January 6, 1999

Features

• 32 macrocells in two logic blocks

• In-System Repro gram m able™ (ISR™)

—JTAG-compliant on-board programming

—Des ign changes don’t cause pinout changes

—Des ign changes don’t cause timi ng changes

•Up to 32 I/Os

—plus 5 dedicated inputs inc luding 4 clock input s

• High speed

—fMAX = 222 MHz

—tPD = 5.0 ns

—tS = 3 ns

—tCO = 4 ns

• Product- term cl ocking

• IEEE 1149.1 JTAG boundary scan

• Programmable slew rate control on individual I/Os

• Low power option on individual logic bl ock basis

• 5V and 3.3V I /O capability

• User-Programm able Bus Hold capabiliti es on all I/Os

• Simple Timing Model

• PCI compliant

• Available in 44-pin TQFP and 44-pin PLCC

• Pinout compatib le with the CY37032V, CY37064/

CY37064V, CY7C371i

Selection Guide CY37032-222 CY37032-200 CY37032- 167 CY37032-125

Maximum Propagat ion Delay, tPD (ns ) 5.0 6.0 6.5 10

Minimum Set-Up, tS (ns ) 3.0 4 4 5.5

Maximum Clock to Output, tCO (ns) 4.0 4 46.5

Typical Suppl y Cur rent, ICC (mA) in Low P ower Mode 15 15 15 15

Shaded areas contain advance information.

Logic Block Diagram

LOGIC

BLOCK

LOGIC

BLOCK

Input Clock/

Input

16 I/Os 16 I/Os

I/O0−I/O15 I/O16−I/O31

TDI

TCLK

TMS TDO

JTA G Tap

Controller

37032-1

PIM

37032-2

I/O27/TDI

I/O26

I/O25

I/O24

CLK1/I4

GND

CLK3/I2

I/O23

I/O22

I/O21

I/O5/TCLK

I/O6

I/O7

CLK2/I0

JTAGEN

GND

CLK0/I1

I/O8

I/O9

I/O10

I/O11

GND

I/O20

I/O2

GND

VCCO

VCC

I/O3

I/O4

I/O1

I/O0

I/O29

I/O30

I/O31

I/O28

I/O19

I/O18

I/O17

I/O16

I/O15

I/O14

I/O13

I/O12

65 34 2

17 19 20 2221 23 24 2726 2825

43 42 4041

I/O2

GND

VCCO

I/O3

I/O4

I/O1

I/O0

I/O29

I/O30

I/O31

I/O28

I/O27/TDI

I/O26

I/O25

I/O24

CLK1/I4

GND

CLK3/I2

I/O23

I/O22

I/O21

GND

I/O20

VCC

I/O18

I/O17

I/O16

I/O15

I/O14

I/O12

I/O5/TCLK

I/O6

I/O7

CLK2/I0

GND

CLK0/I1

I/O8

I/O9

I/O10

I/O11

18 19 20 222113 14 15 171612

44 43 42 4041 39 38 37 3536 34

37032–3

44-pin PLCC

Top View 4 4 -pin TQ FP

View

/TMS

/TDO

I/O13/TMS

I/O19/TDO

JTAGEN

Pin Configurations

Top

CY37032

PRELIMINARY

Functional Description

The CY37032 is an In-System Reprogrammable (ISR) Com-

plex Programmable Logic Device (CPLD) and is part of the

Ultra37000™ fam ily of high- density, high-speed CPLDs. Like

all members of the Ultra37000 family, the CY37032 is de-

signed to bring the ease of use and high perfor mance of the

22V10 to high-density PLDs.

The CY37032 is rich in I /O resources. Each macrocell in the

device features an associated I/O pin, resul ting in 32 I/O pins

on the CY37032.

For a more detailed description of the architecture and fea-

tures of the CY37032 see the Ultra37000 family data sheet .

Fully Routable with 100% Logi c Uti lization

The CY37032 is designed with a robust routing architecture

which allows utili zation of the ent ire de vice wi th a fixed pi nout.

This makes Ultra3 7000 op timal fo r im plementi ng on boar d de-

sign changes using ISR without changing pinouts.

Simple Timing Model

The CY37032 features a very simple timing model with pre-

dict able dela ys. Unlike oth er high-den sity CPLD architectures,

ther e are no hidden spe ed dela ys such as f anout eff ects , inter-

connect delays, or expander delays. The timi ng model allows

for design changes with ISR without causing changes t o sys-

tem performance.

Low Power Operati on

Each Logic Bl ock of t he CY37032 can be configured as either

High-Speed (default) or Low-Power. In the Low-Power mode,

the logic bl ock consumes approximately 50% less power and

slows down by tLP.

Output Slew Rate Control

Each output can be configured with either a fast edge rate

(default) for high perfor mance, or a slow edge rat e for added

noise reduct ion. In the fast edge rate mode, outpu ts switch at

3V/ns max. and i n the slow e dge rate mode, outputs swi tch at

1V/ns max. There is a nominal delay for I/Os using the slow

edge rate mode.

3.3V or 5V I/ O operation

The CY37032 operates with a 5V supply, and can support 5V

or 3.3V I/O levels. VCCO connecti ons provide the capability of

int erf ac ing to eit her a 5V or 3.3 V bu s. By conn ect ing the VCCO

pins to 5V the user insures 5V TTL levels on the outputs. If

VCCO is conne cted to 3.3V the outpu t le v els meet 3.3V J EDEC

standard CMOS levels and are 5V tolerant. A nominal timing

delay is incurred on out put buffers when VCCO i s set to 3 .3V.

This device requires 5V ISR programming.

In System Reprogramming

The CY37032 can be programmed in system using IEEE

1149.1 compliant JTAG programming protocol. The CY37032

can also be programmed on a number of traditional parallel

programmers including Cypress’s

Impulse3

 programmer

and industry standard third-par ty programmers. For an over-

view of IS R programming , refer t o the Ultra37000 Family data

sheet and for UltraISR cabl e and softw are speci fications, refer

to InSRkit: ISR Programming data sheet (CY3600i).

User-Programm able Bus Hold

All outputs of the CY37032 can ei ther be configured into bus

hold mode or l eft floating. Wh en in bus hold m ode, t he undriv-

en outpu ts retai n their last value with a wea k latch. This f eature

allo ws the design er the flexib ility of ei ther el iminating or includ-

ing external pull-up/pull-down resistors. Enabling this feature

affects all I/Os si multaneously.

Design Tools

Development software for the CY37032 is available from

Cypress’s

Warp

 or third-par ty bolt- in software packages as

well as a number of third-party de vel opment pack ages. Please

refer to the

Warp

or third-party tool support data sheets for

fur ther information.

Ma xi mu m R ati n gs

(Above which the useful life may be impaired. For user gui de-

lines , not tested.)

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Pow e r A pplie d ......... ............... .............. ....... –5 5°C to +125°C

Supply Vol tage to Ground Potentia l.............. ..–0.5 V to +7.0V

DC Voltage Appl ied to Outputs

in High Z State................................................–0.5V to +7.0V

DC Input Voltage .... ..... ..... ............ ..... ............ .–0.5V to +7.0V

DC Program Voltage............................................. 4.5 to 5.5V

Current into Outputs.................................................... 16 mA

Static Discharge Voltage . ............ ............ .. ............... .>2001V

(per MIL- STD-883, Method 3015)

Latch-Up Current................... ................. ................. >200 mA

Note:

1. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the

Ultra37000 family devices see the Ultra37000 family data sheet.

Operating Range[1]

Range Ambient

Temperature[1] Junction

Temperature Output

Condition VCC VCCO

Commercial 0°C to +70°C 0°C to +90°C 5.0V 5V ± 0.25V 5V ± 0.25 V

3.3V 5V ± 0.25V 3.3V ± 0.3V

Industrial –40°C to +85°C −40°C to +125°C 5.0V 5V ± 0. 50V 5V ± 0.50V

3.3V 5V ± 0.50V 3.3V ± 0.3V

CY37032

PRELIMINARY

Electrica l Characte ristics Over the Operati ng Range

Parameter Description Test Conditi ons Min. Typ. Max. Unit

VOH Output HIGH Voltage VCC = Min. IOH = –3.2 mA

(Com’l/Ind)[2] 2.4 V

VOHZ Output HIGH Voltage with

Output Disabled[6] VCC = Max. IOH = 0 µA (Com’l /Ind)[3] 4.0 V

IOH = –50 µA (Com’l/Ind)[3] 3.6 V

VOL Output LOW Vol tage VCC = Min. IOL = 16 mA (Com’l/Ind)[2] 0.5 V

VIH Input HIGH Voltage Guarant eed I nput Logi cal HI GH v oltage

for all input s [4] 2.0 VCCmax V

VIL Input LOW Vol tage Guaranteed Input Logical LOW voltage

for all input s[4] −0.5 0.8 V

IIX Input Load Current VI = GND OR VCC −10 10 µA

IOZ Output Leakage Current VO = GND or VCC, Output Disabled −50 50 µA

VCC = Ma x., VO = 3.3V, Output

Disabled[3] 0−70 −125 µA

IOS Out put Short Circuit

Current[5, 6] VCC = Ma x., VOUT = 0.5V −30 −160 mA

IBHL Input Bus Hold LOW Sustaining

Current VCC = Min., VIL = 0.8V +75 µA

IBHH Input Bus Hold HIGH

Sustai ning Current VCC = Min., VIH = 2.0V −75 µA

IBHLO I nput Bus Hold LO W Over driv e

Current VCC = Max. +500 µA

IBHHO I nput Bus Hold HIGH Overdrive

Current VCC = Max. -500 µA

Inductance[6]

Parameter Description Test Condi tions 44-lead TQFP 44-lead PLCC Unit

LMaxi mum Pin Inductance VIN = 5.0V at f = 1 MHz 2 5 nH

Capacitance[6]

Parameter Description Test Conditi ons Max. Unit

CI/O Input/Outp ut Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C 8pF

CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C12 pF

Endurance Chara cteristics[6]

Parameter Description Test Conditions Min. Typ. Unit

NMinimum Reprogramming Cycles Normal Progr amming Conditions[1] 1,000 10,000 Cycles

Notes:

2. IOH = –2 mA, IOL = 2 mA for TDO.

3. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered

significantly by a small leakage current. Note that all I/Os are output disabled during ISR programming. Refer to the application note “Understanding Bus Hold”

for additional information.

4. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

5. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test

problems caused by tester ground degradation.

6. Tested initially and after any design or process changes that may affect these parameters.

CY37032

PRELIMINARY

Note:

7. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.

AC Test Loads and Wav eform s

37032-5

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

OUTPUT

35 pF

INCLUDING

JIG AND

SCOPE

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE

(a) (b)

<2 ns

OUTPUT

238Ω(COM'L)

319Ω(MIL)

170Ω(COM'L)

236Ω(MIL)

99Ω(COM'L)

136Ω(MIL)

Equivalent to: THÉVENIN EQUIVALENT

2.08V(COM'L)

2.13V(MIL)

238Ω(COM'L)

319Ω(MIL)

170Ω(COM'L)

236Ω(MIL) <2 n s

(c)

5 OR 35 pF

37032-4 37032-6

37032-7

Parameter[7] VXOutput Wavefor m—Measurement Level

tER(–) 1.5V

tER(+) 2.6V

tEA(+) 1.5V

tEA(–) Vthe

(d) Test Waveforms

VOH VX

0.5V 37032-8

VOL VX

0.5V

37032-9

VXVOH

0.5V

37032-10

VXVOL

0.5V 37032-11

CY37032

PRELIMINARY

Swi tch ing C h ara cter i sti cs Over the Operating Range[8]

37032-222 37032-200 37032-167 37032-125

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

Co mbin a to r ia l M o d e Para m e te rs

tPD[9,10,11] Input to Combinatorial Output 5 6 6.5 10 ns

tPDL[9,10,11] Input to Output Through Transparent Input

or Output Lat ch 88.5 10 13 ns

tPDLL[9,10,11] I nput t o Output Thr ough Transpar ent I nput

and Output Latches 10 10.5 12 15 ns

tEA[9,10,11] I nput t o Output Enable 8 9 10 14 ns

tER[9] Input to Output Disable 8 9 10 14 ns

Input Register Parameters

tWL Clock or Latch Enable Input LOW Time[6] 22.5 2.5 3ns

tWH Clock or Lat ch Enable Input HIGH Ti me [6] 22.5 2.5 3ns

tIS Input Register or Latch Set-Up Time 2 2 2 2 ns

tIH Input Register or Latch Hold Tim e 2 2 2 2 ns

tICO[9,10,11] Inpu t Regi ster Clock or Latch Enable to

Combinatorial Output 10 11 11 12.5 ns

tICOL[9,10,11] Input Register Cloc k or Latch Enab le to Out-

put Through Tra nsparent Output Latch 11 12 12 16 ns

Synchronous Clocking Param eters

tCO[10,11] Synchronou s Clock ( CLK0, CLK1, CLK2, or

CLK3) or Latch Enable to Output 4.0 4 46.5 ns

tS[9] Set-Up Time from Inp ut t o Synchronous

Clock (CLK0, CLK1, CLK2, or CLK3) or Latch

Enable

3.0 4 4 5.5 ns

tHRegi ster or Latch Data Hold Tim e 0 0 0 0 ns

tCO2[9,10,11] Output Synchronous Clo ck (CLK0, CLK1,

CLK2, o r C LK3) or Latch Enable to Combi-

natorial O utput Dela y (Thr ough L ogic Ar ra y)

99.510 14 ns

tSCS[9] Output Synchronous Clo ck (CLK0, CLK1,

CLK2, o r C LK3) or Latch Enable to Output

Synchronous Cloc k (CLK0, CLK1, CLK2, or

CLK3) or Latch Enable (Through Logic Ar-

ray)

4.5 5 6 8 ns

tSL[9] Set-Up Time from Input Through Transpar-

ent Latch t o Output Register Synchronous

Clock (CLK0, CLK1, CLK2, or CLK3) or Latch

Enable

77.5 7.5 10 ns

tHL Hold Time for I nput Through Transparent

Latch from Output Register Synchronous

Clock (CLK0, CLK1, CLK2, or CLK3) or Latch

Enable

0 0 0 0 ns

Product Term Cloc king Parameter s

tCOPT[9,10,11] Product Term Clock or Lat ch Enable

(PTCLK) to Output 677.5 11 ns

Shaded areas contain advance information

Notes:

8. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.

9. Logic Blocks operating in low power mode, add tLP to this spec.

10. Outputs using Slow Output Slew Rate, add tSLEW to this spec.

11. When VCCO= 3.3V, add t3.3IO to this spec.

CY37032

PRELIMINARY

tSPT Set-Up Time f rom Input to Product Term

Clock or Latch Enable (PTCLK) 22.5 2.5 3ns

tHPT Register or Latch Dat a Hold Ti m e 22.5 2.5 3ns

tCO2PT[9,10,11] Product Ter m Clock or Latch Enable (PT-

CLK) to Output Dela y (Throug h Logic Array) 11 12 14 19 ns

Pipelined Mode Parameters

tICS[9] Input Register Synchronous Clock (CLK0,

CLK1, C L K 2, or CLK3) to Output Register

Synchronous Cloc k (CLK0, CLK1, CLK2, or

CLK3)

4.5 5.0 6 8 ns

Operating Frequency Parameters

fMAX1 Maximum Freque ncy with Internal F eed-

back (Lesser of 1/ tSCS, 1/(tS + tH), or

1/tCO)[6]

222 200 167 125 MHz

fMAX2 Maximum Frequency Data Path i n Output

Registe red/Lat che d Mode (L esser o f 1 /(t WL

+ tWH), 1 /(tS + tH), or 1/tCO)

250 200 200 158 MHz

fMAX3 Maximum Freque ncy with External Feed-

back ( Les ser of 1/(t CO + tS) or 1/(tWL + tWH)) 125 125 125 83 MHz

fMAX4 Maximum Frequency in Pipelined Mode

(Lesser of 1/( tCO + tIS), 1/tICS, 1/(tWL + tWH),

1/(tIS + tIH), or 1/tSCS)

154 154 154 125 MHz

Reset/Preset Parameters

tRW Async hronous Reset Width[6] 7 8 8 10 ns

tRR[9] Asynchronous Reset R ecovery Time[6] 910 10 12 ns

tRO[9, 10, 11 ] Asynchronous Reset to Output 11 12 13 15 ns

tPW Async hronous Preset Wi dth[6] 7 8 8 10 ns

tPR[9] Asynchronous Preset Recovery Time[6] 910 10 12 ns

tPO[9, 10, 11] Asynchronous Preset to Output 11 12 13 15 ns

User O p tion Para meters

tLP Low Power Adder 4 4 4 4 ns

tSLEW Slow Outpu t Slew Rate Adder 2 2 2 2 ns

t3.3IO 3.3V I/O Mode Timing Adder 0.1 0.1 0.1 0.1 ns

JTA G Timing Parameters

tS JTAG Set-Up Time from TDI and TMS to TCK 0 0 0 0 ns

tH JTAG Hol d Time on TDI and TMS 20 20 20 20 ns

tCO JTAG Falling Edge of TCK to TDO 20 20 20 20 ns

fJTAG Maximum JTAG Tap Controller Freque ncy 20 20 20 20 MHz

Shaded areas contain advance information

Swi tch ing C h ara cter i sti cs Over the Operating Range[8] (continued)

37032-222 37032-200 37032-167 37032-125

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

CY37032

PRELIMINARY

Typ i cal I cc C h ara cter i sti cs

0 50 100 150 200 250

Fre

uenc

(

MHz

)

Icc (mA)

H igh S pee d

Low Power

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

Vcc = 5.0V, TA = Room Temperature

CY37032

PRELIMINARY

Swi tch ing Waveforms

tPD

37032-12

INPUT

COMBINATORIAL

OUTPUT

Combinatorial Output

Registered Output with Synchronous Clocking

37032-13

INPUT

SYNCHRONOUS

tCO

REGISTERED

OUTPUT

SYNCHRONOUS

tWL

tWH

tCO2

REGISTERED

OUTPUT

CLOCK

Registered Output with Produ ct Term Clocki ng

tSPT

37032-14

INPUT

PRODUCT TERM

tCOPT

REGISTERED

OUTPUT

tHPT

PRODUCT TERM

tWL

tWH

CLOCK

Input Going Through the Array

CY37032

PRELIMINARY

Swi tch ing Waveforms (continued)

Registered Output with Produ ct Term Clocki ng

tISPT

37032-15

INPUT

PRODUCT TERM

tCO2PT

REGISTERED

OUTPUT

tIHPT

PRODUCT TERM

tWL

tWH

CLOCK

Input Coming From Adjacent Buried Register

Latched Output

tSL

37032-16

INPUT

LATCH ENABLE

tCO

LATCHED

OUTPUT

tHL

tPDL

Registered Input

tIS

37032-17

REGISTERED

INPUT

INPUT REGISTER

CLOCK

tICO

COMBINATORIAL

OUTPUT

tIH

CLOCK

tWL

tWH

CY37032

PRELIMINARY

Swi tch ing Waveforms (continued)

Clock to Clock

37032-18

INPUT REG IST ER

CLOCK

OUTPUT

tSCS

tICS

Latched Input

tIS

37032-19

LATCHED INPUT

LATCH ENABLE

tICO

COMBINATORIAL

OUTPUT

tIH

tPDL

tWL

tWH

LATCH ENABLE

Latched Input and Output

tICS

37032-20

LATCHED INPUT

OUTPUT LATCH

ENABLE

LATCHED

OUTPUT

tPDLL

LATCH ENABLE

tWL

tWH

tICOL

INPUT LATCH

ENABLE

tSL tHL

CY37032

PRELIMINARY

Swi tch ing Waveforms (continued)

Asynchronous Reset

37032-21

INPUT

tRO

REGISTERED

OUTPUT

CLOCK

tRR

tRW

Asynchronous Preset

37032-22

INPUT

tPO

REGISTERED

OUTPUT

CLOCK

tPR

tPW

Output Enable/Disable

37032–23

INPUT

tER

OUTPUTS

tEA

CY37032

PRELIMINARY

In-System Repr ogrammable, ISR, UltraLogic, FLASH370, Ultra37000,

Impulse3

, InSRkit, and

Warp

are tr adem arks of

Cypress Semiconduct or Corporation.

Warp2

and

Warp3

are registered trademarks of Cypress Semiconductor Corporation.

Document #: 38−00712–A

Orde ring Information

Speed

(MHz) Ordering Code Package

Name P ackage Type Operating

Range

222 CY37032P44-222AC A44 44-Pin Thin Quad Flatpack Commercial

CY37032P44-222JC J67 44-Pin Plastic Leaded Chi p Carrier

200 CY37032P44-200AC A44 44-Pin Thin Quad Flatpack Commercial

CY37032P44-200JC J67 44-Pin Plastic Leaded Chi p Carrier

167 CY37032P44-167AC A44 44-Pin Thin Quad Flatpack Commercial

CY37032P44-167JC J67 44-Pin Plastic Leaded Chi p Carrier

CY37032P44-167AI A44 44-Pin Thin Quad Flatpac k Industrial

CY37032P44-167JI J67 44-Pin Plastic Leaded Chip Carrier

125 CY37032P44-125AC A44 44-Pin Thin Quad Flatpack Commercial

CY37032P44-125JC J67 44-Pin Plastic Leaded Chi p Carrier

CY37032P44-125AI A44 44-Pin Thin Quad Flatpac k Industrial

CY37032P44-125JI J67 44-Pin Plastic Leaded Chip Carrier

Shaded areas contain advance information

Package Di agr ams

44-Lead Thin Plastic Quad Flat Pack A44

51-85064-B

CY37032

PRELIMINARY

of any circui try other than circuitry embodied in a Cypress Semiconductor pr oduct. Nor does it conv ey or imply any l icense under patent or other rights. Cypress Semi conductor does not authoriz e

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Di agr ams (cont inued)

44-Lead Plastic Leaded Chip Carrier J67

51-85003-A