PRELIMINARY CY37032 UltraLogicTM 32-Macrocell ISRTM CPLD -- tS = 3 ns Features * 32 macrocells in two logic blocks * In-System ReprogrammableTM (ISRTM) -- JTAG-compliant on-board programming * * * * * * * * * * -- Design changes don't cause pinout changes -- Design changes don't cause timing changes * Up to 32 I/Os -- plus 5 dedicated inputs including 4 clock inputs * High speed -- fMAX = 222 MHz -- tPD = 5.0 ns -- tCO = 4 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis 5V and 3.3V I/O capability User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI compliant Available in 44-pin TQFP and 44-pin PLCC Pinout compatible with the CY37032V, CY37064/ CY37064V, CY7C371i Clock/ Input Input Logic Block Diagram TDI TCLK TMS 4 1 36 I/O 5 /TCLK I/O6 I/O7 CLK2/I0 JTAGEN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17 16 PIM LOGIC BLOCK B 16 16 I/Os I/O16-I/O31 37032-1 16 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 CLK1/I 4 GND I3 CLK3/I2 I/O23 I/O22 I/O21 I/O28 I/O29 44 43 42 41 40 39 38 37 36 35 34 33 32 2 3 31 4 30 5 29 6 28 27 7 GND CLK0/I 1 I/O8 I/O9 I/O10 I/O26 I/O25 I/O24 CLK1/I 4 GND I3 CLK3/I2 I/O23 I/O22 26 8 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 I/O11 I/O21 37032-3 I/O19 /TDO I/O20 VCC GND I/O16 I/O17 I/O18 I/O12 I/O13 /TMS I/O14 I/O15 I/O19 /TDO I/O20 37032-2 I/O12 I/O /TMS 13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O27 /TDI 1 I/O5 /TCLK I/O6 I/O 7 CLK2/I 0 JTAGEN I/O27 /TDI I/O26 I/O25 I/O24 I/O2 I/O4 I/O3 I/O28 I/O29 I/O31 I/O30 I/O 1 I/O 0 GND VCCO 44-pin PLCC Top View I/O31 I/O30 44-pin TQFP Top View I/O1 I/O 0 GND VCCO LOGIC BLOCK A 36 16 I/O 2 I/O 4 I/O 3 Pin Configurations TDO 4 4 16 I/Os I/O0-I/O15 JTAG Tap Controller Selection Guide CY37032-222 CY37032-200 CY37032-167 CY37032-125 Maximum Propagation Delay, tPD (ns) 5.0 6.0 6.5 10 Minimum Set-Up, tS (ns) 3.0 4 4 5.5 Maximum Clock to Output, tCO (ns) 4.0 4 4 6.5 Typical Supply Current, ICC (mA) in Low Power Mode 15 15 15 15 Shaded areas contain advance information. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA95134 * 408-943-2600 January 6, 1999 PRELIMINARY Functional Description CY37032 standard CMOS levels and are 5V tolerant. A nominal timing delay is incurred on output buffers when VCCO is set to 3.3V. This device requires 5V ISR programming. The CY37032 is an In-System Reprogrammable (ISR) Complex Programmable Logic Device (CPLD) and is part of the Ultra37000TM family of high-density, high-speed CPLDs. Like all members of the Ultra37000 family, the CY37032 is designed to bring the ease of use and high performance of the 22V10 to high-density PLDs. In System Reprogramming For a more detailed description of the architecture and features of the CY37032 see the Ultra37000 family data sheet. The CY37032 can be programmed in system using IEEE 1149.1 compliant JTAG programming protocol. The CY37032 can also be programmed on a number of traditional parallel programmers including Cypress's Impulse3 programmer and industry standard third-party programmers. For an overview of ISR programming, refer to the Ultra37000 Family data sheet and for UltraISR cable and software specifications, refer to InSRkit: ISR Programming data sheet (CY3600i). Fully Routable with 100% Logic Utilization User-Programmable Bus Hold The CY37032 is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout. This makes Ultra37000 optimal for implementing on board design changes using ISR without changing pinouts. All outputs of the CY37032 can either be configured into bus hold mode or left floating. When in bus hold mode, the undriven outputs retain their last value with a weak latch. This feature allows the designer the flexibility of either eliminating or including external pull-up/pull-down resistors. Enabling this feature affects all I/Os simultaneously. The CY37032 is rich in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY37032. Simple Timing Model The CY37032 features a very simple timing model with predictable delays. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. The timing model allows for design changes with ISR without causing changes to system performance. Design Tools Development software for the CY37032 is available from Cypress's Warp or third-party bolt-in software packages as well as a number of third-party development packages. Please refer to the Warp or third-party tool support data sheets for further information. Low Power Operation Maximum Ratings Each Logic Block of the CY37032 can be configured as either High-Speed (default) or Low-Power. In the Low-Power mode, the logic block consumes approximately 50% less power and slows down by tLP. (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Output Slew Rate Control Ambient Temperature with Power Applied............................................. -55C to +125C Each output can be configured with either a fast edge rate (default) for high performance, or a slow edge rate for added noise reduction. In the fast edge rate mode, outputs switch at 3V/ns max. and in the slow edge rate mode, outputs switch at 1V/ns max. There is a nominal delay for I/Os using the slow edge rate mode. Supply Voltage to Ground Potential ................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State................................................-0.5V to +7.0V DC Input Voltage ............................................-0.5V to +7.0V 3.3V or 5V I/O operation DC Program Voltage............................................. 4.5 to 5.5V The CY37032 operates with a 5V supply, and can support 5V or 3.3V I/O levels. VCCO connections provide the capability of interfacing to either a 5V or 3.3V bus. By connecting the VCCO pins to 5V the user insures 5V TTL levels on the outputs. If VCCO is connected to 3.3V the output levels meet 3.3V JEDEC Current into Outputs .................................................... 16 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range[1] Range Commercial Industrial Ambient Temperature[1] Junction Temperature Output Condition VCC VCCO 0C to +70C 0C to +90C 5.0V 5V 0.25V 5V 0.25V 3.3V 5V 0.25V 3.3V 0.3V 5.0V 5V 0.50V 5V 0.50V 3.3V 5V 0.50V 3.3V 0.3V -40C to +85C -40C to +125C Note: 1. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000 family devices see the Ultra37000 family data sheet. 2 PRELIMINARY CY37032 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. IOH = -3.2 mA (Com'l/Ind)[2] 2.4 VOH Output HIGH Voltage VCC = Min. VOHZ Output HIGH Voltage with Output Disabled[6] VCC = Max. IOH = 0 A (Com'l/Ind)[3] Typ. Max. Unit V IOH = -50 A (Com'l/Ind) [3] [2] IOL = 16 mA (Com'l/Ind) 4.0 V 3.6 V VOL Output LOW Voltage VCC = Min. 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH voltage for all inputs[4] 2.0 VCCmax V VIL Input LOW Voltage Guaranteed Input Logical LOW voltage for all inputs[4] -0.5 0.8 V IIX Input Load Current -10 10 A IOZ Output Leakage Current VI = GND OR VCC VO = GND or VCC, Output Disabled -50 50 A -125 A -160 mA VCC = Max., VO = 3.3V, Output Disabled[3] -70 0 IOS Output Short Circuit Current[5, 6] VCC = Max., VOUT = 0.5V -30 IBHL Input Bus Hold LOW Sustaining Current VCC = Min., VIL = 0.8V +75 A IBHH Input Bus Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V -75 A IBHLO Input Bus Hold LOW Overdrive Current VCC = Max. +500 A IBHHO Input Bus Hold HIGH Overdrive Current VCC = Max. -500 A Inductance[6] Parameter Description L Maximum Pin Inductance Test Conditions 44-lead TQFP 44-lead PLCC Unit 2 5 nH VIN = 5.0V at f = 1 MHz Capacitance[6] Max. Unit CI/O Parameter Input/Output Capacitance Description VIN = 5.0V at f = 1 MHz at TA = 25C Test Conditions 8 pF CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz at TA = 25C 12 pF Endurance Characteristics[6] Parameter N Description Test Conditions Min. Typ. Unit Minimum Reprogramming Cycles Normal Programming Conditions[1] 1,000 10,000 Cycles Notes: 2. I OH = -2 mA, IOL = 2 mA for TDO. 3. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are output disabled during ISR programming. Refer to the application note "Understanding Bus Hold" for additional information. 4. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 5. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Tested initially and after any design or process changes that may affect these parameters. 3 PRELIMINARY CY37032 AC Test Loads and Waveforms 238 (COM'L) 319 (MIL) 238 (COM'L) 319 (MIL) 5V 5V OUTPUT OUTPUT 170 (COM'L) 236 (MIL) 35 pF INCLUDING JIG AND SCOPE (a) 90% 170 (COM'L) GND 236 (MIL) <2 ns 5 pF INCLUDING JIG AND SCOPE 37032-4 ALL INPUT PULSES 3.0V Equivalent to: THEVENIN EQUIVALENT 99 (COM'L) 136 (MIL) 2.08V(COM'L) OUTPUT 2.13V(MIL) 5 OR 35 pF 37032-7 Parameter[7] VX tER(-) 1.5V Output Waveform--Measurement Level VOH 0.5V VX 37032-8 tER(+) 2.6V VOL VX 0.5V 37032-9 tEA(+) 1.5V VX VOH 0.5V 37032-10 tEA(-) Vthe VX 0.5V VOL 37032-11 (d) Test Waveforms Note: 7. tER measured with 5-pF AC Test Load and t EA measured with 35-pF AC Test Load. 4 10% <2 ns (c) 37032-5 (b) 90% 10% 37032-6 PRELIMINARY CY37032 Switching Characteristics Over the Operating Range[8] Parameter Description 37032-222 37032-200 37032-167 37032-125 Min. Min. Min. Min. Max. Max. Max. Max. Unit Combinatorial Mode Parameters tPD[9,10,11] Input to Combinatorial Output 5 6 6.5 10 ns Input to Output Through Transparent Input or Output Latch 8 8.5 10 13 ns tPDLL[9,10,11] Input to Output Through Transparent Input and Output Latches 10 10.5 12 15 ns tEA[9,10,11] Input to Output Enable 8 9 10 14 ns Input to Output Disable 8 9 10 14 ns tPDL tER [9,10,11] [9] Input Register Parameters tWL Clock or Latch Enable Input LOW Time[6] 2 2.5 2.5 3 ns tWH Clock or Latch Enable Input HIGH Time[6] 2 2.5 2.5 3 ns tIS Input Register or Latch Set-Up Time 2 2 2 2 ns tIH Input Register or Latch Hold Time 2 2 2 2 ns tICO[9,10,11] Input Register Clock or Latch Enable to Combinatorial Output 10 11 11 12.5 ns tICOL[9,10,11] Input Register Clock or Latch Enable to Output Through Transparent Output Latch 11 12 12 16 ns 4.0 4 4 6.5 ns Synchronous Clocking Parameters tCO[10,11] Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output tS[9] Set-Up Time from Input to Synchronous Clock (CLK0, CLK 1, CLK2, or CLK3) or Latch Enable tH tCO2 Register or Latch Data Hold Time [9,10,11] 3.0 4 4 5.5 ns 0 0 0 0 ns Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK 3) or Latch Enable to Combinatorial Output Delay (Through Logic Array) 9 9.5 10 14 ns tSCS[9] Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK 3) or Latch Enable to Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array) 4.5 5 6 8 ns tSL[9] Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0, CLK 1, CLK2, or CLK3) or Latch Enable 7 7.5 7.5 10 ns tHL Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0, CLK 1, CLK2, or CLK3) or Latch Enable 0 0 0 0 ns Product Term Clocking Parameters tCOPT[9,10,11] Product Term Clock or Latch Enable (PTCLK) to Output 6 Shaded areas contain advance information Notes: 8. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 9. Logic Blocks operating in low power mode, add tLP to this spec. 10. Outputs using Slow Output Slew Rate, add tSLEW to this spec. 11. When VCCO = 3.3V, add t3.3IO to this spec. 5 7 7.5 11 ns PRELIMINARY CY37032 Switching Characteristics Over the Operating Range[8] (continued) Parameter tSPT tHPT tCO2PT [9,10,11] Description 37032-222 37032-200 37032-167 37032-125 Min. Min. Min. Min. Max. Max. Max. Max. Unit Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) 2 2.5 2.5 3 ns Register or Latch Data Hold Time 2 2.5 2.5 3 ns Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) 11 12 14 19 ns Pipelined Mode Parameters tICS[9] Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) 4.5 5.0 6 8 ns Operating Frequency Parameters fMAX1 Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO)[6] 222 200 167 125 MHz fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO) 250 200 200 158 MHz fMAX3 Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)) 125 125 125 83 MHz fMAX4 Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) 154 154 154 125 MHz 7 8 8 10 ns Reset/Preset Parameters tRW tRR [9] tRO[9, 10, 11] Asynchronous Reset Width[6] [6] Asynchronous Reset Recovery Time 9 Asynchronous Reset to Output 10 11 [6] 10 12 12 13 ns 15 ns tPW Asynchronous Preset Width 7 8 8 10 ns tPR[9] Asynchronous Preset Recovery Time[6] 9 10 10 12 ns tPO[9, 10, 11] Asynchronous Preset to Output 11 12 13 15 ns User Option Parameters tLP Low Power Adder 4 4 4 4 ns tSLEW Slow Output Slew Rate Adder 2 2 2 2 ns t3.3IO 3.3V I/O Mode Timing Adder 0.1 0.1 0.1 0.1 ns JTAG Timing Parameters tS JTAG Set-Up Time from TDI and TMS to TCK 0 0 0 0 ns tH JTAG Hold Time on TDI and TMS 20 20 20 20 ns tCO JTAG Falling Edge of TCK to TDO 20 20 20 20 ns fJTAG Maximum JTAG Tap Controller Frequency 20 20 20 20 MHz Shaded areas contain advance information 6 PRELIMINARY CY37032 Typical Icc Characteristics 60 H igh S p ee d 50 40 Icc (mA) L ow P o w e r 30 20 10 0 0 50 1 00 1 50 2 00 F r eq u e n c y (M H z) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. Vcc = 5.0V, TA = Room Temperature 7 2 50 PRELIMINARY CY37032 Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT 37032-12 Registered Output with Synchronous Clocking INPUT tS tH SYNCHRONOUS CLOCK tCO REGISTERED OUTPUT tCO2 REGISTERED OUTPUT tWH tWL SYNCHRONOUS CLOCK 37032-13 Registered Output with Product Term Clocking Input Going Through the Array INPUT tSPT tHPT PRODUCT TERM CLOCK tCOPT REGISTERED OUTPUT tWH tWL PRODUCT TERM CLOCK 37032-14 8 PRELIMINARY CY37032 Switching Waveforms (continued) Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT tISPT tIHPT PRODUCT TERM CLOCK tCO2PT REGISTERED OUTPUT tWH tWL PRODUCT TERM CLOCK 37032-15 Latched Output INPUT tHL tSL LATCH ENABLE tPDL tCO LATCHED OUTPUT 37032-16 Registered Input REGISTERED INPUT tIS tIH INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tWL tWH CLOCK 37032-17 9 PRELIMINARY CY37032 Switching Waveforms (continued) Clock to Clock INPUT REGISTER CLOCK tICS tSCS OUTPUT REGISTER CLOCK 37032-18 Latched Input LATCHED INPUT tIS tIH LATCH ENABLE tPDL tICO COMBINATORIAL OUTPUT tWH tWL LATCH ENABLE 37032-19 Latched Input and Output LATCHED INPUT tPDLL LATCHED OUTPUT tICOL tSL INPUT LATCH ENABLE tHL tICS OUTPUT LATCH ENABLE tWL tWH LATCH ENABLE 37032-20 10 PRELIMINARY CY37032 Switching Waveforms (continued) Asynchronous Reset tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK 37032-21 Asynchronous Preset tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK 37032-22 Output Enable/Disable INPUT tER tEA OUTPUTS 37032-23 11 PRELIMINARY CY37032 Ordering Information Speed (MHz) 222 200 167 125 Ordering Code Package Name Package Type CY37032P44-222AC A44 44-Pin Thin Quad Flatpack CY37032P44-222JC J67 44-Pin Plastic Leaded Chip Carrier CY37032P44-200AC A44 44-Pin Thin Quad Flatpack CY37032P44-200JC J67 44-Pin Plastic Leaded Chip Carrier CY37032P44-167AC A44 44-Pin Thin Quad Flatpack CY37032P44-167JC J67 44-Pin Plastic Leaded Chip Carrier CY37032P44-167AI A44 44-Pin Thin Quad Flatpack CY37032P44-167JI J67 44-Pin Plastic Leaded Chip Carrier CY37032P44-125AC A44 44-Pin Thin Quad Flatpack CY37032P44-125JC J67 44-Pin Plastic Leaded Chip Carrier CY37032P44-125AI A44 44-Pin Thin Quad Flatpack CY37032P44-125JI J67 44-Pin Plastic Leaded Chip Carrier Operating Range Commercial Commercial Commercial Industrial Commercial Industrial Shaded areas contain advance information In-System Reprogrammable, ISR, UltraLogic, FLASH370, Ultra37000, Impulse3, InSRkit, and Warp are trademarks of Cypress Semiconductor Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation. Document #: 38-00712-A Package Diagrams 44-Lead Thin Plastic Quad Flat Pack A44 51-85064-B 12 PRELIMINARY CY37032 Package Diagrams (continued) 44-Lead Plastic Leaded Chip Carrier J67 51-85003-A (c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.