RFPIC12F675FT-E/SS - Microchip Technology, Inc.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 1

rfPIC12F675

High Performance RISC CPU:

• Only 35 instructions to learn

- All single cycle instructions except branches

• Operati ng spe ed:

- Precision Internal 4 MH z os cil la tor, factory

calibrated to ±1%

- DC - 20 MHz Res onator/C ryst al/ Cloc k mode s

- DC - 20 MHz crystal oscill ator/c lock input

- DC - 4 MHz external RC oscillator

- DC - 4 MHz XT crystal oscillator

- External Os ci ll ato r modes

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Peripheral Feat ures:

• Memory

- 1024 x 14 words of FLASH program memory

- 128 x 8 bytes of EEPROM data memory

- 64 x 8 bytes of SRAM data memory

- 100,000 write FLASH endurance

- 1,000,000 write EEPROM endurance

- FLASH/d ata EEPROM r etention: > 40 years

• Programmable code protection

• 6 I/O pins with individual direction control, weak

pull-ups, and interr upt-on-pin change

• High current sink/source for direct LED drive

• Analog comparator: 16 internal reference levels

• Analog-to-Digital Converter: 10 bits, 4 channels

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with 3-bit prescaler

• Timer1 can use LP oscillator in INTOSC mode

•5 s wake-up from SLEEP typical with VDD = 3V

• In-Circuit Serial ProgrammingTM (ICSPTM)

Low Power Features:

• Low power consumption: (typical with VDD = 3V)

-14 mA transmitting +6 dBm at 434 MHz

-4 mA transmitti ng -15 dBm at 434 MHz

-500 A, 4.0 MHz INTOSC

-0.6 A SLEEP with watchdog enabled

-0.1 A standby current

• Wide operating voltage range from 2.0 – 5.5V

• Industri al and Extend ed tem pera ture range

Pin Diagram:

UHF ASK/FSK Transmitter:

• Integrated crystal oscillator, VCO, loop filter and

power amp for minimum external components

• ASK data rate: 0 – 40 Kbps

• FSK data rate: 0 – 40 Kbps by crystal pulling

• Output powe r: +1 0 dBm to -12 dBm in 4 steps

• Adjustable transmitter power consumption

• Transmit frequency set by crystal multiplied by 32

• VCO phase locked to quartz crystal reference;

allows narrow band receivers to be used to

maximize range and interference immunity

• Crystal frequency divide by 4 available (REFCLK)

• Used in applications conforming to US FCC Part

15.231 and European EN 300 220 regulations

Applications:

• Automoti ve R em ote Ke yl ess E ntry (R KE) sy st em s

• Autom oti ve ala r m sy ste ms

• Community gate and garage door openers

• Burglar alarm systems

• Building access

• Low power telemetry

• Me ter readi ng

• Tire pressure sensors

• Wireless sensors

Device Frequency Modulation

rfPIC12F675K 290-350 MHz ASK/FSK

rfPIC12F675F 380-450 MHz ASK/FSK

rfPIC12F675H 850-930 MHz ASK/FSK

SSOP

VSS

GP2/T0CKI/INT/COUT

DATAFSK

GP1/CIN-/ICSPCLK

VDD

GP5/T1CKI/OSC1/CLKIN

GP3/MCLR/VPP

RFEN

REFCLK

VDDRF

GP4/T1G/OSC2/CLKOUT

DATAASK

•1 19

rfPIC12F675K/F/H

GP0/CIN+/ICSPDAT

VSSRF

VSSRF ANT

10 11

FSKOUT

RFXTAL

FLASH-Based Micr ocontroller with ASK/FSK Transmitter

rfPIC12F675

DS70091B-page 2 Preliminary  2003-2013 Microchip Technology Inc.

Table of Contents

1.0 Device Overview............................................................................................................................................................................ 3

2.0 Memory Organization ... .................................................................................................................................................................. 5

3.0 GPIO Port................................................................................................................................................................................... 17

4.0 Timer0 Module............................................................................................................................................................................ 25

5.0 Timer1 Module with Gate Control..................................................................................................... ...... .. ..... .. ...... .. ...... . ...... .. .... 28

6.0 Comparator Module............................... .... .... .... ......... .... .... .... ......... .... .... .... ......... .... .... .... ...... ...... .. ...... .. ..... .. ...... .. ...... .. ..... .. ...... 33

7.0 Analog-to-Digital Converter (A/D) Module .............................................................................................. .. ..... .. ...... .. ...... . ...... .. .... 39

8.0 Data EEP ROM Mem o ry.. ................... .................. ........................ .................. ................... ............ .. ...... .. ..... .. ...... .. ...... .. ..... .. ...... 45

9.0 UHF ASK/FSK Transmi tter.................. ....................... ....................... ....................... .................... .. ...... .. ..... .. ...... .. ...... .. ..... .. ...... 49

10.0 Speci a l Features of th e CPU..................... ................... ................... ................... .............. ............ .. ...... .. ..... .. ...... .. ...... .. ..... .. ...... 55

11.0 Instruction Set Summary ........................................................................................................ ...... .. ...... .. ..... .. ...... .. ...... .. ..... .. ...... 73

12.0 Developm ent Support................................................................................................................................................................. 81

13.0 Electrical Specifications........................................................................................................ ...... ...... .. ...... . ...... .. ...... .. ..... .. ...... .. .. 8 7

14.0 DC and AC Characteristics Graphs and Tables................... .... ........... .... .... ......... .... .... .... ........... .... ......................................... 113

15.0 Packag i n g In fo rmation................ ................... ................... ................... ....................... .......... .. ...... .. ...... .. ..... .. ...... .. ...... ..... .. ...... 12 3

Appendix A: Data Sheet Revision History.... .... ...... .... ........... .... .... ........... ...... .... .... ........... .... .... ......................................................... 125

Index ................................................................................................................................................................................................. 127

On-Line Support................. ........... .. .... .... ......... .... .... .... ......... .... .... .... ......... .... .... .... ......... .................................................................. 131

Systems Information and Upgrade Hot Line. ............................................................................................ .. ...... ..... .. ...... .. ...... . ...... .. .. 1 3 1

Reader Response. ............................................................................................................................................................................ 132

Product Identification System............................................................................................................................................................ 133

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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Customer No tific atio n Syst em

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 3

rfPIC12F675

1.0 DEVICE OVERVIEW

This do cu me nt co nta i ns dev ic e spec if i c in for m at ion fo r

the rfPIC12F675. Additional information may be found

in the PICmicroTM Mid-Range Reference Manual

(DS33023), which may be obtained from your local

Microchip Sales Representative or downloaded from

the Microchip web site. The Reference Manual should

be co nside red a co mple men tary docu ment to thi s Dat a

Sheet, and is hig hly rec om m end ed re adi ng for a bett er

understandi ng of the devic e arc hi tec ture a nd o pera t io n

of the peripheral modules.

The r fPIC12F675 comes in a 20 -pin SSOP packa ge.

Figure 1-1 shows a block diagram of the rfPIC12F675

device. Table 1-1 shows th e pi nout de scr ip tion.

FIGURE 1-1: rfPIC12F675 BLOCK DIAGRAM

FLASH

Program

Memory

1K x 14

13 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

8-Level Stack

(13-bit)

RAM

File

Registers

64 x 8

Direct Addr 7

Addr(1)

Addr MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKIN

OSC2/CLKOUT VDD, V SS

Brown-out

Detect

Timing

Generation

GP5/T1CKI/OSC1/CLKIN

Internal

4 MHz

RAM

GP4/AN3/T1G/OSC2/CLKOUT

GP3/MCLR/VPP

GP2/AN2/T0CKI/INT/COUT

GP1/AN1/CIN-/VREF

GP0/AN0/CIN+

Oscillator

Note 1: Higher order bits are from STATUS re gister.

Analog

Timer0 Timer1

DATA

EEPROM

128 bytes

EEDATA

EEADDR

Comparator

Analog to Digital Converter

AN0 AN1AN2 AN3 CIN- CIN+ COUT

T0CKI

T1CKI

VREF

and reference

T1G

Clock

Divider

Voltage

Controlled

Oscillator

RF Power

Amplifier

Crystal

Oscillator

Phase/Freq

Detector

Charge

Pump

FSK Switch

REFCLK

Control

Logic

FSKOUT

VDDRF

VSSRF

RFEN

ANT

RFXTAL

DATAASK

Divide

by 32

DATAFSK

rfPIC12F675

DS70091B-page 4 Preliminary  2003-2013 Microchip Technology Inc.

TABLE 1-1: rfPIC12F675 PINOUT

PIN BUFFER WEAK

PULL-UP DESCRIPTION

IN OUT

DD Direct — — Power Supply

GP5 TTL CMOS Prog General purpose I/O. Individually co ntrolled interrupt-on -change.

Individually enabled pull-up.

T1CKI ST — — Timer1 clock

OSC1 Xtal — Bias XTAL connection

CLKIN ST — — External RC network or clock input

GP4 TTL CMOS Prog General purpose I/O. Individually co ntrolled interrupt-on -change.

Individually enabled pull-up.

T1G ST — — Timer1 gate

AN3 Analog — — A/D Channel 3 input

OSC2 — Xtal Bias XTAL connection

CLKOUT — CMOS — TOSC/4 reference clock

4GP3 TTL — General purpose input. Individ ually controlled inte rrupt-on-

change.

MCLR ST — No Master Clea r Reset

VPP HV — — Programming voltage

5 RFXTAL Xtal Xtal Bias RF Cr ystal

6 RFEN TTL — — RF Enable

7 REFCLK — CMOS — Reference Clock/4 Output (on rfPIC12F675K/F)

Reference Clock/8 Output (on rfPIC12F675H)

8 PS Analog — Bias Power Select

DDRF Direct — — RF Power Supply

10 VSSRF Direct — — RF Ground Reference

11 ANT — OD — RF power amp output to antenna

12 VSSRF Direct — — RF Ground Reference

13 LF Analog Analog — Loop Filter

14 DATAASK TTL — — ASK modulation dat a

15 DATAFSK TTL — — FSK modulation data

16 FSKOUT — OD — FSK output to modulate reference crystal

GP2 ST CMOS Prog General purp ose I/O. Individually contro lled interrupt-on-change.

Individually enabled pull up.

AN2 Analog — — A/D Channel 2 input

COUT — CMOS — Comparator output

T0CKI ST — — External clock for Timer0

INT ST — — External interrupt

GP1 TTL CMOS Prog General purpose I/O. Individually co ntrolled interrupt-on -change.

Individually enabled pull-up.

AN1 Analog — — A/D Channel 1 input

CIN- Analog — — Comparator input - negative

VREF Analog — — External voltage reference

ICSPCLK ST — — Serial programming clock

GP0 TTL CMOS Prog General purpose I/O. Individually co ntrolled interrupt-on -change.

Individually enabled pull-up.

AN0 Analog — — A/D Channel 0 input

CIN+ Analog — — Comparator input - positive

ICSPDAT TTL CMOS — Serial Programming Data I/O

20 VSS Direct — — Ground reference

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, OD = Open Drain output

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 5

rfPIC12F675

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The rfPIC1 2F675 de vice s have a 1 3-bit prog ram cou n-

ter cap a ble of addressi ng an 8K x 14 program me mo ry

space. Only the first 1K x 14 (0000h - 03FFh) for the

rfPIC12F675 devices is physically implemented.

Accessing a location above these boundaries will

cause a wrap around within the first 1K x 14 sp ace. The

RESET vecto r is a t 00 00h an d t he interrupt v ec tor i s at

0004h (see Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE

rfPIC12F675

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into

two banks, which contain the General Purpose regis-

ters and the Special Function registers. The Special

Functio n registers are located in the first 32 lo cations of

each bank. Register locations 20h-5Fh are General

Purpose re giste rs, impleme nted as st atic RA M and a re

mapped across both banks. All other RAM is

unimplemented and returns ‘0’ when read. RP0

(STATUS<5>) is the bank select bit.

• RP0 = 0 Bank 0 is selected

• RP0 = 1 Bank 1 is selected

2.2.1 GENERAL PURPOSE RE GISTER

FILE

The register file is organized as 64 x 8 in the

rfPIC12F6 75 devices. Eac h register is accessed, eith er

directly or indirectly, through the File Select Register

FSR (see Section 2.4).

PC<12:0>

000h

0004

0005

03FFh

0400h

1FFFh

Stack Level 1

Stack Level 8

RESET Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Note: The IRP and RP1 bits STATUS<7:6> are

reser ved and shoul d always be mai ntained

as ‘0’s.

rfPIC12F675

DS70091B-page 6 Preliminary  2003-2013 Microchip Technology Inc.

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-1). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function registers

assoc iated with th e “core” are described in this sec tion.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

FIGURE 2-2: DATA MEMORY MAP OF

THE rfPIC 12F 67 5

Indirect addr.(1)

TMR0

PCL

STATUS

FSR

GPIO

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

7Fh

Bank 0

Unimplemented data memory locations, read as '0'.

1: Not a physical register.

CMCON VRCON

General

Purpose

Registers accesses

20h-5Fh

64 Bytes

EEDATA

EEADR

EECON2(1)

5Fh

60h

File

Address File

Address

WPU

IOC

Indirect addr. (1)

OPTION_REG

PCL

STATUS

FSR

TRISIO

PCLATH

INTCON

PIE1

PCON

OSCCAL

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

FFh

Bank 1

DFh

E0h

ADRESH

ADCON0

EECON1

ADRESL

ANSEL

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 7

rfPIC12F675

TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD Page

Bank 0

00h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 16,63

01h TMR0 Timer0 Module’s Register xxxx xxxx 25

02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 15

03h STATUS IRP(2) RP1(2) RP0 TO PD ZDC C0001 1xxx 9

04h FSR Indirect Data Memory Address Pointer xxxx xxxx 16

05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx 17

06h —Unimplemented — —

07h —Unimplemented — —

08h —Unimplemented — —

09h —Unimplemented — —

0Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 15

0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 11

0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 13

0Dh —Unimplemented — —

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit Timer1 xxxx xxxx 28

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit Timer1 xxxx xxxx 28

10h T1CON —TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 30

11h —Unimplemented — —

12h —Unimplemented — —

13h —Unimplemented — —

14h —Unimplemented — —

15h —Unimplemented — —

16h —Unimplemented — —

17h —Unimplemented — —

18h —Unimplemented — —

19h CMCON —COUT —CINV CIS CM2 CM1 CM0 -0-0 0000 33

1Ah —Unimplemented — —

1Bh —Unimplemented — —

1Ch —Unimplemented — —

1Dh —Unimplemented — —

1Eh ADRESH Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result xxxx xxxx 40

1Fh ADCON0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 41,63

Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: This is not a physical register.

2: These bits are reserved and should always be maintained as ‘0’.

rfPIC12F675

DS70091B-page 8 Preliminary  2003-2013 Microchip Technology Inc.

Bank 1

80h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 16,63

81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 10,26

82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 15

83h STATUS IRP(2) RP1(2) RP0 TO PD ZDC C0001 1xxx 9

84h FSR Indirect Data Memory Address Pointer xxxx xxxx 16

85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 17

86h —Unimplemented — —

87h —Unimplemented — —

88h —Unimplemented — —

89h —Unimplemented — —

8Ah PCLATH ———Write Buffer for Upper 5 bits of Program Counter ---0 0000 15

8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 11

8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 12

8Dh —Unimplemented — —

8Eh PCON ——————POR BOD ---- --0x 14

8Fh —Unimplemented — —

90h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- 14

91h —Unimplemented — —

92h —Unimplemented — —

93h —Unimplemented — —

94h —Unimplemented — —

95h WPU — — WPU5 WPU4 —WPU2 WPU1 WPU0 --11 -111 18

96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 19

97h —Unimplemented — —

98h —Unimplemented — —

99h VRCON VREN —VRR —VR3 VR2 VR1 VR0 0-0- 0000 38

9Ah EEDATA Da ta EEPROM Data Register 0000 0000 45

9Bh EEADR —Dat a EEPROM Address Register -000 0000 45

9Ch EECON1 ————WRERR WREN WR RD ---- x000 46

9Dh EECON2(1) EEPROM Control Register 2 ---- ---- 46

9Eh ADRESL Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result xxxx xxxx 40

9Fh ANSEL —ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 42,63

Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: This is not a physical register.

2: These bits are reserved and should always be maintained as ‘0’.

TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD Page

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 9

rfPIC12F675

2.2.2.1 S TATUS Register

The S TATUS re gi ste r, shown i n Register 2-1, co nt ains:

• the arithmetic s tatus of the ALU

• the RESET status

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchang ed).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any STATUS bits. For other instructions not

affecting any STATUS bits, see the “Instruction Set

Summary”.

Note 1: Bits IRP a nd RP1 (ST ATUS<7:6>) are not

used by the rfPIC12F675 and should be

maintained as clear. Use of these bits is

not recommended, since this may affect

upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDC C

bit 7 bit 0

bit 7 IRP: This bit is reserved and should be maintained as ‘0’

bit 6 RP1: This bit is reserved and should be maintained as ‘0’

bit 5 RP0: Register Bank Select bit (used for direct addressing)

1 = Bank 1 (80h - FFh)

0 = Bank 0 (00h - 7Fh)

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 

For borrow, the polarity is reversed.

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low order bit of the source register

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

rfPIC12F675

DS70091B-page 10 Preliminary  2003-2013 Microchip Technology Inc.

2.2.2.2 OPTION Register

The OPTION register is a readable and writable

configure:

• TMR0/WDT prescaler

• External GP2 /INT inte rrup t

•TMR0

• Weak pull-ups on GPIO

Note: To achieve a 1:1 prescaler assignment for

TMR0, as sign the pre scale r to th e WDT b y

setting PSA bit to ‘1’ (OPTION<3>). See

Section 4.4.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 GPPU: GPIO Pull-up Enab le bit

1 = GPIO pull-u ps are disabled

0 = GPIO pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of GP2/INT pin

0 = Interrupt on falling edge of GP2/INT pin

bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit 

1 = Transition on GP2/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on GP2/T0CKI pin

0 = Increment on low-to-high transition on GP2/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the TIMER0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 11

rfPIC12F675

2.2.2.3 INTCON Register

The INTCON register is a readable and writable

for TMR0 register overflow, GPIO port change and

external GP2/INT pin interrupts.

Note: Interru pt flag bit s are set whe n an in terrupt

conditi on occurs, regardless of the sta te of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bit s are clear prior to enabling

an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE GPIE T0IF INTF GPIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4 INTE: GP2/INT External Interrupt Enable bit

1 = Enables the GP2/INT external interrupt

0 = Disables the GP2/INT external interrupt

bit 3 GPIE: Port Change Interrupt Enable bit(1)

1 = Enables the GPIO port change interrupt

0 = Disables the GPIO port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(2)

1 = TMR0 register has overflowed (must be cleared in softw are)

0 = TMR0 register did not overflow

bit 1 INTF: GP2/INT External Interrupt Flag bit

1 = The GP2/INT external interrupt occurred (must be cleared in software)

0 = The GP2/INT external interrupt did not occur

bit 0 GPIF: Port Change Interrupt Flag bit

1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software)

0 = None of the GP5:GP0 pins have changed state

Note 1: IOC register must also be enabled to enable an interrupt-on-change.

2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and

should be initialized before clearing T0IF bit.

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

rfPIC12F675

DS70091B-page 12 Preliminary  2003-2013 Microchip Technology Inc.

2.2.2.4 PIE1 Regist er

The PIE1 regis te r con t ai ns th e in terrupt enabl e bi t s, a s

shown in Register 2-4.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

EEIE ADIE — — CMIE — — TMR1IE

bit 7 bit 0

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit 

1 = Enables the A/D converter interrupt

0 = Disables the A/D converter interrupt

bit 5-4 Unimplemented: Read as ‘0’

bit 3 CMIE: Comparator Interrupt Enable bit

1 = Enables the comparator interrupt

0 = Disables the comparator interrup t

bit 2-1 Unimplemented: Read as ‘0’

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 13

rfPIC12F675

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-5.

Note: Interru pt fl ag bit s are set when an interrupt

conditi on occ urs , re gardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interr upt flag b its ar e clear prior to e nabling

an interrupt.

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

EEIF ADIF — — CMIF — — TMR1IF

bit 7 bit 0

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation has not completed or has not been started

bit 6 ADIF: A/D Converter Interrupt Flag bit 

1 = The A/D conversion is complete (must be cleared in software)

0 = The A/D conversion is not complete

bit 5-4 Unimplemented: Read as ‘0 ’

bit 3 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

bit 2-1 Unimplemented: Read as ‘0 ’

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

rfPIC12F675

DS70091B-page 14 Preliminary  2003-2013 Microchip Technology Inc.

2.2.2.6 PCON Regist er

The Power Control (PCON) register contains flag bits

to differentiate between a:

• Power- on Reset (POR)

• Brown-out Detect (BOD)

• Watchdog Timer Reset (WDT)

•External MCLR Reset

The PCON Register bits are shown in Register 2-6.

2.2.2.7 OSCCAL Register

The Oscill ator Calibration register (OSCCAL) is used to

calibra te the inte rnal 4 MHz oscill ato r. It cont a ins 6 bits

to adjust the frequency up or down to achieve 4 MHz.

The OSCCAL register bits are shown in Register 2-7.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x

— — — — — — POR BOD

bit 7 bit 0

bit 7-2 Unimplemented: Read as '0'

bit 1 POR: Power-on Reset STATUS bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOD: Brown-out Detect STATUS bit

1 = No Brown-out Detect occurred

0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — —

bit 7 bit 0

bit 7-2 CAL5:CAL0: 6-bit Signed Oscillator Calibration bits

111111 = Maximum freq uency 

100000 = Center frequency

000000 = Minimum frequency

bit 1-0 Unimplemented: Read as '0'

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 15

rfPIC12F675

2.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte

comes from th e PCL register, which is a r eadable and

writable register. The high byte (PC<12:8>) is not

directly rea dable or wr itable and comes from PCLATH.

On any RESET, the PC is cleared. Figure 2-3 shows the

two situations for the loading of the PC. The upper

example in Figure 2-3 sh ows how the P C is lo aded o n

a write to PCL (PCLATH<4:0>  PCH). The lower

example in Figure 2-3 shows how the PC is loaded

during a CALL or GOTO instruction (PCLATH<4:3> 

PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO

A comput ed GOTO is a ccom pli shed by a ddi ng a n offset

to the program counter (ADDWF PCL). When perform-

ing a table read using a computed GOTO method, care

should be ex ercise d if th e t able loca tion c ros ses a PCL

memory boundary (each 256-byte block). Refer to the

Application Note “Implementing a Table Read"

(AN556).

2.3.2 STACK

The rfPIC12F675 Family has an 8-level deep x 13-bit

wide hardwa re stack (see Figure 2-1). The stack space

is not part of either program or da ta space and the stack

pointer is not readable or writable. The PC is PUSHed

onto the stack when a CALL inst ruction is executed, or

an interrupt causes a branch. The stack is POPed in

the event of a RETURN, RETLW or a RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The st ack operates as a circular buffer . This means that

af ter the st ack ha s be en PUSHed ei ght time s, th e nin th

push ove rwrite s the va lue tha t was s tored fro m the firs t

push. The tenth push ov erwr i tes the se co nd push (an d

so on).

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode < 10:0 >

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no STATUS bits to indicate

stack overflow or stack underflow

conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions, or the vectoring to an

interr upt add res s.

rfPIC12F675

DS70091B-page 16 Preliminary  2003-2013 Microchip Technology Inc.

2.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is no t a physica l register. Addres sing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

ally ac cesses data p ointed to b y the File Select register

(FSR). Reading INDF itself indirectly will produce 00h.

Writing to the INDF register indirectly results in a no

operation (although STATUS bits may be affected). An

ef fective 9-bit add ress is obt ained by conc atenating the

8-bit FSR register and the IRP bit (STATUS<7>), as

shown in Figure 2-4.

A simple pro gram to clear R AM locatio n 20h-2Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIR ECT ADDRES S ING

FIGURE 2-4: DIRECT/INDI RECT ADDRESSING rfPIC12F675

movlw 0x20 ;initialize pointer

movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;no clear next

CONTINUE ;yes continue

For memory map detail see Figure 2-2.

Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.

Data

Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1(1) RP0 6 0

From Opcode IRP(1) FSR Register

Bank Select Location Select

00 01 10 11 180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Not Used

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 17

rfPIC12F675

3.0 GPIO PORT

There are as many as six general purpose I/O pins

available. Depending on which peripherals are

enabled , some or all of the pins may not be a vailable as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

3.1 GPIO and the TRISIO Registers

GPIO is an 6-bit wide, bi-directional port. The

corresponding data direction register is TRISIO.

Setting a TRISIO bit (= 1) will make the corresponding

GPIO pin an input (i.e., put the corresponding output

driver in a Hi-impedance mode). Clearing a TRISIO bit

(= 0) will make the corresponding GPIO pin an output

(i.e., pu t the co ntents o f the output latch on the selecte d

pin) . The ex cepti on is GP 3, whic h is inpu t only an d its

TRISIO bit will always read as ‘1’. Example 3-1 shows

how to initialize GPIO.

Readi ng the GPIO regis ter reads the st atus of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. There-

fore, a write to a port impli es that the port pins are read,

this value is modified, and then written to the port data

latch. GP3 reads ‘0’ when MCLREN = 1.

The TRISIO register controls the direction of the

GP pins, even when they are being used as analog

inputs. The user must ensure the bits in the TRISIO

inputs. I/O pins configured as analog inputs always

read ‘0’.

EXAMPLE 3-1: INITIA LI ZING GPIO

3.2 Additional Pin Functions

Every GPIO pin on the rfPIC12F675 has an interrupt-

on-change option and every GPIO pin, except GP3,

has a weak pull-up option. The next two sections

describe these functions.

3.2.1 WEAK PULL-UP

Each of the GPIO pins , except GP3, ha s an individua lly

configurable weak internal pull-up. Control bits WPUx

enable or disable each pull-up. Refer to Register 3-3.

Each we ak p ull -up is au tom aticall y turned off wh en th e

port pin is configured as an output. The pull-ups are

disabled on a Power-on Reset by the GPPU bit

(OPTION<7>).

Note: Additional information on I/O ports may be

found in the PIC Mid-Range Reference

Manual (DS33023)

Note: The ANSEL (9Fh) and CMCON (19h)

registers (9Fh) must be initialized to

configure an analog channel as a digital

input. Pin s confi gur ed as analo g in put s will

read ‘0’.

bcf STATUS,RP0 ;Bank 0

clrf GPIO ;Init GPIO

movlw 07h ;Set GP<2:0> to

movwf CMCON ;digital IO

bsf STATUS,RP0 ;Bank 1

clrf ANSEL ;Digital I/O

movlw 0Ch ;Set GP<3:2> as inputs

movwf TRISIO ;and set GP<5:4,1:0>

;as outputs

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ’0’

bit 5-0: GPIO<5:0>: General Purpose I/O pin.

1 = Port pin is >VIH

0 = Port pin is <VIL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

rfPIC12F675

DS70091B-page 18 Preliminary  2003-2013 Microchip Technology Inc.

U-0 U-0 R/W-x R/W-x R-1 R/W-x R/W-x R/W-x

— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ’0’

bit 5-0: TRISIO<5:0>: General Purpose I/O Tri-State Control bit

1 = GPIO pin configured as an input (tri-stated)

0 = GPIO pin configured as an output.

Note: TRISIO<3> always reads 1.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

— — WPU5 WPU4 —WPU2 WPU1 WPU0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 WPU<5:4>: Weak Pull-up Register bit

1 = Pull-up enabled

0 = Pull-up disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 WPU<2:0>: Weak Pull-up Register bit

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode 

(TRISIO = 0).

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 19

rfPIC12F675

3.2.2 INTERRUPT-ON-CHANGE

Each o f the GP IO pins i s individual ly configu rable as a n

interrupt-on-change pin. Control bits IOC enable or

disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

comp ared w ith the old value la tched on the last rea d of

GPIO. The ‘mismatch’ out puts of the la st read are OR'd

together to set, the GP Port Change Interrupt flag bit

(GPIF) in the INTCON register.

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interr upt in the foll owin g man ner:

a) Any read or write of GPIO. This will end the

mismatch condition.

b) Clear the flag bit GPIF.

A mismatch condition will continue to set flag bit GPIF.

Reading GPIO will end the mismatch condition and

allow flag bit GPIF to be cleared.

Note: If a change on the I/O pin should occur

when th e read o peratio n is be ing ex ecute d

(start of the Q 2 cycle), then the GPIF inter-

rupt flag may not get set.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOC<5:0>: Interrupt-on-Change GPIO Control bit

1 = Interrupt-on-change enabled

0 = Interrupt-on-change disabled

Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be

recognized.

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

rfPIC12F675

DS70091B-page 20 Preliminary  2003-2013 Microchip Technology Inc.

3.3 Pin Descriptions and Diagrams

Each GPIO pin is multiplexed with other functions. The

pins and their c om bi ned functio ns a r e bri efl y de sc ribe d

here. For specific information about individual function s

such as the comparator or the A/D, refer to the

appropriate section in this Data Sheet.

3.3.1 GP0/AN0/CIN+

Figure 3-1 shows th e dia gram fo r this pin. T he GP0 pin

is configurable to function as one of the following:

• a general pur pose I/O

• an analog input for the A/D

• an analog input to the comparator

3.3.2 GP1/AN1/CIN-/VREF

Figure 3-1 shows th e dia gram fo r this pin. T he GP1 pin

is configurable to function as one of the following:

• as a general purpose I/O

• an analog input for the A/D

• an analog input to the comparator

• a voltage reference input for the A/D

FIGURE 3-1: BLOCK DIAGRAM OF GP0

AND GP1 PINS

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPU

RD PORT

PORT

TRISIO

IOC

Interrupt-on-Change

To Comparator

To A/D Converter

Analog

Input Mode

GPPU

Analog

Input Mode

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 21

rfPIC12F675

3.3.3 GP2/AN2/T0CKI/INT/COUT

Figure 3-2 shows the d iagram for th is pi n. The GP2 pi n

is configurable to function as one of the following:

• a general pur pose I/O

• an analog input for the A/D

• the clock input for TMR0

• an external edge triggered interrupt

• a digital output from the comparator

FIGURE 3-2: BLOCK DIAGRAM OF GP2

3.3.4 GP3/MCLR/VPP

Figure 3-3 shows the d iagram for th is pin . The GP3 pin

is configurable to function as one of the following:

• a general purpo se inp ut

• as Ma ster Cle ar Reset

FIGURE 3-3: BLOCK DIAGRAM OF GP3

I/O pin

VDD

VSS

VDD

Weak

Analog

Input Mode

Data Bus

WPU

PORT

TRISIO

IOC

Interrupt-on-Change

To A/D Converter

COUT

Enable

To INT

To TMR0

Analog

Input Mode

GPPU

RD PORT

Analog

Input

Mode

I/O pin

VSS

Data Bus

RD PORT

PORT

IOC

Interrupt-on-Change

RESET MCLRE

TRISIO VSS

MCLRE

rfPIC12F675

DS70091B-page 22 Preliminary  2003-2013 Microchip Technology Inc.

3.3.5 GP4/AN3/T1G/OSC2/CLKOUT

Figure 3-4 shows th e dia gram fo r this pin. T he GP4 pin

is configurable to function as one of the following:

• a general pur pose I/O

• an analog input for the A/D

• a TMR1 gate input

• a crystal/resonator connection

• a clock output

FIGURE 3-4: BLOCK DIAGRAM OF GP4

3.3.6 GP5/T1CKI/OSC1/CLKIN

Figure 3-5 shows the d iagram for th is pin . The GP5 pin

is configurable to function as one of the following:

• a general purpo se I/O

•a TMR1 clock input

• a cryst al/ resonator con nec tio n

• a cloc k inpu t

FIGURE 3-5: BLOCK DIAGRAM OF GP5

I/O pin

VDD

VSS

VDD

Weak

Analog

Input Mode

Data Bus

WPU

PORT

TRISIO

IOC

Interrupt-on-Change

FOSC/4

To A/D Converter

Oscillator

Circuit

OSC1

CLKOUT

Enable

Analog

Input Mode

GPPU

RD PORT

To TMR1 T1G

INTOSC/

RC/EC

(2)

CLK

Modes(1)

CLKOUT

Enable

Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT

Enable.

2: With CLKOUT option .

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPU

PORT

TRISIO

IOC

Interrupt-on-Change

To TMR1 or CLKGEN

INTOSC

Mode

RD PORT

INTOSC

Mode

GPPU

Oscillator

Circuit

OSC2

Note 1: Timer1 LP Oscillator enabled

2: When using Timer1 with LP oscillator, the Schmitt

Trigger is by-passed.

(2)

TMR1LPEN(1)

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 23

rfPIC12F675

TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOD

V alue on all

other

RESETS

05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

19h CMCON —COUT —CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000

81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

95h WPU — — WPU5 WPU4 —WPU2 WPU1 WPU0 --11 -111 --11 -111

96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000

9Fh ANSEL —ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by GPIO.

rfPIC12F675

DS70091B-page 24 Preliminary  2003-2013 Microchip Technology Inc.

NOTES:

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 25

rfPIC12F675

4.0 TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 4-1 is a block dia gram of the T ime r0 module an d

the prescaler shared with the WDT.

4.1 Timer0 Operation

Timer mode is selected by clearing the T0CS bit

(OPTION_REG<5>). In Timer mode, the Timer0

module will increment every instruction cycle (without

prescal er). If TMR0 is written , the in crement is inhibite d

for the following two instruction cycles. The user can

work around this by writing an adjusted value to the

TMR0 register.

Counter mode is selected by setting the T0CS bit

(OPTION_REG<5>). In this mode, the Timer0 module

will increment either on every rising or falling edge of

pin GP2/T0CKI. The incrementing edge is determined

by the source edge (T0SE) control bit

(OPTION_REG <4 >). Clea ring the T0SE bit se lec t s the

rising edge.

4.2 Timer0 Interrupt

A Timer0 interrupt is generated when the TMR0

overflow set s the T0IF bit. The inte rrupt can be maske d

by clearing the T0IE bit (INTCON<5>). The T0IF bit

(INTCON<2>) must be cleared in software by the

Timer0 module Interrupt Service Routine before re-

enabling this interrupt. The Timer0 interrupt cannot

wake the processor from SLEEP since the timer is

shut-off during SLEEP.

FIGURE 4-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Note: Additional information on the Timer0

module is av ai lab le in the PICmicroTM Mid-

Range Reference Manual (DS33023).

Note: Counter mode has specific external clock

requirements. Additional information on

these requirements is available in the

PICmicroTM Mid-Range Reference Manual

(DS33023).

T0CKI

T0SE

CLKOUT

TMR0

Watchdog

Timer

WDT

Time-out

PS0 - PS2

WDTE

Data Bus

Set Flag bit T0IF

on Overflow

T0CS

Note 1: T 0SE , T0CS, PSA, PS 0-PS 2 are bits in the Option register.

SYNC 2

Cycles

8-bit

Prescaler

(= FOSC/4)

PSA

rfPIC12F675

DS70091B-page 26 Preliminary  2003-2013 Microchip Technology Inc.

4.3 Using Timer0 with an External

Clock

When no pr escal er is used, t he ex ternal clo ck inp ut is

the same as the pre sc al er outp ut. Th e sy nch ron iz atio n

of T0CKI, with the internal phase clocks, is accom-

plishe d by sampling the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necess ary for T0C KI to be hi gh for at leas t 2TOSC (and

a small RC delay of 20 ns) and low for at least 2TOSC

(and a small RC delay of 20 ns). Refer to the electrical

specification of the desired device.

Note: The ANSEL (9Fh) and CMCON (19h)

registers must b e initia lized to configure a n

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 GPPU: GPIO Pull-up Enab le bit

1 = GPIO pull-u ps are disabled

0 = GPIO pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of GP2/INT pin

0 = Interrupt on falling edge of GP2/INT pin

bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit 

1 = Transition on GP2/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on GP2/T0CKI pin

0 = Increment on low-to-high transition on GP2/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the TIMER0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 27

rfPIC12F675

4.4 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer. For simplicity, this counter will be referred to as

“prescaler” throughout this Data Sheet. The prescaler

assignment is controlled in software by the control bit

PSA (OPTION_REG<3>). Clearing the PSA bit will

assign the prescaler to Timer0. Prescale values are

select able vi a the PS2:PS0 bit s (OPTIO N_REG<2:0> ).

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing

to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1, x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer.

4.4.1 SWITCHING PRESCALE R

ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed “on the fly” during

program execution). To avoid an unintended device

RESET, the following instruction sequence

(Example 4-1) must be executed when changing the

prescaler assignment from Timer0 to WDT.

EXAMPLE 4-1: CHANGIN G PRESCA LER

(TIMER0WDT)

To change prescaler from the WDT to the TMR0

module , use the se quence shown in Example 4-2. This

preca ution mus t be tak en even if the WDT is dis abled.

EXAMPLE 4-2: CHANGIN G PRESCA LER

(WDTTIMER0)

TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0

bcf STATUS,RP0 ;Bank 0

clrwdt ;Clear WDT

clrf TMR0 ;Clear TMR0 and

; prescaler

bsf STATUS,RP0 ;Bank 1

movlw b’00101111’ ;Required if desired

movwf OPTION_REG ; PS2:PS0 is

clrwdt ; 000 or 001

;

movlw b’00101xxx’ ;Set postscaler to

movwf OPTION_REG ; desired WDT rate

bcf STATUS,RP0 ;Bank 0

clrwdt ;Clear WDT and

; postscaler

bsf STATUS,RP0 ;Bank 1

movlw b’xxxx0xxx’ ;Select TMR0,

; prescale, and

; clock source

movwf OPTION_REG ;

bcf STATUS,RP0 ;Bank 0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

Value on

all other

RESETS

01h TMR0 Timer0 Mod ule Register xxxx xxxx uuuu uuuu

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. 

Shaded cells are not used by the Timer0 module.

rfPIC12F675

DS70091B-page 28 Preliminary  2003-2013 Microchip Technology Inc.

5.0 TIMER1 MODULE WITH GATE

CONTROL

The rfPIC12F67 5 devices have a 16-bit timer. Figure 5-1

shows the basic block diagram of the Timer1 module.

T imer1 has the following features:

• 16-bit timer/counter (TMR1H:TMR1L)

• Readable and writable

• Internal or external clock selection

• Synchronous or asynchronous operation

• Interrupt on overflow from FFFFh to 0000h

• Wake-up upon overflow (Asynchronous mode)

• Optional external enable input (T1G)

• Op tiona l LP oscilla tor

The Timer1 Control register (T1CON), shown in

select the various features of the Timer1 module.

FIGURE 5-1: TIMER1 B LOCK DIAGRAM

Note: Additional information on timer modules is

available in the PICmicroTM Mid-Range

Reference Manual (DS33023).

TMR1H TMR1L

LP Oscillator T1SYNC

TMR1CS

T1CKPS<1:0> SLEEP Input

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronize

Detect

Synchronized

Clock Input

OSC1

OSC2

Set Flag bit

TMR1IF on

Overflow

TMR1

TMR1ON

TMR1GE

TMR1ON

TMR1GE

INTOSC

T1OSCEN

w/o CLKOUT

T1G

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 29

rfPIC12F675

5.1 Timer1 Modes of Operation

Timer1 can operate in one of three modes:

• 16-bit timer with prescaler

• 16-bit synchronous counter

• 16-bit asynchronous counter

In Timer mode, Timer1 is incremented on every

instruction cycle. In Counter mode, Timer1 is

incremented on the rising edge of the external clock

input T 1CKI . In ad dit io n, the C ou nter mo de c loc k can

be synchronized to the microcontroller system clock

or run asynchronously.

In Count er and Timer modules , the c oun ter/t im er cl oc k

can be gated by the T1G input.

If an external clock oscillator is needed (and the

microcontroller is using the INTOSC w/o CLKOUT),

Timer1 can use the LP oscillator as a clock source.

5.2 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit (PIR1<0>) is set. To

enable the inter rupt on rollo ver , you m ust set th ese bits :

• Timer 1 interru pt Enab le bit (PIE1< 0>)

• PEIE bit (INTCON<6>)

• GIE bit (INTCON<7>).

The interrupt is cleared by clearing the TMR1IF in the

Interrupt Service Routine.

5.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4, or 8

divisions of the clock input. The T1CKPS bits

(T1CON<5:4>) control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write

to TMR1H or TMR1L.

FIGURE 5-2: TIMER1 I NCREMEN TIN G EDGE

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first

incr em enti ng ris ing edge.

Note: The T MR1H:TTMR 1L regi ster p air and the

TMR1IF bit should be cleared before

enabling interrupts.

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Ar rows indicate counter in crem ents.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the

clock.

rfPIC12F675

DS70091B-page 30 Preliminary  2003-2013 Microchip Technology Inc.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1 = Timer1 is on if T1G pin is low

0 = Timer1 is on

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale Value

10 = 1:4 Prescale Value

01 = 1:2 Prescale Value

00 = 1:1 Prescale Value

bit 3 T1OSCEN: LP Oscillator Enable Control bit

If INTOSC without CLKOUT oscillator is active:

1 = LP oscillator is enabled for Timer1 clock

0 = LP oscillator is off

Else:

This bit is ignored

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock.

bit 1 TMR1CS: Timer1 C lock Source Select bit

1 = External clock from T1OSO/T1CKI pin (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 31

rfPIC12F675

5.4 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external

clock input is not synchronized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during SLEEP and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer

(Section 5.4.1).

5.4.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L, while the timer is running

from an external asynchronous clock, will ensure a

valid read (taken care of in hardware). However, the

user shoul d keep i n mind that r eadi ng the 16-bit time r

in two 8-b it va lu es i tself, po ses cert ain probl em s, s inc e

the timer may overflow between the reads.

For write s, it is re comm ended that the us er simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may pro duce an

unpredi c table valu e in the timer registe r.

Reading the 16-bit value requires some care.

Examples 12-2 and 12-3 in the PIC Mid-Range MCU

Family Reference Manual (DS33023) show how to

read and write Timer1 when it is running in

Asynchronous mode.

5.5 Timer1 Oscillator

A cryst al osci llator circ uit is built-in between pins OSC1

(input) and OSC2 (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON<3>). The

oscill ator is a lo w powe r os cill ator rate d up t o 37 k Hz. It

will continue to run during SLEEP. It is primarily

intended for a 32 kHz crystal. Table 10-2 shows the

capacitor selection for the Timer1 oscillator.

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the system clock is derived from the internal oscillator.

As with the syste m LP oscil lator, the user must prov ide

a software time delay to ensure proper oscillator

start-up.

While enabled, TRISIO4 and TRISIO5 are set. GP4

and GP5 read ‘0’ and TRISIO4 and TRISIO5 are read

‘1’.

5.6 Timer1 Operation During SLEEP

Timer1 can only operate during SLEEP when setup in

Asynch ronous Counter mode. In this mode, an ext ernal

crystal or clock source can be used to increment the

counter. To setup the timer to wake the device:

• Timer1 must be on (T1CON<0>)

• TMR1IE bit (PIE1<0>) must be set

• PEIE bit (INTCON<6> ) must be set

The device will wake-up on an overflow. If the GIE bit

(INTCON< 7 >) is se t, the de vi ce wil l wa ke -up an d jum p

to the Interrupt Service Routine on an overflow.

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Note: The ANSEL (9Fh) and CMCON (19h)

registers must be initia lized to configu re an

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

Note: The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

Value on

all other

RESETS

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON —TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu

8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

rfPIC12F675

DS70091B-page 32 Preliminary  2003-2013 Microchip Technology Inc.

NOTES:

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 33

rfPIC12F675

6.0 COMPARATOR MODULE

The rfPIC12F675 devices have one analog

comparator. The inputs to the comparator are

multiplexed with t he GP0 and GP1 pins. There is an

on-chip Comparator V oltage Reference that can also

be applied to an input of the comparator. In addition,

GP2 can be configured as the comparator output.

The Comparator Cont rol Register (CMCON), shown

in Register 6-1, contains the bits to control the

comparator.

U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—COUT —CINV CIS CM2 CM1 CM0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6 COUT: Comparator Output bit

When CINV = 0:

1 = VIN+ > VIN-

0 = VIN+ < VIN-

When CINV = 1:

1 = VIN+ < VIN-

0 = VIN+ > VIN-

bit 5 Unimplemented: Read as ‘0’

bit 4 CINV: Comparator Output Inversion bit

1 = Output inverted

0 = Output not inverted

bit 3 CIS: Comparator Input Swit ch bit

When CM2:CM0 = 110 or 101:

1 = VIN- connects to CIN+

0 = VIN- connects to CIN-

bit 2-0 CM2:CM0: Com p ar ator Mode bits

Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

rfPIC12F675

DS70091B-page 34 Preliminary  2003-2013 Microchip Technology Inc.

6.1 Comparator Operation

A single comparator is shown in Figure 6-1, along with

the relationship between the analog input levels and

the digit al ou tput. When the an alog input a t VIN+ is less

than the analog input VIN-, the o utput of the co mparator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 6-1 represent

the uncertainty due to input offsets and response time.

The polarity of the comparator output can be inverted

by setting the CINV bit (CMCON<4>). Clearing CINV

results in a non-inverted output. A complete table

showing the output state versus input conditions and

the polarity bit is shown in Table 6-1.

TABLE 6-1: OUTPUT STATE VS. INPUT

CONDITIONS

FIGURE 6-1: SINGLE COMPARATOR

Note: To use CIN+ and CIN- pins as analog

inputs, the appropriate bits must be

programmed in the CMCON (19h) register .

Input Conditions CINV COUT

VIN- > VIN+0 0

VIN- < VIN+0 1

VIN- > VIN+1 1

VIN- < VIN+1 0

Output

VIN-

VIN+

Output

–

VIN+

VIN-

Note: CINV bit (CMCON<4>) is clear.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 35

rfPIC12F675

6.2 Comparator Configuration

There are eigh t mod es of operat ion fo r the c omp arato r.

The CMCON register , sho wn in Register 6-1, is used to

select the mode. Figure 6-2 shows the eight possible

modes. The TR ISIO regis ter co ntrols the data direction

of the comparator pins for each mode. If the

Comparator mode is changed, the comparator output

level may not be valid for a specified period of time.

Refer to the specifications in Section 13.0.

FIGURE 6-2: COMPARATOR I/O OPERATING MODES

Note: Comparator interrupts should be disabled

during a C omp arator mode change. O ther-

wise, a false interrupt may occur.

Comparator Reset (POR Default Value - low power) Comparator Off (Lowest power)

CM2:CM0 = 000 CM2:CM0 = 111

Comp ara tor witho ut Output Comparator w/o Output and with Internal Reference

CM2:CM0 = 010 CM2:CM0 = 100

Comparator with Ou tpu t and Intern al Refere nc e Multiplexed Input with Internal Reference and Output

CM2:CM0 = 011 CM2:CM0 = 101

Comp ara tor w ith Ou tpu t Multiplexed Input with Internal Reference

CM2:CM0 = 001 CM2:CM0 = 110

A = Analog Input, ports always reads ‘0’

D = Digital Input

CIS = Comparator Input Switch (CMCON<3>)

GP1/CIN-

GP0/CIN+ Off (Read as '0')

GP2/COUT D

GP1/CIN-

GP0/CIN+ Off (Read as '0')

GP2/COUT D

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D From CVREF Module

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D

From CVREF Module

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D

From CVREF Module

CIS = 0

CIS = 1

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D

From CVREF Module

CIS = 0

CIS = 1

rfPIC12F675

DS70091B-page 36 Preliminary  2003-2013 Microchip Technology Inc.

6.3 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 6-3. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. Th e analog input, th erefore, must be betw een

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latchup may occur. A

maximum source impedance of 10 k is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

FIGURE 6-3: ANALOG INPUT MODE

6.4 Comparator Output

The comparator output, COUT, is read through the

CMCON reg is ter. This bit is read-on ly. The comp ara tor

output may also be directly output to the GP2 pin in

three of the eight possible modes, as shown in

Figure 6-2. When in one of thes e modes , the ou tput on

GP2 is asynchronous to the internal clock. Figure 6-4

shows the comparator output block diagram.

The TRISIO<2> bit functions as an output enable/

disable for the GP2 pin while the comparator is in an

Output mode.

FIGURE 6-4: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM

Rs < 10K

AIN CPIN

5 pF

VDD

VT = 0.6V

RIC

Leakage

±500 nA

Vss

Legend: CPIN = Input Capacitance

VT= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to Various Junctions

RIC = Interconnect Resistance

RS= Source Impedance

VA = Analog Voltage

Note 1: When reading the GPIO register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert an analog input according to the

TTL input specification.

2: Analog le vels on any pin that is defined as

a digital inpu t, may caus e the input buff er

to consume more current than is

specified.

To GP2/T0CKI pin

RD CMCON

Set CMIF bit

RESET

To Data Bus

CINV

CVREF

RD CMCON

GP1/CIN-

GP0/CIN+

CM2:CM0

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 37

rfPIC12F675

6.5 Comparator Reference

The com par ato r m od ule also allows t he se lec t io n of a n

internally generated voltage reference for one of the

comparator inputs. The internal reference signal is

used for four of the eight Comparator modes. The

VRCON register, Register 6-2, controls the voltage

reference module shown in Figure 6-5.

6.5.1 CONFIGURING THE VOLTAGE

REFERENCE

The voltage reference can output 32 distinct voltage

levels, 16 in a high range and 16 in a low range.

The follow ing equati ons determi ne the output vo ltages :

6.5.2 VOLTAGE REFERENCE

ACCURACY/ERROR

The full range of VSS to VDD cannot b e r eali zed du e to

the construction of the module. The transistor s on the

top and bottom of the resistor ladder network

(Figure 6-5) keep CVREF from approaching VSS or

VDD. The V olt age Re ference is VDD derived and there-

fore, the CVREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Comparator

Vo ltag e Ref ere nce ca n be f oun d in Section 13.0.

FIGURE 6-5: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

6.6 Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is ensured to have a valid level. If

the internal reference is changed, the maximum delay

of the internal voltage reference must be considered

when using the comparator outputs. Otherwise, the

maximum delay of the comparators should be used

(Table 13-7).

6.7 Operation During SLEEP

Both the comparator and voltage reference, if enabled

before entering SLEEP mode, remain active during

SLEEP. This results in higher SLEEP currents than

shown in the power-down specifications. The

additio nal current consumed by the comp arator and the

voltage reference is shown separately in the specifica-

tions. To minimize power consumption while in SLEEP

mode, turn off the comparator, CM2:CM0 = 111, and

voltage reference, VRCON<7> = 0.

While the comparator is enabled during SLEEP, an

interrupt will wake-up the device. If the device wakes

up from SLEEP, the contents of the CMCON and

VRCON registers are not affected.

6.8 Effects of a RESET

A device RESET forces the CMCON and VRCON

registers to their RESET states. This forces the

comparator module to be in the Comparator Reset

mode, CM2:CM0 = 000 and the volt age reference to it s

off state. Thus, all potential inputs are analog inputs

with the comparator and voltage reference disabled to

consume the smallest current possible.

VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD

VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x

VDD / 32)

VRR

VR3:VR0

16-1 Analog

8RRR RR

CVREF to

16 Stages

Comparator

Input

VREN

VDD

MUX

rfPIC12F675

DS70091B-page 38 Preliminary  2003-2013 Microchip Technology Inc.

6.9 Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of the comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<6>, to

determine the actual change that has occurred. The

CMIF bit, PIR1<3>, is the comparator interrupt flag.

This bit must be reset in software by clearing it to ‘0’.

Since it is also possible to write a '1' to this register, a

simulated interrupt may be initiated.

The CMIE bit (PIE1<3>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit must also be set. If any of these

bits are cleared, th e interrupt is not enable d, though the

CMIF bit wil l stil l be se t if an interrupt condition occ urs .

The user , in the Interrupt Service Routine, can clear the

interrupt in the followi ng manner:

a) Any read or write of CMCON. This will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.

Readi ng C M CO N will end the mi sm atc h c ondition, an d

allow flag bit CMIF to be cleared.

TABLE 6-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

VREN —VRR —VR3 VR2 VR1 VR0

bit 7 bit 0

bit 7 VREN: CVREF Enable bit

1 = CVREF circuit powered on

0 = CVREF circuit powered down, no IDD drain

bit 6 Unimplemented: Read as '0'

bit 5 VRR: CVREF Range Selection bit

1 = Low range

0 = High range

bit 4 Unimplemented: Read as '0'

bit 3-0 VR3:VR0: CVREF value selection 0  VR [3:0]  15

When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

Note: If a change in the CMCON register (COUT)

should occur when a read operation is

being exe cuted (start of the Q2 cycl e), then

the CMIF (PIR1<3>) interrupt flag may not

get set.

Address Name Bit 7 Bi t 6 Bit 5 Bi t 4 Bi t 3 Bi t 2 Bit 1 Bit 0 Value on

POR, BOD

Value on

all other

RESETS

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0

19h CMCON —COUT —CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000

8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0

85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

99h VRCON VREN —VRR —VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000

Legend: x = unkno wn, u = unchanged, - = unimplemen ted, read as ‘0’. Shaded cells are not used by the comparator module.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 39

rfPIC12F675

7.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The analo g-to-digital converter (A/D) allows conversion

of an analog input signal to a 10-bit binary representa-

tion of that signal. The rfPIC12F675 has four analog

inputs, multiplexed into one sample and hold circuit.

The output of the sample and hold is connected to the

input of the converter. The converter generates a

binary result via succ essive approximation and stores

the result in a 10-bit register. The voltage reference

used in the conversion is software selectable to either

VDD or a voltage applied by the VREF pin. Figure 7-1

shows the block diagram of the A/D.

FIGURE 7-1: A/D BLOCK DIAGRAM

7.1 A/D Configuration and Operation

There are two registers available to control the

functionality of the A/D module:

1. ADCON0 (Register 7-1)

2. ANSEL (Register 7-2)

7.1.1 ANALOG PORT PINS

The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO

bits control the operation of the A/D port pins. Set the

corresponding TRISIO bits to set the pin output driver

to its high impedance state. Likewise, set the

corresponding ANS bit to disable the digital input

buffer.

7.1.2 CHANNEL SELECTION

There are four analog channels, AN0 through AN3. The

CHS1:CHS0 bits (ADCON0<3:2>) control which

channel is connected to the sample and hold circuit.

7.1.3 VOLTAGE REFERENCE

There are two options for the voltage reference to the

A/D converte r: either VDD is used, or an an alog volt age

applied to VREF is used. The VCFG bit (ADCON0<6>)

controls the volta ge reference s election. If VCFG is set,

then the voltage on the VREF pin is the reference;

otherwise, VDD is the reference.

7.1.4 CONVERSION CLOCK

The A/D conversion cycle requires 11 TAD. The source

of the conversion clock is software selectable via the

ADCS bits (ANSEL<6:4>). There are seven possible

clock options:

•FOSC/2

•FOSC/4

•FOSC/8

•FOSC/16

•FOSC/32

•FOSC/64

•FRC (dedicated internal RC oscillator)

For correct conversion, the A/D conversion clock

(1/TAD) must be selecte d to ensure a minimum TAD of

1.6 s. Table 7-1 shows a few TAD calculations for

selected frequencies.

GP0/AN0

ADC

GP1/AN1/VREF

GP2/AN2

GP4/AN3

VDD

VREF

ADON

GO/DONE

VCFG = 1

VCFG = 0

CHS1:CHS0

ADRESH ADRESL

ADFM

VSS

Note: Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

rfPIC12F675

DS70091B-page 40 Preliminary  2003-2013 Microchip Technology Inc.

TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES

7.1.5 STARTING A CONVERSION

The A/D conversion is initiated by setting the

GO/DONE bi t ( ADCO N0< 1>). Wh en t he c onv ers ion is

complete, the A/D module:

• Clears the GO/DONE bit

• Sets the ADIF flag (PIR1<6 >)

• Generates an interrupt (if enabled).

If the conversion must be aborted, the GO/DONE bit

can be cleared in software. The ADRESH:ADRESL

A/D conversion sample. Instead, the

ADRESH:ADRESL regi ste r s wi ll re tain th e va lue of th e

previous conversion. After an aborted conversion, a

2 TAD delay is required before another acquisition can

be initiated. Following the delay, an input acquisition is

automatically started on the selected channel.

7.1.6 CONVERSION OUTPUT

The A/D conversion can be supplied in two formats: left

or right shifted. The ADFM bit (ADCON0<7>) controls

the outpu t format. Figure 7-2 s hows the output formats.

FIGURE 7-2: 10-BIT A/D RESULT FORMAT

A/D Clock Source (TAD)Device Fr equ ency

Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz

2 TOSC 000 100 ns(2) 400 ns(2) 500 ns(2) 1.6 s

4 TOSC 100 200 ns(2) 800 ns(2) 1.0 s(2) 3.2 s

8 TOSC 001 400 ns(2) 1.6 s2.0 s6.4 s

16 TOSC 101 800 ns(2) 3.2 s4.0 s12.8 s(3)

32 TOSC 010 1.6 s6.4 s8.0 s(3) 25.6 s(3)

64 TOSC 110 3.2 s12.8 s(3) 16.0 s(3) 51.2 s(3)

A/D RC x11 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the

conversion will be pe rformed during SLEEP.

Note: The GO/DONE bit should not be set in the

same instruction that turns on the A/D.

ADRESH ADRESL

(ADFM = 0) MSB LSB

Bit 7 Bit 0 Bit 7 Bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1) MSB LSB

Bit 7 Bit 0 Bit 7 Bit 0

Unimplemented: Read as ‘0 10-bit A/D Result

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 41

rfPIC12F675

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM VCFG — — CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

bit 7 ADFM: A/D Result Formed Select bit

1 = Right justified

0 = Left justified

bit 6 VCFG: Voltage Reference bit

1 = VREF pin

0 = VDD

bit 5-4 Unimplemented: Read as zero

bit 3-2 CHS1:CHS0: Analog Channel Select bits

00 = Channel 00 (AN0)

01 = Channel 01 (AN1)

10 = Channel 02 (AN2)

11 = Channel 03 (AN3)

bit 1 GO/DONE: A/D Conversion STATUS bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. 

This bit is automatically cleared by hardware when the A/D conversion has completed.

0 = A/D conversion completed/not in progress

bit 0 ADON: A/D Conversion STATUS bit

1 = A/D converter module is operating

0 = A/D converter is shut-off and consumes no operating current

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

rfPIC12F675

DS70091B-page 42 Preliminary  2003-2013 Microchip Technology Inc.

U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1

—ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’.

bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits

000 = FOSC/2

001 = FOSC/8

010 = FOSC/32

x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)

100 = FOSC/4

101 = FOSC/16

110 = FOSC/64

bit 3-0 ANS3:ANS0: Analog Select bits 

(Between analog or digital function on pins AN<3:0>, respectively.)

1 = Analog input; pin is assigned as analog input(1)

0 = Digital I/O; pin is assigned to port or special function

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,

weak pull-up s, and interrup t-on-change. The corresponding TRIS IO bit must be set

to Input mode in order to allow external control of the voltage on the pin.

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 43

rfPIC12F675

7.2 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input mode l is sh ow n in Figure 7-3. The source

impeda nce (RS) and the inte rnal sam pling swi tch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), see

Figure 7-3. The maximum recommended imped-

ance for analog sources is 10 k. As the impedance

is decreased, the acquisition time may be decreased.

After the analog input channel is selected (changed),

this acquisition must be done before the conversion

can be sta rted.

To calculate the minimum acquisition time,

Equation 7-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D).

The 1/2 LSb error is the maximum error allowed for

the A/D to me et its spec ifie d re sol ut ion .

To calculate the minimum acquisition time, TACQ, see

the PIC Mid-Range Reference Manual (DS33023).

EQUATION 7-1: ACQUISITION TIME

FIGURE 7-3: ANALOG INPUT MODEL

TACQ

Amplifier Settling Time +

Hold Capacitor Charging Time +

Temperature Coefficient

TAMP + TC + TCOFF

2s + TC + [(Temperature -25°C)(0.05s/°C)]

CHOLD (RIC + RSS + RS) In(1/2047)

- 120pF (1k + 7k + 10k) In(0.0004885)

16.47s

2s + 16.47s + [(50°C -25C)(0.05s/C)

19.72s

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancel s itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin 

leakage specification.

CPIN

RSANx

5 pF

VDD

VT = 0.6V

VT = 0.6V I LEAKAGE

RIC  1K

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

567891011

(k)

VDD

= 120 pF

± 500 nA

Legend CPIN

I LEAKAGE

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

rfPIC12F675

DS70091B-page 44 Preliminary  2003-2013 Microchip Technology Inc.

7.3 A/D Operation During SLEEP

The A/D converter module can operate during SLEEP.

This requires the A/D clock source to be set to the

internal RC oscillator. When the RC clock source is

selected, the A/D waits one instruction before starting

the co nve rsion . This a llows the SLEEP instruction to be

execut ed, thus e lim inating m uc h o f th e s wi tc hin g n ois e

from the conversion. When the conversion is complete,

the GO/DONE bit is cleared, and the result is loaded

into the ADRESH:ADRESL registers. If the A/D

interrupt is enabled, the device awakens from SLEEP.

If the A/D interrupt is not enabled, the A/D module is

turned off, although the ADON bit remains set.

When the A/D clock source is something other than

RC, a SLEEP instruction causes the present conversion

to be aborted, and the A/D module is turned off. The

ADON bit remains set.

7.4 Effects of RESET

A device RESET forces all registers to their RESET

state. Thus the A/D module is turned off and any

pending conversi on is aborted. The ADRESH:ADRESL

registers are unchanged.

TABLE 7-2: SUMMARY OF A/D REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOD

Value on

all other

RESETS

05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx --uu uuuu

0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0

1Eh ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result xxxx xxxx uuuu uuuu

1Fh ADCON0 ADFM VCFG — — CHS1 CHS0 GO ADON 00-- 00 00 00-- 0000

85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 -- 11 11 11 --11 1111

8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0

9Eh ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result xxxx xxxx uuuu uuuu

9Fh ANSEL —ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -0 00 11 11 -000 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are no t used for A/D co nverter module.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 45

rfPIC12F675

8.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during no rmal operation (full VDD range). Thi s me mory

is not directly mapped in the register file space.

Instead, it is indirectly addressed through the Special

Function Registers. There are four SFRs used to read

and write this memory:

• EECON1

• EECON2 (not a physically implemented register)

• EEDATA

• EEADR

EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEPROM location

being accessed. The rfPIC12F675 devices have 128

bytes of dat a EEPROM with a n add res s ra nge from 0h

to 7Fh.

The EEPROM data memory allows byte rea d and write.

A byte write automatically erases the location and

writes the n ew data (erase be fore write). The EEPROM

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature as well as

from ch ip t o c hi p . Pl ea s e r efe r t o AC Specif ic ati o ns fo r

exact limits.

When the data memory is code protected, the CPU

may continue to read and write the data EEPROM

memory . The device programmer can no longer access

this memory.

Additional information on the Data EEPROM is

available in the PIC Mid-Range Reference Manual

(DS33023).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0

bit 7 bit 0

bit 7-0 EEDATn: Byte value to write to or read from Data EEPROM

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0

bit 7 bit 0

bit 7 Unimplemented: Should be set to '0'

bit 6-0 EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation

Legend:

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

rfPIC12F675

DS70091B-page 46 Preliminary  2003-2013 Microchip Technology Inc.

8.1 EEADR

The EEADR register can address up to a maximum of

128 bytes of data EEPROM. Only seven of the eight

bits in the register (EEADR<6:0>) are required. The

MSb (bit 7) is ignored.

The upper bit should always be ‘0’ to remain upward

compa tible with devic es that have more d ata EEPROM

memory.

8.2 EECON1 AND EECON2

REGISTERS

EECON1 is the control register with four low order bits

physically implemented. The upper four bits are non-

implemented and read as '0's.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On powe r-up, the WR EN bit is clear. The WRER R bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset duri ng normal opera-

tion. In th ese s ituatio ns, follo wing RESET, the user ca n

check the WRERR bit, clear it, and rewrite the location.

The data and address will be cleared, therefore, the

EEDATA and EEADR registers will need to be re-

initialized.

Interrupt flag bit EEIF in the PIR1 register is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the Data EEPROM write sequence.

U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

— — — — WRERR WREN WR RD

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3 WRERR: EEPROM Error Flag bit

1 =A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during 

normal operation or BOD detect)

0 =The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 =Init iates a write cycle (Th e bit is cleared by hardware once write is comp lete. The W R bit

can only be set, not cleared, in software.)

0 =Write cycle to the data EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit

can only be set, not cleared, in software.)

0 = Does not initiate an EEPROM read

Legend:

S = Bit can only be set 

R = Readable bit W = Writ ab le bit U = Unimplement ed bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 47

rfPIC12F675

8.3 READING THE EEPROM DATA

MEMORY

To read a data memory location, the user must write

the address to the EEADR register and then set

control bit RD (EECON1<0>), as shown in

Example 8-1. The data is available, in the very next

cycle, in the EEDATA register. Therefore, it can be

read in the next instruction. EEDATA holds this value

until another read, or until it is written to by the user

(during a write operation).

EXAMPLE 8-1: DATA EEPROM READ

8.4 WRITING TO THE EEPROM DATA

MEMORY

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDATA register. Then the user must follow a

specific sequence to initiate the write for each byte, as

shown in Example 8-2.

EXAM PLE 8-2: DATA EEPROM WRITE

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment. A cycle count is executed during the

required s equence . Any number th at is not equa l to the

required cycles to execute the required sequence will

prevent the data from being writte n into the EEPROM .

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

After a write sequence has been initiated, clearing the

WREN bit wil l not af fect this wr ite cycle. T he WR bit wil l

be inhibi ted from bei ng s et u nle ss the W R EN bit is se t.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit

(PIR<7>) register must be cleared by software.

8.5 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM should be verified (see Example 8-3) to the

desired value to be written.

EXAMPL E 8-3: W RIT E V E RIF Y

8.5.1 USING THE DATA EEPROM

The dat a EEPROM is a hi gh-endu rance, byte a ddress -

able array that has been optimized for the storage of

frequently changing information (e.g., program

variables or other data that are updated often).

Frequently changing values will typically be updated

more of ten than specific ations D12 0 or D120A. If this is

not t he ca se, an arra y re fres h mus t be perf orm ed. For

this reason, variabl es that chan ge infrequently (such as

constants, IDs, calibration, etc.) should be stored in

FLASH program memory.

8.6 PROTECTION AGAINST

SPURIOUS WRITE

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been buil t in. On power-u p, WREN is cleare d. Also, the

Power-up Timer (72 ms duration) prevents

EEPROM write.

The write in itiate seq ue nce an d the WREN bi t together

help prevent an accidental write during:

•brown-out

• power glitc h

• software malfunction

bsf STATUS,RP0 ;Bank 1

movlw CONFIG_ADDR ;

movwf EEADR ;Address to read

bsf EECON1,RD ;EE Read

movf EEDATA,W ;Move data to W

bsf STATUS,RP0 ;Bank 1

bsf EECON1,WREN ;Enable write

bcf INTCON,GIE ;Disable INTs

movlw 55h ;Unlock write

movwf EECON2 ;

movlw AAh ;

movwf EECON2 ;

bsf EECON1,WR ;Start the write

bsf INTCON,GIE ;Enable INTS

Required

Sequence

bcf STATUS,RP0 ;Bank 0

:;Any code

bsf STATUS,RP0 ;Bank 1 READ

movf EEDATA,W ;EEDATA not changed

;from previous write

bsf EECON1,RD ;YES, Read the

;value written

xorwf EEDATA,W

btfss STATUS,Z ;Is data the same

goto WRITE_ERR ;No, handle error

:;Yes, continue

rfPIC12F675

DS70091B-page 48 Preliminary  2003-2013 Microchip Technology Inc.

8.7 DATA EEPROM OPERATION

DURING CODE PROTECT

Data me mory can be code prot ected by program ming

the CPD bit to ‘0’.

When the data memory is code protected, the CPU is

able to read and write data to the Data EEPROM. It is

recommended to code protect the program memory

when code protecting data memory. This prevents

anyone from programming zeroes over the existing

code (which will execute as NOPs) to reach an added

routine, programmed in unused program memory,

which outputs the contents of data memory.

Programming unused locations to ‘0’ will also help

prevent data memory code protection from becoming

breached.

TABLE 8-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

Value on all

other

RESETS

0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0

9Ah EEDATA EEPROM Data Register 0000 0000 0000 0000

9Bh EEADR —EEPROM Address Register -000 0000 -000 0000

9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000

9Dh EECON2(1) EEPROM Control Register 2 ---- ---- ---- ----

Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. 

Shaded cells are not used by Data EEPROM module.

Note 1: EEC ON 2 is not a physical register.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 49

rfPIC12F675

9.0 UHF ASK/FSK TRANSMITTER

9.1 Transmitter Operation

The transmitter is a fully integrated UHF ASK/FSK

transmitter consisting of crystal oscillator, Phase-

Locked Loop (PLL), Power Amplifier (PA) with open-

collector output, and mode control logic. There are 3

variatio ns of th is d ev ice to op tim iz e its pe rform an ce for

the most commonly used frequency bands.

TABLE 9-1: FREQUENCY BANDS

The internal structure of the transmitter is shown in

Figure 9-1. A Colpitts oscillator generates the

reference frequency set by the attached crystal. The

volt age controll ed oscillat or (VCO) convert s the volt age

on the LF pin to a frequency. This frequency is divided

by 32 and compared to the crystal reference. If the

frequency or phase does not match the reference, the

charge pump corrects the voltage on the LF pin. The

VCO output signal is also amplified by the PA, whose

single ended output drives the user’s antenna.

The external components required are a crystal to set

the transmit frequency, a supply bypass capacitor, and

two to se ven biasing/ impedance m atching com ponents

to get m ax im um p ow er to the an tenna. The tw o co ntro l

signals from the microcontroller are connected exter-

nally for maximum design flexibility. The rfPIC12F675

is capable of transmitting data by Amplitude Shift

Keying (ASK) or Frequency Shift Keying (FSK).

The rfPIC12F675 is a radio frequency (RF) emitting

device. Wireless RF devices are governed by a

country ’s regulat ing agency. For exam ple, in the United

States it is the Federal Communications Committee

(FCC) and in Europe it is the European Conference of

Postal and Telecommunications Administrations

(CEPT). It i s the respon sibility of the designer to en sure

that their en d product conforms to rules and regulations

of the country of use and/or sale.

FIGURE 9-1: TRANSMITTER BLOCK

DIAGRAM

9.2 Supply Voltage (VDDRF, VSSRF)

Pins VDDRF and VSSRF supply power and ground

respectively to the transmitter. These power pins are

separate from power supply pins VDD and VSS to the

microcontroller. Both VSSRF pins should be tied to the

ground plane with the shortest possible traces. The

microcontroller ground should be tied to the same RF

groun d potentia l. Howeve r, the VDDRF suppl y can be at

a different po tential than th e mic roc on trol ler as long as

the RFEN and DATA input levels are within specifica-

tion limits .

Device Frequency Modulation

rfPIC12F675K 290-350 MHz ASK/FSK

rfPIC12F675F 390-450 MHz ASK/FSK

rfPIC12F675H 850-930 MHz ASK/FSK

RF devices require correct board level implementa-

tion in order to meet regulatory requirements. Layout

considerations are listed at the end of each subsec-

tion. It i s required to place a ground pla ne on the PCB

to reduce unwanted radio frequency emissions.

Layout Considerations - Provide low impedance

power and ground traces to minimize spurious

emi ssions. A t wo-side d PCB with a ground pl ane on

the bottom layer is highly recommended. Separate

bypass capacitors should be connected as close as

possible to each of the supply pins VDD and VDDRF.

Connect both VSSRF pins to the ground plane using

multipl e PCB vias adja cent to t he VSSRF pads. Do not

share these PCB vias with other ground traces. Filter

the VDDRF with an RC filter if th e microcontroll er noise

spurs exceed regulatory limits.

Clock

Divider

Voltage

Controlled

Oscillator

RF Power

Amplifier

Crystal

Oscillator

Phase/Freq

Detector

Charge

Pump

FSK Switch

REFCLK

Control

Logic

FSKOUT

VDDRF

VSSRF

RFEN

ANT

RFXTAL

DATAASK

Divide

by 32

DATAFSK

rfPIC12F675

DS70091B-page 50 Preliminary  2003-2013 Microchip Technology Inc.

9.3 Crystal Oscillator

The transmitter crystal oscillator is a Colpitts oscillator

that provides the reference frequency to the PLL. It is

independent of the microcontroller oscillator. An

external crystal or AC coupled reference signal is

connected to the XTAL pin. The transmit frequency is

fixed and determined by the crystal frequency

acco rding to the form ula:

Due to the flexible selection of transmit frequency, the

resulting crystal frequency may not be a standard off-

the-shelf value. Therefore, for some carrier frequencie s

the desi gner will have to co nsult a cry stal m anufactu rer

and have a custom crystal manufactured. For

background information on crystal selection see

Application Note AN588, PIC® Microcontroller Oscilla-

tor Design Guide , an d AN 82 6 Cr ys t a l O sc ill ato r Bas ic s

and Crystal Selection for rfPIC™ and PIC® Devices.

For ASK modulation the crystal can be connected

directly from RFXTAL to ground, or in series with an

additional capacitor to trim the frequency. Figure 9-2

shows how the crystal is connected and Table 9-2

shows how the frequency of a typical crystal changes

with capacitance.

The oscillator is enabled when the RFEN input is high.

It takes the crystal approximately 1 ms to start oscillat-

ing. Higher frequency crystals start-up faster than

lower frequencies. The crystal oscillator start time

(TON) is listed in Table 13-11, Transmitter AC

Characteristics. This start-up time is mainly due to the

crystal building up an oscillation, but also includes the

time fo r the P LL t o loc k on th e cry stal fr eq ue ncy.

9.4 ASK Modulation

In ASK modulation the data is transmitted by varying

the output power. The DATAASK pin enables the PA,

toggling the pin turn s the RF ou tput signa l on and of f. A

simple receiver using a tuned filter and peak detector

diode can capture the data. A more advanced super-

heterodyne receiver such as the rfRXD0420 can

greatly increase the range and reduce susceptibility to

interference.

In ASK mode the DATAFSK and FSKOUT pins are not

used an d shou ld both be tie d to gro und. An e xamp le of

a typical ASK circuit is shown in Figure 9-5. The C1

capacitor can be replaced by a short to simplify the

transmitter if the receiver has a wide enough

bandwidth. For a very narrowband receiver the C1

capacitor may need to be replaced by a trimmer cap to

tune the transmitter to the exact frequency.

FIGURE 9-2: ASK CRYSTAL CIRCUIT

TABLE 9-2: XTAL OSC APPROXIMATE FREQ. VS. CAPACITANCE (ASK MODE) (1)



RFXTAL

transmit ff

XTAL

rfPIC12F675K/F/H

C1 Predicted Frequency

(MHz) PPM from 13.55 MHz Transmit Frequency (MHz)

(32 * fXTAL)

22 pF 13.551438 +106 433.646

39 pF 13.550563 +42 433.618

100 pF 13.549844 -12 433.595

150 pF 13.549672 -24 433.5895

470 pF 13.549548 -33 433.5856

1000 pF 13.549344 -48 433.579

Note 1: Standard Operating Conditions (unless otherwise stated) TA = 25°C, RFEN = 1, VDDRF = 3V,

fXTAL = 13.55 MHz

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 51

rfPIC12F675

9.5 FSK Modulation

In FSK modulation the transmit data is sent by varying

the output frequency. This is done by loading the

reference crystal with extra capacitance to pull it to a

slightly lower frequency which the PLL then tracks.

Switching the capacitance in and out with the data

signal toggles the transmi tter betwee n two freque ncies.

These two crystal based frequencies are then

multiplied by 32 for the RF transmit frequency.

Unlike the ASK transmit frequency the FSK center

frequency is not actually transmitted. It is the artificial

point half way between the two transmitted

frequencies, calculated with this formula.

The othe r im po rtant param ete r in FSK is the fre que nc y

deviati on of the transmit frequency . Thi s measures how

far the frequency will swing from the center frequency.

Single ended deviation is calculated with this formula.

An FSK receiver will specify its optimal value of

deviation. The single ended deviation must be greater

than data rate / 4. The minimum deviation is usually

limited by the frequency accuracy of the transmitter and

receiver component s. The maximu m deviation is usually

limited by the pulling characteristics of the transmitter

crystal.

An extra cap acito r and the interna l switch are add ed to

the ASK design to build an FSK transmitter as shown

in Figure 9-3. The C1 cap acitor in se ries with the crystal

determines the maximum frequency.

With the DA TAFSK pin high the FSKOUT pin is o pen and

the C2 capacitor does not affect the frequency. When

the DATAFSK pin goes low, FSKOUT shorts to ground,

and the C2 is thrown in parall el with C1. The s um of th e

two ca ps pulls the o scillation frequency lowe r as shown

in Figure 9-4.

In FSK mode the DATAASK pin should be tied high to

enable the PA. The FSK circuit is shown in Figure 9-6.

Use accurate crystals for narrow bandwidth systems

and large values for C1 to reduce frequency drift.

FIGURE 9-3: FSK CRYSTAL CIRCUIT

FIGURE 9-4: FREQUENCY PULLING

TABLE 9-3: TYPICAL TRANSMIT CENTER FREQUENCY AND DEVIATION (FSK MODE) (1)

minmax ff





minmax ff





XTAL

rfPIC12F675K/F/H

FSKOUT

Frequency

(MHz)

Fmax

Fmin

C1 C1||C2

DATAFSK = 1 DATAFSK = 0

Load C apacitance (pF)

C2 = 1000 pF C2 = 100 pF C2 = 47 pF

C1 (pF) Freq (MHz) / Dev (kHz) Freq (MHz) / Dev (kHz) Freq (MHz) / Dev (kHz)

22 433.612 / 34 433.619 / 27 433.625 / 21

33 433.604 / 25 433.610 / 19 433.614 / 14

39 433.598 / 20 433.604 / 14 433.608 / 10

47 433.596 / 17 433.601 / 11.5 433.604 / 8

68 433.593 / 13 433.598 / 9 433.600 / 5.5

100 433.587 / 8 — —

Note 1: Standard Operating Conditions, TA = 25°C, RFEN = 1, VDDRF = 3V, fXTAL = 13.55 MHz

rfPIC12F675

DS70091B-page 52 Preliminary  2003-2013 Microchip Technology Inc.

FIGURE 9-5: TYP ICAL ASK TRANSMITTER SCHEMATIC

FIGURE 9-6: TYPICAL FSK TRANSMITTER SCHEMATIC

10 11

CLKOUT

RFENIN

DDRF

ANTV

SSRF

GP0/AN0/CIN+/ICSPDAT

GP1/AN1/CIN-/V

REF

/ICSPCLK

GP2/AN2/T0CKI/INT/COUTGP3/MCLR/V

GP4/AN3/T1G/OSC2/CLKOUT

GP5/T1CKI/OSC1/CLKIN

DATA

ASK

RFXTAL

DATA

FSK

OUT

rfPIC12F675K

BT1

0.1 μF

100 pF

5 pF

4 pF

120 nH

4.7 kΩ

SW1SW2

CR2032

Lithium Cell

Loop Antenna

C1 can be shorted

R1 can be omitted

10 11

CLKOUT

RFENIN

DDRF

ANTV

SSRF

GP0/AN0/CIN+/ICSPDAT

GP1/AN1/CIN-/V

REF

/ICSPCLK

GP2/AN2/T0CKI/INT/COUTGP3/MCLR/V

GP4/AN3/T1G/OSC2/CLKOUT

GP5/T1CKI/OSC1/CLKIN

DATA

ASK

RFXTAL

DATA

FSK

OUT

rfPIC12F675K

BT1

1000 pF

0.1 μF

100 pF

5 pF

4 pF

120 nH

220 kΩ

4.7 kΩ

SW1SW2

CR2032

Lithium Cell

Loop Antenna

13.55 MHz

39 pF

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 53

rfPIC12F675

9.6 Clock Output

The clock ou tput is avail able t o the microcont rol ler or

other circuits requiring an accurate reference

frequency. This signal would typically be used to

correct the internal RC oscillator for system designs

that r equire accurate bi t synchr onizatio n or ti ght time

division multiplexing. The REFCLK output can

connect dir ec tl y to t he T0 CKI or T1C KI.

The REFCLK output frequency is the crystal oscillator

divided by 4 on the rfPIC12F675K and rfPIC12F675F.

For the rfP IC12F675H the crystal oscillator is divided

by 8.

9.7 Phase-Locked Loop Filte r

The LF pin connects to an internal node on the PLL

filter. Typically the pin should not be connected. In

specialized cases it may be necessary to load this pin

with extra capacitance to ground. Adding capacitance

reduces the loop filter bandwidth which trades off an

increase in phase noise for a reduction in clock spurs.

Useful diagnostic measurements can be taken on the

LF pin with a high impedance, low capacitance probe.

Meas uri n g th e t i me fr om RFE N g o in g hi gh u nt il t h e L F

voltage stabilizes will determine the minimum delay

befor e the st art of a transmiss ion. For more inform ation

on PLL filters refer to Application Note AN846 Basic

PLL Filters for the rfPIC™/rfHCS.

9.8 Power Amplifier

The PLL output feeds the power amplifier (PA) which

drives the open-collector ANT output. The output

should be DC biased with an inductor to the VDDRF

supply. The output impedance must be matched to the

load impedance to deliver the maximum power. This is

typically done with a transformer or tapped capacitor

circuit. Failure to match the impedance may cause

exces siv e spu rious and ha rmonic e mi ss ion s. For more

information on transformer matching see Application

Note AN831, Matching Smal l Loop Antennas to rfPIC™

Devices. For more information on tapped capacitor

matching see Application Note AN242 Designing an

FCC Approved ASK rfPIC™ Transmitter.

The transmit output power can be adjusted in five

discrete steps from +9 dBm to -70 dBm by varying the

volt age on th e PS pin. Sin ce the PS pi n has an interna l

8 A sourc e the volt age can b e se t w ith a res ist or from

the PS pin to ground as shown in Figure 9-7. Some

possib le resisto r va lue s to se t the c urre nt are show n i n

Table 9-4.

It is usually desirable to select the lowest power level

step that does not compromise communications reli-

ablity. The most import ant benefi t is the conservat ion of

battery power. Another reason is to make it easier to

pass regulatory limits. And a third reason is to reduce

interference to o t he r co mm un ic ati ons in the shared R F

spectru m. Small ine f fici ent anten nas will require h igher

power level setting s than larger efficient ante nnas.

FIGURE 9-7: .POWER SELECT CIRCUIT

TABLE 9-4: POWER SELECT RESISTOR SELECTION (1,2)

Layout considerations - Keep the clock trace short

and narro w yet as far a s possi ble from ot her t races to

reduce capac it a nc e and the as so cia ted current draw.

If the REFCLK trace must pass near the crystal and

LF nodes then shield them with ground traces.

Layout considerations - Keep traces short and if the

optional loop filter capacitor is required, place it as

close as possible to the LF pin with its own via to the

ground plane.

rfPIC12F675

VPS

IPS = 8 A

To powe

select

circuitry

Power Step Output Power

(dBm) PS Voltage

(Volts) R1 Resistance

()RF Transmitter

Current (mA)

4 9 1.6 open 10.7

3 2 0.8 100k (3) 6.5

2-4 0.4 47k (3) 4.7

1-12 0.2 22k (3) 3.5

0-70 0.1 short 2.7

Note 1: Standard Operating Conditions, TA = 25°C, RFEN = 1, VDDRF = 3V, fTRANSMIT = 433.92 MHz

2: Typical values, for complete specifications see data sheet Section 13.0.

3: R1 resistor variations plus IPS current supply variations must not exceed VPS step limits.

rfPIC12F675

DS70091B-page 54 Preliminary  2003-2013 Microchip Technology Inc.

9.9 Digital Control Signals

The mode control logic pin RFEN controls the

operation of the transmitter. When RFEN goes high,

the crystal oscillator starts up. The voltage on the LF

pin ramps up proportionally to the RF frequency. The

PLL can lock onto the frequ ency fa ster than the s tart-

ing up crystal can stabilize. When the LF pin reaches

0.8V, the RF frequency is close to loc ked on the cry s-

tal frequency. This initiates a 150 microsecond delay

to ensure tha t the PLL settles. After the dela y, the PS

bias current and power amplifier are enabled to start

transmitting when DATAASK goes high.

When RFEN is low, the transmitter goes into a very

low power Standby mode. The power amplifier is

disabled and the crystal oscillator stops. The RFEN

pin has an internal pull-down resistor.

9.10 Low Voltage Output Disable

The rfPIC12F675 transmitter has a built in low voltage

disable ce nt er ed at a bou t 1 .8 5V. If the supp ly vo ltage

drops below this voltage the power amplifier is

disabled t o pr event unco ntro lle d tran smis sio ns.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 55

rfPIC12F675

10.0 SPECIAL FEATURES OF THE

CPU

Certain special circuits that deal with the needs of real

time applications are what sets a microcontroller apart

from other processors. The rfPIC12F675 Family has a

host of such features intended to:

• maximize system reliability

• minimize cost through elimination of external

components

• provide power saving operating modes and offer

code protection.

These features are:

• Oscillator selection

• RESET

- Power-o n Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Detect (BOD)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID Locations

• In-Circuit Serial Programming

The rfPIC12F675 has a Watchdog Timer that is

controlled by configuration bits. It runs off its own RC

oscill ator for ad ded reli abili ty. There ar e two ti mers th at

offer necessary delays on power-up. One is the

Oscillator Start-up Timer (OST), intended to keep the

chip in RESET until the crystal oscillator is stable. The

other is the Pow er-up Timer (PWRT), which provide s a

fixed delay of 72 ms (nominal) on power-up only,

designed to keep the part in RESET while the power

supply stabilizes. There is also circuitry to reset the

device if a brown-ou t occurs, whi ch can provide at least

a 72 ms RESET. With these three functions on-chip,

most applications need no external RESET circuitry.

The SLEEP mode is designed to offer a very low

current Power-down mode . The use r can wake-u p from

SLEEP through:

• External RESET

• Watchdog Timer wake-up

• An interrupt

Several oscillator options are also made available to

allow the p art to f it th e a pplicati on. The IN T O SC op tio n

saves system cost while the LP crystal option saves

power. A set of configuration bits are used to select

various options (see Register 10-1).

rfPIC12F675

DS70091B-page 56 Preliminary  2003-2013 Microchip Technology Inc.

10.1 Configuration Bits

The conf iguration bits can be programmed (read as '0'),

or left unprogrammed (read as '1') to select various

device configurations, as shown in Register 10-1.

These bits are mapped in program memory location

2007h.

Note: Address 2007h is beyond the user program

memory space. It belongs to the special

configuration memory space (2000h -

3FFFh), which can be accessed only during

programming. See rfPIC12F675 Program-

ming Specification for more information.

R/P-1 R/P-1 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

BG1 BG0 — — — CPD CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0

bit 13 bit 0

bit 13-12 BG1:BG0: Bandgap Calibration bits for BOD and POR voltage(1)

00 = Lowest bandgap voltage

11 = Highest bandgap voltage

bit 11-9 Unimplemented: Read as ‘0’

bit 8 CPD: Data Code Prote cti on bit(2)

1 = Data memory code protection is disabled

0 = Data memory code protection is enabled

bit 7 CP: Code Protection bit(3)

1 = Program Memory code protection is disabled

0 = Program Memory code protection is enabled

bit 6 BODEN: Brown-out Detect Enable bit(4)

1 = BOD enabled

0 = BOD disabled

bit 5 MCLRE: GP3/MCLR pin function select(5)

1 = GP3/MCLR pin function is MCLR 

0 = GP3/MCLR pin function is digital I/O, MCLR interna lly tied to VDD

bit 4 PWRTE: Power-up Timer Enable bit 

1 = PWRT disabled

0 = PWRT enabled

bit 3 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 2-0 FOSC2:FOSC0: Oscillator Selection bits

111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 

110 = RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN

101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN

100 = INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN

011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN

010 = HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN

001 = XT oscillator: Crys t al /res ona tor on GP4 /OSC 2 /CLKO UT and GP5 /O SC 1/CLKI N

000 = LP oscillator: Low power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN

Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing

the device as specified in the rfPIC12F675 Programming Specification. These bits are reflected in

an export of the configuration word. Microchip Development Tools maintain all calibration bits to

factory settings.

2: The entire data EEPROM will be erased when the code protection is turned off.

3: The entire program memory will be erased, including OSCCAL value, when the code protection is

turned off.

4: Enabling Brown-out Detect does not automatically enable Power-up Timer.

5: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

Legend:

P = Programmed using ICSP

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 57

rfPIC12F675

10.2 Oscillator Configurations

10.2.1 OSCILLAT OR TYPES

The rfPIC12F675 can be operated in eight different

Oscillator Option modes. The user can program three

configuration bits (FOSC2 through FOSC0) to select

one of these eight modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC External Resi stor/Capacito r (2 modes )

• INT O SC Int ern al Os ci ll ator (2 mod es )

• EC External Clock In

10.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1 and OSC2 pins to establish

oscillation (see Figure 10-1). The rfPIC12F675

oscillator design requires the use of a parallel cut

crystal. Use of a series cut crystal may yield a

frequency outside of the crystal manufacturers

specifications. When in XT, LP or HS modes, the

device can have an external clock source to drive the

OSC1 pin (see Figure 10-2).

FIGURE 10-1: CRYSTAL OPERATION (OR

CERAMIC RESONATOR)

HS, XT OR LP OSC

CONFIGURATION

FIGURE 10-2: EXTERNAL CLOCK INPUT

OPERAT ION (HS, XT, EC,

OR LP OSC

CONFIGURATION)

T ABLE 10-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

T ABLE 10-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Note: Additional information on oscillator config-

urations is available in the PICmicroTM

Mid-Range Reference Manual,

(DS33023)

Note 1: See Table 10-1 and Table 10-2 for recommended

values of C1 and C2.

2: A se ries resist or may be requi red for AT strip cut

crystals.

3: RF varies with the Oscillator mode selected

(Approx. value = 10 M

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3) SLEEP

To Internal

PIC12F629/675

Logic

RS(2)

Ranges Char ac teriz ed:

Mode Freq OSC1(C1) OSC2(C2)

XT 455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF

15 - 68 pF

68 - 100 pF

15 - 68 pF

HS 8.0 MHz

16.0 MHz 10 - 68 pF

10 - 22 pF 10 - 68 pF

10 - 22 pF

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time. These values are for design

guidance only. Since each resonator has

its own characteristics, the user should

consult the resonator manufacturer for

appropriate values of external

components.

Mode Freq OSC1(C1) OSC2(C2)

LP 32 kHz 68 - 100 pF 68 - 100 pF

XT 100 kHz

2 MHz

4 MHz

68 - 150 pF

15 - 30 pF

150 - 200 pF

15 - 30 pF

HS 8 MHz

10 MHz

20 MHz

15 - 30 pF

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time. These values are for design

guidance only. Rs may be required in HS

mode as well as XT mode to avoid

overdriving crystals with low drive level

specification. Since each crystal has its

own characteristics, the user should

consult the crystal manufacturer for

appropriate values of external

components.

Clock from

External Sy stem PIC12F629/675

OSC1

OSC2(1)

Open

Note 1: Functions as GP4 in EC Osc mode.

rfPIC12F675

DS70091B-page 58 Preliminary  2003-2013 Microchip Technology Inc.

10.2.3 EXTERNAL CLO CK IN

For applications where a clock is already available

elsewhere , users may di rectly drive the rfPIC12F 675

provided that this external clock source meets the AC/

DC timing requirements listed in Section 13.0.

Figure 10-2 shows how an external clock circuit

should be configured.

10.2.4 RC OSCILLATOR

For applications where precise timing is not a require-

ment, the RC oscillator option is available. The

operation and functionality of the RC oscillator is

dependent upon a number of variables. The RC

oscillator frequency is a function of:

• Supply voltage

• Resistor (REXT) and capacitor (CEXT) values

• Operati ng tem pera ture

The oscillator frequency will vary from unit to unit due

to normal process parameter variation. The difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to account for the

tolerance of the external R and C components.

Figure 10-3 shows how the R/C combination is

connected.

Two options are available for this Oscillator mode

which allow GP4 to be used as a general purpose I/O

or to output FOSC/4.

FIGURE 10-3: RC OSCILLATOR MODE

10.2.5 INTERNAL 4 MHZ OSCILLATOR

When calib rated, the in ternal oscillat or provide s a fixed

4 MHz (nominal) system clock. See Electrical

Specifications, Section 13.0, for information on

variation over voltage and temperature.

Two options are available for this Oscillator mode

which allow GP4 to be used as a general purpose I/O

or to output FOSC/4.

10.2.5.1 Calibrating the Internal Oscillator

A calibration instruction is programmed into the last

location of program memory. This instruction is a

RETLW XX, where the literal is the calibration value.

The literal is placed in the OSCCAL register to set the

calibration of the internal oscillator. Example 10-1

demonstrates how to calibrate the internal oscillator.

For best operation, decouple (with capacitance) VDD

and VSS as close to the device as possible.

EXAMPLE 10-1: CALIBRA TING THE

INTERNAL OSCILLATOR

10.2.6 CLKOUT

The rf PIC12F675 devi ce s can be c onfigu red to provid e

a clock out signal in the INTOSC and RC oscillator

modes. When configured, the oscillator frequency

divided by four (FOSC/4) is output on the GP4/OSC2/

CLKOUT pin. FOSC/4 can be used for test purposes or

to synchronize other logic.

Note: The microcontroller oscillator is indepen-

dent of the RF peripheral oscillator. An

accurate time-base is still possible with

only one crystal. Use the RF crystal on

transmitter and tie the REFCLK signal

back into T0CKI or T1CKI to correct the

RC, INTOSC, or EC clocks. Since REF-

CLK is only active when RFEN=1, it is not

a suitable source for CLKIN.

GP4/OSC2/CLKOUT

CEXT

VDD

REXT

VSS

PIC12F629/675

GP5/OSC1/

FOSC/4

Internal

Clock

CLKIN

Note: Erasing the device will also erase the pre-

programmed internal calibration value for

the inte rnal osci llator. The cali bration value

must be saved prior to erasing part as

specifi ed in the rfPIC12F6 75 Programmin g

specification. Microchip Development

Tools maintain all calibration bits to factory

settings.

bsf STATUS, RP0 ;Bank 1

call 3FFh ;Get the cal value

movwf OSCCAL ;Calibrate

bcf STATUS, RP0 ;Bank 0

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 59

rfPIC12F675

10.3 RESET

The rfPIC12F675 differentiates between various kinds

of RESET:

a) Power-on Reset (POR)

b) WDT Reset during normal operation

c) WDT Reset during SLEEP

d) MCLR Reset during normal operation

e) MCLR Reset during SLEEP

f) Brown-out Detect (BOD)

Some registers are not affected in any RESET

condition; their status is unknown on POR and

unchanged in any other RESET. Most other registers

are reset to a “RESET state” on:

• Power-on Reset

•MCLR Reset

•WDT Reset

• WDT Reset during SLEEP

• Brown-out Detect (BOD) Reset

They are not affected by a WDT wake-up, since this is

viewe d as the resump tio n of normal op era tion . TO and

PD bits are set or cleared diffe rently in diffe rent RESET

situations as indicated in Table 10-4. These bits are

used i n software to dete rmine the n ature of the RESET.

See Table 10-7 for a full descri ption of RESET states of

all registers.

A simplif ied block diagra m of the On-Chip Rese t Circuit

is shown in Figure 10-4.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Table 13-4 in Electrical

Specifications Section for pulse width specification.

FIGURE 10-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

VDD

OSC1/

WDT

Module

VDD Rise

Detect

OST/PWRT

On-chip(1)

RC OSC

WDT

Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST

Enable PWRT

SLEEP

See Table 10-3 for time-out situations.

Note 1: This is a separate oscillator from the INTOSC/EC oscillator.

Brown-out

Detect BODEN

CLKIN

VPP pin

10-bit Ripple Counter

rfPIC12F675

DS70091B-page 60 Preliminary  2003-2013 Microchip Technology Inc.

10.3.1 MCLR

The rfPIC12F675 devices have a noise filter in the

MCLR Reset path. The filter will detect and ignore

small pul ses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

The behavior of the ESD protection on the MCLR pin

has been altered from previous devices of this family.

Voltages appli ed to the p in that ex ceed i t s spe cific ation

can resu lt in both MCLR Rese ts and e xc es sive c urre nt

bey ond t h e de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt .

For this rea son, Microc hip recomme nds that the MCLR

pin no long er be tied direc tly to VDD. The us e of an RC

netw ork, as shown in Figure 10-5, is suggested.

An internal MCLR option is enabled by setting the

MCLRE bit in the configuration word. When enabled,

MCLR is internally tied to VDD. No internal pull-up

option is available for the MCLR pin.

FIGURE 10-5: RECOMMENDED MCLR

CIRCUIT

10.3.2 POWER-ON RESET (POR)

The on-chip POR circuit holds the chip in RESET until

VDD has reached a high enough level for proper

operat ion. To take a dvantage of the POR, simp ly tie the

MCLR pin through a res is tor to VDD. This will eliminate

external RC components usually needed to create

Power-on Reset. A maximum rise time for VDD is

required. See Electrical Specifications for details (see

Section 13.0).

When the device starts normal operation (exits the

RESET condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in RESET until the operating

conditions are met.

For additional information, refer to Application Note

AN607 “Power-up Trouble Shooting”.

10.3.3 POWER-UP TIMER (PWRT)

The P owe r-u p Timer pr ov ides a fi xed 72 ms (nominal)

time-out on power-up only, from POR or Brown-out

Detect. The Power-up Timer operates on an internal

RC oscillator. The chip is kept in RESET as long as

PWRT is active. The PWRT delay allows the VDD to

rise to an accep table lev el. A configurati on bit, PWRTE

can disable (if set) or enable (if cleared or

programmed) the Power-up Timer. The Power-up

Timer should always be enabled when Brown-out

Detect is enabled.

The Power-up Time delay will vary from chip to chip

and due to:

•VDD variation

• Temperature variation

• Process variation

See DC parameters for details (Section 13.0).

10.3.4 OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

Note: The POR circuit does not produce an

internal RESET when VDD declines.

VDD PIC12F629/675

MCLR

1 kor greater

0.1 f

(optio nal, not critic al )

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 61

rfPIC12F675

10.3.5 BROWN-OUT DETECT (BOD)

The rfPIC12F675 members have on-chip Brown-out

Detect circuitry. A configuration bit, BODEN, can

disable (if clear/programmed) or enable (if set) the

Brown-out Detect circuitry. If VDD falls below VBOD for

greater than parameter (TBOD) in Table 13-4 (see

Section 13.0), the Brown-out situation will reset the

devic e. This will occur regardless of VDD slew-rate. A

RESET is not guaranteed to occur if VDD falls below

VBOD for less than parameter (TBOD).

On any RESET (Power-on, Brown-out, Watchdog,

etc.), the chip will remain in RESET until VDD rises

above BVDD (see Figure 10-6). The Power-up Timer

will now be invoked, if enabled, and will keep the chip

in RESET an additional 72 ms.

If VDD drops below BVDD while the Power-up Timer is

running, the chip will go back into a Brown-out Detect

and the Power-u p Timer will be re-initialized. Onc e VDD

rises above BVDD, the Power-up Timer will execute a

72 ms RESET.

FIGURE 10-6: BROWN-OUT SITUATIONS

10.3.6 TIME-OUT SEQUENCE

On power-u p, the tim e-out sequ ence is as fo llows: first,

PWRT time-out is invoked after POR has expired.

Then, OST is activated. The total time-out will vary

based on oscillator configuration and PWRTE bit

status. For example, in EC mode with PWRTE bit

erased (PWRT disabled), there will be no time-out at

all. Figure 10-7, Figure 10-8 and Figure 10-9 depict

time-out sequences.

Since the time-outs oc cur from the POR pulse, if MCLR

is kep t low long e nough , the ti me-out s w ill e xpire. Then

bringing MCLR high will begin execution immediately

(see Figure 10-8). This is useful for testing purposes or

to synchronize more than one rfPIC12F675 device

operating in parallel.

Table 10-6 shows the RESET conditions for some

special registers, while Table 10-7 shows the RESET

conditions for all the registers.

10.3.7 POWER CONTROL (PCON) STATUS

The power CONTROL/STATUS register, PCON

(address 8Eh) has two bits.

Bit0 is BOD (Brown-out). BOD is unknown on Power-

on Reset. It must then be set by the user and checked

on subsequent RESETS to see if BOD = 0, indicat ing

that a brown-o ut has occurred. The BOD STA T US bit is

a don’t care and is not necessarily predictable if the

brown-o ut ci rcu it is dis abl ed (by setting BODEN bit = 0

in the Configuration word).

Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaf fec ted oth erwise. T he user m ust write a

‘1’ to this bit following a Power-on Reset. On a

subsequent RESET, if POR is ‘0’ , it will indica te that a

Power-on Reset must have occurred (i.e., VDD may

have gone too low ).

Note: A Brown-out Detect does not enable the

Power-up Timer if the PWRTE bit in the

configuration word is set.

72 ms(1)

VBOD

VDD

Internal

RESET

VBOD

VDD

Internal

RESET 72 ms(1)

<72 ms

72 ms(1)

VBOD

VDD

Internal

RESET

Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’.

rfPIC12F675

DS70091B-page 62 Preliminary  2003-2013 Microchip Technology Inc.

TABLE 10-3: TIME-OUT IN VARIOUS SITUATIONS

TABLE 10-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE

TABLE 10-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

TABLE 10-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Oscillator Configuration Power-up Brown-out Detect Wake-up

from SLEEP

PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1

XT, HS, LP TPWRT +

1024•TOSC 1024•TOSC TPWRT +

1024•TOSC 1024•TOSC 1024•TOSC

RC, EC, INTOSC TPWRT — TPWRT — —

POR BOD TO PD

0 u 1 1 Power-on Reset

1 0 1 1 Brown-out Detect

u u 0 u WDT Reset

u u 0 0 WDT Wake-up

u u u u MCLR Reset during normal operation

u u 1 0 MCLR Reset during SLEEP

Legend: u = unchanged, x = unknown

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

V alue on all

other

RESETS(1)

03h STATUS IRP RP1 RPO TO PD ZDC C0001 1xxx 000q quuu

8Eh PCON — — — — — — POR BOD ---- --0x ---- --uq

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during

normal operation.

Condition Program

Counter STATUS

Power-on Reset 000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 000h 000u uuuu ---- --uu

MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu

WDT Reset 000h 0000 uuuu ---- --uu

WDT Wake- up PC + 1 uuu0 0uuu ---- --uu

Brown-out Detect 000h 0001 1uuu ---- --10

Interrupt Wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the

interru pt vector (000 4h) a fter ex ecution o f PC+1.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 63

rfPIC12F675

TABLE 10-7: INITIALIZATION CONDITION FOR REGISTERS

Reset

•MCLR Reset during 

normal operation

•MCLR Reset during SLEEP

• WDT Reset

• Brown-out Detect(1)

• Wake-up from SLEEP

through interrupt

• Wake-up from SLEEP

through WDT time-out

W — xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h/80h — — —

TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h/82h 0000 0000 0000 0000 PC + 1(3)

STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4)

FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu

GPIO 05h --xx xxxx --uu uuuu --uu uuuu

PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh/8Bh 0000 0000 0000 000u uuuu uuqq(2)

PIR1 0Ch 00-- 0--0 00-- 0--0 qq-- q--q(2,5)

T1CON 10h -000 0000 -uuu uuuu -uuu uuuu

CMCON 19h -0-0 0000 -0-0 0000 -u-u uuuu

ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 1Fh 00-- 0000 00-- 0000 uu-- uuuu

OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu

TRISIO 85h --11 1111 --11 1111 --uu uuuu

PIE1 8Ch 00-- 0--0 00-- 0--0 uu-- u--u

PCON 8Eh ---- --0x ---- --uu(1,6) ---- --uu

OSCCAL 90h 1000 00-- 1000 00-- uuuu uu--

WPU 95h --11 -111 --11 -111 uuuu uuuu

IOC 96h --00 0000 --00 0000 --uu uuuu

VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu

EEDATA 9Ah 0000 0000 0000 0000 uuuu uuuu

EEADR 9Bh -000 0000 -000 0000 -uuu uuuu

EECON1 9Ch ---- x000 ---- q000 ---- uuuu

EECON2 9Dh ---- ---- ---- ---- ---- ----

ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu

ANSEL 9Fh -000 1111 -000 1111 -uuu uuuu

Legend: u = unchanged, x = unkn own, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 10-6 for RESET value for specific condition.

5: If wake-up was due to data EEPROM write completing, Bit 7 = 1; A/D conversion completing, Bit 6 = 1;

Comparator input changing, bit 3 = 1; or Timer1 rolling over, bit 0 = 1. All other interrupts generating a 

wake-up w i ll cause t hese bits to = u.

6: If RESET was due to brown-out, then bit 0 = 0. All other RESETS will cause bit 0 = u.

rfPIC12F675

DS70091B-page 64 Preliminary  2003-2013 Microchip Technology Inc.

FIGURE 10-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT T ime-out

OST Time-out

Internal RESET

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Interna l R ES ET

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Interna l R ES ET

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 65

rfPIC12F675

10.4 Interrupts

The rfPIC12F675 has 7 sources of interrupt:

• External Inte rrup t GP2/INT

• TMR0 Overfl ow Interru pt

• GPIO Change Interrupts

• Comparator Interrupt

• A/D Interrupt

• TMR1 Overfl ow Interru pt

• EEPROM Data Write Interrupt

The Interrup t Control register (INTCON) and Peripheral

Interrupt register (PIR) record individual interrupt

requests in flag bits. The INTCON register also has

individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>) enables

(if set) all unmaske d interrupts, or disable s (if cleared) all

interrupts. Individual interrupts can be disabled through

their corresponding enable bits in INTCON register and

PIE register. GIE is cleared on RESET.

The return f rom interrupt instruction, RETFIE, exits

interrupt routine, as well as sets the GIE bit, which

re-enables unmasked inter rupts.

The following interrupt flags are contained in the

INTCON register:

• INT pin interrupt

• GP port change interrupt

• TMR0 ove rflo w interru pt

The peripheral interrupt flags are contained in the

special register PIR1. The corresponding interrupt

enable bit is contained in Special Register PIE1.

The following interrupt flags are contained in the PIR

• EEPROM data write interrupt

• A/D interrupt

• Comparator interrupt

• Timer1 overflow interrupt

When an interrupt is serviced:

• The GIE is cleared to disable any further interrupt

• The return address is pushed onto the stack

• The PC is loaded with 0004h

Once in the Interrupt Service Routine, the source(s) of

the interrupt can be determined by polling the interrupt

flag bits. The interrupt flag bit(s) must be cleared in

software before re-enabling interrupts to avoid GP2/

INT recursive interrupts.

For external interrupt events, such as the INT pin, or

GP port change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 10-11). The latency is the same for one or two-

cycle instructions. Once in the Interrupt Service

Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts which were

ignored are still pending to be serviced

when the GIE bit is set again.

rfPIC12F675

DS70091B-page 66 Preliminary  2003-2013 Microchip Technology Inc.

FIGURE 10-10: INTERRUPT LOGIC

TMR1IF

TMR1IE

CMIF

CMIE

T0IF

T0IE

INTF

INTE

GPIF

GPIE

GIE

PEIE

Wake-up (If in SLEEP mode)

Interrupt to C PU

EEIE

EEIF

ADIF

ADIE

IOC-GP0

IOC0

IOC-GP1

IOC1

IOC-GP2

IOC2

IOC-GP3

IOC3

IOC-GP4

IOC4

IOC-GP5

IOC5

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 67

rfPIC12F675

10.4.1 GP2/INT INTERRUPT

External interrupt on GP2/INT pin is edge-triggered;

either rising if INTEDG bit (OPTION<6>) is set, of

falling, if INTEDG bit is clear. When a valid edge

appears on the GP2/INT pin, the INTF bit

(INTCON<1>) is set. This interrupt can be disabled by

clear ing th e INTE control bit (IN TCON<4> ). The I NTF

bit must be cleared in software in the Interrupt Service

Routin e bef ore re-e nab li ng thi s in terru pt. Th e GP2 /IN T

interrupt can wak e-up th e proc es sor f r om SL EEP i f the

INTE bit was set prior to going into SLEEP. The status

of the GIE bit decides whether or not the processor

branche s to the interru pt vector foll owing wake-up. Se e

Section 10.9 for d etails on SLEEP and Figure 10-13 for

timing of wake-up from SLEEP through GP2/INT

interrupt.

10.4.2 TMR0 INTERRUPT

An overflow (FFh  00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

be enabled/disabled by setting/clearing T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 4.0.

10.4.3 GPIO INTERRUPT

An input change on GPIO change sets the GPIF

(INTCON<0>) bit. The interrupt can be enabled/

disabled by setting/clearing the GPIE (INTCON<3>)

bit. Plus individual pins can be configured through the

IOC register.

10.4.4 COMPARATOR INTERRUPT

See Section 6.9 for descripti on of comp arator int errupt.

10.4.5 A/D CONVERTER INTERRUPT

After a c onv ers io n is co mpl ete , the ADIF flag (PIR<6 >)

is set. T he inte rrupt ca n be en abl ed/dis abled by se tting

or clearing ADIE (PIE<6>).

See Section 7.0 for operation of the A/D converter

interrupt.

FIGURE 10-11: INT PIN INTERRUPT TI MING

Note: The ANSEL (9Fh) and CMCON (19h)

registers must be initia lized to configu re an

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

Note: If a change on the I/O pin should occur

when th e read o peratio n is be ing ex ecute d

(start of the Q 2 cycle), then the GPIF inter-

rupt flag may not get set.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC PC+1 PC+1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycle

Inst (PC) Inst (PC+1)

Inst (PC-1) Inst (0004h)

Dummy Cycle

Inst ( PC)

—

512

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC Oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

rfPIC12F675

DS70091B-page 68 Preliminary  2003-2013 Microchip Technology Inc.

TABLE 10-8: SUMMARY OF INTERRUPT REGISTERS

10.5 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt, (e.g., W register and

STATUS register). This must be implemented in

software.

Example 10-2 stores and restores the STATUS and W

in both banks and must be defined at the same offset

from the bank base address (i.e., W_TEMP is defined

at 0x20 in Bank 0 and it must also be defined at 0xA0

in Bank 1 ). The us er registe r, STATUS_TEMP, must be

defined in Bank 0. The Example 10-2:

• Stores the W register

• Stores the STATUS register in Bank 0

• Executes the ISR code

• Restores the STATUS (and bank select bit

• Restore s the W register

EXAMPLE 10-2: SA VING THE ST A TUS AND

W REGISTERS IN RAM

10.6 Watchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip RC

oscillator, which requires no external components. This

RC oscillator is sep arate from the external RC oscillator

of the CLKIN pin and INTOSC. That means that the

WDT will run , even if th e clock on th e OSC1 and OSC 2

pins of the device has been stopped (for example, by

execution of a SLEEP instruction). During normal

operatio n, a WDT time-o ut gen erates a devic e RESET.

If the device is in SLEEP mode, a WDT time-out

causes the device to wake-up and continue with normal

operation. The WDT can be permanently disabled by

programming the configuration bit WDTE as clear

(Section 10.1).

10.6.1 WDT PERIOD

The WDT ha s a nominal tim e-out period of 18 ms, (wi th

no prescaler). The time-out periods vary with tempera-

ture, VDD and process variations from part to part (see

DC specs). If longer time-out periods are desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT under software control by writing

to the OPTION register. Thus, time-out periods up to

2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the presc al er, if assigne d to the WD T, and pre vent

it from timing out and generating a device RESET.

The TO bit in the ST ATUS register will be cleared upon

a Watchdog Timer time-out.

10.6.2 WDT PROGRAMMING

CONSIDERATIONS

It should also be taken in account that under worst case

conditions (i.e., VDD = Min., Temperature = Max., Max.

WDT prescaler) it may take several seconds before a

WDT time-out occurs.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0 Value on

POR, BOD

Value on all

other

RESETS

0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0

8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0

Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. 

Shaded cells are not used by the Interrupt module.

MOVWF W_TEMP ;copy W to temp register,

could be in either bank

SWAPF STATUS,W ;swap status to be saved into W

BCF STATUS,RP0 ;change to bank 0 regardl ess of

current bank

MOVWF STATUS_TEMP ;save status to bank 0 register

:(ISR)

SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into

W, sets bank to original state

MOVWF STATUS ;move W into STATUS register

SWAPF W_TEMP,F ;swap W_TEMP

SWAPF W_TEMP,W ;swap W_TEMP into W

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 69

rfPIC12F675

FIGURE 10-12: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 10-9: SUMMARY OF WATCHDOG TIMER REGISTERS

10.7 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution but are

readable and writable during Program/Verify. Only the

Least Significant 7 bits of the ID locations are used.

10.8 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out for verification purposes.

T0CKI

T0SE

CLKOUT

TMR0

Watchdog

Timer

WDT

Time-out

PS0 - PS2

WDTE

Data Bus

Set Flag bit T0IF

on Overflow

T0CS

Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.

SYNC 2

Cycles

8-bit

Prescaler

(= FOSC/4)

PSA

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V a lue on

POR, BOD

V alue on all

other

RESETS

81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

2007h Config. bits CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 uuuu uuuu uuuu uuuu

Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.

Note: The entire data EEPROM and FLASH

program memory will be erased when the

code protection is turned off. The INTOSC

calibration data is also erased. See

rfPIC12F675 Programming Specification

for more information.

rfPIC12F675

DS70091B-page 70 Preliminary  2003-2013 Microchip Technology Inc.

10.9 Power-Down Mode (SLEEP)

The Power-down mode is entered by executing a

SLEEP instruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running

•PD bit in the STATUS register is cleared

•TO bit is set

• Oscillator driver is turned off

• I/O ports maintain the status they had before

SLEEP was executed (driving high, low, or 

hi-impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD, or VSS, with no external

circuitry drawing current from the I/O pin and the

comparators and CVREF should be disabled. I/O pins

that are hi-impedance inputs should be pulled high or

low externally to avoid switching currents caused by

floating inputs. The T0CKI input should also be at VDD

or VSS for lowest current consumption. The contribu-

tion from on-chip pull-ups on GPIO should be

considered.

The MCLR pin must be at a logic high level (VIHMC).

10.9.1 WAKE-UP FR OM SLEE P

The device can wake-up from SLEEP through one of

the following events:

1. External RESET input on MCLR pin

2. W atchdog Ti mer Wake-up (if WDT was enabled)

3. Interrupt from GP2/INT pin, GPIO change, or a

peripheral interrupt.

The first event will cause a device RESET. The two

latter events are considered a continuation of program

execution. The TO and PD bits in the STA TUS register

can be used to determine the cause of device RESET.

The PD bit, whic h is set on power -u p, is cl ear ed wh en

SLEEP is invoked. TO bit is cleared if WDT Wake-up

occurred.

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake -up throug h an inte rrupt event, th e corres pond -

ing inte rrupt enabl e bit mu st be set (enabl ed). W ake-u p

is regardl es s of the st at e of the GIE bi t. If the G IE bit is

clear (disabled), the device continues execution at the

ins truction after the SLEEP instruction. If the GIE bit is

set (enabled), the device execute s the instruction after

the SLEEP instruction, then branches to the interrupt

address (0004h). In cases where the execution of the

instr u cti o n f oll o w ing SLEEP is not desirable, the user

should hav e an NOP afte r the SLEEP instruction.

The WDT is cleared when the device wakes up from

SLEEP, regardless of the source of wake-up.

FIGURE 10-13: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Note: It s hould be no ted that a RESET generate d

by a WDT time-out does not drive MCLR

pin low.

Note: If the global interrupts are disabled (GIE is

cleared ), but any in terru pt source has bo th

its interrup t enable b it a nd the corres pon d -

ing interrupt flag bits set, the device will

immediately wake-up from SLEEP. The

SLEEP instructi on is com pl ete ly exec ute d.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP Oscillator mode assume d.

2: TOST = 1024TOSC (drawing not to scale). Approximately 1 s delay will be there for RC Osc mode. See Section 12 for wake-up from

SLEEP delay in INT OSC mode.

3: GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-l ine .

4: CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 71

rfPIC12F675

FIGURE 10-14: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

10.10 In-Circuit Serial Programming

The rfPIC12F675 microcontrollers can be serially

progra mmed w hile in t he en d app licati on c ircuit. This is

done with two lines for clock and data, and three lines

for power, ground, and programming voltage.

This allows customers to manufacture boards with

unprogrammed devices, and then program the

microcontroller before shipping the product. This also

allows the most recent firmware or custom firmware to

be programmed.

The device is placed into a Program/Verify mode by

holding the GP0 and GP1 pins low, while raising the

MCLR (VPP) pin from VIL to VIHH (see Programming

Specification). GP0 becomes the programming data

and GP1 becomes the programming clock. Both GP0

and GP1 are Schmitt Trigger inputs in this mode.

After RESET, to place the device into Programming/

Verify mode, the program counter (PC) is at location

00h. A 6-bit command is then supplied to the device.

Depending on the command, 14-bits of program data

are then supplied to or from the device, depending on

whether the command was a load or a read. For

comple te d et ails of s eri al p rogrammi ng, p lea se refer to

the Programming Specifications document.

A typical In-Circuit Serial Programming connection is

shown in Figure 10-14. The programming connections

are isolated from conflicting outputs and capacitive

loads by the 3 resis tors. The VDD connec tion o n MCLR

may no t be re quired if the pin i s conf igured as GP3. Do

not place sensitive circuitry on the GP3/MCLR pin

withou t protection since the VPP sig nal goes w ell above

VDD during programming.

FIGURE 10-15: PARALLEL DIP SOCKET

FOR EMULATION

10.11 In-Circuit Debugging

Since in-circuit debugging requires the loss of clock,

data and MCLR pins, MPLAB® ICD 2 development with

an 8-pin microcontroller is not practical. Since the

MPLAB ICE 2000 emulation module leads would be

too long for the RF signals the following debug/emula-

tion strategy is recommended.

Build a prototype b oard with all your di gital, a nalog, and

RF circuitry . Add an 8 pin DIP socket for the PIC12F675

debuggi ng. Connect th e so cket as sh own in Figure 10-

15. When soldering the rfPIC12F675 down bend up

pins 1-4 and 17-20 so that they do not contact the

board. A PIC12F675 or emulation/debugging develop-

ment tool can be plugged into the socket as in

Figure 10-16.

This t est meth od e ncou rage s RF d evel opm ent to star t

early , as soon as the firmware can toggle the RF enable

and data lines. The socket can even be left in the final

layout for in-circuit production programming. A simple

method for programming is to solder all the

rfPIC12F675 pins to the board and move the 8-pin DIP

socke t to the ba ck side o f the board . Then use the 8-pin

standoff from the MPLAB ICE 2000 emulator to

connect the PCB to a programmer such as the Pro

Mate® II or PICkit™ 1 as in Figure 10-17.

There is an ICD 2 header inteface board for the

PIC12F675, part number AC162050. This special ICD

module is mounted on the top of a header and its

External

Connector

Signals

To Normal

Connections

To Normal

Connections

rfPIC12F675

VDD

VSS

GP3/MCLR/VPP

GP1

GP0

+5V

VPP

CLK

Data I/O

VDD

VSS

GP0

GP1

GP2

VDD

GP5

GP4

GP3

PIC12F675 rfPIC12F675

rfPIC12F675

DS70091B-page 72 Preliminary  2003-2013 Microchip Technology Inc.

signals are routed to the MPLAB ICD 2 connector. On

the bottom of the header is an 8-pin socket that plugs

into the u s er’s target via th e 8-pi n standoff connector.

When the ICD pin on the PIC12F675-ICD device is held

low, the In-Circuit Debugger functionality is enabled.

This function allows simple debugging functions when

used with MPLAB ICD 2. When the microcontroller has

this feature enabled, some of the resources are not

available for general use. Table 10-10 shows resources

consumed by the background debugger:

TABLE 10-10: DEBUGGER RESOURCES

For more i nform at ion , se e 8- Pin M PLAB I CD 2 H ead er

Information Sheet (DS51292) available on Microchip’s

website (www.microchip.co m ).

FIGURE 10-16: IN-CIRCUIT DEBUGGING USIN G THE PARALLEL DIP SOCKET

FIGURE 10-17: IN-CIRCUIT PROGRAMMING USING THE PARALLEL DIP SOCKET

I/O pins ICDCLK, ICDDATA

Stack 1 level

Program Memory Addre ss 0h must be NOP

300h - 3FEh

Socket

DVA12XP081

Standoff

rfPIC12F675

To MPLAB ICE 2000

PCM12XB0

AC162050

Standoff

rfPIC12F675

Socket

Programmer

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 73

rfPIC12F675

11.0 INSTRUCTION SET SUMMARY

The rfPIC12F675 instruction set is highly orthogonal

and is comprised of three basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Each rfPIC12F675 instruction is a 14-bit word divided

into an opcode, which specifies the instruction type,

and one or more operands, which further specify the

operatio n of the instruc tion. The form ats for each of the

categories is presented in Figure 11-1, while the

various opcode fields are summarized in Table 11-1.

Table 11-2 lists the instructions recognized by the

MPASMTM assembler. A complete description of

each instruction is also available in the PIC Mid-

Range Reference Manual ( DS3302 3).

For byte-oriented instructions, ‘f’ represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The desti nation designator specifies where the result of

the operation is to be placed. If ‘d’ is zero , th e r e sult is

placed in the W re gister . If ‘d’ is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operatio n, whi le ‘f’ re pre sen t s t he ad dres s o f the f ile in

which the bit is located.

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

One instr uction cycle co nsists of four os cillator periods ;

for an oscillator frequency o f 4 MHz, t his gives a normal

instruction execution time of 1 s. All instructions are

executed within a single instruction cycle, unless a

conditional test is true, or the program counter is

change d as a result of an instruct ion. When this occurs,

the execution takes two instruction cycles, with the

second cycle executed as a NOP.

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies

a hexadecimal digit.

11.1 READ-MODIFY-WRITE

OPERATIONS

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

For exam pl e, a CLRF GPIO in st ruc tion w i ll read G PIO ,

clear all the data bits, then write the result back to

GPIO. This example would have the unintended result

that the condition that sets the GPIF flag would be

cleared.

TABLE 11-1: OPCODE FIELD

DESCRIPTIONS

FIGURE 11-1: GENERAL FORMAT FOR

INSTRUCTIONS

Note: To maintain upward compatibility with

future products, do not use the OPTION

and TRISIO instructions.

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral field, constant data or label

xDon't care loc ati on (= 0 or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for 

compatibility with all Microchip software tools.

dDestination select; d = 0: store resul t in W,

d = 1: store result in file register f.

Default is d = 1.

PC Program Counter

TO Time-out bit

PD Power-down bit

Byte-orie nte d f ile re gi s ter operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriente d file re gister operati ons

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

rfPIC12F675

DS70091B-page 74 Preliminary  2003-2013 Microchip Technology Inc.

TABLE 11-2: rfPIC12F675 INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-B it Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED F ILE REGIST ER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0xxx

dfff

lfff

0xx0

dfff

ffff

xxxx

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move li te r a l to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR lite r a l w i th W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external

device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Note: Additional information on the mid-range instruction set is available in the PIC Mid-Range MCU Family Ref-

erence Manual (DS33023).

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 75

rfPIC12F675

11.2 Instruction Descripti ons

ADDLW Add Literal and W

Syntax: [label] ADDLW k

Operands: 0  k  255

Operation: (W) + k  (W)

Status Affected: C, DC, Z

Description: The contents of the W register

are ad ded to the eight-bi t literal 'k'

and the result is placed in the W

ADDWF Add W and f

Syntax: [label] ADDWF f,d

Operands: 0  f  127

d 

Operation: (W) + (f)  (destination)

Status Affected: C, DC, Z

Description: Add the contents of t he W register

with register 'f '. If 'd' is 0, the result

is stored in the W register. If 'd' is

1, the result is stored back in 

ANDLW AND Literal with W

Syntax: [label] ANDLW k

Operands: 0  k  255

Operation: (W) .AND. (k)  (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the eight-bit literal

'k'. The result is placed in the W

ANDWF AND W with f

Syntax: [label] ANDWF f,d

Operands: 0  f  127

d 

Operation: (W) .AND. (f)  (destination)

Status Affected: Z

Description: AND the W register with register

'f'. If 'd' is 0, the result is stored in

the W regist er. If 'd' is 1, th e re sult

is stored back in register 'f'.

BCF Bit Clear f

Syntax: [label] BCF f,b

Operands: 0  f  127

0  b  7

Operation: 0  (f<b>)

Status Affe cte d: None

Description: Bit 'b' in register 'f' is cleared.

BSF Bit Set f

Syntax: [label] BSF f,b

Operands: 0  f  127

0  b  7

Operation: 1  (f<b>)

Status Affe cte d: None

Description: Bit 'b' in register 'f' is set.

BTFSS Bit Test f, Skip if Set

Syntax: [label] BTFSS f,b

Operands: 0  f  127

0  b < 7

Operation: skip if (f<b>) = 1

Status Affe cte d: None

Description: If bit 'b' in regi ster 'f' is '0', the nex t

instructi on is ex ecuted.

If bit 'b' is '1', then the next 

instructi on is discard ed an d a NOP

is exec ute d in stead, m ak ing thi s a

2TCY instruction.

BTFSC Bit Test, Skip if Clear

Syntax: [label] BTFSC f,b

Operands: 0  f  127

0  b  7

Operation: skip if (f<b>) = 0

Status Affe cte d: None

Description: If bit 'b' in register 'f' is '1', the next

instruction is executed.

If bit 'b', in register 'f', is '0', the

next instru ction is disca rde d, and

a NOP is executed instead, making

this a 2TCY instruction.

rfPIC12F675

DS70091B-page 76 Preliminary  2003-2013 Microchip Technology Inc.

CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0  k  204 7

Operation: (PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<4:3>)  PC<12:11>

Status Affected: None

Description: Call Subroutine. First, return

address (PC+1) is pushed onto

the stack. The eleven-bit immedi-

ate a ddress is loade d into P C bit s

<10:0>. The upper bits of the PC

are load ed from PCLA TH. CALL is

a two-cycle instruction.

CLRF Clear f

Syntax: [label] CLRF f

Operands: 0  f  127

Operation: 00h  (f)

1  Z

Status Affected: Z

Description: The con ten t s of regi ste r 'f' are

cleared and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h  (W)

1  Z

Status Affected: Z

Description: W register is cleared. Zero bit (Z)

is set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h  WDT

0  WDT prescaler,

1  TO

1  PD

Status Affe cte d: TO, PD

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets

the prescaler of the WDT. 

STATUS bits TO and PD are set.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (destination)

Status Affe cte d: Z

Description: The contents of register 'f' are

complemented. If 'd' is 0, the

result is stored in W. If 'd' is 1, the

result is stored back in register 'f'.

DECF Decrement f

Syntax: [label] DECF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination)

Status Affe cte d: Z

Description: Decrement register 'f'. If 'd' is 0,

the result is stored in the W 

stored back in register 'f'.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 77

rfPIC12F675

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination);

skip if result = 0

Status Affected: None

Description: The contents of register 'f' are

decremented. If 'd' is 0, the result

is placed in the W register. If 'd' is

1, the result is placed back in 

If the result is 1, the next instruc-

tion is executed. If the result is 0,

then a NOP is executed instead,

making it a 2TCY instruction .

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0  k  2047

Operation: k  PC<10:0>

PCLATH<4:3>  PC<12:11>

Status Affected: None

Description: GOTO is an unconditional branch.

The e le ven -bi t im me dia t e v al ue i s

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTO is a two-

cycle instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination)

Status Affected: Z

Description: The contents of register 'f' are

incremented. If 'd' is 0, the result

is placed in the W regis ter. If 'd' is

1, the result is placed back in 

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination),

skip if result = 0

Status Affe cte d: None

Description: The contents of register 'f' are

incremen ted. If 'd' is 0, the result is

placed in the W register. If 'd' is 1,

the result is placed back in 

If the result is 1, the next instruc-

tion is executed. If the result is 0,

a NOP is e xecuted i nstead, ma king

it a 2TCY instruction.

IORLW Inclusive OR Literal with W

Syntax: [ label ] IORLW k

Operands: 0  k  255

Operation: (W) .OR. k  (W)

Status Affe cte d: Z

Description: The con tents of t he W register a re

OR’ed with the eight-bit literal 'k'.

The result is placed in the W 

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .OR. (f)  (destination)

Status Affe cte d: Z

Description: Inclusive OR the W register with

placed in the W re gis ter. If 'd' i s 1,

the result is placed back in 

rfPIC12F675

DS70091B-page 78 Preliminary  2003-2013 Microchip Technology Inc.

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (desti nati on )

Status Affected: Z

Description: The contents of register f are

moved to a destination dependant

upon the status of d. If d = 0, 

destination is W register. If d = 1,

the destination is file register f itself.

d = 1 is useful to test a file register ,

since status flag Z is affected.

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0  k  255

Operation: k  (W)

Status Affected: None

Description: The eight-bit literal 'k' is loaded

into W register. The don’t cares

will assemb le as 0’s.

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0  f  127

Operation: (W)  (f)

Status Affected: None

Description: Move data from W register to 

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

Status Affe cte d: N o ne

Description: No operation.

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS  PC,

1  GIE

Status Affe cte d: N o ne

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0  k  255

Operation: k  (W);

TOS  PC

Status Affe cte d: N o ne

Description: The W register is loaded with the

eight-bit literal 'k'. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 79

rfPIC12F675

RLF Rotate Left f through Carry

Syntax: [ label ]RLF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register 'f' are rotated

one bi t to the lef t throug h the Carry

Flag. If 'd' is 0, the result is placed in

the W register . If 'd' is 1, the result is

stored back in register 'f'.

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS  PC

Status Affected: None

Description: Return f rom subroutine. The stack

is POPed an d t he top o f th e s t a ck

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Affected: C

Description: The con ten t s of regis te r 'f' are

rotat ed one bit to the r ight throug h

the C arry Flag. If 'd' is 0 , the result

is placed in the W register. If 'd' is

1, the result is placed back in 

SLEEP

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h  WDT,

0  WDT prescaler,

1  TO,

0  PD

Status Affe cte d: TO, PD

Description: The power-dow n STATUS bit,

PD is c lea red. Time-out STATUS

bit, TO is set. Watchdog Timer

and its prescaler are cleared.

The proce ssor is put into SLEEP

mode with th e oscillat or stopped.

SUBLW Subtract W from Literal

Syntax: [ label ]SUBLW k

Operands: 0 k 255

Operation: k - (W) W)

Status Affe cte d: C, DC, Z

Description: The W register is subt racted (2’s

complement method) from the

eight-bit literal 'k'. The result is

placed in the W register.

SUBWF Subtract W from f

Syntax: [ label ]SUBWF f,d

Operands: 0 f 127

d  [0,1]

Operation: (f) - (W) destination)

Status

Affected: C, DC, Z

Description: Subtract (2’s complement method)

W register from regi ster 'f'. If 'd' is 0,

the result is stored in the W 

stored back in register 'f'.

rfPIC12F675

DS70091B-page 80 Preliminary  2003-2013 Microchip Technology Inc.

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

Status Affected: None

Description: The upper and lower nibbles of

0, the result is placed in the W

placed in register 'f'.

XORLW Exclusive OR Literal with W

Syntax: [label]XORLW k

Operands: 0 k 255

Operation: (W) .XOR. k W)

Status Affected: Z

Description: The contents of the W register

are XOR’ed with the eight-bit

literal 'k'. The result is placed in

the W register.

XORWF Exclusive OR W with f

Syntax: [label]XORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .XOR. (f) destination)

Status Affe cte d: Z

Description: Exclusive OR the contents of the

W register with register 'f'. If 'd' is

0, the result is stored in the W

stored back in register 'f'.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page1-81

rfPIC12F675

12.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C17 and MPLAB C18 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB C30 C Compiler

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

- MPLAB dsPIC30 Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Progra mmers

-PRO MATE

® II Univer sa l D evi ce Pro g ra mm er

- PICSTART® Plus Development Programmer

• Low Cost Demonstration Boards

- PICDEMTM 1 Demonstration Board

- PICDEM.netTM De monst ration Boar d

- PICDEM 2 Plus Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 4 Demonstration Board

- PICDEM 17 Demonstration Board

- PICDEM 18R Demonstration Board

- PICDEM L IN Demo nstration Board

- PICDEM USB Demonstration Board

• Evaluation Kits

-KEELOQ®

- P ICDEM MSC

-microID

-CAN

- PowerSmart®

-Analog

12.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit

microcontroller market. The MPLAB IDE is a Windows®

based application that contains:

• An inte rface to debugging tools

- simulator

- programmer (sold separately)

- emulator (sol d separately)

- in-circuit debugger (sold separately)

• A full-featured editor with color coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High level source code debugging

• Mouse over variable inspection

• Exten si ve on-l in e help

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug us ing :

- source files (as sembl y or C)

- absolute listing file (mixed assembly and C)

- machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost effective

simulators, through low cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve whe n upgrading to tools w ith increa sing flexi bility

and power.

12.2 MPASM Assembler

The MPASM assembler is a full-featured, universal

macro assembler for all PIC MCUs.

The MPASM assembler generates relocatable object

files for the MPLINK object linker, Intel® standard HEX

files, M AP files to detail memory u sage and symbol re f-

erence, a bsolute LST files that contain source lines and

generated machine code and COFF files for

debugging.

The MPASM assembler features include:

• Integration into MPLAB IDE projects

• User de fined m acros to strea mline asse mbly c ode

• Condit ion al as sem bl y for mult i-p urpo se sourc e

files

• Directives that allow complete control over the

assembly process

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DS70091B-page 1-82 Preliminary  2003-2013 Microchip Technology Inc.

12.3 MPLAB C17 and MPLAB C18 

C Compilers

The MPLAB C17 and MPLAB C18 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the comp ilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

12.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can link

relocatable objects from pre-compiled libraries, using

directives from a linker script.

The MPLIB object librarian manages the creation and

modific ation of li brary fil es of pre-co mpiled c ode. When

a routine from a library is called from a sourc e file, onl y

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, delet ion and extraction

12.5 MPLAB C30 C Compiler

The MPLAB C30 C compiler is a full-featured, ANSI

compliant, optimizing compiler that translates standard

ANSI C programs into dsPIC30F assembly language

source. The compiler also supports many command-

line options and language extensions to take full

adv antage of the dsPIC 30F dev ice hardw are capab ili-

ties, and afford fine control of the compiler code

generator.

MPLAB C30 is distributed with a complete ANSI C

standard library. All library functions have been

validated and conform to the ANSI C library standard.

The library includes functions for string manipulation,

dynamic memory allocation, data conversion,

timekeeping, and math functions (trigonometric,

exponential and hyperbolic). The compiler provides

symbolic information for high level source debugging

with the MPLAB IDE.

12.6 MPLAB ASM30 Assembler, Linker,

and Librarian

MPLAB ASM30 assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 compiler uses the

assembler to produce it’s object file. The assembler

generates relocatable object files that can then be

archived or lin ked with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

12.7 MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code

develop ment in a PC hosted environment by simulatin g

the P IC se ries mic rocon tr oll ers on an i nstru cti on l evel .

On any given instruction, the data areas can be exam-

ined or modified and stimuli can be applied from a file,

or user defined key press, to any pin. The execution

can be performed in Single-Step, Execute Until Break,

or Trace mode.

The MPLAB SIM simulator fully supports symbolic

debugging using the MPLAB C17 and MPLAB C18

C Compilers, as well as the MPASM assembler. The

software simulator offers the flexibility to develop and

debug code outside of the laboratory environment,

making it an excellent, economical software

development tool .

12.8 MPLAB SIM30 Software Simulator

The MPLAB SIM30 software simulator allows code

develop ment in a PC hosted environment by simulatin g

the dsPIC30F series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user defined key press, to any of the pins.

The MPLAB SIM30 simulator fully supports symbolic

debugging using the MPLAB C30 C Compiler and

MPLAB ASM30 assembler . The simulator runs in eith er

a Command Line mode for automated tasks, or from

MPLAB IDE. This high speed simulator is designed to

debug, analyze and optimize time intensive DSP

routines.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page1-83

rfPIC12F675

12.9 MPLAB ICE 2000 

High Performance Universal 

In-Circuit Emulator

The MPLAB ICE 2000 universal in-circuit emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 in-circuit emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing feat ures. Interc hangeabl e proces sor modul es allow

the system to be easily reconfigured for emulation of

different processors. The universal arc hitecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

12.10 MPLAB ICE 4000 

High Performance Universal 

In-Circuit Emulator

The MPLAB ICE 4000 universal in-circuit emulator is

intended to provide the product development engineer

with a co mplete micro controller de sign tool se t for high-

end PIC microcontrollers. Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debuggi ng from a singl e envi ronm ent.

The MPLAB ICD 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanc ed emulator fe atures inc lude complex t riggering

and timing, up to 2 Mb of emulation memory, and the

ability to view variables in real-time.

The MPLAB ICE 4000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were cho-

sen to best make t hes e fe atur es av ail able i n a si mple ,

unified application.

12.11 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low cost, run-time development tool,

connec ting to the h ost PC via an R S-232 or hig h speed

USB interface. This tool is based on the FLASH PIC

MCUs and ca n be used to develop for these and othe r

PIC micr ocontroll ers. The M PLAB ICD 2 uti lizes the in-

circuit debugging capability built into the FLASH

devices. This feature, along with Microchip’s In-Circuit

Serial ProgrammingTM (ICSPTM) protocol, offers cost

effective in-circuit FLASH debug ging from the gra phical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single-

stepping and watching variables, CPU status and

periphera l registers. Running at full speed enables test-

ing hardware and applications in real-time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

12.12 PRO MATE II Universal Device

Programmer

The PRO MATE II is a universal, CE compliant device

programmer with programmable voltage verification at

VDDMIN and VDDMAX for maxi mum reliabi lity. It features

an LCD display for instructions and error messages

and a modular detachable socket assembly to support

various package types. In Stand-Alone mode, the

PRO MATE II d evic e p rogrammer ca n re ad, ve rify, and

program PIC devices without a PC connection. It can

also set code protection in this mode.

12.13 PICSTART Plus Development

Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus development programmer supports

most PIC devices up to 40 pins. Larger pin count

devices, such as the PIC16C92X and PIC17C76X,

may be supported with an adapter socket. The

PICSTART Plus development programmer is CE

compliant.

rfPIC12F675

DS70091B-page 1-84 Preliminary  2003-2013 Microchip Technology Inc.

12.14 PICDEM 1 PIC MCU

Demonstration Board

The PICDE M 1 demo nstrat ion boa rd de monstrate s the

capabilities of the PIC16C5X (PIC16C54 to

PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,

PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All

necessary hardware and software is included to run

basic demo programs. The sample microcontrollers

provi d ed wi t h t he PI C DE M 1 de mo ns t rat i on b o ar d c an

be pro gramme d with a PRO MATE II devi ce pr ogram-

mer, or a PICSTART Plus development programmer.

The PICDE M 1 demonstrati on board can be conne cted

to the MPLAB ICE in-circuit emulator for testing. A

prototype area extends the circuitry for additional

application components. Features include an RS-232

interface, a potentiometer for simulated analog input,

push button switches and eight LEDs.

12.15 PICDEM.net Internet/ E thernet

Demonstration Board

The PICDEM.net demonstration board is an Internet/

Ethernet demonstration board using the PIC18F452

microcontroller and TCP/IP firmware. The board

supports any 40-pin DIP device that conforms to the

standard pinout used by the PIC16F877 or

PIC18C452. This kit features a user friendly TCP/IP

stack, web server with HTML, a 24L256 Serial

EEPROM for Xmodem download to web pages into

Serial EEPROM, ICSP/MPLAB ICD 2 interface

connector, an Ethernet interface, RS-232 interface,

and a 16 x 2 LCD di splay. Also i ncluded is t he book and

CD-ROM “TCP/IP Lean, Web Servers for Embedded

Systems,” by Jeremy Bentham

12.16 PICDEM 2 Plus 

Demonstration Board

The PICDEM 2 Plus demonstration board supports

many 18-, 28-, and 40-pin microcontrollers, including

PIC16F87X and PIC18FXX2 devices. All the neces-

sary ha rdware and s oftwa re is include d to run the dem-

onstration programs. The sample microcontrollers

provi d ed wi t h t he PI C DE M 2 de mo ns t rat i on b o ar d c an

be pro gramme d with a PRO MATE II devi ce pr ogram-

mer, PICSTART Plus development programmer, or

MPLAB ICD 2 with a Universal Programmer Adapter.

The MPLAB I CD 2 and MPLAB I CE in-circuit em ulators

may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area extends the

circuitry for additional application components. Some

of the features include an RS-232 interface, a 2 x 16

LCD display, a piezo sp eaker , an on-board temperatu re

sensor, four LEDs, and sample PIC18F452 and

PIC16F8 77 FLASH microc on trol lers .

12.17 PICDEM 3 PIC16C92X

Demonstration Board

The PICDEM 3 demonstration board supports the

PIC16C923 and PIC16C924 in the PLCC package. All

the necessary hardware and so ftware is included to run

the demonstration programs.

12.18 PICDEM 4 8/14/18-Pin

Demonstration Board

The PICDEM 4 can be used to demonstrate the capa-

bilities of the 8-, 14-, and 18-pin PIC16XXXX and

PIC18XXXX MCUs, including the PIC16F818/819,

PIC16F87/88, PIC16F62XA and the PIC18F1320

Family of microcontrollers. PICDEM 4 is intended to

showcase the many features of these low pin count

parts, including LIN and Motor Control using ECCP.

Special provisions are made for low power operation

with the supercapacitor circuit, and jumpers allow on-

board hardware to be disabled to eliminate current

draw in this mode. Included on th e demo board are pro-

visions for Crystal, RC or Canned Oscillator modes, a

five volt regulator for use with a nine volt wall adapter

or battery, DB-9 RS-232 interface, ICD connector for

programming via ICSP and development with MPLAB

ICD 2, 2x 16 l iqu id c ry st a l di splay, PC B foot prin t s for H -

Bridge motor driver, LIN transceiver and EEPROM.

Also included are: header for expansion, eight LEDs,

four potentiometers, three push buttons and a proto-

typing are a. Inc lud ed with the kit is a PIC16F627A and

a PIC18F1 320. Tutorial firmwar e is inc luded along wi th

the User’s Guide.

12.19 PICDEM 17 Demonstration Board

The P ICDEM 17 dem o ns tr at i on bo ar d is an ev al u at i on

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. A

programmed sample is included. The PRO MATE II

device programmer, or the PICSTART Plus develop-

ment programmer, can be used to reprogram the

device for user tailored application development. The

PICDEM 17 demonstration board supports program

download and execution from external on-board

FLASH memory. A generous prototype area is

available for user hardware expansion.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page1-85

rfPIC12F675

12.20 PICDEM 18R PIC18C601/801

Demonstration Board

The PICDEM 18R demonstration board serves to assist

development of the PIC18C601/801 family of Microchip

microcontrollers. It provides hardware implementation

of both 8-bit Multiplexed/De-multiplexed and 16-bit

Memory modes. The board includes 2 Mb external

FLASH memory and 128 Kb SRAM memory , as well as

serial EEPROM, allowing access to the wide range of

memory types supported by the PIC18C601/801.

12.21 PICDEM LIN PIC16C43X

Demonstration Board

The pow erfu l LIN h ardw a re an d so ftware ki t inc lu des a

series of boards and three PIC microcontrollers. The

small footprint PIC16C432 and PIC16C433 are used

as slaves in the LIN communication and feature on-

board LIN transceivers. A PIC16F874 FLASH micro-

controller serves as the master. All three microcon-

trollers are programmed with firmware to provide LIN

bus co mm un icatio n.

12.22 PICkitTM 1 FLASH Starter Kit

A complete "development system in a box", the PICkit

FLASH Starter Kit includes a convenient multi-section

board for programming, evaluation, and development

of 8/14-pi n FLAS H PI C® microc ontro ll ers . Pow ere d vi a

USB, the board operates un der a simple Windows GUI.

The PICkit 1 Starter Kit includes the user's guide (on

CD ROM), PICkit 1 tutorial software and code for vari-

ous applica tion s. Als o inclu ded are MP LAB® IDE (Inte-

grated Development Environment) software, software

and hardware "Tips 'n Tricks for 8-pin FLASH PIC®

Microcontrollers" Handbook and a USB Interface

Cable. Supports all current 8/14-pin FLASH PIC

microcontrollers, as well as many future planned

devices.

12.23 PICDEM USB PIC16C7X5

Demonstration Board

The PICDEM U SB Demo ns trati on B oard sho ws o ff the

capabilities of the PIC16C745 and PIC16C765 USB

microcontrollers. This board provides the basis for

future USB products.

12.24 Evaluation and 

Programming Tools

In additio n to the PICDEM seri es of circuits, Microchip

has a line of evaluation kits and demonstration software

for the s e p roducts.

•KEELOQ evaluatio n and prog ram mi ng too ls for

Microchip’s HCS Secure Data Products

• CAN developers kit for automotive network

applications

• Analog design boards and filter design software

• PowerSmart battery charg ing evaluation/

calibration kits

•IrDA

® development kit

• microID development and rfLabTM development

software

• SEEVAL® design er k it f or m em ory evaluation and

endurance calculations

• PICDEM MSC demo boards for Switching mode

power supply, high power IR driver, delta sigma

ADC, and flow rate sensor

Check the Microchip web page and the latest Product

Line Card for the complete list of demonstration and

evaluation kits.

rfPIC12F675

DS70091B-page 1-86 Preliminary  2003-2013 Microchip Technology Inc.

NOTES:

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 87

rfPIC12F675

13.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings†

Ambient temperature under bias...........................................................................................................-40 to +125°C

Storage temperature........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS ....................................................................................................... -0.3 to +6.5V

Voltage on VDDRF with respect to VSSRF................................................................................................ -0.3 to +7.0V

Voltage on MCLR with respect to Vss...................................................................................................-0.3 to +13.5V

Voltage on all GPIO pins with respect to VSS............................................................................ -0.3V to (VDD + 0.3V)

Voltage on all other RF Transmitter pins with respect to VSSRF.............................................-0.3V to (VDDRF + 0.3V)

To tal power dissipati on(1) ...............................................................................................................................800 mW

Maximum current out of VSS pin.....................................................................................................................300 mA

Maximum current into VDD pin........................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)20 mA

Output clamp current, IOK (Vo < 0 or Vo >VDD)20 mA

Maximum output current sunk by any GPIO pin ...............................................................................................25 mA

Maximum output current sourced by any GPIO pin..........................................................................................25 mA

Maximum total current sunk by all GPIO pins.................................................................................................125 mA

Maximum tot al cur r ent so urced all GPI O pin s.......... ...... ..... ...... ............................ ............................. .............125 mA

Note 1: Po wer diss ipati on is ca lcu la t ed as follows : 

PDIS = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOL x IOL) + VDDRF x {IDDRF -  IOHRF} +  {(VDDRF-

VOHRF) x IOHRF} + (VOLRF x IOLRF)

† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note: V oltage spik es below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch up. Thus,

a seri es resist or of 50-10 0  should be used when applying a "lo w" level to the MCLR pin, ra ther than pulling

this pin directly to VSS.

rfPIC12F675

DS70091B-page 88 Preliminary  2003-2013 Microchip Technology Inc.

FIGURE 13-1: rfPIC12F675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH, 

-40°C  TA  +125°C

FIGURE 13-2: rfP IC12F 675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 

-40°C  TA  +125°C

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Microcontroller Frequency (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

81612 2010

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Microcon trolle r Frequenc y (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

81612 2010

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 89

rfPIC12F675

FIGURE 13-3: rfPIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 

0°C  TA  +125°C

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Microcon trolle r Frequenc y (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

81612 2010

2.2

rfPIC12F675

DS70091B-page 90 Preliminary  2003-2013 Microchip Technology Inc.

13.1 DC Characteristics: rfPIC12F675-I (Industrial), rfPIC12F675-E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

D001

D001A

D001B

D001C

D001D

VDD Supply Voltage 2.0

2.2

2.5

3.0

4.5

—

5.5

FOSC < = 4 MHz:

rfPIC12F675 wit h A/D off

rfPIC12F675 with A/D on, 0°C to +125°C

rfPIC12F675 wit h A/D on, -40° C to +125°C

4 MHZ < FOSC < = 10 MHz

FOSC > 10 MHz

D002 VDR RAM Data Retention 

Voltage(1) 1.5* — — V Device in SLEEP mode

D003 VPOR VDD Start Voltage to

ensure internal Power-on

Reset signal

— VSS — V See section on Power-on Reset for details

D004 SVDD VDD Rise Rate to ensure 

internal Power-on Reset 

signal

0.05* — — V/ms See section on Power-on Reset for details

D005 VBOD —2.1 — V

D006

D006A

D006B

D006C

VDDRF RF Transmi tter Supp ly

Voltage 2.0

3.0

4.0

5.0

—

5.5

Output Power = 4 dBm

Output Power = 7.5 dBm

Output Power = 8.5 dBm

Output Power = 9 dBm

D007 VLVD RF Low Voltage Disable 1.8 1.85 1.9 V TA +23°C, RFEN = VDDRF

* These parameters are characterized but not tested.

† Data in "Typ" col umn is at 5.0V, 25°C unle ss othe rwis e stated. These param ete rs are for des ig n gui da nce only

and are not tested.

Note1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 91

rfPIC12F675

13.2 DC Characteristics: rfPIC12F675-I (Industrial )

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40C  TA  +85C for industrial

Param

No. Device Char ac teri s tics Min Typ† Max Units Conditions

VDD Note

D010 Supply Current (IDD)(3) — 9 16 A2.0 FOSC = 32 kHz

LP Oscillator Mode

—18 28 A3.0

—34 54 A5.0

D011 —110 150 A2.0 FOSC = 1 MHz

XT Oscillator Mode

—190 280 A3.0

—330 450 A5.0

D012 —220 280 A2.0 FOSC = 4 MHz

XT Oscillator Mode

—370 650 A3.0

—0.6 1.4 mA 5.0

D013 —70 110 A2.0 FOSC = 1 MHz

EC Osci ll ator Mo de

—140 250 A3.0

—260 390 A5.0

D014 —180 250 A2.0 FOSC = 4 MHz

EC Osci ll ator Mo de

—320 470 A3.0

—580 850 A5.0

D015 —340 450 A2.0 FOSC = 4 MHz

INTOSC Mode

—500 700 A3.0

—0.8 1.1 mA 5.0

D016 —180 250 A2.0 FOSC = 4 MHz

EXTRC Mode

—320 450 A3.0

—580 800 A5.0

D017 —2.1 2.95 mA 4.5 FOSC = 20 MHz

HS Osci llator Mode

—2.4 3.0 mA 5.0

† Data in ‘Typ’ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The t est conditio ns for all I DD measurem ents in Active Opera tion mode ar e: OSC1 = exter nal square w ave,

from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loa di ng and s w itching rate , o sc ill ato r ty pe, inte rnal c ode e xec ut ion patte rn, and temp erature als o hav e

an impact on the current consumption.

3: Total devi ce current is the sum of IDD from VDD and IDDRF from VDDRF.

rfPIC12F675

DS70091B-page 92 Preliminary  2003-2013 Microchip Technology Inc.

13.3 DC Charact eristics: rfPIC12F675-I (I ndustrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40C  TA  +85C for industrial

Param

No. Device Char ac teri s tics Min Typ† Max Units Conditions

VDD Note

D020 Power-down Current

(IPD)(3) —0.99 700 nA2.0 WDT, BOD, Comparators, V REF, and

T1OS C disabled

—1.2 770 nA3.0

—2.9 995 nA5.0

D021 —0.3 1.5 A2.0 WDT Current(1)

—1.8 3.5 A3.0

—8.4 17 A5.0

D022 —58 70 A3.0 BOD Current(1)

—109 130 A5.0

D023 —3.3 6.5 A2.0 Comparator Current(1)

—6.1 8.5 A3.0

—11.5 16 A5.0

D024 —58 70 A2.0 CVREF Current(1)

—85 100 A3.0

—138 160 A5.0

D025 —4.0 6.5 A2.0 T1 OSC Current(1)

—4.6 7.0 A3.0

—6.0 10.5 A5.0

D026 —1.2 775 nA3.0 A/D Current(1)

—2.2 1.0 mA5.0

D027 Power-down RF Current

(IPDRF)(3) —0.050 TBD A3.0 RF Transmitter with RFEN=0

† Data in ‘Typ’ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.

3: Total devi ce current is the sum of IPD from VDD and IPDRF from VDDRF.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 93

rfPIC12F675

13.4 DC Characteristics: rfPIC12F675-E (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40C  TA  +125C for extended

Param

No. Device Char ac teri s tics Min Typ† Max Units Conditions

VDD Note

D010E Supply Current (IDD)(3) — 9 16 A2.0 FOSC = 32 kHz

LP Oscillator Mode

—18 28 A3.0

—35 54 A5.0

D011E —110 150 A2.0 FOSC = 1 MHz

XT Oscillator Mode

—190 280 A3.0

—330 450 A5.0

D012E —220 280 A2.0 FOSC = 4 MHz

XT Oscillator Mode

—370 650 A3.0

—0.6 1.4 mA 5.0

D013E —70 110 A2.0 FOSC = 1 MHz

EC Osci ll ator Mo de

—140 250 A3.0

—260 390 A5.0

D014E —180 250 A2.0 FOSC = 4 MHz

EC Osci ll ator Mo de

—320 470 A3.0

—580 850 A5.0

D015E —340 450 A2.0 FOSC = 4 MHz

INTOSC Mode

—500 780 A3.0

—0.8 1.1 mA 5.0

D016E —180 250 A2.0 FOSC = 4 MHz

EXTRC Mode

—320 450 A3.0

—580 800 A5.0

D017E —2.1 2.95 mA 4.5 FOSC = 20 MHz

HS Osci llator Mode

—2.4 3.0 mA 5.0

† Data in ‘Typ’ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The t est conditio ns for all I DD measurem ents in Active Opera tion mode ar e: OSC1 = exter nal square w ave,

from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loa di ng and s w itching rate , o sc ill ato r ty pe, inte rnal c ode e xec ut ion patte rn, and temp erature als o hav e

an impact on the current consumption.

3: Total devi ce current is the sum of IDD from VDD and IDDRF from VDDRF.

rfPIC12F675

DS70091B-page 94 Preliminary  2003-2013 Microchip Technology Inc.

13.5 DC Characteristics: rfPIC12F675-E (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40C  TA  +125C for extended

Param

No. Device Ch aracteristics Min Typ† Max Units Conditions

VDD Note

D020E Power-down Current

(IPD)(3) —0.0011 3.5 A2.0 WDT, BOD, Co mp arat ors, VREF, and

T1OSC disabled

—0.0012 4.0 A3.0

—0.0022 8.0 A5.0

D021E —0.3 6.0 A2.0 WDT Current(1)

—1.8 9.0 A3.0

—8.4 20 A5.0

D022E —58 70 A3.0 BOD Current(1)

—109 130 A5.0

D023E —3.3 10 A2.0 Comparator C urrent(1)

—6.1 13 A3.0

—11.5 24 A5.0

D024E —58 70 A2.0 CVREF Current(1)

—85 100 A3.0

—138 165 A5.0

D025E —4.0 10 A2.0 T1 OSC Current(1)

—4.6 12 A3.0

—6.0 20 A5.0

D026E —0.0012 6.0 A3.0 A/D Current(1)

—0.0022 8.5 A5.0

D027E Power-down RF Current

(IPDRF)(3) —0.050 TBD A3.0 RF Transmitter, RFEN=VSSRF

† Data in ‘Typ’ column is at 5.0V, 25C unl es s o the r wis e stat e d. T h es e pa ram et e rs a r e f or de si g n gui d an ce

only and are not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

periphera l is enabled. The per ipheral  current can be determined by subtracting the base IDD or IPD current

from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.

3: Total devi ce current is the sum of IPD from VDD and IPDRF from VDDRF.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 95

rfPIC12F675

13.6 DC Characteristics: rfPIC12F675K

13.7 DC Characteristics: rfPIC12F675F

13.8 DC Characteristics: rfPIC12F675H

Standard Operating Conditions (unless otherwise stated)

Operating temperature TA  +23C

Operating Frequency fc = 315 MHz

Param

No. Device Char ac teri s tics Min Typ Max Units Conditions

VDD Note

D018A RF Transmitter Current

(IDDRF)(2) 2.0 2.7 5.0 mA 3.0 Power Step 0, RFEN=DATAASK=1

D018B 2.9 3.5 7.0 mA 3.0 Power St ep 1, RFEN=DATAASK=1

D018C 3.2 4.7 7.9 mA 3.0 Power St ep 2, RFEN=DATAASK=1

D018D 4.5 6.5 11 mA 3.0 Power Step 3, RFEN=DATAASK=1

D018E 7.0 10.7 16 mA 3.0 Power St ep 4, RFEN=DATAASK=1

Note 1: The supply current is mainly a fu nction of the operating volt age and frequency . Other factors such as output

loading and temperature also have an impact on the current consumption.

2: Total devi ce current is the sum of IDD from VDD and IDDRF from VDDRF.

Standard Operating Conditions (unless otherwise stated)

Operating temperature TA  +23C

Operating Frequency fc = 434 MHz

Param

No. Device Char ac teri s tics Min Typ Max Units Conditions

VDD Note

D018A RF Transmitter Current

(IDDRF)(2) 2.0 2.7 5.0 mA 3.0 Power Step 0, RFEN=DATAASK=1

D018B 2.9 3.5 7.0 mA 3.0 Power St ep 1, RFEN=DATAASK=1

D018C 3.2 4.7 7.9 mA 3.0 Power St ep 2, RFEN=DATAASK=1

D018D 4.5 6.5 11 mA 3.0 Power Step 3, RFEN=DATAASK=1

D018E 7.0 10.7 16 mA 3.0 Power St ep 4, RFEN=DATAASK=1

Note 1: The supply current is mainly a fu nction of the operating volt age and frequency . Other factors such as output

loading and temperature also have an impact on the current consumption.

2: Total devi ce current is the sum of IDD from VDD and IDDRF from VDDRF.

Standard Operating Conditions (unless otherwise stated)

Operating temperature TA  +23C

Operating Frequency fc = 868 MHz

Param

No. Device Char ac teri s tics Min Typ Max Units Conditions

VDD Note

D018A RF Transmitter Current

(IDDRF)(2) 2.6 4.0 6.5 mA 3.0 Power Step 0, RFEN=DATAASK=1

D018B 3.5 5.3 8.5 mA 3.0 Power St ep 1, RFEN=DATAASK=1

D018C 4.5 6.7 11 mA 3.0 Power Step 2, RFEN=DATAASK=1

D018D 6.0 9.0 14 mA 3.0 Power Step 3, RFEN=DATAASK=1

D018E 9.0 14.0 20 mA 3.0 Power St ep 4, RFEN=DATAASK=1

Note 1: The supply current is mainly a fu nction of the operating volt age and frequency . Other factors such as output

loading and temperature also have an impact on the current consumption.

2: Total devi ce current is the sum of IDD from VDD and IDDRF from VDDRF.

rfPIC12F675

DS70091B-page 96 Preliminary  2003-2013 Microchip Technology Inc.

13.9 DC Characteristics: rfPIC12F675-I (Industrial), rfPIC12F675-E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Input Low Voltage

VIL I/O ports

D030 with TTL buffer VSS —0.8 V4.5V  VDD  5.5V

D030A VSS —0 .15 V DD VOtherwise

D031 with Schmitt Trigger buffer VSS —0.2 VDD VEntire range

D032 MCLR, OSC1 (RC mode) VSS —0.2 VDD V

D033 OSC1 (XT and LP modes) VSS —0.3 V(N ote 1)

D033A OSC1 (HS mode) VSS —0.3 VDD V(Note 1)

D034 DATAASK, DATAFSK, RFEN VSS —0.3 VDDRF V

Input High Voltage

VIH I/O ports —

D040

D040A with TTL buffer 2.0

(0.25 V DD+0.8) —

—VDD

VDD V

V4.5V  VDD 5.5V

otherwise

D041 with Schmitt Trigger buffer 0.8 VDD —VDD ent ire rang e

D042 MCLR 0.8 VDD —VDD V

D043 OSC1 (XT and LP modes) 1.6 —VDD V(Note 1)

D043A OSC1 (HS mode) 0.7 VDD —VDD V(Note 1)

D043B OSC1 (RC mode) 0.9 VDD —VDD V

D044 DATAASK, DATAFSK, RFEN 0.7 VDD —VDDRF V

D070 IPUR GPIO Weak Pull-up Current 50* 250 400* A VDD = 5.0V, VPIN = V SS

D071 DATAASK Weak Pull-up 0.1* 1.5 12* A VDDRF = RFEN = 3.0V

D072 RFENIN Weak Pull-down 0.2* 2.0 20* A VDDRF = RFEN = 3.0V

Input Leakage Current(3)

D060 IIL GPIO ports, DATAASK,

DATAFSK, RFEN —011A VSS VPIN VDD, 

Pin at hi-impedance

D060A Analog inputs —011A VSS VPIN VDD

D060B VREF —011A VSS VPIN VDD

D061 MCLR(2) —015A VSS VPIN VDD

D063 OSC1 —015A VSS VPIN VDD, XT, HS and 

LP osc configuration

Output Low Voltage

D080 VOL I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.)

D083 OSC2/CLKOUT (RC mode) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V (Ind.)

IOL = 1.2 mA, VDD = 4.5V (Ext.)

Output High Voltage

D090 VOH I/O ports VDD - 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.)

D092 OSC2/CLKOUT (RC mode) VDD - 0.7 — — V IOH = -1.3 mA, VDD = 4.5V (Ind.)

IOH = -1.0 mA, VDD = 4.5V (Ext.)

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25C unless oth erwis e s t at ed. These p ara me ters are for desig n g uid anc e o nl y

and are not tested .

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use

an external clock in RC mode.

2: The leakage current on the MCLR pin is strongly depend ent on the applied voltage level. The specified levels

represent normal operating condi tions. Higher leaka ge current may be meas ured at different input volt ages.

3: Negative current is defined as current sourced by the pin.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 97

rfPIC12F675

13.10 DC Characteris tics: rfPI C1 2F675-I (Industrial), rfPIC12F675-E (E xt e nd e d ) ( Con t.)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Capacitive Loading Specs

on Output Pins

D100 COSC2 OSC2 pin — — 15* pF In XT, HS and LP modes when

external clock is used to drive

OSC1

D101 CIO All I/O pins — — 50* pF

Data EEPROM Memory

D120 EDByte Endurance 100K 1M —E/W -40C  TA +85°C

D120A EDByte Endurance 10K 100K —E/W +85°C  TA +125°C

D121 VDRW VDD for Read/Write VMIN —5.5 VUsing EECON to read/write

VMIN = Minimum operating 

voltage

D122 TDEW Erase/Write cycle time — 5 6 ms

D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications

are violated

D124 TREF Number of Total Erase/Write

Cycle s befor e Refres h(1) 1M 10M —E/W -40C  TA +85°C

Program FLASH Memory

D130 EPCell Endurance 10K 100K —E/W -40C  TA +85°C

D130A EDCell Endurance 1K 10K —E/W +85°C  TA +125°C

D131 VPR VDD for Read VMIN —5.5 V VMIN = Minimum operating 

voltage

D132 VPEW VDD for Erase/Write 4.5 —5.5 V

D133 TPEW Erase/Write cycle time — 2 2.5 ms

D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications

are violated

RF Transmitter(2)

D150 RON FSK Switch On resistance —20 60 DATAFSK=0, RFEN=1

D151 ROFF FSK Switch Off resistance 1 — — MDATAFSK=1, RFEN=1

D152A

D152B

D152C

D152D

D152E

VPS RF Power Select

Voltage VSSRF

0.14

0.28

0.57

1.23

—

0.1

0.24

0.51

1.18

VDDRF

Power Level Step 0

Power Level Step 1

Power Level Step 2

Power Level Step 3

Power Level Step 4

D153 IPS Power Select Current 6 8 11 ARFEN=1

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: See Section 8.5.1 for additional information.

2: These limits are tested at room temperature.

rfPIC12F675

DS70091B-page 98 Preliminary  2003-2013 Microchip Technology Inc.

13.11 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created with

one of the following formats:

FIGURE 13-4: LOAD CONDITIONS

1. TppS2ppS

2. TppS

TF Frequency TTime

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppe rcase letter s and their meani ngs:

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) VValid

LLow Z Hi-impedance

Pin Pin

RL=464

CL= 50 pF for al l pins

15 pF for OSC2 output

Load Cond ition 1 Load Condition 2

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 99

rfPIC12F675

13.12 AC CHARACTERISTICS: rfPIC12F675 (INDUSTRIAL, EXTENDED)

FIGURE 13-5: EXTER NAL CLOCK TIMING

TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

FOSC External CLKIN Frequency(1) DC —37 kHz LP Osc mode

DC — 4 MHz XT mode

DC —20 MHz HS mode

DC —20 MHz EC mode

Osci lla tor Freq uen cy (1) 5 — 37 kHz LP Osc mo de

— 4 — MHz INTOSC mo de

DC — 4 MHz RC Osc mo de

0.1 — 4 MHz XT Osc mode

1 — 20 MHz HS Osc mode

1 TOSC External CLKIN Period(1) 27 — sLP Osc mo de

50 —ns HS Osc mode

50 —ns EC Osc mode

250 —ns XT Osc mode

Oscillator Perio d(1) 27 200 sLP Os c mode

—250 —ns INTOSC mo de

250 — — ns RC Osc mode

250 —10,000 ns XT Osc mode

50 —1,000 ns HS Osc mode

2 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC

3TosL,

TosH External CLKIN (OSC1) High

External CLKIN Low 2* — — sLP oscillator, TOSC L/H duty cycle

20* — — ns HS oscillator, TOSC L/H duty

cycle

100 * — — ns XT oscillator, TOSC L/H duty cycle

4TosR,

TosF External CLKIN Rise

External CLKIN Fall — — 50* ns LP oscillator

— — 25* ns XT oscil lat or

— — 15* ns HS oscillat or

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note1: Instruction cycle period (TCY) equa ls four times th e input osc il lator time-b as e pe riod . All specifie d va lues ar e

based on c harac teriza tion da ta f or that p arti cular oscil lator ty pe und er st anda rd opera ting c onditi ons with the

device e xecut ing co de. Exc eedin g t hese s peci fied li mit s ma y resu lt in a n u nst able o scil lator o peratio n an d/or

higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external

clock appl ie d to OSC 1 pin. Whe n an ex tern al c loc k in put is use d, the ‘max ’ cy c le time li mit is ‘DC’ (no clock)

for all devices.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

23344

rfPIC12F675

DS70091B-page 100 Preliminary  2003-2013 Microchip Technology Inc.

TABLE 13-2: PRECISION INTERNAL OSCILLATOR PARAMETERS

Param

No. Sym Characteristic Freq

Tolerance Min Typ† Max Units Conditions

F10 FOSC Internal Calibrated

INTOSC Frequency

13.96 4.00 4.04 MHz VDD = 3.5V, 25C

23.92 4.00 4.08 MHz 2.5V VDD  5.5V

0C  TA  +85C

53.80 4.00 4.20 MHz 2.0V VDD  5.5V

-40C  TA  +85C (IND)

-40C  TA  +125C (EXT)

F14 TIOSC

ST Oscillator Wake-up from

SLEEP start-up time* — — 6 8 s VDD = 2.0V, -40C to +85C

— — 4 6 s VDD = 3.0V, -40C to +85C

— — 3 5 s VDD = 5.0V, -40C to +85C

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 101

rfPIC12F675

FIGURE 13-6: CLKOUT AND I/O TIMING

TABLE 13-3: CLKOUT AND I/O TIMING REQUIREMENTS

OSC1

CLKOUT

I/O pi n

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

20, 21

19 18

Old Value New Val ue

Param

No. Sym Characteristic Min Typ† Max Units Conditions

10 TosH2ckL OSC1 to CLK-

OUT —75 200 ns (Note 1)

11 TosH2ckH OSC1 to CLK-

OUT —75 200 ns (Note 1)

12 TckR CLKOUT rise time —35 100 ns (Note 1)

13 TckF CLKOUT fall time —35 100 ns (Note 1)

14 TckL2ioV CLKOUT to Port out valid — — 20 ns (Note 1)

15 TioV2ckH Port in valid before CLKOUT TOSC + 200

ns — — ns (Note 1)

16 TckH2ioI Port in hold after CLKOUT 0 — — ns (Note 1)

17 TosH2ioV OSC1 (Q1 cycle) to Port out valid —50 150 * ns

— — 300 ns

18 TosH2ioI OSC1 (Q2 cycle) to Port input

invali d (I/O in hold time) 100 — — ns

19 TioV2osH Port input valid to OSC1

(I/O in setup tim e) 0 — — ns

20 TioR Port output ris e time —10 40 ns

21 TioF Port output fall time —10 40 ns

22 Tinp INT pin high or low time 25 — — ns

23 Trbp GPIO change INT high or low time TCY — — ns

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25C unless otherwise stated.

Note 1: Me as urem en ts are tak en in RC mo de where C LKO UT outpu t is 4xTOSC.

rfPIC12F675

DS70091B-page 102 Preliminary  2003-2013 Microchip Technology Inc.

FIGURE 13-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND 

POWER-UP TIMER TIMING

FIGURE 13-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

Reset

I/O Pins

BVDD

RESET (due to BOD)

VDD

(Device in Brown-out Detect)

(Device not in Brown-out Detect)

72 ms time-out(1)

Note 1: 72 ms delay only if PWRTE bit in configuration word is programmed to ‘0’.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 103

rfPIC12F675

TABLE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT DETECT REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

30 TMCLMCLR Pulse Width (low) 2

TBD —

TBD s

ms VDD = 5V, - 40°C to +85°C

Extended temperature

31 TWDT Watchdog Timer Time-out

Period

(No Prescaler)

10 17

17 25

30 ms

ms VDD = 5V, - 40°C to +85°C

Extended temperature

32 TOST Oscillation Start-up Timer

Period —1024TOSC — — TOSC = OSC1 period

33* TPWRT Power-up Timer Period 28*

TBD 72

TBD 132*

TBD ms

ms VDD = 5V, - 40°C to +85°C

Extended Temperature

34 TIOZ I/O Hi-impedance from MCLR

Low or Watchdog Timer Reset — — 2.0 s

BVDD Brown-out Detect Voltage 2.025 —2.175 V

Brown-out Hysteresis TBD — — —

35 TBOD Brown-out Detect Pulse Width 100* — — s VDD  BVDD (D005)

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

rfPIC12F675

DS70091B-page 104 Preliminary  2003-2013 Microchip Technology Inc.

FIGURE 13-9: TIMER0 AND TIMER1 EXTERNAL CLOC K TIMINGS

TABLE 13-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

T0CKI

T1CKI

45 46

47 48

TMR0 or

TMR1

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40* Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescal er 10 — — ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescal er 10 — — ns

42* Tt0P T0C KI Peri o d Greater of:

20 or TCY + 40

— — ns N = prescale value

(2, 4 , ..., 25 6 )

45* Tt1H T1CKI High Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Prescaler 15 — — ns

Asynchronous 30 — — ns

46* Tt1L T1CKI Low Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Prescaler 15 — — ns

Asynchronous 30 — — ns

47* Tt1P T1CKI Input

Period Synchronous Greater of:

30 or TCY + 40

— — ns N = prescale value

(1, 2, 4, 8)

Asynchronous 60 — — ns

Ft1 Timer1 oscillator input frequency range 

(oscillator enabled by setting bit T1OSCEN) DC — 200* kHz

48 TCKEZtmr1 Delay from external clock edge to timer increment 2 TOSC* — 7

TOSC*—

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are 

not tested.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 105

rfPIC12F675

TABLE 13-6: COMPARATOR SPECIFICATIONS

TABLE 13-7: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Comparator Specifications Standard Operating Conditions 

-40°C to +125°C (unless otherwise stated)

Sym Characteristics Min Typ Max Units Comments

VOS Input Offset Voltage — 5.0  10 mV

VCM Input Common Mode Voltage 0 — VDD - 1.5 V

CMRR Common Mode Rejection Ratio +55* — — db

TRT Response Time(1) —150 400* ns

TMC2COVComparator Mode Change to

Output Valid — — 10* s

* These parameters are characterized but not tested.

Note1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from

VSS to VDD - 1.5V.

Volt a ge Refer en ce S pecification s Standard Operating Conditions 

-40°C to +125°C (unless otherwise stated)

Sym Characteristics Min Typ Max Units Comments

Resolution —

—VDD/24*

VDD/32 —

—LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

Absolute Accuracy —

——

— 1/2

1/2* LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

Unit Resistor Valu e (R) —2k* —

Settling Time(1) — — 10* s

* These parameters are characterized but not tested.

Note1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.

rfPIC12F675

DS70091B-page 106 Preliminary  2003-2013 Microchip Technology Inc.

TABLE 13-8: rfPIC12F675 A/D CONVERTER CHARACTERISTICS:

Param

No. Sym Characteristic Min Typ† Max Units Conditions

A01 NRResolution — — 10 bits bit

A02 EABS Total Absolut e

Error* — — 1LSb VREF = 5.0V

A03 EIL Integral Error — — 1LSb VREF = 5.0V

A04 EDL Dif fere ntial Error — — 1LSb No missing codes to 10 bits

VREF = 5.0V

A05 EFS Full Scale Range 2.2* —5.5* V

A06 EOFF Of fs et Error — — 1LSb VREF = 5.0V

A07 EGN Gain Error — — 1LSb VREF = 5.0V

A10 —Monotonicity —guaranteed(3) — — VSS  VAIN  VREF+

A20

A20A VREF Referen ce Voltage 2.0

2.5 — —

VDD + 0.3 VAbsolute minimum to ensure 10-bit

accuracy

A21 VREF Reference V High

(VDD or VREF)VSS — VDD V

A25 VAIN Analog Input 

Voltage VSS — VREF V

A30 ZAIN Recommended

Impedan ce of 

Analog Voltage

Source

— — 10 k

A50 IREF VREF Input 

Current(2) 10

—

1000

A

During VAIN acquisition. 

Based on dif ferential of VHOLD to VAIN.

During A/D conversion cycle.

* These parameters are characterized but not tested.

† Data in ‘Typ’ co lumn is at 5 .0V, 25C unle ss ot herwi se st ated . Thes e pa ram eters a re f or desi gn gui dance onl y

and are not tested.

Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec

includes any such leakage from the A/D module.

2: VREF current is from External VREF or VDD pin, whichever is selected as reference input.

3: The A/D con version resul t never decreases with an increa se in the input v oltage and has no m issing code s.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 107

rfPIC12F675

FIGURE 13-10: rfPIC12F675 A/D CONVERSION TIMING (NORMAL MODE)

TABLE 13-9: rfPIC12F675 A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

987 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 TCY

134 (TOSC/2)(1)

1 TCY

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D Clock Period 1.6 — — s TOSC based, VREF 3.0V

3.0* — — s TOSC based, VREF full range

130 TAD A/D Internal RC

Oscillator Perio d 3.0* 6.0 9.0* sADCS<1:0> = 11 (RC mode)

At VDD = 2.5V

2.0* 4.0 6.0* sAt VDD = 5.0V

131 TCNV Conversion Time

(not including

Acqu isition Time)(1)

—11 — TAD Set GO bit to new data in A/D result

132 TACQ Acquisiti on Time (Note 2)

11.5

—

s

sThe minimum time is the amplifier

settling time. This may be used if th e

“new” inpu t voltag e has not chan ged

by more than 1 LSb (i.e., 4.1 mV @

4.096V) from the last sampled

volt a ge (as stored on CHOLD).

134 TGO Q4 to A/D Clock

Start — TOSC/2 — — If the A/ D clock s ource is se lected as

RC, a time of TCY is added bef ore

the A/D clock starts. This allows the

SLEEP instruction to be executed.

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 7.1 for minimum conditions.

rfPIC12F675

DS70091B-page 108 Preliminary  2003-2013 Microchip Technology Inc.

FIGURE 13-11: rfPIC12F675 A/D CONVERSION TIMING (SLEEP MODE)

TABLE 13-10: rfPIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D Clock Period 1.6 — — s VREF 3.0V

3.0* — — s VREF full range

130 TAD A/D Internal RC

Oscillator Perio d 3.0* 6.0 9.0* sADCS<1:0> = 11 (RC mode)

At VDD = 2. 5V

2.0* 4.0 6.0* sAt VDD = 5.0V

131 TCNV Conversion Time

(not includin g

Acquisiti on Time)(1)

—11 — TAD

132 TACQ Acquisition Time (Note 2)

11.5

—

s

sThe minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

change d by more than 1 LSb (i.e .,

4.1 mV @ 4.096V) from the last

sampled voltage (as stored on

CHOLD).

134 TGO Q4 to A/D Clock

Start — TOSC/2 + TCY — — If the A /D clo ck s ource i s se lec t ed

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEP instruct ion to be

executed.

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 7.1 for minimum conditions.

131

130

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLIN G STOP PED

DONE

NEW_DATA

9 7 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

134

132

1 TCY

(TOSC/2 + TCY)(1)

1 TCY

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 109

rfPIC12F675

TABLE 13-11: rfPIC12F675K RF TRANSMITTER SPECIFICATIONS (315 MHz)

RF Transmitter Specifi catio ns

Standard Operating Conditions 

TA = +23°C (unless otherwise stated)

VDDRF = 3.0V (unless otherwise stated)

FC = 315 MHz (unless otherwise stated)

Sym Characteristics Min Typ Max Units Comments

FCVCO Frequency 290 —350 MHz 32 x FRFXTAL

FXTAL Crystal Frequency 9.06 —10.94 MHz Fundamental mode

FREF Refere nce Frequency 2.265 —2.735 MHz FRFXTAL / 4

CLLoad Capacitance 10 —15 pF

COStatic Capacitance — — 7 pF

RSSeries Resistance — — 70 

ASPUR Spurious respon s e — — -10 dB For FSK operation

FVDD Frequency Stability vs VDDRF — — 3ppm

FTA Frequency Stability vs Temp — — 10 ppm Crystal temp constant

FFSK Deviation 5 — 80 kHz Dep end s on cry stal

parameters

RFSK FSK Data Rate — — 40 Kbit/s NRZ

RASK ASK Data Rate — — 40 Kbit/s NRZ

TON RFEN High to Transmit —1.2 1.5 ms

POFF RF Output Power in Step 0 — — -70 dBm RFEN=1

P1RF Output Power in Step 1 —-12 —dBm RFEN=1

P2RF Output Power in Step 2 —-4 —dBm RFEN=1

P3RF Output Power in Step 3 — 2 — dBm RFEN=1

P4RF Output Power in Step 4 — 4 — dBm RFEN=1, VDDRF=2.0V

—7.5 —dBm RFEN=1, VDDRF=3.0V

—8.5 9.5 dBm RFEN=1, VDDRF=4.0V

—9.0 10.5 dBm RFEN=1, VDDRF=5.0V

L(FM)Phase Noise —-86 —dBc/Hz 200 kHz offset

PSPUR Spurious Emissions — — -54 dBm 47 MHz < f < 74 MHZ

87.5 MHz < f < 118 MHZ

174 MHz < f < 230 MHZ

470 MHz < f < 862 MHZ

RBW = 100 kHz

— — -36 dBm f < 1 GHZ

RBW = 100 kHz

— — -30 dBm f > 1 GHZ

RBW = 1 MHz

rfPIC12F675

DS70091B-page 110 Preliminary  2003-2013 Microchip Technology Inc.

TABLE 13-12: rfPIC12F675F RF TRANSMITTER SPECIFICATIONS (434 MHz)

RF Transmitter Specifi catio ns

Standard Operating Conditions 

TA = +23°C (unless otherwise stated)

VDDRF = 3.0V (unless otherwise stated)

FC = 433.92 MHz (unless otherwise stated)

Sym Characteristics Min Typ Max Units Comments

FCVCO Frequency 380 —450 MHz 32 x FRFXTAL

FXTAL Crystal Frequency 11.88 —14.06 MHz Fundamental mode

FREF Refere nce Frequency 2.97 —3.515 MHz FRFXTAL / 4

CLLoad Capacitance 10 —15 pF

COStatic Capacitance — — 7 pF

RSSeries Resistance — — 70 

ASPUR Spurious respon s e — — -10 dB For FSK operation

FVDD Frequency Stability vs VDDRF — — 3ppm

FTA Frequency Stability vs Temp — — 10 ppm Crystal temp constant

FFSK Deviation 5 — 80 kHz Dep end s on cry stal

parameters

RFSK FSK Data Rate — — 40 Kbit/s NRZ

RASK ASK Data Rate — — 40 Kbit/s NRZ

TON RFEN High to Transmit —0.8 1.2 ms

POFF RF Output Power in Step 0 — — -70 dBm RFEN=1

P1RF Output Power in Step 1 —-12 —dBm RFEN=1

P2RF Output Power in Step 2 —-4 —dBm RFEN=1

P3RF Output Power in Step 3 — 2 — dBm RFEN=1

P4RF Output Power in Step 4 — 4 — dBm RFEN=1, VDDRF=2.0V

—7.5 —dBm RFEN=1, VDDRF=3.0V

—8.5 9.5 dBm RFEN=1, VDDRF=4.0V

—9.0 10.5 dBm RFEN=1, VDDRF=5.0V

L(FM)Phase Noise —-86 —dBc/Hz 200 kHz offset

PSPUR Spurious Emissions — — -54 dBm 47 MHz < f < 74 MHZ

87.5 MHz < f < 118 MHZ

174 MHz < f < 230 MHZ

470 MHz < f < 862 MHZ

RBW = 100 kHz

— — -36 dBm f < 1 GHZ

RBW = 100 kHz

— — -30 dBm f > 1 GHZ

RBW = 1 MHz

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 111

rfPIC12F675

TABLE 13-13: rfPIC12F675H RF TRANSMITTER SPECIFICATIONS (868/915 MHz)

RF Transmitter Specifi catio ns

Standard Operating Conditions 

TA = +23°C (unless otherwise stated)

VDDRF = 3.0V (unless otherwise stated)

FC = 868.3 MHz (unless otherwise stated)

Sym Characteristics Min Typ Max Units Comments

FCVCO Frequency 850 —930 MHz 32 x FRFXTAL

FXTAL Crystal Frequency 26.56 —29.06 MHz Fundamental mode

FREF Refere nce Frequency 3.32 —3.63 MHz FRFXTAL / 8

CLLoad Capacitance 10 —15 pF

COStatic Capacitance — — 7 pF

RSSeries Resistance — — 50 

ASPUR Spurious respon s e — — -10 dB For FSK operation

FVDD Frequency Stability vs VDDRF — — 3ppm

FTA Frequency Stability vs Temp — — 10 ppm Crystal temp constant

FFSK Deviation 5 — 80 kHz Dep end s on cry stal

parameters

RFSK FSK Data Rate — — 40 Kbit/s NRZ

RASK ASK Data Rate — — 40 Kbit/s NRZ

TON RFEN High to Transmit —0.6 1.0 ms

POFF RF Output Power in Step 0 — — -70 dBm RFEN=1

P1RF Output Power in Step 1 —-12 —dBm RFEN=1

P2RF Output Power in Step 2 —-4 —dBm RFEN=1

P3RF Output Power in Step 3 — 2 — dBm RFEN=1

P4RF Output Power in Step 4 — 4 — dBm RFEN=1, VDDRF=2.0V

—7.5 —dBm RFEN=1, VDDRF=3.0V

—8.5 9.5 dBm RFEN=1, VDDRF=4.0V

—9.0 10.5 dBm RFEN=1, VDDRF=5.0V

L(FM)Phase Noise —-82 —dBc/Hz 200 kHz offset

PSPUR Spurious Emissions — — -54 dBm 47 MHz < f < 74 MHZ

87.5 MHz < f < 118 MHZ

174 MHz < f < 230 MHZ

470 MHz < f < 862 MHZ

RBW = 100 kHz

— — -36 dBm f < 1 GHZ

RBW = 100 kHz

— — -30 dBm f > 1 GHZ

RBW = 1 MHz

rfPIC12F675

DS70091B-page 112 Preliminary  2003-2013 Microchip Technology Inc.

NOTES:

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 113

rfPIC12F675

14.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period

of time and matrix samples. 'Typical' represents the mean of the distribution at 25°C. 'Max' or 'min' represents

(mean + 3) or (mean - 3) respectively, where  is standard deviation, over the whole temperature range.

FIGURE 14-1: TYPICAL IPD vs. VDD OVER TEM P (-40°C TO +25°C)

FIGURE 14-2: TYPICAL IPD vs. VDD OVER TEMP (+85°C)

Typical Baselin e IPD

0.0E+00

1.0E-09

2.0E-09

3.0E-09

4.0E-09

5.0E-09

6.0E-09

2 2.5 3 3.5 4 4.5 5 5.5

(

)

PD (A)

-40

Typical Baselin e IPD

0.0E+00

5.0E-08

1.0E-07

1.5E-07

2.0E-07

2.5E-07

3.0E-07

3.5E-07

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

PD (A)

rfPIC12F675

DS70091B-page 114 Preliminary  2003-2013 Mic rochi p Technol ogy Inc.

FIGURE 14-3: TYPICAL IPD vs. VDD OVER TEMP (+125°C)

FIGURE 14-4: MAXIMU M IPD vs. VDD OVER TEMP (-40°C TO +25°C)

Typical Baseline IPD

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

3.5E-06

4.0E-06

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

PD (A)

125

Maximum Baseline I

0.0E+00

1.0E-08

2.0E-08

3.0E-08

4.0E-08

5.0E-08

6.0E-08

7.0E-08

8.0E-08

9.0E-08

1.0E-07

22.533.544.555.5

VDD (V)

IPD

(

)

-40

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 115

rfPIC12F675

FIGURE 14-5: MAXIMU M IPD vs. VDD OVER TEMP (+85°C)

FIGURE 14-6: MAXIMU M IPD vs. VDD OVER TEMP (+12 5°C)

Maximum Baseline IPD

0.0E+00

1.0E-07

2.0E-07

3.0E-07

4.0E-07

5.0E-07

6.0E-07

7.0E-07

8.0E-07

9.0E-07

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

PD (A)

Maximum Baseline IPD

0.0E+00

1.0E-06

2.0E-06

3.0E-06

4.0E-06

5.0E-06

6.0E-06

7.0E-06

8.0E-06

9.0E-06

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

PD (A)

125

rfPIC12F675

DS70091B-page 116 Preliminary  2003-2013 Microchip Tec hnology Inc.

FIGURE 14-7: TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)

FIGURE 14-8: TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)

Typical BOD IPD

100

110

120

130

33.544.555.5

VDD (V)

PD (uA)

-40

125

Typical Comparator IPD

0.0E+00

2.0E-06

4.0E-06

6.0E-06

8.0E-06

1.0E-05

1.2E-05

1.4E-05

1.6E-05

1.8E-05

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

PD (A)

-40

125

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 117

rfPIC12F675

FIGURE 14-9: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40°C TO +25°C)

FIGURE 14-10: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85°C)

Typical A/D I

0.0E+00

5.0E-10

1.0E-09

1.5E-09

2.0E-09

2.5E-09

3.0E-09

3.5E-09

4.0E-09

4.5E-09

5.0E-09

2 2.5 3 3.5 4 4.5 5 5.5

VDD (V)

PD (A)

-40

Typical A/D IPD

0.0E+00

5.0E-08

1.0E-07

1.5E-07

2.0E-07

2.5E-07

3.0E-07

3.5E-07

2 2.5 3 3.5 4 4.5 5 5.5

VDD (V)

IPD

(

)

rfPIC12F675

DS70091B-page 118 Preliminary  2003-2013 Mic rochi p Technol ogy Inc.

FIGURE 14-11: TYP ICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125°C)

FIGURE 14-12: TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40°C TO +125°C),

32 KHZ, C1 AND C2=50 pF)

Typical A/D IPD

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

3.5E-06

22.533.544.555.5

VDD (V)

PD (A)

125

Typical T1 IPD

0.00E+00

2.00E-06

4.00E-06

6.00E-06

8.00E-06

1.00E-05

1.20E-05

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

PD (A)

-40

125

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 119

rfPIC12F675

FIGURE 14-13: TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)

FIGURE 14-14: TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)

Typical C

REF

100

120

140

160

2 2.5 3 3.5 4 4.5 5 5.5

VDD (V)

PD (uA)

-40

125

Typical WDT IPD

2 2.5 3 3.5 4 4.5 5 5.5

VDD

(

)

(uA)

-40

125

rfPIC12F675

DS70091B-page 120 Preliminary  2003-2013 Mic rochip Technology Inc.

FIGURE 14-15: MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1F AND

0.01F DECOUPLING (VDD = 3.5V)

FIGURE 14-16: MAXIMUM AND MINIMUM INTOSC FREQ vs. VDD WITH 0.1F AND 0.01F

DECOUPLING (+25°C)

Internal Oscillator

Frequency vs Temperature

3.80E+06

3.85E+06

3.90E+06

3.95E+06

4.00E+06

4.05E+06

4.10E+06

4.15E+06

4.20E+06

-40°C 0°C 25°C 85°C 125°C

Temperature (°C)

Frequency (Hz)

-3sigma

average

+3sigma

Internal Oscillator

Frequency vs VDD

3.80E+06

3.85E+06

3.90E+06

3.95E+06

4.00E+06

4.05E+06

4.10E+06

4.15E+06

4.20E+06

2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

VDD (V)

Fre

uenc

(

)

-3sigma

average

+3sigma

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 121

rfPIC12F675

FIGURE 14-17: TYPICAL WDT PERIOD vs. VDD (-40C TO +125C)

WDT Tim e - o u t

2 2.5 3 3.5 4 4.5 5 5.5

(V)

Time (

mS)

-40

125

rfPIC12F675

DS70091B-page 122 Preliminary  2003-2013 Mic rochi p Technol ogy Inc.

NOTES:

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 123

rfPIC12F675

15.0 PACKAGING INFORMATION

15.1 Package Marking Information

20-Lead SSOP

XXXXXXXXXXX

YYWWNNN

rfPIC™

12F675H

0314CBP

Example

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Al pha num eri c traceab ili ty code

Pb-free JEDEC designator for Matte Ti n (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full M icroch ip part nu mber ca nnot be m arked on one line, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

rfPIC12F675

DS70091B-page 124 Preliminary  2003-2013 Microchip Technology Inc.

Package Type: 20-Lead SSOP

20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)

10501050



Mold Draft Angle Bottom 10501050



Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840



Foot Angle 0.250.180.10.010.007.004

Lead Thickness 0.940.750.56.037.030.022LFoot Length 7.347.207.06.289.284.278DOverall Length 5.385.255.11.212.207.201E1Molded Package Width 8.187.857.59.322.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff § 1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026

Pitch 20

Number of Pins MAXNOMMINMAXNOMMINDime nsio n Limits MILLIMETERSINCHES*Units







* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-150

Drawing No. C04-072

§ Significant Characteristic

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 125

rfPIC12F675

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A

This is a new data sheet.

Revision B

Added a note to each package outline drawing.

rfPIC12F675

DS70091B-page 126 Preliminary  2003-2013 Microchip Technology Inc.

NOTES:

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 127

rfPIC12F675

INDEX

A/D......................................................................................39

Acquisition Requirements...........................................43

Block Dia g r a m................... ............... ............... ............39

Calculating Acquisition Time.......................................43

Configuration and Operation..................... .. ................39

Effects of a RESET.....................................................44

Internal Sampling Switch (Rss) Impedance....... .... .. .. .43

Operation During SLEEP............................................44

PIC12F675 Converter Characteristics......................106

Source Impedance......................................................43

Summary o f Re g ist e rs.... .. ............... ............... ............44

Absolute Maximum Ratings................................................87

AC Characteristics

Industrial and Extended. .. .. .... ..................... .. . .. .... .... .. .99

Additional Pin Functions .....................................................17

Interrupt-on-Change....................................................19

Weak Pull-up...............................................................17

Analog Input Connection Considerations......................... .. .36

Analog-to-Digital Converter. See A/D

Assembler

MPASM Assembler.....................................................81

Block Diagram

TMR0/WDT Prescaler.................................................25

Block Diagrams

Analog Input Mode................... . .. .. .... .... .. .... ................36

Analog Input Model.............. .... . .. .... .. .... .. .... ................43

Com p ar a tor Output......... ............... .............. ........... ....36

Comparator Voltage Reference..................................37

GP0 and GP1 Pins......................................................20

GP2.............................................................................21

GP3.............................................................................21

GP4.............................................................................22

GP5.............................................................................22

On-C h i p R es e t Circ u it..... ........... .............. ........... ........59

RC Oscillator Mode.....................................................58

Timer1.........................................................................28

Watchdog Timer..........................................................69

Brown-out

Asso ciate d R e g ister s.... ...... ............... ............... ..........6 2

Brown-out Detect (BOD).....................................................61

Brown-out Detect Timing and Characteristics...................102

C Compiler s

MPLAB C17... ........... .......... ............... ............... ..........82

MPLAB C18... ........... .......... ............... ............... ..........82

MPLAB C30... ........... .......... ............... ............... ..........82

Calibrated Internal RC Frequencies.............. .. .. .... ............100

CLKOUT .............................................................................58

Code Examples

Changing Prescaler ....................................................27

Dat a E EPROM Read.... ...... ........... .............. ...............47

Dat a E EPROM W r ite.... ............... .......... ........... ..........4 7

Initializing GPIO..........................................................17

Saving S TATUS a n d W Re g ist e rs in RA M .................68

Write Verify.................................................................47

Code Protection ...... .... ................. .. .. . .. .. .. .... .. .... .. .. . .. .. .... .. .. .69

Comparator.........................................................................33

Asso ciate d R e g ister s.... ...... ............... ............... ..........3 8

Configuration...............................................................35

Effects of a RESET.....................................................37

I/O Operating Modes...................................................35

Interrupts.....................................................................38

Operation.................................................................... 34

Operation During SLEEP............................................ 37

Output......................................................................... 36

Reference................................................................... 37

Response Time .......................................................... 37

Comparator Specifications................ 105, 108, 109, 110, 111

Comparator Voltage Reference Specific ations................ . 105

Configuration Bits ............................................................... 56

Configuring the Voltage Reference..................................... 37

Crystal Operation................................................................ 57

Crystal Oscillator................................................................. 50

Data EEPROM Memory

Asso ciate d R e g ister s/ Bits............ ............... .............. .. 48

Code Protection............... ................. .. .. . .. .. .... .. .. .... .. .. . 48

EEADR Register......................................................... 45

EECO N 1 R eg iste r ...... ............... ............... .............. .... 45

EECO N 2 R eg iste r ...... ............... ............... .............. .... 45

EEDATA Register....................................................... 45

Data Memory Organization................................................... 5

DC Characteristi cs

Extended and Industrial.......... .... .... .. .... . .. .. .... .... .. .... ... 96

Industrial..................................................................... 90

Demonstration Boards

PICDEM 1................................................................... 84

PICDEM 17................................................................. 84

PICDEM 18R PIC18C601/801 ........... ................. .... .. . 85

PICDEM 2 Plus........................................................... 84

PICDEM 3 PIC16C92X............................................... 84

PICDEM 4................................................................... 84

PICDEM LIN PIC16C43X........................................... 85

PICDEM USB PIC16C7X5......................................... 85

PICDEM.net Internet/Ethernet.................................... 84

Development Support......................................................... 81

Device Overview................................................................... 3

EEPROM Data Memory

Reading...................................................................... 47

Spu ri o us Write.............. ........... .......... ............... .......... 47

Write Verify................................................................. 47

Writing ........................................................................ 47

Electrical Specifications...................................................... 87

Errata.................................................................................... 2

Evaluati o n and Progr a m m i n g T o o ls......... ............... ............ 85

Firmware Instructions ......................................................... 73

General Purpose Register File ............................................. 5

GPIO

Asso ciate d R e g ister s...... ... .............. ............... ............ 23

GPIO Port.......... ............... ........... .............. ........... .............. 17

GPIO, TRISIO Registers..................................................... 17

ID Locations........................................................................ 69

In-Circuit Debugger.. .... .. .. .... .. .. . .. .. .... .. .. .... .. .. . .. .. .... .. .. .... .. .. . 71

In-Circuit Serial Programming............................................. 71

Indirect Addressing, INDF and FSR Registers.... .. .. .. .. .. .. .. . 16

Instruction Format............................................................... 73

Instruction Set..................................................................... 73

ADDLW....................................................................... 75

ADDWF ...................................................................... 75

ANDLW....................................................................... 75

ANDWF ...................................................................... 75

BCF ............................................................................ 75

rfPIC12F675

DS70091B-page 128 Preliminary  2003-2013 Microchip Technology Inc.

BSF.............................................................................75

BTFSC ........................................................................75

BTFSS ........................................................................75

CALL...........................................................................76

CLRF...........................................................................76

CLRW .........................................................................76

CLRWDT.....................................................................76

COMF .........................................................................76

DECF ..........................................................................76

DECFSZ......................................................................77

GOTO .........................................................................77

INCF............................................................................77

INCFSZ.......................................................................77

IORLW ........................................................................77

IORWF........................................................................77

MOVF..........................................................................78

MOVLW ......................................................................78

MOVWF ......................................................................78

NOP............................................................................78

RETFIE.......................................................................78

RETLW .......................................................................78

RETURN.....................................................................79

RLF.............................................................................79

RRF.............................................................................79

SLEEP ........................................................................79

SUBLW.......................................................................79

SUBWF.......................................................................79

SWAPF.......................................................................80

XORLW.......................................................................80

XORWF.......................................................................80

Summary Ta b le...... ........... .......... ........... .......... ...........74

Internal 4 MHz Oscillator.....................................................58

Internal Sampling Switch (Rss) Impedance.................. . .. .. .43

Interrupts.............................................................................65

A/D C on v e r te r...... ........... .......... ............... ............... ....67

Comparator.................................................................67

Context Saving ............................................................68

GP2/INT......................................................................67

GPIO...........................................................................67

Summary o f Re g ist e rs ........ .. ............... .............. .........68

TMR0 ..........................................................................67

MCLR..................................................................................60

Memory Organization

Dat a E EPROM Me mory...... ............... .............. ...........45

Mode Control Logic.............. .... .. .... .. .. .... .. . .. .... .. .... .. .... .. . .. .. .54

MPLAB ASM30 Assembler, Linker, Librarian .....................82

MPLAB ICD 2 In-Circuit Debugger......................................83

MPLAB ICE 2000 High Performance Universal 

In-Circuit Emulator ..............................................................83

MPLAB ICE 4000 High Performance Universal 

In-Circuit Emulator ..............................................................83

MPLAB Integrated Development Environment 

Software..............................................................................81

MPLI N K O b je c t Linker / MPLIB Obje c t Libra r ia n ........... .......82

OPC ODE Fiel d De s cr ip tions..... ...... ...... ....... .......... ........... ..73

Oscillator Configurations.....................................................57

Oscilla t o r Sta r t- u p Time r ( O ST) .............. ....... ...... ...... .........60

Package Marking Information ............ .... .. . .. .. .. .... .. .... .. ......123

Pack a g i n g In forma tio n... ............... .......... ........... ...............123

PCL and PCLATH..... .... .. .... . .. .. .... .... .. .... ..................... .. . .. ...15

Computed GOTO........................................................15

Stack...........................................................................15

Phase-Locked Loop (PLL).................................................. 53

PICkit 1 FLASH Starter Kit.................................................. 85

PICSTART Plus Development Programmer....................... 83

Pin Descriptions and Diagrams ..... .. ............... .. .. .. . .. .. .. .. .. .. . 20

Pow er Amplif ie r.... ........... .......... ........... .......... ........... .......... 53

Power Control/Status Register (PCON).............................. 61

Pow er Select (Tabl e ).... .. .......... ............... .......... ............... ..53

Power-Down Mode (SLEEP).......................... .. .. .. . .. .. .. .... .. . 70

Power-on Reset (POR)....................................................... 60

Power-up Timer (PWRT).................................................... 60

Prescaler............................................................................. 27

Switching Presca l e r Assignment .... ...... ...................... 27

PRO MATE II Un iv e r sa l Devi ce Pr o g r amme r...... ... .......... ..83

Program Memory Organization...... ................. .. .. .. . .. .. .. .... .. .. . 5

Programming, Device Instructions...................................... 73

RC Oscillator....................................................................... 58

READ-MODIFY-WRITE OPERATIONS............................. 73

Registers

ADCON0 ( A/ D Contr o l)....... ....... .............. ........... ........ 41

ANSEL (Analog Select).............................................. 42

CMCON (C omparator Co n trol).. .......... ............... ........ 33

CONFIG (Con fi g u ration Word) ........... ........... ............. 56

EEADR (EEPROM Address)...................................... 45

EECO N 1 (EEPR O M Contr o l)........ ...... ........... .......... ..46

EEDAT (EEPROM Data)............................................ 45

INTCON (Interrupt Control)......................................... 11

IOCB (Interrupt-on-Change GPIO)............................. 19

MapsPIC12F629 ........................................................... 6

PIC12F675 ........................................................... 6

OPTI O N _ R EG ( O p tio n )................... .......... ........... 10, 26

OSCCAL (Oscillator Calibration) ................................ 14

PCON (Power Control)...............................................14

PIE1 (Peripheral Interrupt Enable 1)..... .... .. ................ 12

PIR1 (Peripheral Interrupt 1).... . .. .. .. .... .. .. .... .. . .. .. .. .... .. . 13

STATUS ....................................................................... 9

T1CON ( T im e r1 C o n tr o l)........ ... .......... ...... ........... ...... 30

VRCON (Voltage Reference Control).................. .. .. ... 38

WPU (Weak Pull-up)...................................................18

RESET................................................................................ 59

Revision History................................................................ 125

Soft wa re Sim u la tor (MPLAB SIM) ......... .......... ........... ........ 82

Software Simulator (MPLAB SIM30) .................................. 82

Spe cial Feat u r e s o f th e CP U.... ...... ....... .......... ........... ........ 55

Special Function Registers................................................... 6

Spe cia l Functions R e g i sters Su mmar y................ ........... ......7

Time-out Sequence ............................................................ 61

Timer0................................................................................. 25

Asso ciate d R e g ister s.. .. ............... .............. ............... ..27

External Clock............................................................. 26

Interrupt ...................................................................... 25

Operation.................................................................... 25

T0CKI ......................................................................... 26

Timer1

Asso ciate d R e g ister s.. .. ............... .............. ............... ..31

Asynchronous Counter Mode.. . .. .. .. .... .. .. .. .... .............. 31

Reading and Writing..................... .... .. ................ 31

Interrupt ...................................................................... 29

Mod es o f O p e rations........ ............... .......... ........... ......29

Operation During SLEEP............................................ 31

Oscillator..................................................................... 31

Prescaler .................................................................... 29

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 129

rfPIC12F675

Timer1 Module with Gate Control ..... .. .. .... .. .. .... .. .. . .. .. .... .. .. .28

Timing Diagrams

CLKOUT and I/O. ................. .. .. . .. .. .... .. .. .... .. .. . .. .. .... .. .101

External Clock.............................................................99

INT Pin Interrupt..........................................................67

PIC12F675 A/D Conversion (Normal Mode).............107

PIC12F675 A/D Conversion Timing 

(SLEEP Mode)..........................................................108

RESET, Watchdog Timer, Oscillator Start-up 

Timer and Power-up Timer................. .. .... .. ..............102

Time-out Sequence on Power-up (MCLR not Tied to

VDD)/Case 1 ................................................................64

Case 2 ................................................................64

Time-out Sequence on Power-up (MCLR Tied

to VDD)........................................................................64

Timer0 and Timer1 External Clock ...........................104

Timer1 Incrementing Edge..........................................29

Timin g Pa r a meter Symbol o g y....... ........... .......... ........... ......9 8

UHF AS K/ FSK Tran sm itter

CEPT ..........................................................................49

FCC.............................................................................49

Radio Frequency.........................................................49

Transmitter..................................................................49

Voltage Reference Accuracy/Error .....................................37

Watchdog Timer

Summary o f Re g ist e rs.... .. ............... ............... ............69

Watchdog Timer (WDT)......................................................68

WWW, On-Line Support ............ .... ....................... . .. .... .. .... ...2

rfPIC12F675

DS70091B-page 130 Preliminary  2003-2013 Microchip Technology Inc.

NOTES:

 2003-2013 Microchip Technology Inc. DS70091B-page 131

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchip.com. This w eb si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

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resources, user’s guides and hardware support

documents, latest software releases and archived

software

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Questions (FAQ), technical support requests,

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program member listing

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Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

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To register, access the Microchip web site at

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“Customer Change Notification” and follow the

registration instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Offi ce

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical s upport is avail able throug h the web si te

at: http://microchip.com/support

DS70091B-page 132  2003-2013 Microchip Technology Inc.

READER RESP ONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at

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DS70091B

1. What are the best features of this doc ument ?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 133

rfPIC12F675

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or deliv ery, refer to the factory or the listed sales office.

* JW Devices are UV er asable and can be pro grammed to any device conf iguration. JW Devi ces meet the electr ical requirement of

each oscillator type.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Worldwide Site (www.microchip.com)

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device : Standard VDD range

T: (Tape and Reel)

Temperature Range I = -40C to +85C

E= -40C to +125C

Package SS = SSOP

Pattern 3-Digit Pattern Code for QTP (blank otherwise)

Examples:

a) rfPIC12F675F – E/SS 301 = Extended Temp.,

SSOP package, 434 MHz, QTP pattern #301

b) rfPIC12F675FHT – I/SS = Industrial Temp.,

SSOP package, 868 MHz, Tape and Reel

rfPIC12F675

DS70091B-page 134 Preliminary  2003-2013 Microchip Technology Inc.

 2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 135

Information contained in this publication regarding device

applications and the like is p rovided only for your conveni ence

and may be supers eded by update s. It i s your respon sibili ty to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PIC 32 logo, rfPIC, SST, SST Logo, SuperFlash

and UNI/O are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MTP, SEEVAL and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestr o, BodyCom,

chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net , dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Prog r a mming, IC SP, Mi n d i, MiWi , MPAS M, MPF, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net , PICki t,

PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,

Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA

and Z-Scale are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip

Technology Germany II GmbH & Co. & KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 9781620769683

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of t he m ost secure families of its kind on the m arket today, when used in the

intended manner and under normal conditions.

• The re are dishonest and possi bl y illegal met hods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolvi ng. We at Microchip are committed to continuously i mprov ing t he code protection f eatures of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

DS70091B-page 136 Preliminary  2003-2013 Microchip Technology Inc.

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11/29/12