CY28405-2
Rev 1.0, November 22, 2006 Page 3 of 16
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
izes to their default setting upon power-up, and therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for pow-
er management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 1. Frequency Select Table (FS_A FS_B)
FS_A FS_B CPU SRC 3V66 PCIF/PCI REF0 REF1 USB/DOT
0 0 100 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz
0B6b7REF/NREF/NREF/NREF/NREF/NREF/NREF/N
0 1 200 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz
1 0 133 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz
1 B6b7 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1
FS_A FS_B CPU SRC 3V66 PCIF/PCI REF0 REF1 USB/DOT
0 0 200 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz
0 1 400 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz
1 0 266 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz
Table 3. Command Code Definition
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1Start 1Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9 Write = 0 9 Write = 0
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code – 8 Bit
'00000000' stands for block operation
11:18 Command Code – 8 Bit
'00000000' stands for block operation
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Byte Count – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29:36 Data byte 1 – 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
38:45 Data byte 2 – 8 bits 30:37 Byte count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge from master
.... ...................... 39:46 Data byte from slave – 8 bits