TPS43330QDAPRQ1 - Texas Instruments

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

LOW I

, SINGLE BOOST, DUAL SYNCHRONOUS BUCK CONTROLLER

Check for Samples: TPS43330-Q1,TPS43332-Q1

1FEATURES

2• Qualified for Automotive Applications • Separate Enable Inputs (ENA, ENB)

• AEC-Q100 Test Guidance With the Following • Frequency Spread Spectrum (TPS43332)

Results: • Selectable Forced Continuous Mode or

– Device Temperature Grade 1: –40°C to Automatic Low-Power Mode at Light Loads

125°C Ambient Operating Temperature • Sense Resistor or Inductor DCR Sensing

– Device HBM ESD Classification Level H2 • Out-of-Phase Switching Between Buck

– Device CDM ESD Classification Level C2 Channels

• Two Synchronous Buck Controllers • Peak Gate-Drive Current 1.5 A

• One Pre-Boost Controller • Thermally Enhanced 38-Pin HTSSOP (DAP)

PowerPAD™ Package

• Input Range up to 40 V, (Transients up to 60

V), Operation Down to 2 V When Boost is APPLICATIONS

Enabled • Automotive Start-Stop, Infotainment,

• Low Power Mode IQ: 30 µA (One Buck On), Navigation Instrument Cluster Systems

35 µA (Two Bucks On) • Industrial and Automotive Multi-Rail DC Power

• Low Shutdown Current Ish < 4 µA Distribution Systems and Electronic Control

• Buck Output Range 0.9 V to 11 V Units

• Boost Output Selectable: 7 V, 10 V, or 11 V

• Programmable frequency and External

Synchronization Range 150 kHz to 600 kHz

DESCRIPTION

The TPS43330-Q1 and TPS43332-Q1 include two current-mode synchronous buck controllers and a voltage-

mode boost controller. The devices are ideally suited as a pre-regulator stage with low Iq requirements and for

applications that must survive supply drops due to cranking events. The integrated boost controller allows the

devices to operate down to 2 V at the input without seeing a drop on the buck regulator output stages. At light

loads, the buck controllers can be enabled to operate automatically in low-power mode, consuming just 30 µA of

quiescent current.

The buck controllers have independent soft-start capability and power-good indicators. External MOSFET

protection is provided by current foldback in the buck controllers and cycle-by-cycle current limitation in the boost

controller. The switching frequency can be programmed over 150 kHz to 600 kHz or synchronized to an external

clock in the same range. Additionally, the TPS43332-Q1 offers frequency-hopping spread-spectrum operation.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS43330/2

VBuckA

VBuckB

VBAT

2 V

V BAT

VBU CK B V BUC K A

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

Figure 1. Typical Application Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION(1)

TJOPTION PACKAGE(2) ORDERABLE PART NUMBER

Frequency-hopping spread spectrum OFF TPS43330QDAPRQ1

–40ºC to 150ºC DAP

Frequency-hopping spread spectrum ON TPS43332QDAPRQ1

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

space

ABSOLUTE MAXIMUM RATINGS(1)

MIN MAX UNIT

Voltage Input voltage: VIN, VBAT –0.3 60 V

Enable inputs: ENA, ENB –0.3 60 V

Bootstrap inputs: CBA, CBB –0.3 68 V

Phase inputs: PHA, PHB –0.7 60 V

Phase inputs: PHA, PHB (for 150 ns) –1 60 V

Feedback inputs: FBA, FBB –0.3 13 V

Error amplifier outputs: COMPA, COMPB –0.3 13 V

Voltage High-side MOSFET driver: GA1-PHA, GB1-PHB –0.3 8.8 V

(buck function: Low-side MOSFET drivers: GA2, GB2 –0.3 8.8 V

BuckA and BuckB) Current-sense voltage: SA1, SA2, SB1, SB2 –0.3 13 V

Soft start: SSA, SSB –0.3 13 V

Power-good output: PGA, PGB –0.3 13 V

Power-good delay: DLYAB –0.3 13 V

Switching-frequency timing resistor: RT –0.3 13 V

SYNC, EXTSUP –0.3 13 V

Low-side MOSFET driver: GC1 –0.3 8.8 V

Error-amplifier output: COMPC –0.3 13 V

Voltage Enable input: ENC –0.3 13 V

(boost function) Current-limit sense: DS –0.3 60 V

Output-voltage select: DIV –0.3 8.8 V

P-channel MOSFET driver: GC2 –0.3 60 V

Voltage

(PMOS driver) P-channel MOSFET driver: VIN-GC2 –0.3 8.8 V

Gate-driver supply: VREG –0.3 8.8 V

Junction temperature: TJ–40 150 °C

Temperature Operating temperature: TA–40 125 °C

Storage temperature: Tstg –55 165 °C

Human-body model (HBM) AEC-Q11 ±2 kV

Classification Level H2

FBA, FBB, RT, DLYAB ±400

Charged-device model (CDM) AEC-Q11

Electrostatic VBAT, ENC, SYNC, VIN ±750

Classification Level C2

discharge ratings All other pins ±500 V

PGA, PGB ±150

Machine model (MM) All other pins ±200

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to GND.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

THERMAL INFORMATION TPS4333x-Q1

THERMAL METRIC(1) DAP UNIT

38 PINS

θJA Junction-to-ambient thermal resistance(2) 27.3

θJCtop Junction-to-case (top) thermal resistance(3) 19.6

θJB Junction-to-board thermal resistance(4) 15.9 °C/W

ψJT Junction-to-top characterization parameter(5) 0.24

ψJB Junction-to-board characterization parameter(6) 6.6

θJCbot Junction-to-case (bottom) thermal resistance(7) 1.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT

Input voltage: VIN, VBAT 4 40

Enable inputs: ENA, ENB 0 40

Boot inputs: CBA, CBB 4 48

Buck function:

BuckA and BuckB Phase inputs: PHA, PHB –0.6 40 V

voltage Current-sense voltage: SA1, SA2, SB1, SB2 0 11

Power-good output: PGA, PGB 0 11

SYNC, EXTSUP 0 9

Enable input: ENC 0 9

Boost function Voltage sense: DS 40 V

DIV 0 VREG

Operating temperature: TA–40 125 °C

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

DC ELECTRICAL CHARACTERISTICS

VIN = 8 V to 18 V, TJ= –40°C to 150°C (unless otherwise noted)

NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

1.0 Input Supply

Boost controller enabled, after initial start-up

1.1 VBat Supply voltage 2 40 V

condition is satisfied

Input voltage required for device 6.5 40

on initial start-up

1.2 VIN V

Buck regulator operating range 4 40

after initial start-up

VIN falling. After a reset, initial start-up conditions 3.5 3.6 3.8 V

may apply.(1)

1.3 VIN UV Buck undervoltage lockout VIN rising. After a reset, initial start-up conditions 3.8 4 V

may apply.(1)

VBOOST_UNLOC

1.4 Boost unlock threshold VBAT rising 8.2 8.5 8.8 V

KVIN = 13 V, BuckA: LPM, BuckB: off, TA= 25°C 30 40 µA

LPM quiescent current:

1.5 Iq_LPM_ VIN = 13 V, BuckB: LPM, BuckA: off, TA= 25°C

(2)

VIN = 13 V, BuckA, B: LPM, TA= 25°C 35 45 µA

VIN = 13 V, BuckA: LPM, BuckB: off, TA= 125°C 40 50 µA

LPM quiescent current:

1.6 Iq_LPM VIN = 13 V, BuckB: LPM, BuckA: off, TA= 125°C

(2)

VIN = 13 V, BuckA, B: LPM, TA= 125°C 45 55 µA

SYNC = 5 V, TA= 25°C

VIN = 13 V, BuckA: CCM, BuckB: off, TA= 25°C 4.85 5.3

Quiescent current:

1.7 Iq_NRM mA

normal (PWM) mode(2) VIN = 13 V, BuckB: CCM, BuckA: off, TA= 25°C

VIN = 13 V, BuckA, B: CCM, TA= 25°C 7 7.6

SYNC = 5 V, TA= 125°C

VIN = 13 V, BuckA: CCM, BuckB: off, TA= 125°C 5 5.5

Quiescent current:

1.8 Iq_NRM mA

normal (PWM) mode(2) VIN = 13 V, BuckB: CCM, BuckA: off, TA= 125°C

VIN = 13 V, BuckA, B: CCM, TA= 125°C 7.5 8

1.9 Ibat_sh Shutdown current BuckA, B: off, VBat = 13 V , TA= 25°C 2.5 4 µA

1.10 Ibat_sh Shutdown current BuckA, B: off, VBat = 13 V, TA= 125°C 3 5 µA

2.0 Input Voltage VBAT - Undervoltage Lockout

VBAT falling. After a reset, initial start-up 1.8 1.9 2 V

conditions may apply.(1)

2.1 VBATUV Boost-input undervoltage VBAT rising. After a reset, initial start-up 2.4 2.5 2.6 V

conditions may apply.(1)

2.2 UVLOHys Hysteresis 500 600 700 mV

2.3 UVLOfilter Filter time 5 µs

3.0 Input Voltage VIN - Overvoltage Lockout

VIN rising 45 46 47

3.1 VOVLO Overvoltage shutdown V

VIN falling 43 44 45

3.2 OVLOHys Hysteresis 1 2 3 V

3.3 OVLOfilter Filter time 5 µs

(1) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.

(2) Quiescent current specification is non-switching current consumption without including the current in the external-feedback resistor

divider.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 V to 18 V, TJ= –40°C to 150°C (unless otherwise noted)

NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

4.0 Boost Controller

4.1 Vboost7-VIN Boost VOUT = 7 V DIV = low, VBAT = 2 V to 7 V 6.8 7 7.3 V

Boost-enable threshold Boost VOUT = 7 V, VBAT falling 7.5 8 8.5

4.2 Vboost7-th Boost-disable threshold Boost VOUT = 7 V, VBAT falling 8 8.5 9 V

Boost hysteresis Boost VOUT = 7 V, VBAT falling 0.4 0.5 0.6

4.3 Vboost10-VIN Boost VOUT = 10 V DIV = open, VBAT = 2 V to 10 V 9.7 10 10.4 V

Boost-enable threshold Boost VOUT = 10 V, VBAT falling 10.5 11 11.5

4.4 Vboost10-th Boost-disable threshold Boost VOUT = 10 V, VBAT falling 11 11.5 12 V

Boost hysteresis Boost VOUT = 10 V, VBAT falling 0.4 0.5 0.6

4.5 Vboost11-VIN Boost VOUT = 11 V DIV = VREG, VBAT = 2 V to 11 V 10.7 11 11.4 V

Boost-enable threshold Boost VOUT = 11 V, VBAT falling 11.5 12 12.5

4.6 Vboost11-th Boost-disable threshold Boost VOUT = 11 V, VBAT falling 12 12.5 13 V

Boost hysteresis Boost VOUT = 11 V, VBAT falling 0.4 0.5 0.6

Boost-Switch Current Limit

4.7 VDS Current-limit sensing DS input with respect to PGNDA 0.175 0.2 0.225 V

4.8 tDS Leading-edge blanking 200 ns

Gate Driver for Boost Controller

4.9 IGC1 Peak Gate-driver peak current 1.5 A

4.10 rDS(on) Source and sink driver VREG = 5.8 V, IGC1 current = 200 mA 2 Ω

Gate Driver for PMOS

4.11 rDS(on) PMOS OFF 10 20 Ω

4.12 IPMOS_ON Gate current VIN = 13.5 V, Vgs = –5 V 10 mA

4.13 tdelay_ON Turnon delay C = 10 nF 5 10 µs

Boost-Controller Switching Frequency

4.14 fsw-Boost Boost switching frequency fSW_Buck / 2 kHz

4.15 DBoost Boost duty cycle 90%

Error Amplifier (OTA) for Boost Converters

VBAT = 12 V 0.8 1.35

4.16 GmBOOST Forward transconductance mS

VBAT = 5 V 0.35 0.65

5.0 Buck Controllers

5.1 VBuckA/B Adjustable output-voltage range 0.9 11 V

Measure FBX pin 0.792 0.800 0.808 V

Internal reference and tolerance

5.2 Vref, NRM voltage in normal mode –1% 1%

Measure FBX pin 0.784 0.800 0.816 V

Internal reference and tolerance

5.3 Vref, LPM voltage in low-power mode –2% 2%

V sense for forward-current limit in

5.4 FBx = 0.75 V (low duty cycle) 60 75 90 mV

CCM

Vsense V sense for reverse-current limit in

5.5 FBx = 1 V –65 –7.5 –23 mV

CCM

5.6 VI-Foldback V sense for output short FBx = 0 V 17 32.5 48 mV

5.7 tdead Shoot-through delay, blanking time 20 ns

High-side minimum on-time 100 ns

5.8 DCNRM Maximum duty cycle (digitally 98.75%

controlled)

5.9 DCLPM Duty cycle, LPM 80%

LPM entry-threshold load current

ILPM_Entry as fraction of maximum set load 1% .(3)

current

5.10 LPM exit-threshold load current as

ILPM_Exit fraction of maximum set load (3) 10%

current

(3) The exit threshold is specified to be always higher than the entry threshold.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 V to 18 V, TJ= –40°C to 150°C (unless otherwise noted)

NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-Side External NMOS Gate Drivers for Buck Controller

5.11 IGX1_peak Gate-driver peak current 1.5 A

5.12 rDS(on) Source and sink driver VVREG = 5.8 V, IGX1 current = 200 mA 2 Ω

Low-Side NMOS Gate Drivers for Buck Controller

5.13 IGX2_peak Gate driver peak current 1.5 A

5.14 RDS ON Source and sink driver VREG = 5.8 V, IGX2 current = 200 mA 2 Ω

Error Amplifier (OTA) for Buck Converters

COMPA, COMPB = 0.8 V,

5.15 GmBUCK Transconductance 0.72 1 1.35 mS

source/sink = 5 µA, test in feedback loop

5.16 IPULLUP_FBx Pullup current at FBx pins FBx = 0 V 50 100 200 nA

6.0 Digital Inputs: ENA, ENB, ENC, SYNC

6.1 VIH Higher threshold VIN = 13 V 1.7 V

6.2 VIL Lower threshold VIN = 13 V 0.7 V

6.3 RIH_SYNC Pulldown resistance on SYNC VSYNC = 5 V 500 kΩ

6.4 RIL_ENC Pulldown resistance on ENC VENC = 5 V 500 kΩ

Pullup current source on ENA,

6.5 IIL_ENx VENx = 0 V, 0.5 2 µA

ENB

7.0 Boost Output Voltage: DIV

7.1 VIH_DIV Higher threshold VREG = 5.8 V Vreg – 0.2 V

7.2 VIL_DIV Lower threshold 0.2 V

7.3 Voz_DIV Voltage on DIV if unconnected Voltage on DIV if unconnected Vreg / 2 V

8.0 Switching Parameter – Buck DC-DC Controllers

8.1 fSW_Buck Buck switching frequency RT pin: GND 360 400 440 kHz

8.2 fSW_Buck Buck switching frequency RT pin: 60-kΩexternal resistor 360 400 440 kHz

Buck adjustable range with

8.3 fSW_adj RT pin: external resistor 150 600 kHz

external resistor

8.4 fSYNC Buck synchronization range External clock input 150 600 kHz

8.5 fSS Spread-spectrum spreading TPS4333-Q1 only 5%

9.0 Internal Gate-Driver Supply

Internal regulated supply VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = high 5.5 5.8 6.1 V

9.1 VREG IVREG = 0 mA to 100 mA, EXTSUP = 0 V,

Load regulation 0.2% 1%

SYNC = high

Internal regulated supply EXTSUP = 8.5 V 7.2 7.5 7.8 V

9.2 VREG(EXTSUP) IEXTSUP = 0 mA to 125 mA, SYNC = High

Load regulation 0.2% 1%

EXTSUP = 8.5 V to 13 V

EXTSUP switch-over voltage IVREG = 0 mA to 100 mA,

9.3 VEXTSUP-th 4.4 4.6 4.8 V

threshold EXTSUP ramping positive

9.4 VEXTSUP-Hys EXTSUP switch-over hysteresis 150 250 mV

9.5 IREG-Limit Current limit on VREG EXTSUP = 0 V, normal mode as well as LPM 100 400 mA

IREG_EXTSUP- Current limit on VREG when using IVREG = 0 mA to 100 mA,

9.6 125 400 mA

Limit EXTSUP EXTSUP = 8.5 V, SYNC = High

10.0 Soft Start

10.1 ISSx Soft-start source current SSA and SSB = 0 V 0.75 1 1.25 µA

11.0 Oscillator (RT)

11.1 VRT Oscillator reference voltage 1.2 V

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 V to 18 V, TJ= –40°C to 150°C (unless otherwise noted)

NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

12.0 Power Good / Delay

12.1 PGpullup Pullup for A and B to Sx2 50 kΩ

12.2 PGth1 Power-good threshold FBx falling –5% –7% –9%

12.3 PGhys Hysteresis 2%

12.4 PGdrop Voltage drop IPGA = 5 mA 450 mV

12.5 IPGA = 1 mA 100 mV

12.6 PGleak Power-good leakage VSx2 = VPGx = 13 V 1 µA

12.7 tdeglitch Power-good deglitch time 2 16 µs

External capacitor = 1 nF

12.8 tdelay Reset delay 1 ms

VBUCKX < PGth1

12.9 tdelay_fix Fixed reset delay No external capacitor, pin open 20 50 µs

Activate current source (current to

12.10 IOH 30 40 50 µA

charge external capacitor)

Activate current sink (current to

12.11 IIL 30 40 50 µA

discharge external capacitor)

13.0 Overtemperature Protection

Junction-temperature shutdown

13.1 Tshutdown 150 165 °C

threshold

13.2 Thys Junction-temperature hysteresis 15 °C

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

19 20

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC SYNC

DLYAB

AGND

PGB

SSB

COMPB

FBB

SB2

SB1

PGNDB

GB2

PHB

GB1

CBB

VREG

DIV

EXTSUP

VIN

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

DEVICE INFORMATION

DAP PACKAGE

(TOP VIEW)

PIN FUNCTIONS

NAME NO. I/O DESCRIPTION

AGND 23 O Analog ground reference

A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck

CBA 5 I controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the

high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.

A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck

CBB 34 I controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the

high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.

Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the

COMPA 13 O target for the peak current through the inductor of BuckA. This voltage is clamped on the upper and lower ends to

provide current-limit protection for the external MOSFETs.

Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the

COMPB 26 O target for the peak current through the inductor of BuckB. This voltage is clamped on the upper and lower ends to

provide current-limit protection for the external MOSFETs.

COMPC 18 O Error-amplifier output and loop-compensation node of the boost regulator

The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter

DIV 36 I at 11 V, a low input sets the value at 7 V, and a floating pin sets 10 V.

The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-

DLYAB 21 O good comparators. When this pin is left open, the power-good delay is set to an internal default value of 20 µs

typical.

This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection.

DS 2 I Alternatively, it can be connected to a sense resistor between the source of the low-side MOSFET and ground via

a filter network for better noise immunity.

Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.5 V

ENA 16 I enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and

ENB are low, the device is shut down and consumes less than 4 µA of current.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

PIN FUNCTIONS (continued)

NAME NO. I/O DESCRIPTION

Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.5 V

ENB 17 I enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and

ENB are low, the device is shut down and consumes less than 4 µA of current.

This input enables and disables the boost regulator. An input voltage higher than 1.5 V enables the controller.

Voltages lower than 0.7 V disable the controller. Because this pin provides and internal pulldown resistor (500 kΩ)

ENC 19 I it must be pulled high to enable the boost function. When enabled, the controller starts switching as soon as VBAT

falls below the boost threshold, depending upon the programmed output voltage.

EXTSUP can be used to supply the VREG regulator from one of the TPS43330/2 buck regulator rails to reduce

EXTSUP 37 I power dissipation in cases where VIN is expected to be high. When EXTSUP is open or lower than 4.6 V, the

regulator is powered from VIN.

Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of

FBA 12 I 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output

voltage.

Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of

FBB 27 I 0.8 V. A suitable resistor-divider network between the buck output and the feedback pin sets the desired output

voltage.

External high-side N-channel MOSFET for buck regulator BuckA can be driven from this output. The output

GA1 6 O provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference

provided by PHA and has a voltage swing provided by CBA.

External low-side N-channel MOSFET for buck regulator BuckA can be driven from this output. The output

GA2 8 O provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.

External high-side N-channel MOSFET for buck regulator BuckB can be driven from this output. The output

GB1 33 O provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference

provided by PHB and has a voltage swing provided by CBB.

External low-side N-channel MOSFETs for buck regulator BuckB can be driven from this output. The output

GB2 31 O provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.

An external low-side N-channel MOSFET for the boost regulator can be driven from this output. This output

GC1 3 O provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.

A floating output drive to control the external P-channel MOSFET is available at this pin. This MOSFET can be

GC2 4 O used to bypass the boost rectifier diode or a reverse protection diode when the boost is not switching or if boost is

disabled, and thus reduce power losses.

Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the

PGA 15 O feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either Vin or

Vbat drops below its respective undervoltage threshold.

Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the

PGB 24 O feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either Vin or

Vbat drops below its respective undervoltage threshold.

PGNDA 9 O Power ground connection to the source of the low-side N-channel MOSFETs of BuckA.

PGNDB 30 O Power ground connection to the source of the low-side N-channel MOSFETs of BuckB

Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gate-

PHA 7 O driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.

Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gate-

PHB 32 O driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.

The operating switching frequency of the buck and boost controllers is set by connecting a resistor to ground on

RT 22 O this pin. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for

the boost controller.

SA1 10 I High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for

each buck controller. The current-sense element should be chosen to set the maximum current through the

inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics

SA2 11 I across duty cycle and VIN. (SA1 positive node, SA2 negative node).

SB1 29 I High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for

each buck controller. The current-sense element should be chosen to set the maximum current through the

inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics

SB2 28 I across duty cycle and VIN. (SB1 positive node, SB2 negative node).

Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of

0.8 V or the SSA pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate

SSA 14 O capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected to another

supply can also be used to provide a tracking input to this pin.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

PIN FUNCTIONS (continued)

NAME NO. I/O DESCRIPTION

Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of

0.8 V or the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate

SSB 25 O capacitor connected here can be used to set the soft-start ramp interval. A resistor-divider connected to another

supply can also be used to provide a tracking input to this pin.

If an external clock is present on this pin, the device detects it and the internal PLL locks onto the external clock.

This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600

kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits

SYNC 20 I transition to low-power mode. An open or low allows discontinuous mode operation and entry into low-power

mode at light loads. On the TPS43332, a high level enables frequency-hopping spread spectrum, whereas an

open or a low level disables it.

Battery input sense for the boost controller. If the boost controller is enabled and the voltage at VBAT falls below

VBAT 1 I the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed

boost output voltage.

Main Input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally, it

VIN 38 I powers the internal control circuits of the device.

An external capacitor on this pin is required to provide a regulated supply for the gate drivers of the buck and

boost controllers. A capacitance in the order of 4.7 µF is recommended. The regulator can be used such that it is

VREG 35 O either powered from VIN or EXTSUP. This pin has current-limit protection and should not be used to drive any

other loads.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

VIN

SYNC

GA1

FBA

GA2

CBA

SA1

SA2

PGNDA

COMPA

ENA

PGA

GC2

VREG

DLYAB

PHA

SSA

EXTSUP

Filter timer

–

0.8V

PWM

comp +

Slope Comp

OTA

Current sense

Amp

PWM logic

40 Am

Internal ref

(Band gap)

VREF

SA2

VREF

Gate Driver

Supply

Internal

Oscillator

SYNC &

LPM

180 deg

ENA

1 Am

Source/

Sink

Logic

ENB

VIN

500 nA

1 Am

SSB

ENB

Duplicate for second

Buck controller channel

GB1

FBB

GB2

CBB

SB1

SB2

PGNDB

COMPB

PGB

PHB

VREG

SSA

PWM

Logic

Vref

VBAT

VIN

0.2V

OTA

OCP

DIV

COMPC

GC1

ENC

PWM

comp

AGND

Second Buck Controller

Channel

VREG

PGNDA

FBA

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

Figure 2. Functional Block Diagram

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

SOFT-START OUTPUTS (BUCK)

2ms/DIV

VOUTA

VOUTB

1V/DIV

OUTPUT CURRENT (A)

EFFICIENCY (%)

EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS)

POWER LOSS (mW)

EFFICIENCY,

SYNC = LOW

POWER LOSS,

SYNC = HIGH

POWER LOSS,

SYNC = LOW

EFFICIENCY,

SYNC = HIGH

VIN = 12V, VOUT = 5V, SWITCHING FREQUENCY = 400kHz

INDUCTOR = 4.7µH, RSENSE = 10mW

0.0001 0.001 0.01 0.1 110

100

0.1

100

1000

10000

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

TYPICAL CHARACTERISTICS

Figure 3. Figure 4.

Figure 5. Figure 6.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

CRANKING PULSE BOOST RESPONSE

(12V to 4V IN 1ms AT BOOST DIRECT OUTPUT 25W)

20ms/DIV

VBAT (BOOST INPUT)

5V/DIV

VIN (BOOST OUTPUT)

5V/DIV

IIND

10A/DIV

VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A,

SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,

RSENSE = 7.5mOHM, CIN = 440µF, COUT = 660µF

CRANKING PULSE BOOST RESPONSE

(12V to 3V IN 1ms AT BUCK OUTPUTS 7.5W/11.5W)

20ms/DIV

VBAT (BOOST INPUT)

5V/DIV

VOUT BUCKA AC-COUPLED

200mV/DIV

VOUT BUCKB AC-COUPLED

200mV/DIV

IIND

10A/DIV

VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A,

SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,

RSENSE = 7.5mOHM, CIN = 440µF, COUT = 660µF

OUTPUT CURRENT (A)

EFFICIENCY (%)

EFFICIENCY ACROSS OUTPUT CURRENTS (BOOST)

VIN (BOOST OUTPUT) = 10V, SWITCHING FREQUENCY = 200kHz,

INDUCTOR = 1.0µH, RSENSE = 7.5mW

0.01 110

100

VBAT = 8V

VBAT = 5V

VBAT = 3V

LOAD STEP RESPONSE (BOOST)

(0 TO 5A AT 2.5A/µs)

2ms/DIV

VIN (BOOST OUTPUT) AC-COUPLED

IIND

5A/DIV

500mV/DIV

VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V,

SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,

RSENSE = 7.5m , CIN = 440µF, COUT = 660µFW

BUCK LOAD STEP: LOW POWER MODE EXIT

(90 mA TO 4 A AT 2.5 A/µs)

VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz

INDUCTOR = 4.7 µH, RSENSE = 10 mW

50 µs/DIV

VOUT AC-COUPLED

100 mV/DIV

IIND

2 A/DIV

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Figure 7. Figure 8.

Figure 9. Figure 10.

Figure 11. Figure 12.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

INDUCTOR CURRENTS (BOOST)

VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V,

SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,

RSENSE = 7.5m , CIN = 440µF, COUT = 660µFW

2µs/DIV

3A LOAD

5A/DIV

100mA LOAD

5A/DIV

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

TYPICAL CHARACTERISTICS (continued)

Figure 13.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

REGULATED FBx VOLTAGE vs TEMPERATURE (BUCK)

TEMPERATURE (°C)

REGULATED FBx VOLTAGE (mV)

-40 -15 10 35 60 85 110 135 160

795

796

797

798

799

800

801

802

803

804

805

CURRENT LIMIT VS DUTY CYCLE (BUCK)

DUTY CYCLE (%)

PEAK CURRENT SENSE VOLTAGE (mV)

0 10 20 30 40 50 60 70 80 90 100

VIN = 8V

VIN = 12V

CURRENT SENSE PINS INPUT CURRENT (BUCK)

OUTPUT VOLTAGE (V)

SENSE CURRENT (µA)

01 2 345678 9 10 11 12

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

150°C

25°C

FOLDBACK CURRENT LIMIT (BUCK)

FBx VOLTAGE (V)

PEAK CURRENT SENSE VOLTAGE (mV)

0 0.2 0.4 0.6 0.8

BOTH BUCKS ON

ONE BUCK ON

NEITHER BUCK ON

Quiescent Current (µA)

Temperature (°C)

-40 -15 10 35 60 85 110 135 160

NO-LOAD QUIESCENT CURRENT

ACROSS TEMPERATURE

BUCKx PEAK CURRENT LIMIT vs. COMPx VOLTAGE

COMPx VOLTAGE (V)

PEAK CURRENT SENSE VOLTAGE (mV)

SYNC = LOW

SYNC = HIGH

0.65 0.8 0.95 1.1 1.25 1.4 1.55

-37.5

-25

-12.5

12.5

37.5

62.5

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Figure 14. Figure 15.

Figure 16. Figure 17.

Figure 18. Figure 19.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

I ×Δt

C = (Farads)

ΔV

f = (X=24kΩ×MHz)

f =24× RT

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

DETAILED DESCRIPTION

BUCK CONTROLLERS: NORMAL MODE PWM OPERATION

Frequency Selection and External Synchronization

The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior

and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,

depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching

frequency to 400 kHz. The frequency can also be set by a resistor at RT, according to the formula:

For example,

600 kHz requires 40 kΩ

150 kHz requires 160 kΩ

It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to

600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the

specified range. The device can also detect a loss of clock at this pin, and when this condition is detected, the

device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical

switching frequencies, 180 degrees out-of-phase.

Enable Inputs

The buck controllers are enabled using independent enable inputs from the ENA and ENB pins. These are high-

voltage pins, with a threshold of 1.5 V for high level, and can be connected directly to the battery for self-bias.

The low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open

circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device

is shut down and consumes a current less than 4 µA.

Feedback Inputs

The output voltage is set by choosing the right resistor feedback divider network connected to the FBx (feedback)

pins. Choose this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-

nA pullup current source as a protection feature in case the pins open up as a result of physical damage.

Soft-Start Inputs

In order to avoid large inrush currents, both buck controllers have an independent programmable soft-start timer.

The voltage at the SSx pins acts as the soft-start reference voltage. A 1-µA pullup current is available at the SSx

pins, and by choosing a suitable capacitor, a ramp of the desired soft-start speed can be generated. After start-

up, the pullup current ensures that SSx is higher than the internal reference of 0.8 V; 0.8 V then becomes the

reference for the buck controllers. The soft-start ramp time is defined by:

where,

ISS = 1 µA (typical)

∆V = 0.8 V

CSS is the required capacitor for ∆t, the desired soft-start time.

Alternatively, the soft-start pins can be used as tracking inputs. In this case, they should be connected to the

supply to be tracked via a suitable resistor-divider network.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

DCR

Inductor L

VBUCK X

Sx2

Sx1

TPS43330/2

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

Current-Mode Operation

Peak-current-mode control regulates the peak current through the inductor such that the output voltage is

maintained to its set value. The error between the feedback voltage at FBx and the internal reference produces a

signal at the output of the error amplifier (COMPx) which serves as the target for the peak inductor current. The

current through the inductor is sensed as a differential voltage at Sx1–Sx2 and compared with this target during

each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing COMPx to fall or rise

respectively, thus increasing or decreasing the current through the inductor until the average current matches the

load. In this way, the output voltage is maintained in regulation.

The top N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the inductor

current reaches its peak value. Once this MOSFET is turned off, and after a small delay (shoot-through delay)

the lower N-channel MOSFET is turned on until the start of the next clock cycle. In dropout operation, the high-

side MOSFET stays on continuously. In every fourth clock cycle, the duty cycle is limited to 95% in order to

charge the bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators.

During dropout, the buck regulator switches at one-fourth of its normal frequency.

Current Sensing and Current Limit with Foldback

The maximum value of COMPx is clamped such that the maximum current through the inductor is limited to a

specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value

due to a short circuit or overcurrent condition, the clamped voltage at the COMPx successively decreases, thus

providing current foldback protection. This protects the high-side external MOSFET from excess current (forward-

direction current limit).

Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully

on, the COMPx node drops low. It is clamped on the lower end as well, in order to limit the maximum current in

the low-side MOSFET (reverse-direction current limit).

The current through the inductor is sensed by an external resistor. The sense resistor should be chosen such

that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This

value is specified at low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5 V output and

12 V input), 50 mV is a more reasonable value, considering tolerances and mismatches. The typical

characteristics provide a guide for using the correct current-limit sense voltage.

The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range.

This allows DCR current sensing using the dc resistance of the inductor for higher efficiency. DCR sensing is

shown in Figure 20. Here, the series resistance (DCR) of the inductor is used as the sense element. The filter

components should be placed close to the device for noise immunity. Remember that while the DCR sensing

gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic

inductor series resistance. Hence, it may often be advantageous to use the more-accurate sense resistor for

current sensing.

Figure 20. DCR Sensing Configuration

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

DELAY

DLYAB

t 1 msec

C 1 nF

L×f =200

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

Slope Compensation

Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable operation

at all conditions. For optimal performance of this circuit, the following condition must be satisfied in the choice of

inductor and sense resistor:

where

L is the buck regulator inductor in henries.

RSis the sense resistor in ohms.

fsw is the buck regulator switching frequency in hertz.

Power-Good Outputs and Filter Delays

Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx

pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold

has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-

drain output at the PGx pins. An internal 50-kΩpullup resistor to Sx2 is available, or an external resistor can be

used. When a buck controller is shut down, the power-good indicator is pulled down internally. Connecting the

pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow

through the resistor when the buck controller is powered down.

In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, an

internal delay circuit for de-glitching is used. Similarly, when the output voltage returns to its set value after a long

negative transient, the power-good indicator is asserted high (the open-drain pin released) after the same delay.

This can be used to delay the reset to the circuits being powered from the buck regulator rail. The delay of this

circuit can be programmed by using a suitable capacitor at the DLYAB pin according to the equation:

When the DLYAB pin is open, the delay is set to a default value of 20 µs typical. The power-good delay timing is

common to both the buck rails, but the power-good comparators and indicators function independently.

Light-Load PFM Mode

An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks.

When the SYNC pin is low or open, the buck controllers are allowed to operate in discontinuous mode at light

loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor current is detected.

In discontinuous mode, as the load decreases, the duration of the clock period when both the high-side and low-

side MOSFETs are turned off increases (deep discontinuous mode). In case the duration exceeds 60% of the

clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design ensures

that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have been chosen

appropriately as recommended in the slope compensation section.

In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.

Whenever the FBx value falls below the reference, the high-side MOSFET is turned on for a pulse duration

inversely proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET is turned off

and the current in the inductor decays until it becomes zero. The low-side MOSFET is not turned on. The next

pulse occurs the next time FBx falls below the reference value. This results in a constant volt-second ton

hysteretic operation with a total device quiescent current consumption of 30 µA when a single buck channel is

active and 35 µA when both channels are active.

As the load increases, the pulses become more and more frequent and move closer to each other until the

current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency

current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher

than 80% duty cycle of the high-side MOSFET.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

GC1

TPS43330 /2

VIN

Vbat

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

The TPS43330-Q1and TPS43332-Q1 an support the full-current load during low-power mode until the transition

to normal mode takes place. The design ensures the low-power mode exit occurs at 10% (typical) of full-load

current if the inductor and sense resistor have been chosen as recommended. Moreover, there is always a

hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.

In the event that both buck controllers are active, low-power mode is only possible when both buck controllers

have light loads that are low enough for low-power mode entry. When the boost controller is enabled, low-power

mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to

GND. If DIV is high (VREG), low-power mode is inhibited.

Boost Controller

The boost controller has a fixed-frequency voltage-mode architecture and includes cycle-by-cycle current-limit

protection for the external N-channel MOSFET. The switching frequency is derived from and set to one-half of

the buck-controller switching frequency. The output voltage of the boost controller at the VIN pin is set by an

internal resistor-divider network and is programmable to 7 V, 10 V or 11 V, based on the low, open, or high

status, respectively, of the DIV pin. A change of the DIV setting is not recognized while the device is in low-

power mode.

The boost controller is enabled by the active-high ENC pin and is active when the input voltage at the VBAT pin

has crossed the unlock threshold of 8.5 V at least once. After that, the boost controller is armed and starts

switching as soon as VIN falls below the value set by the DIV pin and regulates the VIN voltage. Thus, the boost

regulator maintains a stable input voltage for the buck regulators during transient events such as a cranking

pulse at VBAT.

Whenever the voltage at the DS pin exceeds 200 mV, the boost external MOSFET is turned off by pulling the

CG1 pin low. By connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET

source and ground, cycle-by-cycle overcurrent protection for the MOSFET can be achieved. The on-resistance of

the MOSFET or the value of the sense resistor must be chosen in such a way that the on-state voltage at the DS

does not exceed 200 mV at the maximum-load and minimum-input-voltage conditions. When a sense resistor is

used , a filter network is recommended to be connected between the DS pin and the sense resistor for better

noise immunity.

The boost output (VIN) can also be used to supply other circuits in the system. However, they should be high-

voltage tolerant. The boost output is regulated to the programmed value only when VIN is low, and so VIN can

reach battery levels.

Figure 21. External Drain-Source Voltage Sensing

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

GC1

TPS43330 /2

VIN

Vbat

RISEN

RIFLT

CIFLT

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

Figure 22. External Current Shunt Resistor

Frequency-Hopping Spread Spectrum (TPS43332 Only)

The TPS43332 features a frequency-hopping pseudo-random spectrum-spreading architecture. On this device,

whenever the SYNC pin is high, the internal oscillator frequency is varied from one cycle to the next within a

band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a linear-

feedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift

frequency shifts only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies.

Table 1. Frequency-Hopping Control

Sync Frequency Spread Spectrum (FSS) Comments

Terminal

Device in forced continuous mode, internal PLL locks into external clock

External clock Not active between 150 kHz and 600 kHz.

Device can enter discontinuous mode. Automatic LPM entry and exit,

Low or open Not active depending on load conditions

TPS43330: FSS not active

High Device in forced continuous mode

TPS43332: FSS active

Table 2. Mode of Operation

ENABLE AND INHIBIT PINS DRIVER STATUS DEVICE STATUS QUIESCENT CURRENT

ENA ENB ENC SYNC BUCK CONTROLLERS BOOST CONTROLLER

Low Low Low X Shutdown Disabled Shutdown Approximately 4 µA

Low Buck B: LPM enabled Approximately 30 µA (light loads)

Low High Low Buck B running Disabled

High Buck B: LPM inhibited mA range

Low Buck A: LPM enabled Approximately 30 µA (light loads)

High Low Low Buck A running Disabled

High Buck A: LPM inhibited mA range

Low Buck A/B: LPM enabled Approximately 35 µA (light loads)

BuckA and BuckB

High High Low Disabled

running

High Buck A/B: LPM inhibited mA range

Low Low Low X Shutdown Disabled Shutdown Approximately 4 µA

Approximately 50 µA (no boost,

Low Buck B: LPM enabled

Boost running for VIN < set light loads)

Low High High Buck B running boost output

High Buck B: LPM inhibited mA range

Approximately 50 µA (no boost,

Low Buck A: LPM enabled

Boost running for VIN < set light loads)

High Low High Buck A running boost output

High Buck A: LPM inhibited mA range

Approximately 60 µA (no boost,

Low Buck A/B: LPM enabled

BuckA and BuckB Boost running for VIN < set light loads)

High High High running boost output

High Buck A/B: LPM inhibited mA range

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

LDO

EXTSUP

LDO

VIN

VIN EXTSUP

VREG

typ 5.8 V typ 7.5 V

typ 4.6 V

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

Gate-Driver Supply (VREG, EXTSUP)

The gate drivers of the buck and boost controllers are supplied from an internal linear regulator whose output

(5.8 V typical) is available at the VREG pin and should be decoupled using at least a 3.3-µF ceramic capacitor.

This pin has internal current-limit protection and should not be used to power any other circuits.

The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6 V

(typical). In case VIN expected to go to high levels, there can be excessive power dissipation in this regulator,

especially at high switching frequencies and when using large external MOSFETs. In this case, it is

advantageous to power this regulator from the EXTSUP pin, which can be connected to a supply lower than VIN

but high enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6 V, the linear

regulator automatically switches to EXTSUP as its input to provide this advantage. Efficiency improvements are

possible when one of the switching regulator rails from the TPS43330-Q1 or TPS43332-Q1 or any other voltage

available in the system is used to power EXTSUP. The maximum voltage that should be applied to EXTSUP is

13 V.

Figure 23. Internal Gate-Driver Supply

Using a large value for EXTSUP is advantageous, as it provides a large gate drive and hence better on-

resistance of the external MOSFETs. A 0.1-µF ceramic capacitor is recommended for decoupling the EXTSUP

pin when not being used.

During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt

regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in

low-power mode as well.

External P-Channel Drive (GC2) and Reverse Battery Protection

The TPS43330-Q1 and TPS43332-Q1 include a gate driver for an external P-channel MOSFET which can be

connected across the rectifier diode of the boost regulator. This is useful to reduce power losses when the boost

controller is not switching. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive

a P-channel MOSFET. When VBAT falls below the boost-enable threshold, the gate driver turns off the P-

channel MOSFET and the diode is no longer bypassed.

The gate driver can also be used to bypass any additional protection diodes connected in series, as shown in

Figure 24.Figure 25 also shows a different scheme of reverse battery protection, which may require only a

smaller-sized diode to protect the N-channel MOSFET, as it conducts only for a part of the switching cycle.

Because it is not always in the series path, the system efficiency can be improved.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330/2

GC2

VBAT

Fuse

VIN

GC1

COMPC

VBAT

C14

Fuse (S1)

C13

C15C17

C16

R10

TPS43330/2

GC2

VIN

GC1

COMPC

VBAT

Vbat

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

Figure 24. Reverse Battery Protection Option 1 for Buck Boost Configuration

Figure 25. Reverse Battery Protection Option 2 for Buck Boost Configuration

Undervoltage Lockout and Overvoltage Protection

The TPS43330-Q1 and TPS43332-Q1 start up at a VIN voltage of 6.5 V (minimum), required for the internal

supply (VREG). Once it has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage

level, the undervoltage lockout disables the device. Note: if Vin drops, VREG drops as well; hence, the gate-drive

voltage is reduced, whereas the digital logic is fully functional. Note as well, even if ENC is high, the boost

requires the unlock-voltage of typically 8.5 V to be exceeded once, before it can be activated (see the Boost

Controller section herein). A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the

device. In order to prevent transient spikes from shutting down the device, the under- and overvoltage protection

have filter times of 5 µs (typical).

When the voltages return to the normal operating region, the enabled switching regulators start including a new

soft-start ramp for the buck regulators.

When the boost controller is enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage

lockout and pulls the boost gate driver (GC1) low (this action has a filter delay of 5 µs, typical). As a result, VIN

falls at a rate dependent on its capacitor and load, eventually triggering VIN undervoltage. A short falling

transient at VBAT even lower than 2 V can thus be survived, if VBAT returns above 2.5 V before VIN is

discharged to the undervoltage threshold.

Thermal Protection

The TPS43330-Q1 or TPS43332-Q1 protects itself from overheating using an internal thermal shutdown circuit. If

the die temperature exceeds the thermal shutdown threshold of 165ºC due to excessive power dissipation (for

example, due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers are turned

off and restarted when the temperature has fallen by 15ºC.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

COMPx

VIN

VREF

10 V

12 V

C 1

C 2

RESR

OTA-gmEA

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

APPLICATION INFORMATION

The following example illustrates the design process and component selection for the TPS43330. The design

goal parameters are given in Table 3.

Table 3. Application Example

PARAMETER VBUCK A VBUCK B BOOST

VIN 6 V to 30 V VIN 6 V to 30 V VBAT - 5 V (cranking

Input voltage 12 V - typical 12 V - typical pulse input) to 30 V

Output voltage, VO5 V 3.3 V 10 V

Maximum output current, IO3 A 2 A 2.5 A

Load step output tolerance, ∆VO±0.2 V ±0.12 V ±0.5 V

Current output load step, ∆IO0.1 A to 3 A 0.1 A to 2 A 0.1 A to 2.5 A

Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

This is a starting point and theoretical representation of the values to be used for the application, further

optimization of the components derived may be required to improve the performance of the device.

Boost Component Selection

A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in its

transfer function. The RHP zero is inversely related to the load current and inductor value and directly related to

the input voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the

bandwidth is too close to the RHP zero frequency, the regulator may become unstable.

Thus, for high-power systems with low input voltages, a low inductor value is chosen. This increases the

amplitude of the ripple currents in the N-channel MOSFET, the inductor, and the capacitors for the boost

regulator. They must be designed with the ripple-to-RHP zero trade-off in mind and considering the power

dissipation effects in the components due to parasitic series resistance.

A boost converter that operates in the discontinuous mode does not contain the RHP zero in its transfer function.

However, this needs an even lower inductor value and has high ripple currents. Also, ensure that the regulator

never enters the continuous-conduction mode; otherwise, it may become unstable.

Figure 26. Boost Compensation Components

This design is done assuming continuous-conduction mode. During light load conditions, the boost converter

operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for

stability.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

SENSE

0.2 V

R 25 m

7.85 A

= = W

RIPPLE

PEAK INmax

I3.1 A

I I 6.3 A + 7.85 A

2 2

= + = =

max max

54.9 H

2 2.52 2 200

BAT ON BAT

IN IN SW

V T V V

I I f A kHz m

= = =

* * * *

BAT

INmax (at V = 5 V) 31.3 W

I 6.3 A

5 V

OUT

INmax

P25 W

P 31.3 W

Efficiency 0.8

= = =

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

Boost Maximum Input Current IIN_MAX

The maximum input current is drawn at the minimum input voltage and maximum load. The efficiency for VBAT =

5 V at 2.5 A is 80%, based on the typical characteristics plot.

Hence,

Boost Inductor Selection, L

Allow input ripple current of 40% of IIN max at VBAT = 5 V.

Choose a lower value of 4 µH in order to ensure a high RHP-zero frequency while making a compromise that

expects a high current ripple. Also, this can make the boost converter operate in discontinuous conduction mode,

where it is easier to compensate.

The inductor saturation current must be higher than the peak inductor current and some percentage higher than

the maximum current-limit value set by the external sensing resistive element.

This rating should be determined at the minimum input voltage, maximum output current, and maximum core

temperature for the application.

Inductor Ripple Current, IRIPPLE

Based on an inductor value of 4 µH, the ripple current is approximately 3.1 A.

Peak Current in Low-Side FET, IPEAK

Based on this peak current value, the external current-sense resistor RSENSE is calculated.

Select 20 mΩ, allowing for tolerance.

The filter component values RIFLT and CIFLT for current sense are 1.5 kΩand 1 nF, respectively. This allows for

good noise immunity.

Right Half-Plane Zero RHP Frequency, fRHP

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

ESR ESR

O ESR

ESR

f Hz, assume R = 40 m

2 C R

f 6 kHz

2 660 F 0.04

1 1

f 3.1 kHz

2 L C 2 4 H 660 F

= =

= W

p ´ ´

p ´ m ´ W

p ´ ´ p ´ m ´ m

RHP

BAT min

INmax

BAT min

O min

4 H

2 I L

2 L C

10 I 10 6.3 A

C L

V 5 V

C 635 F

³ ´ m

£p´ ´

p´ ´

æ ö

´æ ö

ç ÷ ´ = ç ÷

ç ÷ è ø

è ø

³ m

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

Output Capacitor, CO

To ensure stability, output capacitor COis chosen such that

Select CO= 680 µF.

This capacitor is usually aluminum electrolytic with ESR in the tens of milliohms. This is good for loop stability,

because it provides a phase boost due to the ESR. The output filter components, L and C, create a double pole

(180-degree phase shift) at a frequency fLC and the ESR of the output capacitor RESR creates a zero for the

modulator at frequency fESR. These frequencies can be determined by the following:

This satisfies fLC ≤0.1 fRHP.

Bandwidth of Boost Converter, fC

Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between

stability and transient response:

fLC < fESR< fC< fRHP Zero

fC< fRHP Zero / 3

fC< fSW / 6

fLC < fC/ 3

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

RIPPLE

SW IN

RIPPLE

SW C1

ESR RIPPLE ESR

V 10 mV

8 f C

C 194-μF

8 f V

V I R 40 mV

D = =

´ ´

= =

´ ´ D

D = ´ =

G/20

6 2

R3 7.2 k

85 10 A / V V

10 10

C1 22 nF

2 f R3 2 10 kHz 7.2 k

C1 22 nF

C2 223 pF

f 200 kHz

2 7.2 k 22 nF 1

2 R3 C1 1 2

= = W

´ ´

= = =

p ´ ´ p ´ ´ W

= = =

æ ö æ ö

p ´ W ´ ´ -

p ´ ´ ´ - ç ÷

ç ÷ è ø

è ø

C C

LC ESR

10 kHz 10 kHz

G 40 log 20 log

3.1 kHz 6 kHz

f f

G 40 log 20 log

f f

15.9 dB= -

æ ö æ ö

= ç ÷ - ç ÷

ç ÷

ç ÷ è ø

è ø

æ ö æ ö =

ç ÷ ç ÷

è ø è ø

O ESR O

O C

V R I

4 C f

2.5 A

0.04 2.5 A 0.19 V

4 660 F 10 kHz

+D = ´ D ´ ´

= W ´ + =

´ m ´

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

Output Ripple Voltage Due to Load Transients, ∆VO

Assume a bandwidth of fC= 10 kHz.

Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters

are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases,

smaller component choices for the boost output may be used.

Selection of Components for Type II Compensation

The required loop gain for unity-gain bandwidth (UGB) is

The boost-converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage. This allows a

constant loop response across the input-voltage range and makes it easier to compensate by removing the

dependency on VBAT.

Input Capacitor, CIN

The input ripple required is lower than 50 mV.

Therefore, our recommendation is 220 µF with 10-mΩESR.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

ON min

IN max SW

V3.3 V

t 275 ns

V f 30 V 400 kHz

= = =

´ ´

I Pk

BOOSTFET Pk DS(on) r f SW

BOOSTFET

V I

P (I ) r (1 TC) D (t t ) f

P (7.85 A) 0.02 (1 0.4) 0.53 (20 ns 20 ns) 200 kHz 1.07 W

´ ´ ´ ´ ´

æ ö

= ´ + ´ + ´ + ´

ç ÷

è ø

æ ö

= W + + + =

ç ÷

è ø

D D(PEAK) F

INMIN

out F

P I V (1 D)

V5 V

D 1 1 0.53

V V 10 V 0.6 V

P 7.85 A 0.6 V (1 0.53) 2.2 W

= ´ ´ -

= - = - =

+ +

= ´ ´ - =

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

Output Schottky Diode D1 Selection

A Schottky diode with low forward conducting voltage VFover temperature and fast switching characteristics is

required to maximize efficiency. The reverse breakdown voltage should be higher than the maximum input

voltage, and the component should have low reverse leakage current. Additionally, the peak forward current

should be higher than the peak inductor current. The power dissipation in the Schottky diode is given by:

Because this is activated for the low-input-voltage profile related to the crank pulse, the duration is less than

25 ms.

Low-Side MOSFET (BOT_SW3)

The times trand tfdenote the rising and falling times of the switching node and are related to the gate-driver

strength of the TPS43330/2 and gate Miller capacitance of the MOSFET. The first term denotes the conduction

losses which are minimized when the on-resistance of the MOSFET is low. The second term denotes the

transition losses which arise due to the full application of the input voltage across the drain-source of the

MOSFET as it turns on or off. They are higher at high output currents and low input voltages (due to the large

input peak current) and when the switching time is low.

Note: The on-resistance, rDS(on), has a positive temperature coefficient, which produces the (TC = d × ΔT) term

that signifies the temperature dependence. (Temperature coefficient d is available as a normalized value from

MOSFET data sheets and can be assumed to be 0.005 / °C as a starting value.)

BuckA Component Selection

Minimum On-Time, tON min

This is higher than the minimum duty cycle specified (100 ns typical). Hence, the minimum duty cycle is

achievable at this frequency.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

Current-Sense Resistor RSENSE

Based on the typical characteristics for the VSENSE limit with VIN versus duty cycle, the sense limit is

approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple

currents, choose VSENSE maximum of 50 mV.

Select 15 mΩ.

Inductor Selection L

As explained in the description of the buck controllers, for optimal slope compensation and loop response, the

inductor should be chosen such that:

KFLR = coil-selection constant = 200

Choose a standard value of 8.2 µH. For the buck converter, the inductor saturation currents and core should be

chosen to sustain the maximum currents.

Inductor Ripple Current IRIPPLE

At the nominal input voltage of 12 V, this gives a ripple current of 30% of IO max ≈1 A.

Output Capacitor CO

Select an output capacitance COof 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(Ripple) ≈15 mV

and a ∆V drop of ≈180 mV during a load step, which does not trigger the power-good comparator and is within

the required limits.

Bandwidth of Buck Converter fC

Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between

stability and transient response.

• Crossover frequency fCbetween fSW / 6 and fSW / 10. Assume fC= 50 kHz.

• Select the zero fz≈fC/ 10

• Make the second pole fP2 ≈fSW / 2

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

CFB REF

BUCK

CO O

Gm R3 K V

f2 C V

1mS 24 k 8.33 S 0.8 V

f2 100 μF 5 V 50.9 kHz

´ ´

p ´

´ W ´ ´

p ´ ´

10 10

C1 1.33 nF

2 R3 f 2 24 k 50 kHz

= = =

p ´ ´ p ´ W ´

C O O

BUCK CFB REF BUCK CFB REF

2 f V C 2 50 kHz 5 V 100μF

R3 23.57 k

Gm K V Gm K V

p ´ ´ ´ p ´ ´ ´

= = = W

´ ´ ´ ´

Vref

RLCOMP

VSENSE

Type 2A

GmBUCK

RESR

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

Selection of Components for Type II Compensation

Figure 27. Buck Compensation Components

where VO=5V,CO= 100 µF, GmBUCK = 1 mS, VREF = 0.8 V, KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an

internal constant)

Use the standard value of R3 = 24 kΩ.

Use standard value of 1.5 nF.

The resulting bandwidth of buck converter fC

This is close to the target bandwidth of 50 kHz.

The resulting zero frequency fZ1

This is close to the fC/ 10 guideline of 5 kHz.

The second pole frequency fP2

This is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

2 R3 C1

1.1nF 27 pF

2 30 k 1.1 nF

400 kHz 1

p ´ ´ ´

= =

p ´ W ´ ´

æ ö -

ç ÷

è ø

æ ö -

ç ÷

è ø

10 10

C1 1.1 nF

2 R3 f 2 30 k 50 kHz

= = =

p ´ ´ p ´ W ´

C O O

BUCK CFB REF

2 f V C

Gm K V

2 50 kHz 3.3 V 100 F

1 mS 4.16 S 0.8 V

31k

p ´ ´ ´

=´ ´

p ´ ´ ´ m

´ ´

= = W

ON min

IN max SW

V3.3 V

t 275 ns

V f 30 V 400 kHz

= = =

´ ´

REF

V0.8 V 0.16

V 5 V

b = = =

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

Resistor Divider Selection for Setting VOVoltage

Choose the divider current through R1 and R2 to be 50 µA. Then

And

Therefore, R2 = 16 kΩand R1 = 84 kΩ.

BuckB Component Selection

Using the same method as for VBUCKA, the following parameters and components are realized.

This is higher than the min duty cycle specified (100 ns typical).

∆Iripple current ≈0.4 A (approx. 20% of IO max)

Select an output capacitance COof 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(ripple) ≈7.5 mV

and ∆V drop of ≈120 mV during a load step.

Assume fC= 50 kHz.

Use standard value of R3 = 30 kΩ.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

REF

V0.8 V

V 3.3 V

0.242b = = =

1 1

f2 R3 C2 2 30 k 27 pF 196 kHz=

p ´ ´ p ´ W ´

= =

1 1

f 4.8 kHz

2 R3 C1 2 30 k 1.1 nF

= = =

p ´ ´ p ´ W ´

BUCK CFB REF

O O

Gm R3 K V

f2 C V

1mS 30 k 4.16 S 0.8 V 48 kHz

2 100 μF 3.3 V

´ ´

p ´

´ W ´ ´

= =

p ´ ´

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

This is close to the target bandwidth of 50 kHz.

The resulting zero frequency fZ1

This is close to the fCguideline of 5 kHz.

The second pole frequency fP2

This is close to the fSW / 2 guideline of 200 kHz.

Hence, all requirements for a good loop response are satisfied.

Resistor Divider Selection for Setting VOVoltage

Choose the divider current through R1 and R2 to be 50 µA. Then

And

Therefore, R2 = 16 kΩand R1 = 50 kΩ.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

buckLOWERFET O DS(on) F O d SW

P (I ) r (1 TC) (1 D) V I (2 t ) f= ´ + ´ - + ´ ´ ´ ´

2I O

BuckTOPFET O DS(on) r f SW

V I

P (I ) r (1 TC) D (t t ) f

æ ö

= ´ + ´ + ´ + ´

ç ÷

è ø

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

BuckX High-Side and Low-Side N-Channel MOSFETs

The gate-drive supply for these MOSFETs is supplied by an internal supply, which is 5.8 V typical under normal

operating conditions. The output is a totem pole, allowing full voltage drive of VREG to the gate with peak output

current of 1.2 A. The high-side MOSFET is referenced to a floating node at the phase terminal (PHx), and the

low-side MOSFET is referenced to the power-ground (PGx) terminal. For a particular application, these

MOSFETs should be selected with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-

source breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.

The times trand tfdenote the rising and falling times of the switching node and are related to the gate-driver

strength of the TPS43330-Q1 and TPS43332-Q1, and the gate Miller capacitance of the MOSFET. The first term

denotes the conduction losses, which are minimized when the on-resistance of the MOSFET is low. The second

term denotes the transition losses, which arise due to the full application of the input voltage across the drain-

source of the MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.

In addition, during the dead time tdwhen both the MOSFETs are off, the body diode of the low-side MOSFET

conducts, increasing the losses. This is denoted by the second term in the above equation. Using external

Schottky diodes in parallel with the low-side MOSFETs of the buck converters helps to reduce this loss.

Note: rDS(on) has a positive temperature coefficient, which is accounted for in the TC term for rDS(on). TC = d ×

ΔT[°C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and can be

assumed to be 0.005 / ºC as a starting value.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

VBAT

TPS43330-Q1

TPS43332-Q1

2.5V to 40V

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC SYNC

DLYAB

AGND

PGB

SSB

COMPB

FBB

SB2

SB1

PGNDB

GB2

PHB

GB1

CBB

VREG

DIV

EXTSUP

VIN

3.9µH

0.1µF

3.3µF

10nF

1nF

5kΩ5kΩ

100µF

COUTB

15µH

0.03Ω VBUCKB –3.3V, 6.6W

8.2µH

10µF 680µF

COUT1

100µF

COUTA

VBUCKA - 5V, 15W 0.015Ω

7.2kΩ

22nF

220pF

24kΩ

1.5nF

33pF 30kΩ 1.1nF 27pF

16kΩ

50kΩ

16kΩ

84kΩ

TOP-SW1

BOT-SW1 BOT-SW2

TOP-SW2

TOP-SW3

BOT-SW3

220µF

1kΩ

L2 L3

0.02Ω

BOOST 10V, 25W

1.5kΩ

1nF

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

Schematics

The following section summarizes the previously calculated example and gives schematic and component

proposals.

Table 4. Application Example 1

PARAMETER VBUCK A VBUCK B BOOST

VIN 6 V to 30 V VIN 6 V to 30 V VBAT - 5 V (cranking

Input voltage 12 V - typical 12 V - typical pulse input) to 30 V

Output voltage, VO5 V 3.3 V 10 V

Maximum output current, IO3 A 2 A 2.5 A

Load step output tolerance, ∆VO±0.2 V ±0.12 V ±0.5 V

Current output load step, ∆IO0.1 A to 3 A 0.1 A to 2 A 0.1 A to 2.5 A

Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

Figure 28. Simplified Application Schematic, Example 1

Table 5. Application Example 1 – Component Proposals

Name Component Proposal Value

L1 MSS1278T-392NL (Coilcraft) 4 µH

L2 MSS1278T-822ML (Coilcraft) 8.2 µH

L3 MSS1278T-153ML (Coilcraft) 15 µH

D1 SK103 (Micro Commercial Components)

TOP_SW3 IRF7416 (International Rectifier)

TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW3 IRFR3504ZTRPBF (International Rectifier)

COUT1 EEVFK1J681M (Panasonic) 680 µF

COUTA, COUTB ECASD91A107M010K00 (Murata) 100 µF

CIN EEEFK1V331P (Panasonic) 220 µF

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

VBAT

TPS43330-Q1

TPS43332-Q1

5V to 30V

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC SYNC

DLYAB

AGND

PGB

SSB

COMPB

FBB

SB2

SB1

PGNDB

GB2

PHB

GB1

CBB

VREG

DIV

EXTSUP

VIN

3.9µH

0.1µF

3.3µF

10nF

1nF

5kΩ5kΩ

330µF

COUTB

6.8µH

0.01Ω VBUCKB –3.3V, 16.5W

10µH

10µF 1.5mF

COUT1

150µF

COUTA

VBUCKA - 5V, 13.5W 0.015Ω

6.2kΩ

47nF

330pF

24kΩ

1.8nF

47pF 27kΩ 1.5nF 47pF

16kΩ

50kΩ

16kΩ

84kΩ

TOP-SW1

BOT-SW1 BOT-SW2

TOP-SW2

TOP-SW3

BOT-SW3

330µF

1kΩ

L2 L3

0.015Ω

BOOST 10V, 25W

1.5kΩ

560pF

80kΩ

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

Table 6. Application Example 2

PARAMETER VBUCK A VBUCK B BOOST

VIN 5 V to 30 V VIN 6 V to 30 V VBAT - 5 V (cranking

Input voltage 12 V - typical 12 V - typ pulse input) to 30V

Output voltage, VO5 V 3.3 V 10 V

Maximum output current, IO2.7 A 5 A 3 A

Load step output tolerance, ∆VO±0.2 V ±0.12 V ±0.5 V

Current output load step, ∆IO0.1 A to 2.7 A 0.1 A to 5 A 0.1 A to 3 A

Converter switching frequency, fSW 300 kHz 300 kHz 150 kHz

Figure 29. Simplified Application Schematic, Example 2

Table 7. Application Example 2 – Component Proposals

Name Component Proposal Value

L1 MSS1278T-392NL (Coilcraft) 3.9 µH

L2 MSS1278T-103ML (Coilcraft) 10 µH

L3 MSS1278T-682ML (Coilcraft) 6.8 µH

D1 SK103 (Micro Commercial Components)

TOP_SW3 IRF7416 (International Rectifier)

TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW3 IRFR3504ZTRPBF (International Rectifier)

COUT1 EEVFK1V152M (Panasonic) 1.5 mF

COUTA ECASD91A157M010K00 (Murata) 150 µF

COUTB ECASD90G337M008K00 (Murata) 330 µF

CIN EEEFK1V331P (Panasonic) 330 µF

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

VBAT

TPS43330-Q1

TPS43332-Q1

5V to 30V

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC SYNC

DLYAB

AGND

PGB

SSB

COMPB

FBB

SB2

SB1

PGNDB

GB2

PHB

GB1

CBB

VREG

DIV

EXTSUP

VIN

3.9µH

0.1µF

3.3µF

10nF

1nF

5kΩ5kΩ

100µF

COUTB

22µH

0.045Ω VBUCKB –3.3V, 16.5W

10µH

10µF 470µF

COUT1

150µF

COUTA

VBUCKA - 5V, 15W 0.015Ω

8.2kΩ

18nF

220pF

39kΩ

1nF

20pF 36kΩ 1nF 47pF

16kΩ

34kΩ

16kΩ

84kΩ

TOP-SW1

BOT-SW1 BOT-SW2

TOP-SW2

TOP-SW3

BOT-SW3

330µF

1kΩ

L2 L3

0.03Ω

BOOST 10V, 20W

1.5kΩ

470pF

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

Table 8. Application Example 3

PARAMETER VBUCK A VBUCK B BOOST

VIN 5 V to 30 V VIN 6 V to 30 V VBAT - 5 V (cranking

Input voltage 12 V - typical 12 V - typical pulse input) to 30 V

Output voltage, VO5 V 2.5 V 10 V

Maximum output current, IO3 A 1 A 2 A

Load step output tolerance, ∆VO±0.2 V ±0.12 V ±0.5 V

Current output load step, ∆IO0.1 A to 3 A 0.1 A to 1 A 0.1 A to 2 A

Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

Figure 30. Simplified Application Schematic, Example 3

Table 9. Application Example 3 – Component Proposals

Name Component Proposal Value

L1 MSS1278T-392NL (Coilcraft) 3.9 µH

L2 MSS1278T-822ML (Coilcraft) 8.2 µH

L3 MSS1278T-223ML (Coilcraft) 22 µH

D1 SK103 (Micro Commercial Components)

TOP_SW3 IRF7416 (International Rectifier)

TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW3 IRFR3504ZTRPBF (International Rectifier)

COUT1 EEVFK1V471Q (Panasonic) 470 µF

COUTA ECASD91A157M010K00 (Murata) 150 µF

COUTB ECASD40J107M015K00 (Murata) 100 µF

CIN EEEFK1V331P (Panasonic) 330 µF

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82C –MARCH 2011–REVISED JULY 2012

Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package

Figure 31. Power Dissipation Derating Profile Based on High-K JEDEC PCB

PCB Layout Guidelines

Grounding and PCB Circuit Layout Considerations

Boost converter

1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low side-current sense-

resistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to

Schottky diode D1 to the COUT1 capacitor. The negative terminal of the input capacitor and the negative

terminal of the sense resistor must be connected together with short trace lengths.

2. The overcurrent-sensing shunt resistor may require noise filtering, and this capacitor should be close to the

IC pin.

Buck Converter

1. Connect the drain of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor COUT1.

The trace length between these terminals should be short.

2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx.

3. The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel

with each other. Any filtering capacitors for noise should be placed near the IC pins.

4. The resistor divider for sensing the output voltage is connected between the positive terminal of its respective

output capacitor and COUTA or COUTB and the IC signal ground. These components and the traces should

not be routed near any switching nodes or high-current traces.

Other Considerations

1. PGNDx and AGND should be shorted to the thermal pad. Use a star ground configuration if connecting to a

non-ground plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and

voltage-sense feedback ground networks to this star ground.

2. Connect a compensation network between the compensation pins and IC signal ground. Connect the

oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits

should NOT be located near the dv/dt nodes; these include the gate-drive outputs, phase pins, and boost

circuits (bootstrap).

3. Reduce the surface area of the high-current-carrying loops to a minimum, by ensuring optimal component

placement. Ensure the bypass capacitors are located as close as possible to their respective power and

ground pins.

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC

V IN

EXTSUP

D IV

VREG

CBB

GB1

PHB

GB2

PGNDB

SB1

SB2

FBB

COMPB

SSB

PGB

AGND

DLYAB

SYNC

VBUCKA

VBUCKB

POW ER

INPUT

VBOOST

Exposed Pad

connec ted to GND

P lane

M ic ro con tro ller

Pow er L ines

Connec tion to GND P lane o f PCB th rough v ias

Connec tion to top /bo ttom o fPCB through v ias

Vo ltage Ra ilO u tpu ts

TPS43330-Q1

TPS43332-Q1

SLVSA82C –MARCH 2011–REVISED JULY 2012

www.ti.com

PCB Layout

REVISION HISTORY

Changes from Revision B (July 2012) to Revision C Page

• Corrected year of revision date from 2011 to 2012 .............................................................................................................. 1

Product Folder Link(s): TPS43330-Q1 TPS43332-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 23-Jul-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TPS43330QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TPS43332QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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