TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 LOW IQ, SINGLE BOOST, DUAL SYNCHRONOUS BUCK CONTROLLER Check for Samples: TPS43330-Q1, TPS43332-Q1 FEATURES 1 * * 2 * * * * * * * * Qualified for Automotive Applications AEC-Q100 Test Guidance With the Following Results: - Device Temperature Grade 1: -40C to 125C Ambient Operating Temperature - Device HBM ESD Classification Level H2 - Device CDM ESD Classification Level C2 Two Synchronous Buck Controllers One Pre-Boost Controller Input Range up to 40 V, (Transients up to 60 V), Operation Down to 2 V When Boost is Enabled Low Power Mode IQ: 30 A (One Buck On), 35 A (Two Bucks On) Low Shutdown Current Ish < 4 A Buck Output Range 0.9 V to 11 V Boost Output Selectable: 7 V, 10 V, or 11 V Programmable frequency and External Synchronization Range 150 kHz to 600 kHz * * * * * * * Separate Enable Inputs (ENA, ENB) Frequency Spread Spectrum (TPS43332) Selectable Forced Continuous Mode or Automatic Low-Power Mode at Light Loads Sense Resistor or Inductor DCR Sensing Out-of-Phase Switching Between Buck Channels Peak Gate-Drive Current 1.5 A Thermally Enhanced 38-Pin HTSSOP (DAP) PowerPADTM Package APPLICATIONS * * Automotive Start-Stop, Infotainment, Navigation Instrument Cluster Systems Industrial and Automotive Multi-Rail DC Power Distribution Systems and Electronic Control Units DESCRIPTION The TPS43330-Q1 and TPS43332-Q1 include two current-mode synchronous buck controllers and a voltagemode boost controller. The devices are ideally suited as a pre-regulator stage with low Iq requirements and for applications that must survive supply drops due to cranking events. The integrated boost controller allows the devices to operate down to 2 V at the input without seeing a drop on the buck regulator output stages. At light loads, the buck controllers can be enabled to operate automatically in low-power mode, consuming just 30 A of quiescent current. The buck controllers have independent soft-start capability and power-good indicators. External MOSFET protection is provided by current foldback in the buck controllers and cycle-by-cycle current limitation in the boost controller. The switching frequency can be programmed over 150 kHz to 600 kHz or synchronized to an external clock in the same range. Additionally, the TPS43332-Q1 offers frequency-hopping spread-spectrum operation. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2012, Texas Instruments Incorporated TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com VBAT V BUCK A VBuckA V BA T TPS43330/2 VB U CK B VBuckB 2V Figure 1. Typical Application Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TJ -40C to 150C (1) (2) 2 OPTION Frequency-hopping spread spectrum OFF Frequency-hopping spread spectrum ON PACKAGE (2) DAP ORDERABLE PART NUMBER TPS43330QDAPRQ1 TPS43332QDAPRQ1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 space ABSOLUTE MAXIMUM RATINGS (1) Voltage MIN MAX Input voltage: VIN, VBAT -0.3 60 V Enable inputs: ENA, ENB -0.3 60 V Bootstrap inputs: CBA, CBB -0.3 68 V Phase inputs: PHA, PHB -0.7 60 V -1 60 V Feedback inputs: FBA, FBB -0.3 13 V Error amplifier outputs: COMPA, COMPB -0.3 13 V High-side MOSFET driver: GA1-PHA, GB1-PHB -0.3 8.8 V Low-side MOSFET drivers: GA2, GB2 -0.3 8.8 V Current-sense voltage: SA1, SA2, SB1, SB2 -0.3 13 V Soft start: SSA, SSB -0.3 13 V Power-good output: PGA, PGB -0.3 13 V Power-good delay: DLYAB -0.3 13 V Switching-frequency timing resistor: RT -0.3 13 V SYNC, EXTSUP -0.3 13 V Low-side MOSFET driver: GC1 -0.3 8.8 V Error-amplifier output: COMPC -0.3 13 V Enable input: ENC -0.3 13 V Current-limit sense: DS -0.3 60 V Output-voltage select: DIV -0.3 8.8 V P-channel MOSFET driver: GC2 -0.3 60 V P-channel MOSFET driver: VIN-GC2 -0.3 8.8 V Gate-driver supply: VREG -0.3 8.8 V Junction temperature: TJ -40 150 C Operating temperature: TA -40 125 C Storage temperature: Tstg -55 165 C Phase inputs: PHA, PHB (for 150 ns) Voltage (buck function: BuckA and BuckB) Voltage (boost function) Voltage (PMOS driver) Temperature Human-body model (HBM) AEC-Q11 Classification Level H2 Electrostatic discharge ratings Charged-device model (CDM) AEC-Q11 Classification Level C2 Machine model (MM) (1) 2 FBA, FBB, RT, DLYAB 400 VBAT, ENC, SYNC, VIN 750 All other pins 500 PGA, PGB 150 All other pins 200 UNIT kV V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 3 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com THERMAL INFORMATION TPS4333x-Q1 THERMAL METRIC (1) DAP UNIT 38 PINS Junction-to-ambient thermal resistance (2) JA 27.3 (3) JCtop Junction-to-case (top) thermal resistance JB Junction-to-board thermal resistance (4) 15.9 JT Junction-to-top characterization parameter (5) 0.24 JB Junction-to-board characterization parameter (6) 6.6 JCbot Junction-to-case (bottom) thermal resistance (7) 1.2 (1) (2) (3) (4) (5) (6) (7) 19.6 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS Buck function: BuckA and BuckB voltage Boost function MIN MAX Input voltage: VIN, VBAT 4 40 Enable inputs: ENA, ENB 0 40 Boot inputs: CBA, CBB 4 48 -0.6 40 Current-sense voltage: SA1, SA2, SB1, SB2 0 11 Power-good output: PGA, PGB 0 11 SYNC, EXTSUP 0 9 Enable input: ENC 0 9 0 VREG -40 125 Phase inputs: PHA, PHB Voltage sense: DS 40 DIV Operating temperature: TA 4 Submit Documentation Feedback UNIT V V C Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 DC ELECTRICAL CHARACTERISTICS VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. PARAMETER 1.0 Input Supply 1.1 VBat 1.2 1.3 1.4 MIN Boost controller enabled, after initial start-up condition is satisfied Supply voltage Input voltage required for device on initial start-up VIN VIN TEST CONDITIONS VBOOST_UNLOC Buck undervoltage lockout Boost unlock threshold MAX 2 40 6.5 40 4 40 UNIT V V Buck regulator operating range after initial start-up UV TYP VIN falling. After a reset, initial start-up conditions may apply. (1) 3.5 VIN rising. After a reset, initial start-up conditions may apply. (1) VBAT rising 8.2 3.6 3.8 V 3.8 4 V 8.5 8.8 V 30 40 A 35 45 A 40 50 A 45 55 A 4.85 5.3 7 7.6 5 5.5 K VIN = 13 V, BuckA: LPM, BuckB: off, TA = 25C 1.5 Iq_LPM_ LPM quiescent current: (2) VIN = 13 V, BuckB: LPM, BuckA: off, TA = 25C VIN = 13 V, BuckA, B: LPM, TA = 25C VIN = 13 V, BuckA: LPM, BuckB: off, TA = 125C 1.6 Iq_LPM LPM quiescent current: (2) VIN = 13 V, BuckB: LPM, BuckA: off, TA = 125C VIN = 13 V, BuckA, B: LPM, TA = 125C SYNC = 5 V, TA = 25C 1.7 Iq_NRM Quiescent current: normal (PWM) mode (2) VIN = 13 V, BuckA: CCM, BuckB: off, TA = 25C VIN = 13 V, BuckB: CCM, BuckA: off, TA = 25C VIN = 13 V, BuckA, B: CCM, TA = 25C mA SYNC = 5 V, TA = 125C Iq_NRM Quiescent current: normal (PWM) mode (2) VIN = 13 V, BuckA, B: CCM, TA = 125C 7.5 8 1.9 Ibat_sh Shutdown current BuckA, B: off, VBat = 13 V , TA = 25C 2.5 4 A 1.10 Ibat_sh Shutdown current BuckA, B: off, VBat = 13 V, TA = 125C 3 5 A 2.0 Input Voltage VBAT - Undervoltage Lockout 2.1 (1) (2) VIN = 13 V, BuckA: CCM, BuckB: off, TA = 125C 1.8 VBATUV Boost-input undervoltage 2.2 UVLOHys Hysteresis 2.3 UVLOfilter Filter time 3.0 Input Voltage VIN - Overvoltage Lockout 3.1 VOVLO Overvoltage shutdown 3.2 OVLOHys Hysteresis 3.3 OVLOfilter Filter time VIN = 13 V, BuckB: CCM, BuckA: off, TA = 125C mA VBAT falling. After a reset, initial start-up conditions may apply. (1) 1.8 1.9 2 V VBAT rising. After a reset, initial start-up conditions may apply. (1) 2.4 2.5 2.6 V 500 600 700 mV 5 s VIN rising 45 46 47 VIN falling 43 44 45 1 2 3 5 V V s If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V. Quiescent current specification is non-switching current consumption without including the current in the external-feedback resistor divider. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 5 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. PARAMETER 4.0 Boost Controller 4.1 Vboost7-VIN 4.2 4.3 4.4 Vboost7-th Vboost10-VIN Vboost10-th 4.5 Vboost11-VIN 4.6 Vboost11-th TEST CONDITIONS MIN TYP MAX Boost VOUT = 7 V DIV = low, VBAT = 2 V to 7 V 6.8 7 7.3 Boost-enable threshold Boost VOUT = 7 V, VBAT falling 7.5 8 8.5 Boost-disable threshold Boost VOUT = 7 V, VBAT falling 8 8.5 9 Boost hysteresis Boost VOUT = 7 V, VBAT falling 0.4 0.5 0.6 Boost VOUT = 10 V DIV = open, VBAT = 2 V to 10 V 9.7 10 10.4 Boost-enable threshold Boost VOUT = 10 V, VBAT falling 10.5 11 11.5 Boost-disable threshold Boost VOUT = 10 V, VBAT falling 11 11.5 12 Boost hysteresis Boost VOUT = 10 V, VBAT falling 0.4 0.5 0.6 Boost VOUT = 11 V DIV = VREG, VBAT = 2 V to 11 V 10.7 11 11.4 Boost-enable threshold Boost VOUT = 11 V, VBAT falling 11.5 12 12.5 Boost-disable threshold Boost VOUT = 11 V, VBAT falling 12 12.5 13 Boost hysteresis Boost VOUT = 11 V, VBAT falling 0.4 0.5 0.6 DS input with respect to PGNDA 0.175 0.2 0.225 UNIT V V V V V V Boost-Switch Current Limit 4.7 VDS Current-limit sensing 4.8 tDS Leading-edge blanking 200 V ns Gate Driver for Boost Controller 4.9 IGC1 4.10 rDS(on) Peak Gate-driver peak current Source and sink driver 1.5 VREG = 5.8 V, IGC1 current = 200 mA A 2 Gate Driver for PMOS 4.11 rDS(on) PMOS OFF 4.12 IPMOS_ON Gate current VIN = 13.5 V, Vgs = -5 V 10 4.13 tdelay_ON Turnon delay C = 10 nF 20 10 mA 5 10 s Boost-Controller Switching Frequency 4.14 fsw-Boost Boost switching frequency 4.15 DBoost Boost duty cycle fSW_Buck / 2 kHz 90% Error Amplifier (OTA) for Boost Converters 0.8 1.35 VBAT = 5 V 0.35 0.65 GmBOOST 5.0 Buck Controllers 5.1 VBuckA/B Adjustable output-voltage range 5.2 Vref, NRM Internal reference and tolerance voltage in normal mode Measure FBX pin 5.3 Vref, LPM Internal reference and tolerance voltage in low-power mode Measure FBX pin 5.4 Vsense 5.5 Forward transconductance VBAT = 12 V 4.16 0.9 V sense for reverse-current limit in CCM VI-Foldback V sense for output short tdead Shoot-through delay, blanking time 0.784 DCNRM Maximum duty cycle (digitally controlled) 5.9 DCLPM Duty cycle, LPM ILPM_Entry LPM entry-threshold load current as fraction of maximum set load current ILPM_Exit LPM exit-threshold load current as fraction of maximum set load current 5.10 (3) 6 V V 0.800 0.816 V 2% 60 75 90 mV FBx = 1 V -65 -7.5 -23 mV FBx = 0 V 17 32.5 48 mV High-side minimum on-time 5.8 11 0.808 1% -2% FBx = 0.75 V (low duty cycle) 5.7 0.800 -1% V sense for forward-current limit in CCM 5.6 0.792 mS 20 ns 100 ns 98.75% 80% 1% (3) . (3) 10% The exit threshold is specified to be always higher than the entry threshold. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-Side External NMOS Gate Drivers for Buck Controller 5.11 IGX1_peak Gate-driver peak current 5.12 rDS(on) Source and sink driver 1.5 VVREG = 5.8 V, IGX1 current = 200 mA A 2 2 Low-Side NMOS Gate Drivers for Buck Controller 5.13 IGX2_peak Gate driver peak current 5.14 RDS ON Source and sink driver 1.5 VREG = 5.8 V, IGX2 current = 200 mA A Error Amplifier (OTA) for Buck Converters 5.15 GmBUCK Transconductance COMPA, COMPB = 0.8 V, source/sink = 5 A, test in feedback loop 5.16 IPULLUP_FBx Pullup current at FBx pins 6.0 Digital Inputs: ENA, ENB, ENC, SYNC 6.1 VIH 6.2 VIL 6.3 6.4 0.72 1 1.35 mS FBx = 0 V 50 100 200 nA Higher threshold VIN = 13 V 1.7 Lower threshold VIN = 13 V RIH_SYNC Pulldown resistance on SYNC VSYNC = 5 V 500 k RIL_ENC Pulldown resistance on ENC VENC = 5 V 500 k 6.5 IIL_ENx Pullup current source on ENA, ENB VENx = 0 V, 0.5 7.0 Boost Output Voltage: DIV 7.1 VIH_DIV Higher threshold 7.2 VIL_DIV Lower threshold 7.3 Voz_DIV Voltage on DIV if unconnected 8.0 Switching Parameter - Buck DC-DC Controllers 8.1 fSW_Buck Buck switching frequency RT pin: GND 360 400 440 kHz 8.2 fSW_Buck Buck switching frequency RT pin: 60-k external resistor 360 400 440 kHz 8.3 fSW_adj Buck adjustable range with external resistor RT pin: external resistor 150 600 kHz 8.4 fSYNC Buck synchronization range External clock input 150 600 kHz 8.5 fSS Spread-spectrum spreading TPS4333-Q1 only 9.0 Internal Gate-Driver Supply 5.8 6.1 V 9.1 VREG 0.2% 1% 7.5 7.8 9.2 VREG(EXTSUP) 0.2% 1% 9.3 4.6 4.8 V VREG = 5.8 V V 0.7 2 Vreg - 0.2 A V 0.2 Voltage on DIV if unconnected V Vreg / 2 V V 5% Internal regulated supply VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = high Load regulation IVREG = 0 mA to 100 mA, EXTSUP = 0 V, SYNC = high Internal regulated supply EXTSUP = 8.5 V Load regulation IEXTSUP = 0 mA to 125 mA, SYNC = High EXTSUP = 8.5 V to 13 V VEXTSUP-th EXTSUP switch-over voltage threshold IVREG = 0 mA to 100 mA, EXTSUP ramping positive 9.4 VEXTSUP-Hys EXTSUP switch-over hysteresis 150 250 mV 9.5 IREG-Limit Current limit on VREG EXTSUP = 0 V, normal mode as well as LPM 100 400 mA 9.6 IREG_EXTSUP- Current limit on VREG when using EXTSUP IVREG = 0 mA to 100 mA, EXTSUP = 8.5 V, SYNC = High 125 400 mA Soft-start source current SSA and SSB = 0 V 0.75 1.25 A Limit 10.0 Soft Start 10.1 ISSx 11.0 Oscillator (RT) 11.1 VRT Oscillator reference voltage Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 5.5 7.2 4.4 1 1.2 Submit Documentation Feedback V V 7 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. PARAMETER TEST CONDITIONS 12.0 Power Good / Delay 12.1 PGpullup Pullup for A and B to Sx2 12.2 PGth1 Power-good threshold 12.3 PGhys Hysteresis 12.4 PGdrop Voltage drop -5% -7% MAX UNIT k -9% 2% 12.6 PGleak Power-good leakage 12.7 tdeglitch Power-good deglitch time IPGA = 5 mA 450 mV IPGA = 1 mA 100 mV 1 A 16 s VSx2 = VPGx = 13 V 2 12.8 tdelay Reset delay External capacitor = 1 nF VBUCKX < PGth1 12.9 tdelay_fix Fixed reset delay No external capacitor, pin open 12.10 IOH Activate current source (current to charge external capacitor) 12.11 IIL Activate current sink (current to discharge external capacitor) 13.0 Overtemperature Protection 13.1 Tshutdown Junction-temperature shutdown threshold 13.2 Thys Junction-temperature hysteresis Submit Documentation Feedback TYP 50 FBx falling 12.5 8 MIN 1 ms 20 50 s 30 40 50 A 30 40 50 A 150 165 C 15 C Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 DEVICE INFORMATION DAP PACKAGE (TOP VIEW) VBAT 1 38 DS 2 37 GC1 3 36 DIV GC2 4 35 VREG CBA 5 34 CBB GA1 6 33 GB1 PHA 7 32 PHB GA2 8 31 9 30 SA1 10 29 SB1 SA2 11 28 SB2 FBA 12 27 13 26 SSA 14 25 SSB PGA 15 24 PGB PGNDA COMPA VIN EXTSUP GB2 PGNDB FBB COMPB ENA 16 23 AGND ENB 17 22 RT 18 21 DLYAB 19 20 SYNC COMPC ENC PIN FUNCTIONS NO. I/O AGND NAME 23 O Analog ground reference DESCRIPTION CBA 5 I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge. CBB 34 I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge. COMPA 13 O Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the inductor of BuckA. This voltage is clamped on the upper and lower ends to provide current-limit protection for the external MOSFETs. COMPB 26 O Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the inductor of BuckB. This voltage is clamped on the upper and lower ends to provide current-limit protection for the external MOSFETs. COMPC 18 O Error-amplifier output and loop-compensation node of the boost regulator DIV 36 I The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter at 11 V, a low input sets the value at 7 V, and a floating pin sets 10 V. DLYAB 21 O The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the powergood comparators. When this pin is left open, the power-good delay is set to an internal default value of 20 s typical. DS 2 I This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection. Alternatively, it can be connected to a sense resistor between the source of the low-side MOSFET and ground via a filter network for better noise immunity. ENA 16 I Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.5 V enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device is shut down and consumes less than 4 A of current. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 9 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com PIN FUNCTIONS (continued) NAME ENB NO. 17 I/O DESCRIPTION I Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.5 V enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device is shut down and consumes less than 4 A of current. ENC 19 I This input enables and disables the boost regulator. An input voltage higher than 1.5 V enables the controller. Voltages lower than 0.7 V disable the controller. Because this pin provides and internal pulldown resistor (500 k) it must be pulled high to enable the boost function. When enabled, the controller starts switching as soon as VBAT falls below the boost threshold, depending upon the programmed output voltage. EXTSUP 37 I EXTSUP can be used to supply the VREG regulator from one of the TPS43330/2 buck regulator rails to reduce power dissipation in cases where VIN is expected to be high. When EXTSUP is open or lower than 4.6 V, the regulator is powered from VIN. FBA 12 I Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage. FBB 27 I Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor-divider network between the buck output and the feedback pin sets the desired output voltage. GA1 6 O External high-side N-channel MOSFET for buck regulator BuckA can be driven from this output. The output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference provided by PHA and has a voltage swing provided by CBA. GA2 8 O External low-side N-channel MOSFET for buck regulator BuckA can be driven from this output. The output provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG. GB1 33 O External high-side N-channel MOSFET for buck regulator BuckB can be driven from this output. The output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference provided by PHB and has a voltage swing provided by CBB. GB2 31 O External low-side N-channel MOSFETs for buck regulator BuckB can be driven from this output. The output provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG. GC1 3 O An external low-side N-channel MOSFET for the boost regulator can be driven from this output. This output provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG. GC2 4 O A floating output drive to control the external P-channel MOSFET is available at this pin. This MOSFET can be used to bypass the boost rectifier diode or a reverse protection diode when the boost is not switching or if boost is disabled, and thus reduce power losses. PGA 15 O Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either Vin or Vbat drops below its respective undervoltage threshold. PGB 24 O Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either Vin or Vbat drops below its respective undervoltage threshold. PGNDA 9 O Power ground connection to the source of the low-side N-channel MOSFETs of BuckA. PGNDB 30 O Power ground connection to the source of the low-side N-channel MOSFETs of BuckB PHA 7 O Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gatedriver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired. PHB 32 O Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gatedriver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired. RT 22 O The operating switching frequency of the buck and boost controllers is set by connecting a resistor to ground on this pin. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for the boost controller. SA1 10 I SA2 11 I SB1 29 I SB2 28 I SSA 14 O 10 High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. The current-sense element should be chosen to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN. (SA1 positive node, SA2 negative node). High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. The current-sense element should be chosen to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN. (SB1 positive node, SB2 negative node). Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of 0.8 V or the SSA pin voltage. An internal pullup current source of 1 A is present at the pin, and an appropriate capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected to another supply can also be used to provide a tracking input to this pin. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 PIN FUNCTIONS (continued) NAME SSB NO. 25 I/O DESCRIPTION O Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of 0.8 V or the SSB pin voltage. An internal pullup current source of 1 A is present at the pin, and an appropriate capacitor connected here can be used to set the soft-start ramp interval. A resistor-divider connected to another supply can also be used to provide a tracking input to this pin. SYNC 20 I If an external clock is present on this pin, the device detects it and the internal PLL locks onto the external clock. This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits transition to low-power mode. An open or low allows discontinuous mode operation and entry into low-power mode at light loads. On the TPS43332, a high level enables frequency-hopping spread spectrum, whereas an open or a low level disables it. VBAT 1 I Battery input sense for the boost controller. If the boost controller is enabled and the voltage at VBAT falls below the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed boost output voltage. VIN 38 I Main Input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally, it powers the internal control circuits of the device. O An external capacitor on this pin is required to provide a regulated supply for the gate drivers of the buck and boost controllers. A capacitance in the order of 4.7 F is recommended. The regulator can be used such that it is either powered from VIN or EXTSUP. This pin has current-limit protection and should not be used to drive any other loads. VREG 35 Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 11 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com 38 Internal ref (Band gap) EXTSUP 37 Gate Driver Supply VREG 35 VIN PWM logic VREG Internal Oscillator 22 180 deg RT Duplicate for second Buck controller channel Slope Comp SYNC GC2 SYNC & LPM 20 PWM comp + + 6 GA1 7 PHA 8 GA2 9 PGNDA 10 SA1 11 SA2 12 FBA 13 COMPA 15 PGA 21 DLYAB Current sense Amp + - + OTA + gm - + 0.8V SA2 FBA EN VREF Filter timer 1mA SSA CBA SSA Source/ Sink Logic 4 5 14 ENA VIN VREF 40 mA ENA 500 nA 16 VREF 1mA SSB 25 ENB 17 COMPC 40 mA VIN ENB 500 nA 18 OTA VBAT 1 DIV 36 DS 2 gm + Second Buck Controller Channel Vref OCP 0.2V + - + VIN VREG GC1 3 ENC 19 AGND 23 PGNDA PWM comp PWM Logic 34 CBB 33 GB1 32 PHB 31 GB2 30 PGNDB 29 SB1 28 SB2 27 FBB 26 COMPB 24 PGB Figure 2. Functional Block Diagram 12 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 TYPICAL CHARACTERISTICS EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS) VIN = 12V, VOUT = 5V, SWITCHING FREQUENCY = 400kHz INDUCTOR = 4.7H, RSENSE = 10mW 90 10000 EFFICIENCY, SYNC = LOW 1000 EFFICIENCY (%) 80 70 60 POWER LOSS, SYNC = HIGH 100 50 40 POWER LOSS, SYNC = LOW 30 10 1 20 EFFICIENCY, SYNC = HIGH 10 0 0.0001 POWER LOSS (mW) 100 0.1 0.001 0.01 0.1 1 10 OUTPUT CURRENT (A) Figure 3. Figure 4. SOFT-START OUTPUTS (BUCK) VOUTA VOUTB 1V/DIV 2ms/DIV Figure 5. Figure 6. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 13 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) BUCK LOAD STEP: LOW POWER MODE EXIT (90 mA TO 4 A AT 2.5 A/s) VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz INDUCTOR = 4.7 H, RSENSE = 10 mW 100 mV/DIV VOUT AC-COUPLED 2 A/DIV IIND 50 s/DIV Figure 7. Figure 8. EFFICIENCY ACROSS OUTPUT CURRENTS (BOOST) LOAD STEP RESPONSE (BOOST) (0 TO 5A AT 2.5A/s) VIN (BOOST OUTPUT) = 10V, SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0H, RSENSE = 7.5mW VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V, SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0H, RSENSE = 7.5mW, CIN = 440F, COUT = 660F 100 90 VBAT = 8V EFFICIENCY (%) 80 500mV/DIV 70 VIN (BOOST OUTPUT) AC-COUPLED VBAT = 5V 60 VBAT = 3V 50 40 30 20 5A/DIV 10 IIND 0 0.01 1 OUTPUT CURRENT (A) 10 2ms/DIV Figure 9. Figure 10. CRANKING PULSE BOOST RESPONSE (12V to 3V IN 1ms AT BUCK OUTPUTS 7.5W/11.5W) CRANKING PULSE BOOST RESPONSE (12V to 4V IN 1ms AT BOOST DIRECT OUTPUT 25W) VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A, SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0H, RSENSE = 7.5mOHM, CIN = 440F, COUT = 660F VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A, SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0H, RSENSE = 7.5mOHM, CIN = 440F, COUT = 660F 5V/DIV VBAT (BOOST INPUT) 5V/DIV 0V 0V 200mV/DIV 200mV/DIV 10A/DIV VOUT BUCKA AC-COUPLED VBAT (BOOST INPUT) VIN (BOOST OUTPUT) 5V/DIV VOUT BUCKB AC-COUPLED 0V 10A/DIV IIND 0A 20ms/DIV IIND 0A 20ms/DIV Figure 12. Figure 11. 14 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 TYPICAL CHARACTERISTICS (continued) INDUCTOR CURRENTS (BOOST) VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V, SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0H, RSENSE = 7.5mW, CIN = 440F, COUT = 660F 3A LOAD 5A/DIV 100mA LOAD 5A/DIV 2s/DIV Figure 13. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 15 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) BUCKx PEAK CURRENT LIMIT vs. COMPx VOLTAGE PEAK CURRENT SENSE VOLTAGE (mV) NO-LOAD QUIESCENT CURRENT ACROSS TEMPERATURE Quiescent Current (A) 60 50 BOTH BUCKS ON 40 30 ONE BUCK ON 20 10 NEITHER BUCK ON 0 -40 -15 10 85 35 60 Temperature (C) 110 135 160 75 62.5 50 37.5 25 12.5 SYNC = LOW 0 -12.5 -25 SYNC = HIGH -37.5 0.65 0.8 0.95 FOLDBACK CURRENT LIMIT (BUCK) 150C 25C 3 5 4 6 7 8 9 10 11 12 PEAK CURRENT SENSE VOLTAGE (mV) SENSE CURRENT (A) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 2 80 70 60 50 40 30 20 10 0 0 0.2 OUTPUT VOLTAGE (V) 0.4 Figure 17. CURRENT LIMIT VS DUTY CYCLE (BUCK) PEAK CURRENT SENSE VOLTAGE (mV) REGULATED FBx VOLTAGE vs TEMPERATURE (BUCK) REGULATED FBx VOLTAGE (mV) 805 804 803 802 801 800 799 798 797 796 795 -15 10 35 60 85 110 135 160 80 70 60 VIN = 8V 50 40 VIN = 12V 30 20 10 0 0 10 20 Figure 18. Submit Documentation Feedback 30 40 50 60 70 80 90 100 DUTY CYCLE (%) TEMPERATURE (C) 16 0.8 0.6 FBx VOLTAGE (V) Figure 16. -40 1.55 Figure 15. CURRENT SENSE PINS INPUT CURRENT (BUCK) 1 1.4 COMPx VOLTAGE (V) Figure 14. 0 1.25 1.1 Figure 19. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 DETAILED DESCRIPTION BUCK CONTROLLERS: NORMAL MODE PWM OPERATION Frequency Selection and External Synchronization The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz, depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching frequency to 400 kHz. The frequency can also be set by a resistor at RT, according to the formula: fSW = X (X=24kxMHz) RT fSW =24x 109 RT For example, 600 kHz requires 40 k 150 kHz requires 160 k It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the specified range. The device can also detect a loss of clock at this pin, and when this condition is detected, the device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies, 180 degrees out-of-phase. Enable Inputs The buck controllers are enabled using independent enable inputs from the ENA and ENB pins. These are highvoltage pins, with a threshold of 1.5 V for high level, and can be connected directly to the battery for self-bias. The low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 A (typical). As a result, an open circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device is shut down and consumes a current less than 4 A. Feedback Inputs The output voltage is set by choosing the right resistor feedback divider network connected to the FBx (feedback) pins. Choose this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100nA pullup current source as a protection feature in case the pins open up as a result of physical damage. Soft-Start Inputs In order to avoid large inrush currents, both buck controllers have an independent programmable soft-start timer. The voltage at the SSx pins acts as the soft-start reference voltage. A 1-A pullup current is available at the SSx pins, and by choosing a suitable capacitor, a ramp of the desired soft-start speed can be generated. After startup, the pullup current ensures that SSx is higher than the internal reference of 0.8 V; 0.8 V then becomes the reference for the buck controllers. The soft-start ramp time is defined by: I xt CSS = SS V (Farads) where, ISS = 1 A (typical) V = 0.8 V CSS is the required capacitor for t, the desired soft-start time. Alternatively, the soft-start pins can be used as tracking inputs. In this case, they should be connected to the supply to be tracked via a suitable resistor-divider network. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 17 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com Current-Mode Operation Peak-current-mode control regulates the peak current through the inductor such that the output voltage is maintained to its set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the output of the error amplifier (COMPx) which serves as the target for the peak inductor current. The current through the inductor is sensed as a differential voltage at Sx1-Sx2 and compared with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing COMPx to fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current matches the load. In this way, the output voltage is maintained in regulation. The top N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the inductor current reaches its peak value. Once this MOSFET is turned off, and after a small delay (shoot-through delay) the lower N-channel MOSFET is turned on until the start of the next clock cycle. In dropout operation, the highside MOSFET stays on continuously. In every fourth clock cycle, the duty cycle is limited to 95% in order to charge the bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators. During dropout, the buck regulator switches at one-fourth of its normal frequency. Current Sensing and Current Limit with Foldback The maximum value of COMPx is clamped such that the maximum current through the inductor is limited to a specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value due to a short circuit or overcurrent condition, the clamped voltage at the COMPx successively decreases, thus providing current foldback protection. This protects the high-side external MOSFET from excess current (forwarddirection current limit). Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully on, the COMPx node drops low. It is clamped on the lower end as well, in order to limit the maximum current in the low-side MOSFET (reverse-direction current limit). The current through the inductor is sensed by an external resistor. The sense resistor should be chosen such that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This value is specified at low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5 V output and 12 V input), 50 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics provide a guide for using the correct current-limit sense voltage. The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range. This allows DCR current sensing using the dc resistance of the inductor for higher efficiency. DCR sensing is shown in Figure 20. Here, the series resistance (DCR) of the inductor is used as the sense element. The filter components should be placed close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance. Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing. Inductor L TPS43330/2 VBUCK X DCR R1 C1 Sx2 VC Sx1 Figure 20. DCR Sensing Configuration 18 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 Slope Compensation Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable operation at all conditions. For optimal performance of this circuit, the following condition must be satisfied in the choice of inductor and sense resistor: LxfSW =200 RS where L is the buck regulator inductor in henries. RS is the sense resistor in ohms. fsw is the buck regulator switching frequency in hertz. Power-Good Outputs and Filter Delays Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an opendrain output at the PGx pins. An internal 50-k pullup resistor to Sx2 is available, or an external resistor can be used. When a buck controller is shut down, the power-good indicator is pulled down internally. Connecting the pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow through the resistor when the buck controller is powered down. In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, an internal delay circuit for de-glitching is used. Similarly, when the output voltage returns to its set value after a long negative transient, the power-good indicator is asserted high (the open-drain pin released) after the same delay. This can be used to delay the reset to the circuits being powered from the buck regulator rail. The delay of this circuit can be programmed by using a suitable capacitor at the DLYAB pin according to the equation: tDELAY 1 msec = CDLYAB 1 nF When the DLYAB pin is open, the delay is set to a default value of 20 s typical. The power-good delay timing is common to both the buck rails, but the power-good comparators and indicators function independently. Light-Load PFM Mode An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. When the SYNC pin is low or open, the buck controllers are allowed to operate in discontinuous mode at light loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor current is detected. In discontinuous mode, as the load decreases, the duration of the clock period when both the high-side and lowside MOSFETs are turned off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have been chosen appropriately as recommended in the slope compensation section. In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference. Whenever the FBx value falls below the reference, the high-side MOSFET is turned on for a pulse duration inversely proportional to the difference VIN - Sx2. At the end of this on-time, the high-side MOSFET is turned off and the current in the inductor decays until it becomes zero. The low-side MOSFET is not turned on. The next pulse occurs the next time FBx falls below the reference value. This results in a constant volt-second ton hysteretic operation with a total device quiescent current consumption of 30 A when a single buck channel is active and 35 A when both channels are active. As the load increases, the pulses become more and more frequent and move closer to each other until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher than 80% duty cycle of the high-side MOSFET. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 19 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com The TPS43330-Q1and TPS43332-Q1 an support the full-current load during low-power mode until the transition to normal mode takes place. The design ensures the low-power mode exit occurs at 10% (typical) of full-load current if the inductor and sense resistor have been chosen as recommended. Moreover, there is always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes. In the event that both buck controllers are active, low-power mode is only possible when both buck controllers have light loads that are low enough for low-power mode entry. When the boost controller is enabled, low-power mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to GND. If DIV is high (VREG), low-power mode is inhibited. Boost Controller The boost controller has a fixed-frequency voltage-mode architecture and includes cycle-by-cycle current-limit protection for the external N-channel MOSFET. The switching frequency is derived from and set to one-half of the buck-controller switching frequency. The output voltage of the boost controller at the VIN pin is set by an internal resistor-divider network and is programmable to 7 V, 10 V or 11 V, based on the low, open, or high status, respectively, of the DIV pin. A change of the DIV setting is not recognized while the device is in lowpower mode. The boost controller is enabled by the active-high ENC pin and is active when the input voltage at the VBAT pin has crossed the unlock threshold of 8.5 V at least once. After that, the boost controller is armed and starts switching as soon as VIN falls below the value set by the DIV pin and regulates the VIN voltage. Thus, the boost regulator maintains a stable input voltage for the buck regulators during transient events such as a cranking pulse at VBAT. Whenever the voltage at the DS pin exceeds 200 mV, the boost external MOSFET is turned off by pulling the CG1 pin low. By connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET source and ground, cycle-by-cycle overcurrent protection for the MOSFET can be achieved. The on-resistance of the MOSFET or the value of the sense resistor must be chosen in such a way that the on-state voltage at the DS does not exceed 200 mV at the maximum-load and minimum-input-voltage conditions. When a sense resistor is used , a filter network is recommended to be connected between the DS pin and the sense resistor for better noise immunity. The boost output (VIN) can also be used to supply other circuits in the system. However, they should be highvoltage tolerant. The boost output is regulated to the programmed value only when VIN is low, and so VIN can reach battery levels. Vbat VIN TPS43330/2 DS GC1 Figure 21. External Drain-Source Voltage Sensing 20 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 Vbat VIN TPS43330/2 GC1 DS RIFLT CIFLT RISEN Figure 22. External Current Shunt Resistor Frequency-Hopping Spread Spectrum (TPS43332 Only) The TPS43332 features a frequency-hopping pseudo-random spectrum-spreading architecture. On this device, whenever the SYNC pin is high, the internal oscillator frequency is varied from one cycle to the next within a band of 5% around the value programmed by the resistor at the RT pin. The implementation uses a linearfeedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift register is long enough to make the hops pseudo-random in nature and is designed in such a way that the frequency shifts only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies. Table 1. Frequency-Hopping Control Sync Terminal Frequency Spread Spectrum (FSS) Comments External clock Not active Device in forced continuous mode, internal PLL locks into external clock between 150 kHz and 600 kHz. Low or open Not active Device can enter discontinuous mode. Automatic LPM entry and exit, depending on load conditions TPS43330: FSS not active High Device in forced continuous mode TPS43332: FSS active Table 2. Mode of Operation ENABLE AND INHIBIT PINS ENA ENB ENC Low Low Low Low High High Low Low Low High High Low Low Low Low Low High High SYNC X Low High Low High Low High X Low DRIVER STATUS BUCK CONTROLLERS Shutdown Disabled Buck B running Disabled Buck A running Disabled Low High Low High High Low High QUIESCENT CURRENT Shutdown Approximately 4 A Buck B: LPM enabled Approximately 30 A (light loads) Buck B: LPM inhibited mA range Buck A: LPM enabled Approximately 30 A (light loads) Buck A: LPM inhibited mA range Buck A/B: LPM enabled Approximately 35 A (light loads) Buck A/B: LPM inhibited mA range Disabled Shutdown Disabled Shutdown Approximately 4 A Buck B running Boost running for VIN < set boost output Buck B: LPM enabled Approximately 50 A (no boost, light loads) Buck B: LPM inhibited mA range Boost running for VIN < set boost output Buck A: LPM enabled Approximately 50 A (no boost, light loads) Buck A: LPM inhibited mA range Boost running for VIN < set boost output Buck A/B: LPM enabled Approximately 60 A (no boost, light loads) Buck A/B: LPM inhibited mA range Buck A running High High DEVICE STATUS BuckA and BuckB running High High BOOST CONTROLLER BuckA and BuckB running Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 21 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com Gate-Driver Supply (VREG, EXTSUP) The gate drivers of the buck and boost controllers are supplied from an internal linear regulator whose output (5.8 V typical) is available at the VREG pin and should be decoupled using at least a 3.3-F ceramic capacitor. This pin has internal current-limit protection and should not be used to power any other circuits. The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6 V (typical). In case VIN expected to go to high levels, there can be excessive power dissipation in this regulator, especially at high switching frequencies and when using large external MOSFETs. In this case, it is advantageous to power this regulator from the EXTSUP pin, which can be connected to a supply lower than VIN but high enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6 V, the linear regulator automatically switches to EXTSUP as its input to provide this advantage. Efficiency improvements are possible when one of the switching regulator rails from the TPS43330-Q1 or TPS43332-Q1 or any other voltage available in the system is used to power EXTSUP. The maximum voltage that should be applied to EXTSUP is 13 V. VIN typ 5.8 V LDO VIN EXTSUP typ 7.5 V LDO EXTSUP typ 4.6 V VREG Figure 23. Internal Gate-Driver Supply Using a large value for EXTSUP is advantageous, as it provides a large gate drive and hence better onresistance of the external MOSFETs. A 0.1-F ceramic capacitor is recommended for decoupling the EXTSUP pin when not being used. During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in low-power mode as well. External P-Channel Drive (GC2) and Reverse Battery Protection The TPS43330-Q1 and TPS43332-Q1 include a gate driver for an external P-channel MOSFET which can be connected across the rectifier diode of the boost regulator. This is useful to reduce power losses when the boost controller is not switching. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel MOSFET. When VBAT falls below the boost-enable threshold, the gate driver turns off the Pchannel MOSFET and the diode is no longer bypassed. The gate driver can also be used to bypass any additional protection diodes connected in series, as shown in Figure 24. Figure 25 also shows a different scheme of reverse battery protection, which may require only a smaller-sized diode to protect the N-channel MOSFET, as it conducts only for a part of the switching cycle. Because it is not always in the series path, the system efficiency can be improved. 22 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 R10 GC2 D3 TPS43330/2 Q6 Q7 L3 Fuse (S1) VIN Vbat D2 C16 C17 D1 C15 C14 DS GC1 COMPC C13 R9 VBAT Figure 24. Reverse Battery Protection Option 1 for Buck Boost Configuration GC2 VBAT VIN Fuse TPS43330/2 DS GC1 COMPC VBAT Figure 25. Reverse Battery Protection Option 2 for Buck Boost Configuration Undervoltage Lockout and Overvoltage Protection The TPS43330-Q1 and TPS43332-Q1 start up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once it has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage lockout disables the device. Note: if Vin drops, VREG drops as well; hence, the gate-drive voltage is reduced, whereas the digital logic is fully functional. Note as well, even if ENC is high, the boost requires the unlock-voltage of typically 8.5 V to be exceeded once, before it can be activated (see the Boost Controller section herein). A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the device. In order to prevent transient spikes from shutting down the device, the under- and overvoltage protection have filter times of 5 s (typical). When the voltages return to the normal operating region, the enabled switching regulators start including a new soft-start ramp for the buck regulators. When the boost controller is enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage lockout and pulls the boost gate driver (GC1) low (this action has a filter delay of 5 s, typical). As a result, VIN falls at a rate dependent on its capacitor and load, eventually triggering VIN undervoltage. A short falling transient at VBAT even lower than 2 V can thus be survived, if VBAT returns above 2.5 V before VIN is discharged to the undervoltage threshold. Thermal Protection The TPS43330-Q1 or TPS43332-Q1 protects itself from overheating using an internal thermal shutdown circuit. If the die temperature exceeds the thermal shutdown threshold of 165C due to excessive power dissipation (for example, due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers are turned off and restarted when the temperature has fallen by 15C. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 23 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com APPLICATION INFORMATION The following example illustrates the design process and component selection for the TPS43330. The design goal parameters are given in Table 3. Table 3. Application Example PARAMETER VBUCK A VBUCK B BOOST VIN 6 V to 30 V 12 V - typical VIN 6 V to 30 V 12 V - typical VBAT - 5 V (cranking pulse input) to 30 V Output voltage, VO 5V 3.3 V 10 V Maximum output current, IO 3A 2A 2.5 A Input voltage Load step output tolerance, VO Current output load step, IO Converter switching frequency, fSW 0.2 V 0.12 V 0.5 V 0.1 A to 3 A 0.1 A to 2 A 0.1 A to 2.5 A 400 kHz 400 kHz 200 kHz This is a starting point and theoretical representation of the values to be used for the application, further optimization of the components derived may be required to improve the performance of the device. Boost Component Selection A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in its transfer function. The RHP zero is inversely related to the load current and inductor value and directly related to the input voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the bandwidth is too close to the RHP zero frequency, the regulator may become unstable. Thus, for high-power systems with low input voltages, a low inductor value is chosen. This increases the amplitude of the ripple currents in the N-channel MOSFET, the inductor, and the capacitors for the boost regulator. They must be designed with the ripple-to-RHP zero trade-off in mind and considering the power dissipation effects in the components due to parasitic series resistance. A boost converter that operates in the discontinuous mode does not contain the RHP zero in its transfer function. However, this needs an even lower inductor value and has high ripple currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, it may become unstable. VIN CO 7V COMPx OTA-gmEA R ESR 10 V C1 + VREF C2 R3 12 V Figure 26. Boost Compensation Components This design is done assuming continuous-conduction mode. During light load conditions, the boost converter operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for stability. 24 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 Boost Maximum Input Current IIN_MAX The maximum input current is drawn at the minimum input voltage and maximum load. The efficiency for VBAT = 5 V at 2.5 A is 80%, based on the typical characteristics plot. POUT 25 W PINmax = = = 31.3 W Efficiency 0.8 Hence, IINmax (at VBAT = 5 V) = 31.3 W = 6.3 A 5V Boost Inductor Selection, L Allow input ripple current of 40% of IIN max at VBAT = 5 V. L= VBAT * TON IIN max VBAT = IIN max* 2 * fSW 5V = 2.52A * 2 * 200kHz = 4.9 mH Choose a lower value of 4 H in order to ensure a high RHP-zero frequency while making a compromise that expects a high current ripple. Also, this can make the boost converter operate in discontinuous conduction mode, where it is easier to compensate. The inductor saturation current must be higher than the peak inductor current and some percentage higher than the maximum current-limit value set by the external sensing resistive element. This rating should be determined at the minimum input voltage, maximum output current, and maximum core temperature for the application. Inductor Ripple Current, IRIPPLE Based on an inductor value of 4 H, the ripple current is approximately 3.1 A. Peak Current in Low-Side FET, IPEAK I PEAK = IINmax + I RIPPLE 3.1 A = 6.3 A + = 7.85 A 2 2 Based on this peak current value, the external current-sense resistor RSENSE is calculated. 0.2 V RSENSE = = 25 mW 7.85 A Select 20 m, allowing for tolerance. The filter component values RIFLT and CIFLT for current sense are 1.5 k and 1 nF, respectively. This allows for good noise immunity. Right Half-Plane Zero RHP Frequency, fRHP Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 25 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com Output Capacitor, CO To ensure stability, output capacitor CO is chosen such that fRHP fLC 10 10 2p L CO V BAT min 2p IINmax L ae 10 IINmax CO c c VBAT min e 2 2 o ae 10 6.3 A o / L = c / 4 mH / 5V e o o COmin 635 mF Select CO = 680 F. This capacitor is usually aluminum electrolytic with ESR in the tens of milliohms. This is good for loop stability, because it provides a phase boost due to the ESR. The output filter components, L and C, create a double pole (180-degree phase shift) at a frequency fLC and the ESR of the output capacitor RESR creates a zero for the modulator at frequency fESR. These frequencies can be determined by the following: f ESR = f ESR = f LC = 1 2p CO RESR Hz, assume RESR = 40 mW 1 = 6 kHz 2p 660 mF 0.04 W 1 2 p L CO = 1 2p 4 mH 660 mF = 3.1 kHz This satisfies fLC 0.1 fRHP. Bandwidth of Boost Converter, fC Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between stability and transient response: fLC < fESR< fC< fRHP Zero fC < fRHP Zero / 3 fC < fSW / 6 fLC < fC / 3 26 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 Output Ripple Voltage Due to Load Transients, VO Assume a bandwidth of fC = 10 kHz. DVO = R ESR DI O + DI O 4 CO f C = 0.04 W 2.5 A + 2.5 A = 0.19 V 4 660 mF 10 kHz Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases, smaller component choices for the boost output may be used. Selection of Components for Type II Compensation The required loop gain for unity-gain bandwidth (UGB) is ae fC o ae fC o G = 40 log c / - 20 log c // cf c fLC / e ESR o e o ae 10 kHz o ae 10 kHz o / - 20 log c / = 15.9 dB e 3.1 kHz o e 6 kHz o G = 40 log c The boost-converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage. This allows a constant loop response across the input-voltage range and makes it easier to compensate by removing the dependency on VBAT. 10G/20 R3 = C1 = 85 10-6 A / V 2 VO = 7.2 kW 10 10 = = 22 nF 2p f C R3 2p 10 kHz 7.2 kW C2 = C1 aef 2p R3 C1 c SW e 2 o / -1 o = 22 nF ae 200 kHz o 2p 7.2 kW 22 nF c / -1 2 e o = 223 pF Input Capacitor, CIN The input ripple required is lower than 50 mV. IRIPPLE DVC1 = = 10 mV 8 fSW CIN CIN = IRIPPLE 8 fSW DVC1 = 194-F DVESR = IRIPPLE R ESR = 40 mV Therefore, our recommendation is 220 F with 10-m ESR. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 27 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com Output Schottky Diode D1 Selection A Schottky diode with low forward conducting voltage VF over temperature and fast switching characteristics is required to maximize efficiency. The reverse breakdown voltage should be higher than the maximum input voltage, and the component should have low reverse leakage current. Additionally, the peak forward current should be higher than the peak inductor current. The power dissipation in the Schottky diode is given by: PD = ID(PEAK) VF (1 - D) D = 1- VINMIN Vout + VF = 1- 5V = 0.53 10 V + 0.6 V PD = 7.85 A 0.6 V (1 - 0.53) = 2.2 W Because this is activated for the low-input-voltage profile related to the crank pulse, the duration is less than 25 ms. Low-Side MOSFET (BOT_SW3) ae VI IPk PBOOSTFET = (IPk )2 rDS(on) (1 + TC) D + c c 2 e o // (tr + t f ) fSW o ae VI IPk PBOOSTFET = (7.85 A)2 0.02 W (1 + 0.4) 0.53 + c e 2 o / (20 ns + 20 ns) 200 kHz = 1.07 W o The times tr and tf denote the rising and falling times of the switching node and are related to the gate-driver strength of the TPS43330/2 and gate Miller capacitance of the MOSFET. The first term denotes the conduction losses which are minimized when the on-resistance of the MOSFET is low. The second term denotes the transition losses which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. They are higher at high output currents and low input voltages (due to the large input peak current) and when the switching time is low. Note: The on-resistance, rDS(on), has a positive temperature coefficient, which produces the (TC = d x T) term that signifies the temperature dependence. (Temperature coefficient d is available as a normalized value from MOSFET data sheets and can be assumed to be 0.005 / C as a starting value.) BuckA Component Selection Minimum On-Time, tON min VO 3.3 V t ON min = = = 275 ns VIN max f SW 30 V 400 kHz This is higher than the minimum duty cycle specified (100 ns typical). Hence, the minimum duty cycle is achievable at this frequency. 28 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 Current-Sense Resistor RSENSE Based on the typical characteristics for the VSENSE limit with VIN versus duty cycle, the sense limit is approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple currents, choose VSENSE maximum of 50 mV. Select 15 m. Inductor Selection L As explained in the description of the buck controllers, for optimal slope compensation and loop response, the inductor should be chosen such that: KFLR = coil-selection constant = 200 Choose a standard value of 8.2 H. For the buck converter, the inductor saturation currents and core should be chosen to sustain the maximum currents. Inductor Ripple Current IRIPPLE At the nominal input voltage of 12 V, this gives a ripple current of 30% of IO max 1 A. Output Capacitor CO Select an output capacitance CO of 100 F with low ESR in the range of 10 m. This gives VO(Ripple) 15 mV and a V drop of 180 mV during a load step, which does not trigger the power-good comparator and is within the required limits. Bandwidth of Buck Converter fC Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between stability and transient response. * Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz. * Select the zero fz fC / 10 * Make the second pole fP2 fSW / 2 Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 29 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com Selection of Components for Type II Compensation VO RESR RL R1 VSENSE GmBUCK CO R2 Vref COMP Type 2A R3 R0 C2 C1 Figure 27. Buck Compensation Components R3 = 2p f C VO CO = 2p 50 kHz 5 V 100F GmBUCK K CFB VREF GmBUCK K CFB VREF = 23.57 kW where VO = 5 V, CO = 100 F, GmBUCK = 1 mS, VREF = 0.8 V, KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant) Use the standard value of R3 = 24 k. C1 = 10 10 = 2p R3 fC = 1.33 nF 2p 24 kW 50 kHz Use standard value of 1.5 nF. The resulting bandwidth of buck converter fC fC = fC = GmBUCK R3 KCFB 2p CO VREF VO 1mS 24 kW 8.33 S 0.8 V 2p 100 F 5 V = 50.9 kHz This is close to the target bandwidth of 50 kHz. The resulting zero frequency fZ1 This is close to the fC / 10 guideline of 5 kHz. The second pole frequency fP2 This is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied. 30 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 Resistor Divider Selection for Setting VO Voltage b= VREF 0.8 V = = 0.16 VO 5V Choose the divider current through R1 and R2 to be 50 A. Then And Therefore, R2 = 16 k and R1 = 84 k. BuckB Component Selection Using the same method as for VBUCKA, the following parameters and components are realized. VO 3.3 V t ON min = = = 275 ns VIN max f SW 30 V 400 kHz This is higher than the min duty cycle specified (100 ns typical). Iripple current 0.4 A (approx. 20% of IO max) Select an output capacitance CO of 100 F with low ESR in the range of 10 m. This gives VO (ripple) 7.5 mV and V drop of 120 mV during a load step. Assume fC = 50 kHz. R3 = = 2p f C VO CO GmBUCK K CFB VREF 2p 50 kHz 3.3 V 100 mF 1mS 4.16 S 0.8 V = 31kW Use standard value of R3 = 30 k. C1 = 10 2p R3 fC C2 = 10 = C1 ae fSW e 2 2p R3 C1 c = = 1.1nF 2p 30 kW 50 kHz o / -1 o 1.1nF ae 400 kHz o 2p 30 kW 1.1nF c / -1 2 e o = 27 pF Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 31 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 fC = = GmBUCK R3 K CFB 2 p CO www.ti.com VREF VO 1mS 30 kW 4.16 S 0.8 V 2p 100 F 3.3 V = 48 kHz This is close to the target bandwidth of 50 kHz. The resulting zero frequency fZ1 fZ1 = 1 2p R3 C1 1 = = 4.8 kHz 2p 30 kW 1.1nF This is close to the fC guideline of 5 kHz. The second pole frequency fP2 fP2 = 1 2p R3 C2 1 = 2p 30 kW 27 pF = 196 kHz This is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied. Resistor Divider Selection for Setting VO Voltage V 0.8 V b = REF = = 0.242 VO 3.3 V Choose the divider current through R1 and R2 to be 50 A. Then And Therefore, R2 = 16 k and R1 = 50 k. 32 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 BuckX High-Side and Low-Side N-Channel MOSFETs The gate-drive supply for these MOSFETs is supplied by an internal supply, which is 5.8 V typical under normal operating conditions. The output is a totem pole, allowing full voltage drive of VREG to the gate with peak output current of 1.2 A. The high-side MOSFET is referenced to a floating node at the phase terminal (PHx), and the low-side MOSFET is referenced to the power-ground (PGx) terminal. For a particular application, these MOSFETs should be selected with consideration for the following parameters: rDS(on), gate charge Qg, drain-tosource breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package. The times tr and tf denote the rising and falling times of the switching node and are related to the gate-driver strength of the TPS43330-Q1 and TPS43332-Q1, and the gate Miller capacitance of the MOSFET. The first term denotes the conduction losses, which are minimized when the on-resistance of the MOSFET is low. The second term denotes the transition losses, which arise due to the full application of the input voltage across the drainsource of the MOSFET as it turns on or off. They are lower at low currents and when the switching time is low. ae V I o PBuckTOPFET = (IO )2 rDS(on) (1 + TC) D + c I O / (tr + t f ) f SW e 2 o 2 PbuckLOWERFET = (IO ) rDS(on) (1 + TC) (1 - D) + VF IO (2 t d ) fSW In addition, during the dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET conducts, increasing the losses. This is denoted by the second term in the above equation. Using external Schottky diodes in parallel with the low-side MOSFETs of the buck converters helps to reduce this loss. Note: rDS(on) has a positive temperature coefficient, which is accounted for in the TC term for rDS(on). TC = d x T[C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and can be assumed to be 0.005 / C as a starting value. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 33 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com Schematics The following section summarizes the previously calculated example and gives schematic and component proposals. Table 4. Application Example 1 PARAMETER VBUCK A VBUCK B BOOST VIN 6 V to 30 V 12 V - typical VIN 6 V to 30 V 12 V - typical VBAT - 5 V (cranking pulse input) to 30 V Output voltage, VO 5V 3.3 V 10 V Maximum output current, IO 3A 2A 2.5 A Input voltage Load step output tolerance, VO Current output load step, IO 0.2 V 0.12 V 0.5 V 0.1 A to 3 A 0.1 A to 2 A 0.1 A to 2.5 A 400 kHz 400 kHz 200 kHz Converter switching frequency, fSW 2.5V to 40V L1 VBAT D1 BOOST 10V, 25W 3.9H 10F CIN 220F 680F COUT1 TOP-SW3 1k VIN VBAT EXTSUP DS BOT-SW3 1.5k 0.02 1nF TOP-SW1 VBUCKA - 5V, 15W 0.015 DIV GC2 VREG CBA CBB L2 0.1F 3.3F TOP-SW2 L3 0.1F 0.1F GB1 GA1 8.2H 100F COUTA GC1 PHA PHB GA2 GB2 VBUCKB - 3.3V, 6.6W 0.03 15H 100F COUTB BOT-SW2 BOT-SW1 PGNDB PGNDA 84k SA1 SA2 FBA TPS43330-Q1 or TPS43332-Q1 50k SB1 SB2 FBB 16k 16k 33pF 1.5nF 24k 10nF COMPA COMPB SSA SSB PGA PGB ENA AGND 27pF 30k 1.1nF 10nF 5k 5k ENB 220pF 22nF 7.2k COMPC ENC RT DLYAB 1nF SYNC Figure 28. Simplified Application Schematic, Example 1 Table 5. Application Example 1 - Component Proposals Component Proposal Value L1 Name MSS1278T-392NL (Coilcraft) 4 H L2 MSS1278T-822ML (Coilcraft) 8.2 H L3 MSS1278T-153ML (Coilcraft) 15 H D1 SK103 (Micro Commercial Components) TOP_SW3 IRF7416 (International Rectifier) TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW3 IRFR3504ZTRPBF (International Rectifier) COUT1 EEVFK1J681M (Panasonic) 680 F COUTA, COUTB ECASD91A107M010K00 (Murata) 100 F CIN EEEFK1V331P (Panasonic) 220 F 34 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 Table 6. Application Example 2 PARAMETER Input voltage VBUCK A VBUCK B BOOST VIN 5 V to 30 V 12 V - typical VIN 6 V to 30 V 12 V - typ VBAT - 5 V (cranking pulse input) to 30V 10 V Output voltage, VO 5V 3.3 V Maximum output current, IO 2.7 A 5A 3A Load step output tolerance, VO 0.2 V 0.12 V 0.5 V 0.1 A to 2.7 A 0.1 A to 5 A 0.1 A to 3 A 300 kHz 300 kHz 150 kHz Current output load step, IO Converter switching frequency, fSW 5V to 30V L1 VBAT D1 BOOST 10V, 25W 3.9H 10F CIN 330F 1.5mF COUT1 TOP-SW3 1k VIN VBAT EXTSUP DS BOT-SW3 1.5k 0.015 560pF TOP-SW1 VBUCKA - 5V, 13.5W 0.015 DIV GC2 VREG CBA CBB L2 0.1F 3.3F 0.1F 0.1F 10H 150F COUTA GC1 GA1 GB1 PHA PHB GA2 GB2 TOP-SW2 L3 0.01 VBUCKB - 3.3V, 16.5W 6.8H 330F COUTB BOT-SW2 BOT-SW1 PGNDB PGNDA 84k SA1 SA2 FBA TPS43330-Q1 or TPS43332-Q1 50k SB1 SB2 FBB 16k 16k 47pF 1.8nF 24k 10nF COMPA COMPB SSA SSB PGA PGB ENA AGND 47pF 27k 1.5nF 10nF 5k 5k ENB RT 80k 330pF 47nF 6.2k COMPC ENC DLYAB 1nF SYNC Figure 29. Simplified Application Schematic, Example 2 Table 7. Application Example 2 - Component Proposals Component Proposal Value L1 Name MSS1278T-392NL (Coilcraft) 3.9 H L2 MSS1278T-103ML (Coilcraft) 10 H L3 MSS1278T-682ML (Coilcraft) 6.8 H D1 SK103 (Micro Commercial Components) TOP_SW3 IRF7416 (International Rectifier) TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW3 IRFR3504ZTRPBF (International Rectifier) COUT1 EEVFK1V152M (Panasonic) 1.5 mF COUTA ECASD91A157M010K00 (Murata) 150 F COUTB ECASD90G337M008K00 (Murata) 330 F CIN EEEFK1V331P (Panasonic) 330 F Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 35 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com Table 8. Application Example 3 PARAMETER VBUCK A VBUCK B BOOST VIN 5 V to 30 V 12 V - typical VIN 6 V to 30 V 12 V - typical VBAT - 5 V (cranking pulse input) to 30 V Output voltage, VO 5V 2.5 V 10 V Maximum output current, IO 3A 1A 2A 0.2 V 0.12 V 0.5 V 0.1 A to 3 A 0.1 A to 1 A 0.1 A to 2 A 400 kHz 400 kHz 200 kHz Input voltage Load step output tolerance, VO Current output load step, IO Converter switching frequency, fSW 5V to 30V L1 VBAT D1 BOOST 10V, 20W 3.9H 10F CIN 330F 470F COUT1 TOP-SW3 1k VIN VBAT EXTSUP DS BOT-SW3 1.5k 0.03 470pF TOP-SW1 VBUCKA - 5V, 15W 0.015 DIV GC2 VREG CBA CBB L2 0.1F 3.3F TOP-SW2 L3 0.045 0.1F 0.1F 10H 150F COUTA GC1 GA1 GB1 PHA PHB GA2 GB2 VBUCKB - 3.3V, 16.5W 22H 100F COUTB BOT-SW2 BOT-SW1 PGNDB PGNDA 84k SA1 SA2 FBA TPS43330-Q1 or TPS43332-Q1 34k SB1 SB2 FBB 16k 16k 20pF COMPA 1nF COMPB 36k 39k 10nF SSA SSB PGA PGB ENA AGND 47pF 1nF 10nF 5k 5k ENB 220pF 18nF 8.2k COMPC ENC RT DLYAB 1nF SYNC Figure 30. Simplified Application Schematic, Example 3 Table 9. Application Example 3 - Component Proposals Component Proposal Value L1 Name MSS1278T-392NL (Coilcraft) 3.9 H L2 MSS1278T-822ML (Coilcraft) 8.2 H L3 MSS1278T-223ML (Coilcraft) 22 H D1 SK103 (Micro Commercial Components) TOP_SW3 IRF7416 (International Rectifier) TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW3 IRFR3504ZTRPBF (International Rectifier) COUT1 EEVFK1V471Q (Panasonic) 470 F COUTA ECASD91A157M010K00 (Murata) 150 F COUTB ECASD40J107M015K00 (Murata) 100 F CIN EEEFK1V331P (Panasonic) 330 F 36 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 TPS43330-Q1 TPS43332-Q1 www.ti.com SLVSA82C - MARCH 2011 - REVISED JULY 2012 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package Figure 31. Power Dissipation Derating Profile Based on High-K JEDEC PCB PCB Layout Guidelines Grounding and PCB Circuit Layout Considerations Boost converter 1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low side-current senseresistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to Schottky diode D1 to the COUT1 capacitor. The negative terminal of the input capacitor and the negative terminal of the sense resistor must be connected together with short trace lengths. 2. The overcurrent-sensing shunt resistor may require noise filtering, and this capacitor should be close to the IC pin. Buck Converter 1. Connect the drain of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor COUT1. The trace length between these terminals should be short. 2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx. 3. The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel with each other. Any filtering capacitors for noise should be placed near the IC pins. 4. The resistor divider for sensing the output voltage is connected between the positive terminal of its respective output capacitor and COUTA or COUTB and the IC signal ground. These components and the traces should not be routed near any switching nodes or high-current traces. Other Considerations 1. PGNDx and AGND should be shorted to the thermal pad. Use a star ground configuration if connecting to a non-ground plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltage-sense feedback ground networks to this star ground. 2. Connect a compensation network between the compensation pins and IC signal ground. Connect the oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits should NOT be located near the dv/dt nodes; these include the gate-drive outputs, phase pins, and boost circuits (bootstrap). 3. Reduce the surface area of the high-current-carrying loops to a minimum, by ensuring optimal component placement. Ensure the bypass capacitors are located as close as possible to their respective power and ground pins. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 Submit Documentation Feedback 37 TPS43330-Q1 TPS43332-Q1 SLVSA82C - MARCH 2011 - REVISED JULY 2012 www.ti.com PCB Layout POW ER IN PUT Powe r L ines Connec tion to GND P lane o fPCB th rough v ias Connec tion to top /bo ttom o fPCB th rough v ias Vo ltage Ra ilO u tpu ts V BOOST VBAT V IN EXTSUP GC1 D IV GC2 VREG CBA CBB GA1 GB1 PHA PHB GA2 GB2 PGNDA PGNDB SA1 SB1 SA2 SB2 FBA FBB COMPA COMPB SSA SSB PGA PGB ENA AGND ENB RT COMPC ENC M ic rocon tro lle r VBUCKB VBUCKA DS DLYAB Exposed Pad connec ted to GND P lane SYNC REVISION HISTORY Changes from Revision B (July 2012) to Revision C * 38 Page Corrected year of revision date from 2011 to 2012 .............................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS43330-Q1 TPS43332-Q1 PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS43330QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS43332QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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