KMPC875ZT66 - Freescale Semiconductor, Inc.

Freescale Semiconducto r

Technical Data

This hardware specification contains detailed information on

power consi derations, DC/AC electrical characteristics, and

AC timing specifications for the M PC875/MPC870. The

CPU on the MPC875/MPC870 is a 32-bit core built on

Power Architecture™ technology that incorporates memory

management units (MMUs) and instruction and data caches.

For functional characteristics of the MPC875/MPC870, refer

to the MPC885 PowerQUICC™ Family Reference Manual.

T o locate published errata or updates for this document, refer

to the MPC875/MPC870 product summary page on our

website listed on the back cover of this document or , contact

your local Fr ees cale sales office.

Docu ment Number : MPC875 EC

Rev. 4, 08/2007

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Maximum T olerated Ratings . . . . . . . . . . . . . . . . . . . 9

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 10

5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7. Thermal Calculation and Measurement . . . . . . . . . . 12

8. Power Supply and Power Sequencing . . . . . . . . . . . 14

9. Mandatory Reset Configurations . . . . . . . . . . . . . . . 15

10. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

11. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 17

12. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 45

13. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 47

14. USB Electrical Characteristics . . . . . . . . . . . . . . . . . 67

15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 67

16. Mechani cal Data and Ordering Inf ormation . . . . . . . 71

17. Document Revision History . . . . . . . . . . . . . . . . . . . 80

MPC875/MPC870 PowerQUICC™

Hardware Specificatio ns

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

2Freescale Semiconductor

Overview

1Overview

The MPC875/M P C870 is a ver satile single-chip integrated microprocessor and peripheral combination

that can be used in a variety of contr oller applications and communications and networking systems. The

MPC875/MPC870 provides enhanced ATM functionality over that of other ATM-enabled members of the

MPC860 fa mily.

Table 1 shows the functionality supported by the MPC875/MPC8 70.

2Features

The MPC8 75/MPC870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx

core, a system integration unit (SIU), and a communications processor module (CPM).

The following list summarizes the key MPC875/MPC870 features:

• Embedded MPC8xx core up to 133 MHz

• Maximum frequency operation of the external bus is 80 MHz (i n 1:1 mode)

— The 133-MHz core frequency supports 2:1 mode only

— The 66-/80-MHz core fr equencies support both the 1:1 and 2:1 modes

• Single-issue, 32-bit core (compatible with the Power Architecture definition) with thirty-two

32-bit general-pur pose registers (GPR s)

— The core performs br anch prediction with conditional prefetch and without conditional

execution

— 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1)

– Instruction cache is two-way, set-associative with 256 sets in 2 bl ocks

– Data cache is two-way, set-associative with 256 sets

– Cache cohere ncy for both instruction and data caches is maintained on 128-bit (4-word)

cache blocks

– Caches are physically addressed, implement a least recently used (LRU) replacement

algorithm, and are lockable on a cache block basis

— MMUs with 32-entry TLB, fully associative instruction and data TLBs

— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address

spaces and 16 prote ction groups

— Advanced on-chip emulation debug mode

• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

Table 1. MPC875/MPC870 De vices

Part Cache (Kbytes) Ethernet SCC SMC USB Security

Engine

I Cache D Cache 10BaseT 10/100

MPC875 8812111Yes

MPC870 8 8 — 2 — 1 1 No

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 3

Features

• Thirty-two address lines

• Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Eac h bank can be a chip select or RAS to support a DRAM bank

— Up to 30 wait states programmable per memory bank

— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory

devices

— DRAM controller programmable to s upport most s i ze and speed memory interfaces

— Four CAS lines , four WE lines, and one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbytes–256 Mbytes)

— Selectable write protection

— On-chip bus arbitration logic

• Genera l-pur pose timers

— Four 16-bit timers or two 32-bit timers

— Gate mode can enable/disable count ing

— Interrupt can be masked on ref erence match and event capture

• Two Fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE Std. 802.3® CDMA/CS

that interface through M I I and/or RMII interfaces

• System inte gration unit (SIU)

— Bus monitor

— S oftware watchdog

— Periodic interrupt timer (PI T)

— Clock synthesizer

— Decremen ter and time base

— Reset controller

— IEEE 1149.1™ Std. test access port (JTAG)

• Security engine is optimized to handle all the algorithms associat ed with IPsec, SSL/TLS, SRTP,

IEEE 802.11i® standard, and iSCSI processing. Available on the MP C875, the security engine

contains a crypto-channel, a controller, and a set of crypto hardware acceler at ors (CHA s) . The

CHAs are:

— Data encr yption standard execution unit (DEU)

– DES, 3DES

– Two key (K1, K2, K1) or three key (K1, K2, K3)

– ECB and CB C modes for both DES and 3DES

— Advanced encr yption standard unit ( AESU)

– Implements the Rijndael symmetric key cipher

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

4Freescale Semiconductor

Features

– ECB, CBC, and counter modes

– 128-, 192-, and 256-bit key lengths

— Message digest execution unit (MDEU)

– SHA with 160- or 256-bit mess age digest

– MD5 with 128- bit message digest

– HMAC with either algorithm

— Mas t er/sl ave lo gic, with DMA

– 32-bit addre ss /32-bit data

– Operation at MP C8xx bus frequency

— Crypto-channel supporting multi-command descriptors

– Integrated controller managing crypt o-execution units

– Buffer size of 256 bytes f or each execution unit, with flow control for large data sizes

• Interrupts

— Six external interrupt request (IRQ ) lines

— Twelve port pins with interrupt c apability

— Twenty- three internal interrupt sources

— P rogrammable priority between SCCs

— Programmable highest priority re quest

• Communications proc essor module (CPM)

— RISC cont ro lle r

— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT

MODE, and RESTART TRANSMIT)

— Supports continuous mode transmission and reception on all serial channels

— 8-Kbytes of dual-port RAM

— Several serial DMA (SDMA) channels to support the CPM

— Three parallel I/O regis ters with open-drain capability

• On-chip 16 × 16 multiply accumulate controller (MAC)

— One operation per clock (two-clock latency, one-clock blockage)

— MAC operates concurrently with other instructions

— FIR loop—Four clocks per four multiplies

• Four baud-rate generators

— Inde pendent (can be connected to SCC or SMC)

— Allows changes during operation

— Autobaud support option

• SCC (serial communication controller)

— Ethernet/IEEE 802.3® standard, suppor ting full 10-Mbps operation

— HDLC/SDLC

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 5

Features

— HDLC bus (implements an HDLC-based local area network (LAN))

— Asynchronous HDLC to support point-to-point protocol (PPP )

— AppleTalk

— Univer sal asynchronous receiver transmitter (UART)

— Synchronous UART

— Serial infr ared (IrDA)

— Binary synchronous communicat ion (BISYNC)

— Totally transparent (bit streams)

— Totally transparent (frame based with optional cyclic redundancy check (C RC))

• SMC (serial management channel )

— UART (low-speed operation)

— Transparent

• Universal serial bus (USB)—Supports operation as a USB function endpoint, a USB host

controller, or both for testing purposes (loopback diagnostics)

— USB 2.0 full-/low-speed compa tible

— The USB function mode has the following fe ature s:

– Four independent endpoints support control, bulk, interrupt, and isochronous data tran sfers

– CRC16 generation and checking

– CRC5 checking

– NRZI encoding/decoding with bit stuffing

– 12- or 1.5-Mbps data rate

– Flexible data buffers with multiple buffers per frame

– Automatic retransmission upon transmit error

— The USB host c ontroller has the following features:

– Supports control, bulk, interrupt , and isochr onous data transfers

– CRC16 generation and checking

– NRZI encoding/decoding with bit stuffing

– Supports both 12- and 1.5-Mbps data rates (automatic generation of pr eamble token and

data rate configuration) . Note that low-speed operation require s an external hub.

– Flexible data buffers with multiple buffers per frame

– Supports local loopback mode for diagnostics (12 M bps only)

• Serial peripheral interface (SPI)

— S upports master and s lave modes

— Supports multiple-master operation on the same bus

• Inter -integrat ed circuit (I2C) port

— S upports master and s lave modes

— Supports a multiple- maste r environment

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

6Freescale Semiconductor

Features

• The MPC875 has a time-slot assigner (TSA) that suppor ts one TDM bus (TDMb)

— Allows SCC and SMC to run in multiplexed and/or non-multiplexed operation

— S upports T1, C EPT, PCM highway, IS DN bas ic rate, ISDN primary ra te, user-defined

— 1- or 8-bit resolution

— Allows independent transmit and receive routing, frame synchronization, and c l ocking

— Allows dynamic changes

— Can be internally connected to two serial channels (one SCC and one SMC)

• PCMCIA interface

— Master (socket) i nterface, release 2.1-compliant

— Supports one independent PCMCIA socket on the MPC875/MPC870

— Eight memory or I/O windows supported

• Debug interface

— Eight comparators: four operate on instruction address, two operate on data address, and two

operate on data

— Supports conditions: = ≠<>

— Eac h watchpoint can generate a break point interna lly

• Normal high and normal low power modes to conserve power

• 1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility

• The MPC875/M PC870 comes in a 256-pin ball grid ar ray (PBGA) package

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 7

Features

The MPC875 block diagram is shown in Figure 1.

Figure 1. MPC875 Bl ock Diagram

Bus

System Inter face Unit (SIU)

Embedded

Parallel I/O

Memory Controller

Timers Interrupt

Controllers 8-Kbyte

Dual-Po r t RAM

System Functions

8-Kbyte

Instruction Cache

32-Ent ry ITLB

Instruction MMU

8-Kbyte

Data Cache

32-Ent ry DTLB

Data MMU

Instruction

Bus

Load/Store

Bus

Unified

4 Baud Rate

Generators

Parallel Interface

Internal

Bus In terface

Unit

External

Bus Interface

Unit

Timers

32-Bit RISC Cont rol ler

and Program

ROM

Se r ia l In te rface

SPI

SMC1

MPC8xx

Processor

Core

SCC4

PC MC IA -ATA In te rfa ce

Virtual IDMA

and

Serial DMAs

Security Engine

AESU DEU MDEU

Controller

Channel

DMAs

FIFOs

10/100

MIII/RMII

BaseT

Media Access

Control

Fast Ethernet

Controller

USB

Slave/ Ma ster IF

DMAs

Time-Slot Assigner

Port

Bus In terface

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

8Freescale Semiconductor

Features

The MPC870 block diagram is shown in Figure 2.

Figure 2. MPC870 Bl ock Diagram

Bus

System Int erface Unit (SIU)

Embedded

Parallel I/O

Memory Controller

Timers Interrupt

Controllers 8-Kbyte

Dual-Port RAM

System Functions

8-Kbyte

Instr uction Cache

32-Entry ITLB

Instruction MMU

8-Kbyte

Data Cache

32-Entry DTLB

Data MMU

Instruction

Bus

Load/Store

Bus

Unified

4 Baud Rate

Generators

Parallel Interface

Internal

Bus Interface

Unit

External

Bus Interface

Unit

Timers

32-Bit RIS C Contro ll er

and Program

ROM

Se r ia l In te rface

SPISMC1

MPC8xx

Processor

Core

PCM CIA-ATA Inte rface

Virtu al IDMA

and

Serial DMAs

DMAs

FIFOs

10/100

MIII/RMII

BaseT

Media Acce ss

Control

Fast Ethernet

Controller

USB

Slave/Master IF

DMAs

Port

Bus Interface

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 9

Maximum Tolerated Ratings

3 Maximum Tolerated Ratings

This section provides the maximum tolerated voltage and temperature ranges for the MPC875/MPC870.

Table 2 displa ys the maximum tolerated ratings and Table 3 displays the operating temper atur es.

Figure 3 shows the undershoot and overshoot voltages at the interfaces of the MPC875/MPC870.

Figure 3. Undershoot/Over shoot Voltage for VDDH and VDDL

Table 2. Maxi mum Toler a te d Ratings

Rating Symbol Value Unit

Supply voltage1

1The power supply of the device must start its ramp from 0.0 V.

VDDL (core voltage) –0.3 to 3.4 V

VDDH (I/O voltage) –0.3 to 4 V

VDDSYN –0.3 to 3.4 V

Diff erence betw een

VDDL and V DDSYN

<100 mV

Input voltage2

2Functional operating condit ions are pro vided with the DC electri cal speci fications i n Table 6. Abs o lute ma x imum rati n g s are

stress ratings only; functional operation at the maxima is not guaranteed. Stress be yond those listed ma y affect device

reliability or cause permanent damage to the device.

Caution: All inputs that to ler ate 5 V cannot b e more than 2.5 V greater than VDDH. This restriction applies to power up and

normal ope ra tion (t hat is , i f the MPC875/MPC87 0 i s unpow ere d, a v ol tage g reater than 2 .5 V must no t be appl ied t o it s input s).

Vin GND – 0.3 to VDDH V

Storage tempera tur e range Tstg –55 to +150 °C

GND

GND – 0.3 V

GND – 0.7 V Not to Exceed 10%

VDDH/VDDL + 20%

VDDH/VDDL

VDDH/VDDL + 5%

of tinterface1

1. tinterface refers to the cl ock period ass o ciated with the bus cloc k interface.

VIH

VIL

Note:

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

10 Freescale Semiconductor

The r m al C ha r ac ter is t ic s

This device contains circuitry protecting against damage due to high-static voltage or electrical fields;

however, it is advised that normal prec autions be taken to avoid application of any voltages higher than

maximum-rated voltage s to this high-impedance circuit. Reliability of operation is enhanced if unused

inputs a re tied to an a ppropriate logic voltage level ( f or example, either GND or VDDH).

4 Thermal Characteristics

Table 4 shows the thermal characteristi cs for the MPC875/MPC870.

Table 3. Op erating Temp eratur es

Rating Symbol Value Unit

Tem perature 1 (stan dard)

1Minimum temperatures are guaranteed as ambient temperatur e, TA. Maximum temperatur es are guaranteed as junct ion

temperature, TJ.

TA(min) 0°C

TJ(max) 95 °C

Temperature (extended) TA(min) –40 °C

TJ(max) 100 °C

Table 4. MP C875/MPC870 Thermal Resistanc e Data

Rating Environment Symbol Value Unit

Junction-to-ambient1

1Junction temperature is a func ti on of on -chip powe r di ssipation, package the rmal resi stance, mo unting site (board)

temper ature, ambient temperatur e, airflo w , power diss ip ation of other components on the boar d, a nd board thermal resis tan ce.

Natural convection Single-layer board (1s) RθJA2

2Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

43 °C/W

Four-la yer board (2s2p) RθJMA3

3Per JEDEC JESD51-6 with the board horizontal.

Airfl ow (200 ft/min) Single- layer board (1s) RθJMA336

Four-la yer board (2s2p) RθJMA326

Junction-to-board4

4Thermal res istance between the die and the printed-circuit board per JEDEC JESD51-8. B oard temperature is measured on

the top surface of the board near the package.

RθJB 20

Junction-t o-case 5

5Indi cates the a verage thermal resistance be tween the di e and the case t op surf ace as measur ed by the co ld plate met hod (MIL

SPEC-883 Method 1012.1) wit h the col d plate tem peratur e used for the case temp erature. For exposed pad pack ages where

the pad would be ex pected to be solde red, junction-to-case thermal res istance is a simulated v alue from the junct ion to the

exposed pad without contact resistance.

RθJC 10

Junction- to- package top6

6Thermal characterizat ion paramet er i ndicating the temp erature difference be tween the package top and the junction

temperature per JEDEC JESD51- 2.

Natural convection ΨJT 2

Airflow (200 ft/min) ΨJT 2

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 11

Power Dissipation

5 Po we r Di ssip ation

Table 5 pr ovides information on power dissipation. The modes are 1:1, where CPU and bus speeds are

equal, and 2:1, where CPU frequency is twice bus speed.

NOTE

The values in Table 5 represent VDDL-based power dissipation and do not

include I/O power dissipation over VDDH. I/O power dissipation varies

widely by appl icati on due to buffe r curr ent , depending on external circuitry.

The V DDSYN power dissipation is negligible.

6 DC Characteristics

Table 6 provides the DC electrical characteristics for the MPC875/MPC870.

Table 5. Power Dissipation (PD)

Die Revision Bus Mode Frequency Typical1

1Typical power dissi pation is measured at VDDL = VDDSYN = 1.8 V, and VDDH is at 3.3 V.

Maximum2

2Maximum power di ssipation at VDDL = VDDSYN = 1.9 V, and VDDH is at 3.5 V.

Unit

0 1:1 66 MHz 310 390 mW

80 MHz 350 430 mW

2:1 133 MHz 430 495 mW

Table 6. DC Electrical Specification s

Characteristic Symbol Min Max Unit

Operating voltage VDDH (I/O) 3. 135 3.465 V

VDDL (core) 1.7 1.9 V

VDDSYN11.7 1.9 V

Difference

between VDDL

and VDDSYN

—100mV

Input high volt age (al l inputs except EXTAL and EXTCLK)2VIH 2.0 3.465 V

Input low voltage3VIL GND 0.8 V

EXTAL , EXTCLK in put hi gh voltage VIHC 0.7 × VDDH VDDH V

Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK, and

DSDI pins) for 5-V tolerant pins1Iin — 100 µA

Input leakage current, Vin = VDDH (except TMS, TRST, DSCK, and

DSDI) IIn —10µA

Input leakage curren t, Vin = 0 V (e xcept TMS, TRST , DSCK, and DSDI

pins) IIn —10µA

Input capacitance4Cin —20pF

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

12 Freescale Semiconductor

Thermal Calculation and Measurement

7 Thermal Calculation and Measurement

For the following discussions, PD = (VDDL × IDDL) + PI/O, where PI/O is the power dissipation of the I/O

drivers.

NOTE

The VDDSYN power dissipation is negligible.

7.1 Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction t emperat ure, TJ, in °C can be obtained from the following equation:

TJ = TA + (R θJA × PD)

where:

TA = ambient temperature (°C)

RθJA = package junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in package

The junction-to- ambient thermal res istance is an industry standa rd value that provides a quick and easy

estimation of thermal performance. However , the answer is only an estimate; test cases have demonstrated

that errors of a fact or of two (in the quantity TJ – TA) are possible.

Output hi gh volta ge, IOH = –2.0 mA, VDDH = 3.0 V (except XTAL and

open-drain pins) VOH 2.4 — V

Output low volt age

IOL = 2.0 mA (CLK O UT)

IOL = 3.2 mA5

IOL = 5.3 mA6

IOL = 7.0 mA (TXD1/PA14, TXD2/PA12)

IOL = 8.9 mA (TS, TA, TEA , BI, BB, HRESET, SRESET)

VOL —0.5V

1The difference between VDDL and VDDSYN cannot be more than 100 m V.

2The sign als PA[0:15], PB[14:31], PC[4:15] , PD[3:15], PE(14:31), TDI, TDO, TCK, TRST , TMS , MII1_TXEN, and MII_MDIO are

5-V tolerant. The minimum voltage is still 2.0 V.

3VIL(m a x ) for th e I2C int erface is 0.8 V rather than the 1.5 V as spec if ied in the I 2C standard.

4Input capacitance is peri odically sampled.

5A(0:31), TSIZ0/REG, TSIZ1, D(0:31), IRQ(2:4), IRQ6, RD/WR, BURST, IP_B(0:1), PA(0:4), PA(6:7), PA(10: 11), PA15, PB19,

PB(23:31), PC(6:7), PC(10:13), PC15, PD8, PE(14: 31), MII1_CRS, MII_MDIO, MII1_ TXEN, and MII 1_CO L.

6BDIP/GPL_B(5) , BR, BG, F R Z/ IRQ 6 , CS(0 :7 ), WE(0:3), BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,

GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, U P WAITB /GPL_ B4, GP L_A 5, ALE_A, CE1_A, CE2_A, OP(0:3) , and

BADDR(28:30).

Table 6. DC Electrical Specifications (continued)

Characteristic Symbol Min Max Unit

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 13

Th er m al C al culation an d Mea suremen t

7.2 Estimation with Junction-to-Case Thermal Resistance

Historica lly, thermal resistan ce has frequently been expressed as the sum of a junction-to-case thermal

resistance and a case-to-ambient thermal resistance:

RθJA = RθJC + RθCA

where:

RθJA = junction-to-ambient thermal resista nce (°C/W)

RθJC = junction-t o -ca se thermal resis tan ce (°C/W)

RθCA = case-to-ambient thermal resi stance (°C/W)

RθJC is device-related and cannot be influenced by the user. The user adjusts the thermal environment to

af fect the cas e-to-ambi ent thermal resistance, RθCA. For instance, the user can change the airflow around

the device, add a heat sink, change the mounting arrangement on the printed-circuit board, or change the

thermal dis sipation on the printed-circuit board surrounding the device. This ther mal model is most useful

for ceramic packages with heat sinks where some 90% of the heat f lows through the case and the heat sink

to the ambient environment. For most packages , a better model is required.

7.3 Estimat ion with Junc tion-to-Board Thermal Resistance

A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor

model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case

thermal resistance covers the situation where a heat sink is used or where a subst antial amount of heat is

dissipated from the top of the package. The junction-to-board thermal resistanc e describes the ther mal

performance when most of the heat is conducted to the printed-circuit board. It has been observed that the

thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the

board temperature. If the board temperature is known, an estimate of the junction temperature in the

environment can be made usi ng the following equ ation:

TJ = TB + (RθJB ×PD)

where:

RθJB = junction-to-board thermal resistance (°C/W)

TB = board temperature (°C)

PD = power dissipation in package

If the board temperature is known and the heat loss from the package case to the air can be ignored,

acceptable predictions of junction temperature can be made. For this method to work, the board and board

mounting must be similar to the test board used to determine the junction-to-board thermal resistance,

namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground

plane.

7.4 Estimation Using Simulation

When the board te mperature is not known, a thermal simulation of the application is needed. The simple

two-re sistor mode l can be u sed with the the r ma l sim ulat ion of the applic ation [2], or a mor e accurate a nd

complex model of the package can be used in the thermal simulati on.

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

14 Freescale Semiconductor

Power Supply and Power Sequencing

7.5 Experimental Determination

To determine th e junction temperature of the devi ce in the application after prototypes are available, the

therma l character izat ion para met er (ΨJT) can be used to determine the junction temperature with a

measurement of the tempe rature at the top center of the package case using the following equation:

TJ = TT + (ΨJT ×PD)

where:

ΨJT = thermal character ization paramete r

TT = thermocouple temperature on top of package

PD = power dissipation in package

The thermal characterization parameter is measured per the JESD51-2 specification published by JEDEC

using a 40 gauge t ype T thermocouple epoxied to the top center of the package case. The thermocouple

should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is

placed over the the rmocouple junction and over about 1 mm of wire extending from the junction. The

thermocouple wire is placed flat agai nst the package case t o avoid measurement errors caused by the

cooling effects of the thermocouple wire.

7.6 References

Semiconductor Equipment and Materials International (415) 964-5111

805 East Middlefield Rd

Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) specifications 800-854-7179 or

(Available from Global Engineering Documents) 303-397-7956

JEDEC Specifications http://www.jedec.org

1. C.E. T ri plett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Contr oller Module,” Proceedings of SemiT herm, San Diego, 1998, pp. 47–54.

2. 2. B. J oiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal

Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego,

1999, pp. 212–220.

8 Pow er Supply and Power Sequencing

This section pr ovides design considerations for the M PC875/MPC870 power supply. The

MPC875/MPC870 has a core voltage (VDDL) and PLL voltage (VDDSYN) , which both operate at a lower

voltage than the I/O voltage (VDDH). The I/O section of the MPC875/MPC870 is supplied with 3.3 V

across VDDH and VSS (GND).

The signals PA[0:3], PA [8:11], PB 15, PB[24:25], PB[28:31], PC[4:7] , PC[12:13], PC15, PD[3:15], TDI,

TDO, TCK, TRST, TMS, MII_TXEN, and MII_MDIO are 5 V tolerant. No input can be more than 2.5 V

greater than VDDH. In addi tion, 5-V tolerant pins cannot exceed 5.5 V, and remaining input pins cannot

exceed 3.465 V. This restriction applies to power up, power down, and nor mal operation.

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 15

Mandatory Reset Configurations

One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp

up at different rates. The rates depend on the nature of the power supply, the type of load on each power

supply, and the manner in which different voltages are derived. The following restrictions apply:

•V

DDL mus t not exceed VDDH during power up and power down

•V

DDL mus t not exceed 1.9 V, and VDDH must not exceed 3.465 V

These cautions are necessary for the long-term reliability of t he part. If they are viol ated, the electrostatic

dischar ge (ESD) protection diodes are forward-biased, and excessive current can flow through these

diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in

Figure 4 ca n be added to meet these requirements. The MUR420 Schottky diodes control the maximum

potential difference between the external bus and core power supplies on power up, and the 1N5820 diodes

regulate the maximum potential difference on power down.

Figure 4. Example Voltage Sequencing Cir cuit

9 Mand atory Reset Configu rations

The MPC875/M P C870 requires a ma ndatory configuration dur ing reset.

If hardware reset configuration word (HRCW) is enabled, the HR CW[DBGC ] value needs to be set to

binary X1 in the HRCW and the SIUMCR[DBGC] should be programmed with the same value in the boot

code after res et. This can be done by as serting the RSTCONF during HRESET assertion.

If HRCW is disabled, the SIUMCR [DBGC] should be programmed with b inary X1 in the boot code after

reset by negating the RSTCONF during the HR ESET assertion.

The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR need to be configured

with the mandatory values in Table 7 in the boot code after the reset is negated.

Table 7. Mandator y Reset Configuration of MPC875/MPC870

(Binary)

HRCW (Hardware reset conf iguration word) HRCW[DBGC] X1

SIUMCR (SIU module configuration r egister) SIUMCR[DBGC] X1

MBMR (Machi ne B mode register) MBMR[GPLB4DI S} 0

PAPAR (Port A pin assignment r egister) PAPAR[5:9]

PAPAR[12:13] 0

VDDH VDDL

1N5820

MUR420

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

16 Freescale Semiconductor

Layout Practices

10 Layout Practices

Each VDD pin on the MPC875/MPC870 should be provided with a low-impedance path to the board’s

supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power

supply pins drive distinct gr oups of logic on chip. The VDD power supply should be bypassed to ground

using at leas t four 0.1-µF bypass capacitors located as close as possible to the four sides of the package.

Each board designed should be characterized and additional appropriate decoupling capacitors s hould be

used if required. The capacitor leads and associated printed-circuit traces connecting to chip V DD and

GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-l ayer board

employing two inner layers as VDD and GND planes should be used.

All output pins on the MPC875/MPC870 have fast rise and fall times. Printed circ uit (PC) trace

interconnection length should be minimized in order to minimize undershoot and ref lections caused by

these fast out put switching t imes. This recommendation particularly applies to the address and data buses.

Maximum PC trace lengths of 6 inches are recommended. Capacitance calculations should consider all

device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and

bypassing becom es especial ly critical in systems with higher capacitive loads because these loads create

higher tra nsient curr ents in the VDD and GND circ uits. Pull up all unused inputs or signals that will be

inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For

more information, refer to Section 14.4.3, “Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1),” i n

the MPC885 PowerQUICC™ Family Refe rence Manual.

PADI R (Port A data direction register) PADI R[5: 9]

PADIR[12:13] 0

PBPAR (Port B pin assignment regi ster) PBPAR[14:18]

PBPAR[20:22] 0

PBDIR (Port B data direction regi ster) PBDIR[14: 8]

PBDIR[20:22] 0

PCPAR (Port C pin assignment register) PCPAR[ 4:5]

PCPAR[8:9]

PCPAR[14]

PCDIR (Port C data directi on register) PCDIR[4:5]

PCDIR[8:9]

PCDIR[14]

PDPAR (Port D pin assignment register) PDPAR[ 3:7]

PDPAR[9:5] 0

PDDIR (Port D data directi on register) PDDIR[3:7]

PDDIR[9:15] 0

Table 7. Mandator y Reset Configuration of MPC875/ MPC870 (continued)

(Binary)

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 17

Bus Signal Timing

11 Bus Signal Timing

The maximum bus speed supported by the MPC875/MPC870 is 80 MHz. Higher-speed parts must be

operated in half-speed bus mode (for example, an MPC875/MPC870 used at 133 MHz must be configured

for a 66 MHz bus). Table 8 shows the frequency ranges for standard part frequencies in 1:1 bus mode, and

Table 9 shows the frequency ranges for standard part frequencies in 2:1 bus mode.

Table 10 provides the bus operation timing for the MPC875/MPC870 at 33, 40, 66, and 80 MHz.

The timing for the MPC875/MPC870 bus shown Table 10, assumes a 50-pF load for maximum delays and

a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load m aximum delay

Table 8. Frequency Ranges f o r Standard Part Frequencies (1:1 Bus Mode)

Par t Frequency 66 MHz 80 MHz

Min Max Min Max

Core frequency 40 66.67 40 80

Bus frequency 40 66.67 40 80

Table 9. Frequency Ranges f o r Standard Part Frequencies (2:1 Bus Mode)

Par t Frequency 66 MHz 80 MHz 133 MHz

Min Max Min Max Min Max

Core frequency 40 66.67 40 80 40 133

Bus frequency 20 33.33 20 40 20 66

Table 10. Bus Operation Timing s

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

B1 Bus period (CLKOUT), see Table 8 ————————ns

B1a EXTCLK to CLKOUT phase skew—If

CLKOUT is an integer multiple of EXTCLK,

then the rising edge of EXTCLK is aligned with

the ri sing e dge of CLKOUT. F or a non-in teger

multiple of EXTCLK, this synchronization is

lost, and the risi ng edges o f EXTCLK and

CLKOUT have a cont inuously varying phase

skew.

–2 +2 –2 +2 –2 +2 –2 +2 ns

B1b CLKOUT frequency jit ter peak-to-peak — 1 — 1 — 1 — 1 ns

B1c Frequency jitt er on EXTCLK — 0.50 — 0.50 — 0.50 — 0.50 %

B1d CLK O U T phase jitter peak -t o-peak for

OSCLK ≥ 15 M H z —4—4—4—4ns

CLKOUT phase jit ter peak-to-peak fo r

OSCLK < 15 MHz —5—5—5—5ns

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

18 Freescale Semiconductor

Bus Signal Timing

B2 CLKOUT pulse width low (MIN = 0. 4 ×B1,

MAX = 0.6 ×B1) 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns

B3 CLKOUT pul se width high (MIN = 0.4 ×B1,

MAX = 0.6 ×B1) 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns

B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns

B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 4.00 ns

B7 CLK OUT t o A(0: 31), BADDR( 28:30) , RD/WR,

BURST, D(0: 31) output hold (MIN = 0. 25 ×B1) 7.60 — 6.30 — 3.80 — 3.13 — ns

B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR

output hold (MIN = 0.25 ×B1) 7.60 — 6.30 — 3.80 — 3.13 — ns

B7b CLK OUT t o BR, BG, FRZ, VFLS( 0:1), VF(0:2)

IWP(0:2), LWP(0:1), STS output hold

(MIN = 0.25 ×B1)

7.60 — 6.30 — 3.80 — 3.13 — ns

B8 CLK OUT t o A(0: 31), BADDR( 28:30) , RD/WR,

BURST, D(0:31) v alid (MAX = 0.25 ×B1 + 6.3) — 13.80 — 12.50 — 10.00 — 9.43 ns

B8a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR

valid (MAX = 0.25 ×B1 + 6.3) — 13.80 — 12.50 — 10.00 — 9.43 ns

B8b CLKOUT to BR, B G, VFLS(0: 1), VF(0: 2),

IWP(0:2), FRZ, LWP(0:1), STS valid 2

(MAX = 0.25 ×B1 + 6.3)

— 13.80 — 12.50 — 10.00 — 9.43 ns

B9 CLK OUT t o A(0: 31), BADDR( 28:30) , RD/WR,

BURST, D(0:31), TSIZ(0:1), REG, RS V, PT R

High-Z (MAX = 0.25 ×B1 + 6.3)

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns

B11 CLKOUT to TS, BB asser tion

(MAX = 0.25 ×B1 + 6.0) 7.60 13.60 6.30 12.30 3.80 9.80 3.13 9.13 ns

B11a CLKOUT to TA, BI assertion (when driven by

the memor y controller or PCMCIA interface)

(MAX = 0 .00 ×B1 + 9.301)

2.50 9.30 2.50 9.30 2.50 9.80 2.5 9.3 ns

B12 CLKOUT to TS, BB negation

(MAX = 0 .25 ×B1 + 4.8) 7.60 12.30 6.30 11.00 3.80 8.50 3.13 7.92 ns

B12a CLKOUT to TA, BI negati on (when driven by

the memor y controller or PCMCIA interface)

(MAX = 0 .00 ×B1 + 9.00)

2.50 9.00 2.50 9.00 2.50 9.00 2.5 9.00 ns

B13 CLKOUT to TS, BB High -Z (M IN = 0 .2 5 ×B1) 7.60 21.60 6.30 20.30 3.80 14.00 3.13 12.93 ns

B13a CLK OUT t o TA, BI High-Z (when dri ven b y the

memory control ler or PCMCIA interface)

(MIN = 0.00 ×B1 + 2.5)

2.50 15.00 2.50 15.00 2.50 15.00 2.5 15.00 ns

B14 CLKOUT to TEA assertion

(MAX = 0.00 ×B1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns

Tabl e 10. Bus Operat i on Tim i ng s (c onti nued)

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 19

Bus Signal Timing

B15 CLKOUT to TEA High-Z

(MIN = 0.00 ×B1 + 2.50) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns

B16 TA, BI val id to CLKOUT (set up ti m e)

(MIN = 0.00 ×B1 + 6.00) 6.00 — 6.00 — 6.00 — 6 — ns

B16a TEA, KR, RETR Y, CR vali d to CLKOUT (setup

ti me ) (MIN = 0 .0 0 ×B1 + 4.5 ) 4.50 — 4.50 — 4.50 — 4.50 — ns

B16b BB, BG, BR, val id to CL KOUT (s e tup ti me)2

(4MIN = 0.00 ×B1 + 0.00) 4.00 — 4.00 — 4.00 — 4.00 — ns

B17 CLKOUT to TA, TEA , BI, B B, BG , BR vali d

(hold time) (MIN = 0.00 ×B1 + 1.003)1.00 — 1.00 — 2.00 — 2.00 — ns

B17a CLKOUT to KR, R ETRY, C R val id (hol d ti m e)

(MIN = 0.00 ×B1 + 2.00) 2.00 — 2.00 — 2.00 — 2.00 — ns

B18 D( 0:31) valid to CLKOUT rising edge (setup

time)4 (MIN = 0.00 ×B1 + 6.00) 6.00 — 6.00 — 6.00 — 6.00 — ns

B19 CLKOUT rising edge to D(0:31) valid (hold

time)4 (MIN = 0.00 ×B1 + 1.005)1.00 — 1.00 — 2.00 — 2.00 — ns

B20 D(0:31) valid to CLKOUT falling edge (setup

time)6 (MIN = 0.0 0 ×B1 + 4.00) 4.00 — 4.00 — 4.00 — 4.00 — ns

B21 CLKOUT falling edge to D(0:31) vali d (hold

time)6 (MIN = 0.00 ×B1 + 2.00) 2.00 — 2.00 — 2.00 — 2.00 — ns

B22 CLKOUT rising edge to C S asserted GPCM

ACS = 00 (MAX = 0.25 ×B1 + 6.3) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns

B22a CLKOUT falling edge to CS asserted GPCM

ACS = 10, TRLX = 0 (MAX = 0.00 ×B1 + 8.00) — 8.00 — 8.00 — 8.00 — 8.00 ns

B22b CLKOUT falling edge to CS asserted GPCM

ACS = 11, TRLX = 0, EBDF = 0

(MAX = 0 .25 ×B1 + 6.3)

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns

B22c CLKOUT falling edge to CS asserted GPCM

ACS = 11, TRLX = 0, EBDF = 1

(MAX = 0 .375 ×B1 + 6.6)

10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns

B23 CLKOUT rising edge to C S negat ed GPCM

read access, GPCM write access ACS = 00,

TRLX = 0 and CSNT = 0

(MAX = 0 .00 ×B1 + 8.00)

2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns

B24 A(0:31) and BADDR(28: 30) to CS asserted

GPCM ACS = 10, TRLX = 0

(MIN = 0.25 ×B1 – 2.00)

5.60 — 4.30 — 1.80 — 1.13 — ns

B24a A(0:31) and BADDR(28: 30) to CS asserted

GPCM ACS = 11, TRLX = 0

(MIN = 0.50 ×B1 – 2.00)

13.20 — 10.50 — 5.60 — 4.25 — ns

Tabl e 10. Bus Operat i on Tim i ng s (c onti nued)

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

20 Freescale Semiconductor

Bus Signal Timing

B25 CLKOUT rising edge to O E,

WE(0:3)/BS_B[ 0:3] asserted

(MAX = 0 .00 ×B1 + 9.00)

— 9.00 9.00 9.00 — 9.00 ns

B26 CLKOUT rising edge to O E neg ated

(MAX = 0 .00 ×B1 + 9.00) 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns

B27 A(0:31) and BADDR(28: 30) to CS asserted

GPCM ACS = 10, TRLX = 1

(MIN = 1.25 ×B1 – 2.00)

35.90 — 29.30 — 16.90 — 13.60 — ns

B27a A(0:31) and BADDR(28: 30) to CS asserted

GPCM ACS = 11, TRLX = 1

(MIN = 1.50 ×B1 – 2.00)

43.50 — 35.50 — 20.70 — 16.75 — ns

B28 CLKOUT rising edge to W E(0: 3)/BS_B[0: 3]

negated GPCM write access CSNT = 0

(MAX = 0 .00 ×B1 + 9.00)

— 9.00 — 9.00 — 9.00 — 9.00 ns

B28a CLKOUT falli ng edge to WE ( 0:3)/BS_B[0:3]

negated GPCM write access TRLX = 0,

CSNT = 1, EBD F = 0

(MAX = 0 .25 ×B1 + 6.80)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 9.93 ns

B28b CLKOUT falling edge to CS negated GPCM

write acces s TRLX = 0, CSNT = 1 ACS = 10 or

ACS = 11, EBDF = 0

(MAX = 0.25 ×B1 + 6.80)

— 14.30 — 13.00 — 10.50 — 9.93 ns

B28c CLKOUT falling edge to WE (0:3)/BS_B[0:3]

negated GPCM write access TRLX = 0,

CSNT = 1 write ac cess TRLX = 0, CSNT = 1,

EBDF = 1 (MAX = 0.375 ×B1 + 6.6)

10.90 18.00 10.90 18.00 5.20 12.30 4.69 11.29 ns

B28d CLKOUT falling edge to CS negated GPCM

write access TRLX = 0, CSNT = 1, ACS = 10

or ACS = 11, EBDF = 1

(MAX = 0 .375 ×B1 + 6.6)

— 18.00 — 18.00 — 12.30 — 11.30 ns

B29 WE(0:3)/BS_B[0:3] negated to D(0:31) High-Z

GPCM write acc ess, CSNT = 0, EBDF = 0

(MIN = 0.25 ×B1 – 2.00)

5.60 — 4.30 — 1.80 — 1.13 — ns

B29a WE(0:3)/BS_B[0:3] negated to D(0:31) High-Z

GPCM write access , TRLX = 0, CSNT = 1,

EBDF = 0 (MIN = 0.50 ×B1 – 2.00)

13.20 — 10.50 — 5.60 — 4.25 — ns

B29b CS negated to D(0:31) High -Z GPCM write

access, ACS = 00, TRLX = 0 and CSNT = 0

(MIN = 0.25 ×B1 – 2.00)

5.60 — 4.30 — 1.80 — 1.13 — ns

B29c CS negated to D(0 :31) High -Z GPCM write

access, TRLX = 0, CSNT = 1, ACS = 10 or

A CS = 11, EBDF = 0 (MI N = 0.50 ×B1 – 2.00)

13.20 — 10.50 — 5.60 — 4.25 — ns

Tabl e 10. Bus Operat i on Tim i ng s (c onti nued)

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 21

Bus Signal Timing

B29d WE(0:3)/BS_B[0:3] negated to D(0:31) High-Z

GPCM write access , TRLX = 1, CSNT = 1,

EBDF = 0 (MIN = 1.50 ×B1 – 2.00)

43.50 — 35.50 — 20.70 — 16.75 — ns

B29e CS negated to D(0:31) High -Z GPCM write

access, TRLX = 1, CSNT = 1, ACS = 10 or

A CS = 11, EBDF = 0 (MIN = 1.50 ×B1 – 2.00)

43.50 — 35.50 — 20.70 — 16.75 — ns

B29f WE(0:3/BS_B[0:3]) negated to D(0:31) High-Z

GPCM write access , TRLX = 0, CSNT = 1,

EBDF = 1 (MIN = 0.375 ×B1–6.30)

5.00 — 3.00 — 0.00 — 0.00 — ns

B29g CS negated to D(0:31) High -Z GPCM write

access, TRLX = 0, CSNT = 1 ACS = 10 or

ACS = 11, EBDF = 1

(MIN = 0.375 ×B1 – 6.30)7

5.00 — 3.00 — 0.00 — 0.00 — ns

B29h WE(0:3)/BS_B[0:3] negated to D(0:31) High-Z

GPCM write access , TRLX = 1, CSNT = 1,

EBDF = 1 (MIN = 0.375 ×B1–3.30)

38.40 — 31.10 — 17.50 — 13.85 — ns

B29i CS negated to D(0:31) (0: 3) High- Z GPCM

write access , TRLX = 1, CSNT = 1, A CS = 10

or ACS = 11, EBDF = 1

(MIN = 0.375 ×B1 – 3.30)

38.40 — 31.10 — 17.50 — 13.85 — ns

B30 CS, W E(0:3) /BS_B[0:3] negat ed to A(0:31),

BADDR(28:30) inva lid GPCM write access8

(MIN = 0.25 ×B1 – 2.00)

5.60 — 4.30 — 1.80 — 1.13 — ns

B30a WE(0:3)/ BS_B[0:3] negated to A(0:31),

BADDR(28:30) inva lid GPCM, write acces s,

TRLX = 0, CSNT = 1, CS negated to A(0:31 ),

invalid GPCM write access TRLX = 0,

CSNT = 1, ACS = 10 or A CS == 11, EBDF = 0

(MIN = 0.50 ×B1 – 2.00)

13.20 — 10.50 — 5.60 — 4.25 — ns

B30b WE(0:3)/BS_B[0:3] negated to A(0:31), invalid

GPCM BADDR(2 8:3 0), in valid GPCM write

access, TRLX = 1, CSNT = 1. CS negated to

A(0:31), in valid GPCM write access TRLX = 1,

CSNT = 1, A CS = 1 0 or A CS == 11, EBDF = 0

(MIN = 1.50 ×B1 – 2.00)

43.50 — 35.50 — 20.70 — 16.75 — ns

B30c WE(0:3)/ BS_B[0:3] negated to A(0:31),

BADDR(28:30) inva lid GPCM write access ,

TRLX = 0, CSNT = 1. CS negated to A(0:31)

invalid GPCM write access, TRLX = 0,

CSNT = 1 ACS = 10 or ACS == 11, EBDF = 1

(MIN = 0.375 ×B1 – 3.00)

8.40 — 6.40 — 2.70 — 1.70 — ns

Tabl e 10. Bus Operat i on Tim i ng s (c onti nued)

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

22 Freescale Semiconductor

Bus Signal Timing

B30d WE(0:3)/ BS_B[0:3] negated to A(0:31),

BADDR(28:30) inva lid GPCM write access

TRLX = 1, CSNT =1, CS negat ed to A(0:31)

invalid GPCM write access TRLX = 1,

CSNT = 1, ACS = 10 or 11, EBDF = 1

38.67 — 31.38 — 17.83 — 14.19 — ns

B31 CLKOUT falling edg e to CS valid as requested

by c ontrol bit CST4 in th e co rrespon ding wo rd

in the UPM (MAX = 0.00 ×B1 + 6.00)

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

B31a CLK OUT f alling edge to CS valid as requested

by c ontrol bit CST1 in th e co rrespon ding wo rd

in the UPM (MAX = 0.25 ×B1 + 6.80)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

B31b CLKOUT rising edge to CS valid, as requested

by c ontrol bit CST2 in th e co rrespon ding wo rd

in the UPM (MAX = 0.00 ×B1 + 8.00)

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

B31c CLKOUT rising edge to CS valid, as requested

by c ontrol bit CST3 in th e co rrespon ding wo rd

in the UPM (MAX = 0.25 ×B1 + 6.30)

7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns

B31d CLK OUT f alling edge to CS valid as requested

by c ontrol bit CST1 in th e co rrespon ding wo rd

in the UPM EBDF = 1

(MAX = 0.375 ×B1 + 6.6)

13.30 18.00 11.30 16.00 7.60 12.30 4.69 11.30 ns

B32 CLKOUT falling edge to BS vali d as request ed

by con tr ol bi t BST4 in the cor respondi ng w ord

in the UPM (MAX = 0.00 ×B1 + 6.00)

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

B32a CLKOUT falling edge to BS val id as re quested

by con tr ol bi t BST1 in the cor respondi ng w ord

in the UPM, EBDF = 0

(MAX = 0.25 ×B1 + 6.80)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

B32b CLKOUT rising edge to BS vali d, as r equested

by con tr ol bi t BST2 in the cor respondi ng w ord

in the UPM (MAX = 0.00 ×B1 + 8.00)

1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns

B32c CLKOUT rising edge to BS v alid, as requ ested

by con tr ol bi t BST3 in the cor respondi ng w ord

in the UPM (MAX = 0.25 ×B1 + 6.80)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

B32d CLKOUT falling edge to BS val id as re quested

by con tr ol bi t BST1 in the cor respondi ng w ord

in the UPM, EBDF = 1

(MAX = 0.375 ×B1 + 6.60)

13.30 18.00 11.30 16.00 7.60 12.30 4.49 11.30 ns

B33 CLKOUT falling edge to GPL valid as

requested by cont rol bit GxT4 in the

corresponding word i n the UPM

(MAX = 0.00 ×B1 + 6.00)

1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns

Tabl e 10. Bus Operat i on Tim i ng s (c onti nued)

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 23

Bus Signal Timing

B33a CLKOUT rising edge to GPL valid as

requested by cont rol bit GxT3 in the

corresponding word i n the UPM

(MAX = 0.25 ×B1 + 6.80)

7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns

B34 A(0:31) , BADDR(28: 30), and D(0:31) to CS

valid, as request ed by control bit CST4 in the

corresponding word i n the UPM

(MIN = 0.25 ×B1 – 2.00)

5.60 — 4.30 — 1.80 — 1.13 — ns

B34a A(0:31) , BADDR(28: 30), and D(0:31) to CS

valid, as request ed by control bit CST1 in the

corresponding word i n the UPM

(MIN = 0.50 ×B1 – 2.00)

13.20 — 10.50 — 5.60 — 4.25 — ns

B34b A(0:31) , BADDR(28: 30), and D(0:31) to CS

valid, as request ed by CST2 in the

corresponding word i n UPM

(MIN = 0.75 ×B1 – 2.00)

20.70 — 16.70 — 9.40 — 6.80 — ns

B35 A(0:31), BADDR(28:30) to CS valid as

requested by control bit BST4 in the

corresponding word i n the UPM

(MIN = 0.25 ×B1 – 2.00)

5.60 — 4.30 — 1.80 — 1.13 — ns

B35a A(0:31) , BADDR(28: 30), and D(0:31) to BS

valid as requested by BST1 in the

corresponding word i n the UPM

(MIN = 0.50 ×B1 – 2.00)

13.20 — 10.50 — 5.60 — 4.25 — ns

B35b A(0:31) , BADDR(28: 30), and D(0:31) to BS

valid as requested by control bit BST2 in the

corresponding word i n the UPM

(MIN = 0.75 ×B1 – 2.00)

20.70 — 16.70 — 9.40 — 7.40 — ns

B36 A(0:31) , BADDR(28: 30), and D(0:31) to GPL

valid as requested by control bit GxT4 in the

corresponding word i n the UPM

(MIN = 0.25 ×B1 – 2.00)

5.60 — 4.30 — 1.80 — 1.13 — ns

B37 UPWAIT valid to CL KOUT falling edge9

(MIN = 0.00 ×B1 + 6.00) 6.00 — 6.00 — 6.00 — 6.00 — ns

B38 CLKOUT falling edge to UPWAIT valid9

(MIN = 0.00 ×B1 + 1.00) 1.00 — 1.00 — 1.00 — 1.00 — ns

B39 AS valid to CLKOUT rising edge10

(MIN = 0.00 ×B1 + 7.00) 7.00 — 7.00 — 7.00 — 7.00 — ns

B4 0 A( 0 :3 1 ), T S IZ ( 0: 1 ), R D / WR, BURST val id to

CLKOUT rising edge

(MIN = 0.00 ×B1 + 7.00)

7.00 — 7.00 — 7.00 — 7.00 — ns

B41 TS valid to CLKOUT r ising edge (setup tim e)

(MIN = 0.00 ×B1 + 7.00) 7.00 — 7.00 — 7.00 — 7.00 — ns

Tabl e 10. Bus Operat i on Tim i ng s (c onti nued)

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

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24 Freescale Semiconductor

Bus Signal Timing

B42 CLKOUT rising edge to TS valid (h old t im e )

(MIN = 0.00 ×B1 + 2.00) 2.00 — 2.00 — 2.00 — 2.00 — ns

B43 AS negation to memory controller signals

negati on (MAX = TBD) — TBD — TBD — TBD — TBD ns

1For part speeds above 50 MHz, use 9. 80 ns for B11a.

2The timing required for BR input is relevant when the MPC875/ MP C870 is selected to work with the internal bus a rbiter. The

ti ming for BG input i s rel evant when the MPC875/MPC870 is selected to work with the external bus arbiter.

3For part speeds above 50 MHz, use 2 ns for B17.

4The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input si gnal is asserted.

5For part speeds above 50 MHz, use 2 ns for B19.

6The D(0:31) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read accesses

controlled by chip-select s under cont rol of the user-programmable machine ( UPM) in the memory controller, for data beats

where DLT3 = 1 in the RAM words. (This is onl y the case where data is latc hed on the falling edge of CLKOUT.)

7This formula applies to bus operati on up to 50 MHz.

8The ti ming B30 refers t o CS when A CS = 00 and to WE(0:3) when CSNT = 0.

9The si gnal UPW AIT is consi dered asynch ronous to the CLK OUT and syn chronized internall y . The ti ming s specified in B37 and

B38 are specified to enable the freeze of the UPM output signals as described in Figure 20.

10 The AS s ig nal i s consi dered a sync hron ous to the CLKOUT. Th e timi ng B39 is specif ied i n order t o all ow th e be havi or spec ifie d

in Figure 23.

Tabl e 10. Bus Operat i on Tim i ng s (c onti nued)

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

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Freescale Semiconductor 25

Bus Signal Timing

Figure 5 provide s the control timing diagram.

Figure 5 . Con t rol Ti m in g

Figure 6 provide s the timing for the external clock.

Figure 6. External Clock Timing

CLKOUT

Outputs

Inputs

A Maximum output delay specification.

B Mi nimum output hold ti m e.

C Minimum input set up time specification.

D Minimum input hol d ti m e specification.

CLKOUT

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26 Freescale Semiconductor

Bus Signal Timing

Figure 7 provides the timing for the synchronous output signal s.

Figu re 7. Sy nchronou s Output Si gnals Timi ng

Figure 8 provides the timing for the synchronous active pull-up and open-drain output signals.

Figure 8. Syn chronous Active Pull-Up Resistor and Ope n-Drain Ou tputs Signals Timing

CLKOUT

Output

Signals

Output

Signals

Output

Signals

B7 B9

B8a

B9B7a

B8b

B7b

CLKOUT

TS, BB

TA, B I

TEA

B13

B12B11

B11 B12a

B13a

B15

B14

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 27

Bus Signal Timing

Figure 9 provides the timing for the synchronous input signal s.

Figure 9. Synchronous Input Signals Timing

Figure 10 provides normal case timing for input data. It also applies to normal read accesses under the

contr ol of the user-programma ble ma chi ne (UPM) in the memory controller.

Fig ure 10 . Inpu t Dat a Ti m i ng i n N orma l C ase

CLKOUT

TA, BI

TEA, KR ,

RETRY, CR

BB, BG, BR

B16

B17

B16a

B17a

B16b

B17

CLKOUT

D[0:31]

B16

B17

B19

B18

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

28 Freescale Semiconductor

Bus Signal Timing

Figure 11 provi des the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in

the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

Figure 11. Input Data Timing when Controlled by UPM in the Memory Contr oller and DLT3 = 1

Figure 12 through Figure 15 provide the timing for the external bus read contr olle d by various GPCM

factors.

Figure 12. External Bus Read Timing (GPCM Controlled— ACS = 00)

CLKOUT

D[0:31]

B20

B21

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31]

B11 B12

B23

B22

B26

B19

B18

B25

B28

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 29

Bus Signal Timing

Figure 13. External Bus Read Timing (GP CM Controlled—T RLX = 0, ACS = 10)

Figure 14. External Bus Read Timing (GP CM Controlled—T RLX = 0, ACS = 11)

CLKOUT

A[0:31]

CSx

D[0:31]

B11 B12

B22a B23

B26

B19B18

B25B24

CLKOUT

A[0:31]

CSx

D[0:31]

B11 B12

B22b

B22c B23

B24a B25 B26

B19B18

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30 Freescale Semiconductor

Bus Signal Timing

Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, A CS = 11)

CLKOUT

A[0:31]

CSx

D[0:31]

B11 B12

B22a

B27

B27a

B22b B22c B19B18

B26

B23

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 31

Bus Signal Timing

Figure 16 through Figure 18 provide the timing for the external bus write controlled by various GPCM

factors.

Figure 16. External Bu s Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31]

B11

B22 B23

B12

B30

B28B25

B26

B8 B9

B29

B29b

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

32 Freescale Semiconductor

Bus Signal Timing

Figure 17. External Bus Write Timi ng (GPCM Controlled—T RLX = 0, CSNT = 1)

B23

B30a B30c

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31]

B11

B22

B12

B28b B28d

B25

B26

B28a

B28c

B29c B29g

B29a B29f

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 33

Bus Signal Timing

Figure 18. External Bus Write Timi ng (GPCM Controlled—T RLX = 1, CSNT = 1)

B23B22

B12B11

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31]

B30dB30b

B28b B28d

B25 B29e B29i

B26 B29d B29h

B28a B28c B9B8

B29b

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34 Freescale Semiconductor

Bus Signal Timing

Figure 19 provide s the timing for the external bus controlled by the UPM.

Figure 19. E xter nal Bus Timin g (UPM Controlled Signals)

CLKOUT

CSx

B31d

B31

B34

B32b

GPL_A[0:5],

GPL_B[0:5]

BS_A[0:3]

A[0:31]

B31c

B31b

B34a

B32

B32a B32d

B34b

B36

B35b

B35a

B35

B33

B32c

B33a

B31a

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 35

Bus Signal Timing

Figure 20 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.

Figure 20. As ynchronous UPWAIT Asser ted Detection in UPM Handled Cycles Timing

Figure 21 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.

Figur e 21. Asynch ronous UPWAIT Negated Detection in UP M Handled Cycles Timing

CLKOUT

CSx

UPWAIT

GPL_A[0:5],

GPL_B[0:5]

BS_A[0:3]

B37

B38

CLKOUT

CSx

UPWAIT

GPL_A[0:5],

GPL_B[0:5]

BS_A[0:3]

B37

B38

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36 Freescale Semiconductor

Bus Signal Timing

Figure 22 provides the timing for the synchronous external master access controlled by the GPCM.

Figure 22. Synch ronous External Master Access Ti ming (GP CM Handled ACS = 00)

Figure 23 provides the timing for the asynchronous external master memory access controlled by the

GPCM.

Figure 23. Asyn chronous Externa l Master Memo ry Access Timing (GP CM Co ntrolled—ACS = 00)

Figure 24 provides the timing for the asynchronous external master control signals nega tion.

Fig ure 24. A s ynchronou s Ex te rna l Maste r—C ontrol Si gnals Negat io n Ti m in g

CLKOUT

A[0:31],

TSIZ[0:1],

R/W, BURST

CSx

B41 B42

B40

B22

CLKOUT

A[0:31],

TSIZ[0:1],

R/W

CSx

B39

B40

B22

CSx, W E [0:3],

OE, GP L x ,

BS[0:3]

B43

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 37

Bus Signal Timing

Table 11 pr ovides the interrupt timing for the M P C875/MPC870.

Figure 25 provide s the interrupt detection timing for the external level- sens itive lines.

Figure 25. I nter rupt Detectio n Timing for External Level Sensitive Lines

Figure 26 provide s the interrupt detection timing for the external edge- sensi tive lines.

Figure 26. Interrupt Detection Timing for External Edge-Sensitive Lines

Table 11. Interrupt Timing

Num Characteristic1

1The I39 and I40 ti m ings d escri be the testing conditions under which the IRQ lin es are tested when being defined as le vel

sensitive. The IRQ lines are sy nchroni zed in ternally and do not ha ve t o be asse rted or negat ed with ref ere nce to the CLK O UT.

The I41, I42, and I43 timi ngs ar e specified to allow correct functionin g of the IRQ lines det ection circui try and have no direct

relation with the tot al system interrupt latency t hat the MPC875/MPC870 is able to support.

All Frequencies Unit

Min Max

I39 IRQx v alid to CLKOUT rising edge (setup ti m e) 6.00 ns

I40 IRQx hold ti me after CLK O UT 2.00 ns

I41 IRQx pulse width low 3.00 ns

I42 IRQx pulse width high 3.00 ns

I43 IRQx edg e-to-edge time 4 ×TCLOCKOUT —

CLKOUT

IRQx

I39

I40

CLKOUT

IRQx

I41 I42

I43

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38 Freescale Semiconductor

Bus Signal Timing

Table 12 shows the PCMCIA timing for the MPC875/MPC 870.

Table 12. PCMCIA Timing

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

P44 A(0:31), REG valid to PCMCI A str obe

asserted1 (MIN = 0.75 ×B1 – 2.00)

1PSST = 1. Otherwise add PSST times cycl e ti me .

PSHT = 0. Otherwi se add PSHT times cycle time.

These synchronous timings defi ne when the WAITA signal s are detected in order to freeze (or reli eve) the PCMCIA current

cycle. The WAITA assertion wil l be ef fective only i f it is detected 2 cycles before the PSL ti me r expiration. See Chapter 16,

“PCMCIA Interface,” in the

MPC885 PowerQUICC™ Family Refere nce M anual

20.70 — 16.70 — 9.40 — 7.40 — ns

P45 A(0:31), REG valid to ALE negation1

(MIN = 1.00 ×B1 – 2.00) 28.30 — 23.00 — 13.20 — 10.50 — ns

P46 CLKOUT to REG va lid

(MAX = 0.25 ×B1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns

P47 CLKOUT to REG inva li d

(MIN = 0.25 ×B1 + 1.00) 8.60 — 7.30 — 4.80 — 4.125 — ns

P48 CLKOUT to CE1, CE2 asserted

(MAX = 0.25 ×B1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns

P49 CLKOUT to CE1, CE2 negated

(MAX = 0.25 ×B1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns

P50 CLKOUT to PCOE, IORD , PCWE, IOWR

assert time (MAX = 0.00 ×B1 + 11.00) — 11.00 — 11.00 — 11.00 — 11.00 ns

P51 CLKOUT to PCOE, IORD , PCWE, IOWR

negate tim e (MAX = 0.00 ×B1 + 11.00) 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns

P52 CLKOUT to ALE asser t t ime

(MAX = 0 .25 ×B1 + 6.30) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns

P53 CLKOUT to ALE negate time

(MAX = 0 .25 ×B1 + 8.00) — 15.60 — 14.30 — 11.80 — 11.13 ns

P54 PCWE, I OWR negated to D(0:31)

invalid1 (MIN = 0.25 ×B1–2.00) 5.60 — 4.30 — 1.80 — 1.125 — ns

P55 WAITA and WAITB vali d to CLKOUT

rising edge1 (MIN = 0.00 ×B1 + 8.00) 8.00 — 8.00 — 8.00 — 8.00 — ns

P56 CLKOUT rising edge to WAITA and

WAITB invalid1 (MIN = 0.00 ×B1 + 2. 00) 2.00 — 2.00 — 2.00 — 2.00 — ns

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 39

Bus Signal Timing

Figure 27 provides the PCMCIA access cycle timing for the external bus read.

Fi gure 27. PCMCIA Access Cycles Timing External Bus Read

CLKOUT

A[0:31]

REG

CE1/CE2

PCOE, IORD

D[0:31]

ALE

B19B18

P53P52 P52

P51P50

P48 P49

P46 P45

P44

P47

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40 Freescale Semiconductor

Bus Signal Timing

Figure 28 provides the PCMCIA access cycle timing for the external bus write.

Figure 28. PCMCIA Access Cycles Timing Extern al Bus Write

Figure 29 provides the PCMCIA WAIT signals detection timing.

Figure 29. PCM CIA WAIT Signals Detection Timing

CLKOUT

A[0:31]

REG

CE1/CE2

PCWE, IOWR

D[0:31]

ALE

B9B8

P53P52 P52

P51P50

P48 P49

P46 P45

P44

P47

P54

CLKOUT

WAITA

P55

P56

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 41

Bus Signal Timing

Table 13 shows the PCMCIA port timing for the MPC875/MPC870.

Figure 30 provides the PCMCIA output port timing for the MPC875/MPC870.

Figure 30. PCMCIA Output Port Timing

Figure 31 provides the PCM CIA input port timing for the MPC 875/MPC870.

Figure 31. PCMCIA Input P ort Timing

Ta b le 13 . PCMC IA Por t Tim ing

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

P57 CLKOUT to OPx val id

(MAX = 0.00 ×B1 + 19.00) — 19.00 — 19.00 — 19.00 — 19.00 ns

P58 HRESET negated to OPx drive1

(MIN = 0.75 ×B1 + 3.00)

1OP2 and OP3 onl y.

25.70 — 21.70 — 14.40 — 12.40 — ns

P59 IP_Xx val id to CLKOUT r ising edge

(MIN = 0.00 ×B1 + 5.00) 5.00 — 5.00 — 5.00 — 5.00 — ns

P60 CLKOUT rising edge to IP_Xx invalid

(MIN = 0.00 ×B1 + 1.00) 1.00 — 1.00 — 1.00 — 1.00 — ns

CLKOUT

HRESET

Output

Signals

OP2, OP3

P57

P58

CLKOUT

Input

Signals

P59

P60

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42 Freescale Semiconductor

Bus Signal Timing

Table 14 shows the debug port timing for the MPC875/MPC870.

Figure 32 provides the input timing for the debug port clock.

Fi gure 32. De bug Port Cl ock I nput T iming

Figure 33 provides the timing for the debug port.

Figure 33. Debug Port Timings

Table 14 . De bug Port Ti m in g

Num Characteristic All Frequencies Unit

Min Max

D61 DSCK cycle time 3 ×TCLOCKOUT —

D62 DSCK clock pul se width 1.25 ×TCLOCKOUT —

D63 DSCK rise and fall times 0.00 3.00 ns

D64 DSDI input data set up time 8.00 ns

D65 DSDI data hol d ti me 5.00 ns

D66 DSCK low to DSDO data valid 0.00 15.00 ns

D67 DSCK low to DSDO invali d 0.00 2.00 ns

DSCK

D61

D63

D62

D63

DSCK

DSDI

DSDO

D64

D65

D66

D67

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 43

Bus Signal Timing

Table 15 shows the reset timi ng for the MPC875/MPC870.

Table 15. Reset Timing

Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit

Min Max Min Max Min Max Min Max

R69 CLKOUT to HRESET high impedance

(MAX = 0.00 ×B1 + 20.00) — 20.00 — 20.00 — 20.00 — 20.00 ns

R70 CLKOUT to SRESET high impedance

(MAX = 0.00 ×B1 + 20.00) — 20.00 — 20.00 — 20.00 — 20.00 ns

R71 RSTCONF pulse width

(MIN = 17.00 ×B1) 515.20 — 425.00 — 257.60 — 212.50 — ns

R72 — —————————

R73 Config uration data to HRESET rising

edge setup time

(MIN = 15.00 ×B1 + 50.00)

504.50 — 425.00 — 277.30 — 237.50 — ns

R74 Config uration data to RSTCONF rising

edge setup time

(MIN = 0.00 ×B1 + 350.00)

350.00 — 350.00 — 350.00 — 350.00 — ns

R75 Configuration dat a hold time after

RSTCONF negation

(MIN = 0.00 ×B1 + 0.00)

0.00 — 0.00 — 0.00 — 0.00 — ns

R76 Configuration dat a hold time after

HRESET negation

(MIN = 0.00 ×B1 + 0.00)

0.00 — 0.00 — 0.00 — 0.00 — ns

R77 HRESET and RSTCONF asser ted to

data out drive

(MAX = 0.00 ×B1 + 25.00)

— 25.00 — 25.00 — 25.00 — 25.00 ns

R78 RSTCONF negated to data out high

impedance (MAX = 0.00 ×B1 + 25.00) — 25.00 — 25.00 — 25.00 — 25.00 ns

R79 CLKOUT of last rising edge before c hip

three-states HRESET to data out high

impedance (MAX = 0.00 ×B1 + 25.00)

— 25.00 — 25.00 — 25.00 — 25.00 ns

R80 DSDI, DSCK setup (MIN = 3.00 ×B1) 90.90 — 75.00 — 45.50 — 37.50 — ns

R81 DSDI, DSCK hold time

(MIN = 0.00 ×B1 + 0.00) 0.00 — 0.00 — 0.00 — 0.00 — ns

R82 SRESET negated to CLKOUT rising

edge for DSDI and DSCK sampl e

(MIN = 8.00 ×B1)

242.40 — 200.00 — 121.20 — 100.00 — ns

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

44 Freescale Semiconductor

Bus Signal Timing

Figure 34 shows the reset timing for the data bus configuration.

Figure 34. Reset Timing—Configuration from Data Bus

Figure 35 provide s the reset timing for the data bus weak drive during configuration.

Figure 35. Reset Timin g—D ata Bus Weak Drive During Configuration

Figure 36 provides the reset timing for the debug port configuration.

Figure 36. Reset Timing—Debug Port Configuration

HRESET

RSTCONF

D[0:31 ] (IN)

R71

R74

R73

R75

R76

CLKOUT

HRESET

D[0:31] (OUT )

(Weak)

RSTCONF

R69

R79

R77 R78

CLKOUT

SRESET

DSCK, DSDI

R70

R82

R80R80

R81 R81

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 45

IEEE 1149.1 Electrical Specifications

12 IEEE 1149.1 Electrical Specifications

Table 16 provides the JTAG tim ings for the MPC875/MPC870 shown in Figure 37 through Figure 40.

Figure 37. JTAG Test Clock Inpu t Timing

Table 16. JTAG Timing

Num Characteristic All Frequencies Unit

Min Max

J82 TCK cycle time 100.00 — ns

J83 TCK clock pulse width measured at 1.5 V 40.00 — ns

J84 TCK rise and fall times 0.00 10.00 ns

J85 TMS, TDI dat a setup time 5.00 — ns

J86 TMS, TDI dat a hold ti me 25.00 — ns

J87 TCK low to TDO data valid — 27.00 ns

J88 T CK low to TD O d at a invalid 0. 00 — n s

J89 TCK low to TDO high impedance — 20.00 ns

J90 TRST assert time 100.00 — ns

J91 TRST setup ti me to TCK lo w 40.00 — ns

J92 TCK falling edge to output valid — 50.00 ns

J93 TCK falling edge to output valid out of hi gh impedance — 50.00 ns

J94 TCK falling edge to output high impedance — 50.00 ns

J95 Bounda ry scan inpu t valid to TCK rising edge 50.00 — ns

J96 TCK rising edge to bound ary scan inp ut inv alid 50.00 — ns

TCK

J82 J83

J84 J84

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

46 Freescale Semiconductor

IEEE 1149.1 Electrical Specifications

Figure 38. JTAG T est Access Port Timing Diagram

Figure 39. JTAG TRST Ti m i ng Diagr am

Fig ure 40. Bo undar y Scan (JTAG ) T im ing Diagr am

TCK

TMS, TDI

TDO

J85

J86

J87

J88 J89

TCK

TRST

J91

J90

TCK

Output

Signals

Output

Signals

Output

Signals

J92 J94

J93

J95 J96

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 47

CPM Electrical Characterist ics

13 CPM Electrical Characteristics

This section provides the AC and DC electrical specif ications for the communications pr ocesso r module

(CPM) of the MPC875/MP C870.

13 .1 Port C Inter rupt AC Electrical Specifications

Table 17 provid es the timings for Port C interrupts.

Figure 41 shows the Port C interrupt detection timing.

Figure 41 . Port C In te rrupt Detect io n Ti m in g

13.2 IDMA Controller AC Electrical Specifications

Table 18 provides the IDMA controller timings as shown in Figure 42 through Figure 45.

Table 17 . Por t C Int errupt Ti m in g

Num Characteristic 33.34 MHz Unit

Min Max

35 Port C in terr upt pul se width low (edge-tri ggered mode) 55 — ns

36 Port C interrupt minimum time between active edges 55 — ns

Table 18 . IDMA Controller Timing

Num Characteristic All Frequencies Unit

Min Max

40 DREQ s et u p ti m e to cl o ck hig h 7 — ns

41 DREQ hold t ime fr om clock hig h1

1Applie s to high- t o -low m o de ( E D M = 1 ).

TBD — ns

42 SDACK ass ertion delay fro m clock high — 1 2 ns

43 SDACK nega tion delay from cloc k low — 12 ns

44 SDACK nega ti on delay f rom TA low — 20 ns

45 SDACK nega tion delay from cloc k high — 15 ns

46 TA asserti on to rising edge of the clock setup tim e (applies to external TA)7—ns

Port C

(Input)

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

48 Freescale Semiconductor

CP M Electrical Characteristics

Figure 42. IDMA External Requests Timing Diagram

Figu re 43. S DACK Timin g Diagram—Peri pheral Wri te, External ly-Generated TA

DREQ

(Input)

CLKO

(Output)

DATA

CLKO

(Output)

R/W

(Output)

SDACK

(Input)

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 49

CPM Electrical Characterist ics

Figure 44. SDA CK Timing Diagram—Peri ph eral Wri te, Internal ly-Generated TA

Fi gure 45 . SDACK Timing Diagram— Peripheral Read, Internally-Gener ated TA

DATA

42 44

CLKO

(Output)

R/W

(Output)

SDACK

DATA

42 45

CLKO

(Output)

R/W

(Output)

SDACK

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

50 Freescale Semiconductor

CP M Electrical Characteristics

13 .3 Baud Rate Generator AC Electrical Specifications

Table 19 provid es the baud rate genera tor timings as shown in Figure 46.

Figure 46. Baud Rate Generator Timing Diagram

13 .4 Timer AC Elec t rical Specificati on s

Table 20 provides the genera l-purpose timer timings as shown in Figure 47.

Table 19. Baud Rate Generator Timing

Num Characteristic All Frequencies Unit

Min Max

50 BRGO rise and fall time — 10 ns

51 BRGO duty cycle 40 60 %

52 BRGO cycle 40 — ns

Ta ble 2 0 . Time r Timin g

Num Characteristic All Frequencies Unit

Min Max

61 TIN/TGATE rise and fall time 10 — ns

62 TIN/TGATE low ti me 1 — clk

63 TIN/TGATE high time 2 — clk

64 TIN/TGATE cycle time 3 — clk

65 CLKO low to TOUT v alid 3 25 ns

BRGOX

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 51

CPM Electrical Characterist ics

Figure 47. CPM General-Purpose Timers Timing Diagram

13 .5 S erial Interface AC Electr ical Specifications

Table 21 provid es the serial interfa ce (SI ) timings as shown in Figure 48 through Figure 52.

Table 21. SI Timing

Num Characteristic All Frequencies Unit

Min M ax

70 L1RCLKB, L1TCLKB frequency (DSC = 0)1, 2 — SYNCCLK/2.5 MHz

71 L1RCLKB , L1TCLKB widt h low (DSC = 0)2P + 10 — ns

71a L1RCLKB, L1TCLKB width high (DSC = 0)3P + 10 — ns

72 L1TXDB, L1ST1 and L1ST2, L1RQ, L1CLKO rise/fall time — 15.00 ns

73 L1RSYNCB , L1TSYNCB valid to L1CLKB edg e (SYNC setup ti me) 20.00 — ns

74 L1CLKB edge to L1RSYNCB, L1TSYNCB, invalid (SYNC hold time) 35.00 — ns

75 L1RSYNCB , L1TSYNCB rise/fa ll ti me — 15.00 ns

76 L1RXDB v alid to L1CLKB edge (L 1RXDB setup ti me ) 17. 00 — ns

77 L1CLKB edge to L1RXDB in valid (L1RXDB hold ti m e) 13.00 — ns

78 L1CLKB edge to L1ST1 and L1ST2 valid410.00 45.00 ns

78A L1SYNCB valid to L1ST1 and L1ST2 valid 10.00 45.00 ns

79 L1CLKB edge to L1ST1 and L1ST2 inval id 10.00 45. 00 ns

80 L1CLKB edge to L1TXDB valid 10.00 55.00 ns

80A L1TSYNCB valid to L1TXDB valid410.00 55.00 ns

81 L1CLKB edge to L1TXDB hig h impedance 0.00 42.00 ns

82 L1RCLKB, L1TCLKB frequency (DSC = 1) — 16.00 or

SYNCCLK/2 MHz

83 L1RCLKB, L1TCLKB width low (DSC = 1) P + 10 — ns

CLKO

TIN/TGATE

(Input)

TOUT

(Output)

626361

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

52 Freescale Semiconductor

CP M Electrical Characteristics

Figure 48. SI Receive Timing Diagram with Normal Clocking (DSC = 0)

83a L1RCLKB, L1TCLKB width high (DSC = 1)3P + 10 — ns

84 L1CLKB edge to L1CLKOB valid (DSC = 1) — 30.00 ns

85 L1RQB v alid before falling edge of L1TSYNCB41.00 — L1TCLK

86 L1GRB set up ti m e242.00 — ns

87 L1GRB hold time 42.00 — ns

88 L1CLKB edge to L1SYNCB valid (FSD = 00) CNT = 0000, BYT = 0,

DSC = 0) —0.00ns

1The ratio SYNCCLK/L1RCLKB must be greater than 2.5/1.

2These specs are val id for IDL mode only.

3Wher e P = 1/CLKOUT. Thus, fo r a 25-MHz CLKO1 rate, P = 40 ns.

4These st rob es and TxD on the first bit of the fr ame beco me vali d after the L1CLK B edge or L1SYNCB , whichev er come s later.

Table 21. SI Timing (continued)

Num Characteristic All Frequencies Unit

Min M ax

L1RXDB

(Input)

L1RCLKB

(FE = 0, CE = 0)

(Input)

L1RCLKB

(FE = 1, CE = 1)

(Input)

L1RSYNCB

(Input)

L1ST(2–1)

(Output)

70 71a

RFSD=1

74 77

BIT0

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 53

CPM Electrical Characterist ics

Figure 49. SI Receive Timing with Double-Speed Cloc king (DSC = 1)

L1RXDB

(Input)

L1RCLKB

(FE = 1, CE = 1)

(Input)

L1RCLKB

(FE = 0, CE = 0)

(Input)

L1RSYNCB

(Input)

L1ST(2–1)

(Output)

RFSD=1

74 77

83a

L1CLKOB

(Output)

BIT0

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

54 Freescale Semiconductor

CP M Electrical Characteristics

Figure 50. SI Transmit Timing Diagram (DSC = 0)

L1TXDB

(Output)

L1TCLKB

(FE = 0, CE = 0)

(Input)

L1TCLKB

(FE = 1, CE = 1)

(Input)

L1TSYNCB

(Input)

L1ST(2–1)

(Output)

71 70

80a

TFSD=0

BIT0

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 55

CPM Electrical Characterist ics

Figure 51. SI Transmit Timing with Double Speed Cloc king (DSC = 1)

L1TXDB

(Output)

L1RCLKB

(FE = 0, CE = 0)

(Input)

L1RCLKB

(FE = 1, CE = 1)

(Input)

L1RSYNCB

(Input)

L1ST(2–1)

(Output)

TFSD=0

78a

83a

L1CLKOB

(Output)

BIT0

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

56 Freescale Semiconductor

CP M Electrical Characteristics

Fig ure 52. I D L Ti m i ng

B17 B16 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 MB15

L1RXDB

(Input)

L1TXDB

(Output)

L1ST(2–1)

(Output)

L1RQB

(Output)

12345678910 11 12 13 14 15 16 17 18 19 20

B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M

L1GRB

(Input)

L1RSYNCB

(Input)

L1RCLKB

(Input)

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 57

CPM Electrical Characterist ics

13.6 S CC in NMSI Mode Electrical Sp ecificati ons

Table 22 provides the NMSI external clock timing.

Table 23 pr ovides the NMSI internal clock timing.

Table 22. NMSI External Clock Ti ming

Num Characteristic All Frequencies Unit

Min Max

100 RCLK3 and TCLK3 wid th hi gh1

1The ratios SYNCCLK/RCLK3 and SYNCCLK/TCLK3 must be greater than or equal to 2.25/1.

1/SYNCCLK — ns

101 RCLK3 and TCLK3 width low 1/SYNCCLK + 5 — ns

102 RCLK3 and TCLK3 rise/fall ti me — 15.00 ns

103 TXD3 active delay (from TCLK3 falling edge) 0.0 0 50.00 ns

104 RTS3 active/inactive delay (f rom TCLK3 falling edge) 0.00 50.00 ns

105 CTS3 setup time to TCLK3 rising edge 5.00 — ns

106 RXD3 setup time to RCLK3 rising edge 5.00 — ns

107 RXD3 hold time from RCLK3 rising edge2

2Also applies to CD and CTS hold time when they are used as external SYNC signals.

5.00 — ns

108 CD3 setup time to RCLK3 rising edge 5.00 — ns

Table 23. NMSI Internal Clock Timing

Num Characteristic All Frequencies Unit

Min Max

100 RCLK3 and TCLK3 fr equency1

1The rat ios SYNCCLK/RCLK3 and SYNCCLK/TCLK3 must be greater or equal to 3/1.

0.00 SYNCCLK/3 MHz

102 RCLK3 and TCLK3 rise/fall time — — ns

103 TXD3 active delay (from TCLK3 falling edge) 0.00 30.00 ns

104 RTS3 active/inactive delay (f rom TCLK3 falling edge) 0.00 30.00 ns

105 CTS3 setup time to TCLK3 rising edge 40.00 — ns

106 RXD3 setup time to RCLK3 rising edge 40.00 — n s

107 RXD3 hold time from RCLK3 rising edge2

2Also applies to CD and CTS hold time when they are used as external SYNC signals.

0.00 — ns

108 CD3 setup tim e to RCLK3 rising edge 40.00 — ns

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

58 Freescale Semiconductor

CP M Electrical Characteristics

Figure 53 through Figure 55 show the NMSI timings.

Figur e 53. SC C NMSI Receive Timi ng Diagram

Figure 54. SCC NMSI Transmit Timing Diagram

RCLK3

CD3

(Input)

102

100

107

108

107

RxD3

(Input)

CD3

(SYNC Input)

102 101

106

TCLK3

CTS3

(Input )

102

100

104

107

TxD3

(Output)

CTS3

(SYNC Input)

102 101

RTS3

(Output)

105

103

104

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 59

CPM Electrical Characterist ics

Figure 55. HDLC Bu s Timing Diagr am

13.7 Ethernet Electrical Specifications

Table 24 provides the E thernet timings as shown in Figure 56 through Figure 58.

Table 24 . E t hernet Ti m in g

Num Characteristic All Frequencies Unit

Min Max

120 CLSN width high 40 — ns

121 RCLK3 rise/fall time — 15 ns

122 RCLK3 width low 40 — ns

123 RCLK3 clock peri od 180 120 ns

124 RXD3 setup time 20 — ns

125 R X D 3 ho ld ti me 5—ns

126 RENA active delay (from RCLK3 rising edge of the last data bit) 10 — ns

127 RENA width low 100 — ns

128 TCLK3 rise/fall time — 15 ns

129 TCLK3 wid th l ow 40 — ns

130 TCLK3 clock period199 101 ns

131 TXD3 active delay (from TCLK3 ris ing e dge) — 50 ns

132 TXD3 inactive delay (from TCLK3 ris ing edge) 6. 5 50 ns

133 TENA active del ay (from TCLK3 rising edge) 10 50 ns

134 TENA inactive delay (from TCLK3 rising edge) 10 50 ns

TCLK3

CTS3

(Echo Input)

102

100

104

TxD3

(Output)

102 101

RTS3

(Output)

103

104107

105

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

60 Freescale Semiconductor

CP M Electrical Characteristics

Figure 56 . Eth ernet Co ll i sio n Ti m in g D i agram

Figure 57. Ether net Receive Tim ing Diagram

138 C L KO1 low to SDACK asserted2—20ns

139 C L KO1 low to SDACK negated2—20ns

1The ratios SYNCCLK/RCLK3 and SYNCCLK/TCLK3 must be greater than or equal to 2/1.

2SDACK is asserted whenever the SDMA writes the incoming frame DA i nto memor y.

Table 24 . Ethernet Ti m i ng (c on t inu ed)

Num Characteristic All Frequencies Unit

Min Max

CLSN(CTS1)

120

(Input)

RCLK3

121

RxD3

(Input)

121

RENA(CD3)

(Input )

125

124 123

127

126

Last Bit

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 61

CPM Electrical Characterist ics

Figure 58. Etherne t Tran smi t Timing Diagram

13.8 SM C Transparent AC Electrical Specifications

Table 25 provides the SMC transparent timings as shown in Figure 59.

Table 25. SMC Transparent Timing

Num Characteristic All Frequencies Unit

Min Max

150 S M C L K cl ock pe riod 1

1 SYNCCLK must be at least twice as fast as SMCLK.

100 — ns

151 SMCLK width low 50 — ns

151A SMCLK width high 50 — ns

152 SMCLK rise/fall time — 15 ns

153 SMTXD active delay (from SMCLK falling edge) 10 50 ns

154 SMRXD/SMSYNC setu p time 20 — ns

155 RXD1/SMSYNC hol d ti me 5 — ns

TCLK3

128

TxD3

(Output)

128

TENA(RTS3)

(Input)

Notes:

Transmi t clock invert (TCI) b it in GSM R is set .

If RENA is negated before TENA or RENA is not asserted at all during transmit, then the

CSL bit is set i n the buffer descriptor at th e end of th e frame trans mission.

RENA(CD3)

(Input)

133 134

132

131 121

129

(Note 2)

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

62 Freescale Semiconductor

CP M Electrical Characteristics

Figure 59. SMC T r an sparent Timing Diagram

13.9 SPI Master AC Electrical Specifications

Table 26 provides the SPI master timings as shown in Figure 60 and Figure 61.

Ta ble 26. S P I Master Timin g

Num Characteristic All Frequencies Unit

Min Max

16 0 Master cycle time 4 1024 tcyc

161 Master clock (SCK) high or lo w ti m e 2 512 tcyc

162 Master data setup time (inputs) 15 — ns

163 Master data hold time (inputs) 0 — ns

164 Master data valid (after SCK edge ) — 10 ns

165 Master data hold time (outputs) 0 — ns

166 Rise time output — 15 ns

167 Fall time output —15ns

SMCLK

SMRXD

(Input)

152

150

SMTXD

(Output)

152 151

SMSYNC

151

154 153

155

154

155

Note 1

Note:

This del ay is equal to an integer number of character-l ength cloc ks.1.

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 63

CPM Electrical Characterist ics

Figure 60. SPI Master (CP = 0) Timing Diagram

Figure 61. SPI Master (CP = 1) Timing Diagram

SPIMOSI

(Output)

SPICLK

(CI = 0)

(Output)

SPICLK

(CI = 1)

(Output)

SPIMISO

(Input)

162

Data

166167161

161 160

msb lsb msb

msb Data lsb msb

167 166

163

166

167

165 164

SPIMOSI

(Output)

SPICLK

(CI = 0)

(Output)

SPICLK

(CI = 1)

(Output)

SPIMISO

(Input)

Data

166167161

161 160

msb lsb msb

msb Data lsb msb

167 166

163

166

167

165 164

162

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

64 Freescale Semiconductor

CP M Electrical Characteristics

13.10 SPI Slave AC Electrical Specifications

Table 27 provides the SPI slave timings as shown in Figure 62 and Figure 63.

Figure 62. SPI Slave (CP = 0) Timing Diagram

Ta ble 27. S P I Slave Timing

Num Characteristic All Frequencies Unit

Min Max

170 Slave cycle time 2—t

cyc

171 Slave enable lead time 15 — ns

172 Slave enable lag time 15 — ns

173 Sla ve clock ( SPICLK) high or low time 1 — tcyc

174 Slave sequential transfer delay (does not require deselect) 1 — tcyc

175 Slave data setup time (inputs) 20 — ns

176 Slave data hold tim e (i nputs) 20 — ns

177 S lave ac ce ss t ime — 50 n s

SPIMOSI

(Input)

SPICLK

(CI = 0)

(Input)

SPICLK

(CI = 1)

(Input)

SPIMISO

(Output)

180

Data

181182173

173 170

msb lsb msb

181

177 182

175 179

SPISEL

(Input)

171172

174

Datamsb lsb msbUndef

181

178

176 182

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 65

CPM Electrical Characterist ics

Figure 63. SPI Slave (CP = 1) Timing Diagram

13.11 I2C AC Electrical Specifications

Table 28 provides the I2C (SCL < 100 kHz) timings.

Ta ble 28. I2C Timing (SCL < 100 kHZ)

Num Characteristic All Frequencies Unit

Min Max

200 SCL clock frequency (slave) 0 100 kHz

20 0 SCL clock frequency (master)11.5 100 kHz

202 Bus free time between transm issions 4.7 — μs

203 Low per iod of SCL 4.7 — μs

204 H igh per iod o f SC L 4. 0 — μs

205 Star t condition setup time 4.7 — μs

206 Star t condition hold tim e 4.0 — μs

207 D a ta hol d ti m e 0—μs

208 D a ta se tup tim e 250 — ns

209 SDL/SCL rise time — 1 μs

SPIMOSI

(Input)

SPICLK

(CI = 0)

(Input)

SPICLK

(CI = 1)

(Input)

SPIMISO

(Output)

180

Data

181182

msb lsb

181

177 182

175 179

SPISEL

(Input)

174

Data

msb lsbUndef

178

176 182

msb

172

173

171 170

181

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

66 Freescale Semiconductor

CP M Electrical Characteristics

Table 29 provides the I2C (SCL > 100 kHz) timings.

Figure 64 shows the I2C bus timing.

Figure 6 4. I 2C Bus Timin g Diag ram

210 SDL/SCL fall time — 300 ns

211 Stop conditi on setup time 4.7 — μs

1SCL frequency is giv en by SCL = BRGCLK_frequency/((BRG register + 3) ×pre_scalar ×2).

The ratio SYNCCLK/(BRGCLK/pre_scalar) must be greater than or equal to 4/1.

Ta ble 29. I2C Timing (SCL > 100 kHZ)

Num Characteristic Expression All Frequencies Unit

Min Max

200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz

20 0 SCL clock frequency (master)1

1SCL frequency is giv en by SCL = BRGCLK_frequency/((BRG register + 3) ×pre_scalar ×2).

The ratio SYNCCLK/(BRGCLK/pre_scalar) must be greater than or equal to 4/1.

fSCL BRGCLK/16512 BRGCLK/48 Hz

202 Bus free time between transm issions — 1/(2.2 ×fSCL) — s

203 Low peri od of SCL — 1/(2.2 ×fSCL) — s

204 H igh per iod o f SC L — 1/(2 . 2 ×fSCL) — s

205 Star t condition setup time — 1/(2.2 ×fSCL) — s

206 Star t condition hold tim e — 1/(2.2 ×fSCL) — s

207 D a ta hol d ti m e — 0 — s

208 D a ta se tup tim e — 1/(40 ×fSCL) — s

209 S D L/ SCL r i s e ti m e — — 1/ (10 ×fSCL) s

210 S D L/ SCL fall ti m e — — 1/ (33 ×fSCL) s

211 Stop conditi on setup time — 1/2(2.2 ×fSCL) — s

Table 28. I2C Timing (SCL < 100 kHZ) (con tinued)

Num Characteristic All Frequencies Unit

Min Max

SCL

202

205

203

207

204

208

206 209 211210

SDA

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 67

USB Electrical Ch aracteristics

14 U SB Elect rical Characteristics

This section provides the AC timings for the USB interfac e.

14.1 USB Interface AC T iming Specification s

The USB Port uses the tr ans m it clock on SCC1. Table 30 lists the USB interface timings .

15 FEC Elec trical Characteristi cs

This section provides the AC electri cal specifications for the Fast Ethernet controller (FEC). Note that the

timing specifications for the M II signals are independent of system clock frequency (part speed

designation). Also, M II signals use TTL signal levels compatible with devices operating at either 5.0 or

3.3 V.

15.1 MII and Reduced MII Receive Signal Timing

The receiver functions cor rectly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. The

reduced MII (RMII) r eceiver functions correctly up to a RMII_REFCLK maximum f requency of 50 MHz

+ 1%. There is no minimum frequency requirement. In addition, the processor clock f r equency must

exceed the MII_RX_CLK frequency – 1%.

Table 31 provid es information on the MII rec eiv e signal timing.

Table 30. USB Interface AC Timi ng Spec ifications

Name Characteristic All Frequencies Unit

Min Max

US1 USBCLK frequency of oper ati on 1

Low speed

F ull speed

1USBCLK accuracy shoul d be ±500 ppm or bet ter. USBCLK may be stopped to conserve power.

MHz

US4 USBCLK duty cycle (measure d at 1.5 V) 45 55 %

Table 31. MII Receive Signal Timing

Num Characteristic Min Max Unit

M1 MII_RXD[3:0], MII _RX_DV, MII_RX_ER t o MII_RX_CLK set up 5 — ns

M2 MII_RX_CLK t o MII_ RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns

M3 MII_RX_CLK pul se width high 35% 65% MII_RX_CLK period

M4 MII_RX_CLK pulse width low 35% 65% M II _RX_CLK peri od

M1_RMII R MII _RXD[1 :0] , RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK

setup 4— ns

M2_RMII RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR

hold 2— ns

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

68 Freescale Semiconductor

FEC Electrical Characteristics

Figure 65 shows MII re ceive signal timing.

Figure 65. M I I Receive Sig nal Timing Diagra m

15.2 MII and Reduced MII Transmit Signal Timing

The transmitter functions correctly up to a MII_TX_CLK maximum fr equency of 25 MHz + 1%. There is

no minimum frequency requirement. In addition, the processor clock frequency must exceed the

MII_TX_CLK frequency – 1%.

Table 32 provid es information on the MII trans mit signal timing.

Table 32. MII Transmi t Signal Timing

Num Characteristic Min Max Unit

M5 MII_TX_CLK to MII_T XD[3: 0], MII_TX_EN, MII_TX_ER in valid 5 — ns

M6 MII_TX_CLK to MII_T XD[3:0], MII_TX_EN, MII _TX_ER valid — 25 ns

M7 MII_TX_CLK pul se width high 35% 65% MII_TX_CLK period

M8 MII_TX_CLK pul se width low 35% 65% MII_TX_CLK period

M 20 _ RM I I RMII_ T X D[1 :0 ], RM II _ TX _ E N to RMII_ R EF C L K se tu p 4 — n s

M21_RMII RM II_TXD[1:0], RMII _TX_EN data hold from RMII _REFCLK rising

edge 2— ns

M1 M2

MII_R X_CLK (Input)

MII_R XD[3:0] (Inputs)

MII_RX_DV

MII_RX_ER

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 69

FEC Electrical Characteristics

Figure 66 shows the M II trans mit signal timing diagra m.

Figure 66. MII Transmit Sig nal Timing Diagram

15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 33 provid es information on the MII async inputs signal timing.

Figure 67 shows the MII asynchronous inputs signal timing diagram.

Figure 67. MII Async In puts Timing Diagram

15 .4 MII Serial Management Chann e l Timing (MII_MDIO, MII_MDC)

Table 34 provides information on t he MII seri al management channel signal timing. The FEC functions

correctly with a maximum MDC frequency in excess of 2.5 MHz.

Table 33. MII Async Inp uts Signal Timing

Num Characteristic Min Max Unit

M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period

Table 34 . M I I S eri a l Ma nagem ent Channel Tim in g

Num Characteristic Min Max Unit

M10 MII_MDC falling edge to MII_MDIO output invalid (minimum propagation

delay) 0— ns

M11 MII_MDC fall ing edge to MII_MDIO output valid (max prop delay) — 25 ns

M12 MII_MDIO (i nput) to MII_MDC rising edge setup 10 — ns

M13 MII_MDIO (i nput) to MII_MDC rising edge hol d 0 — ns

M14 MII_MDC pulse width high 40% 60% MII_MDC period

M15 MII_MDC pulse width low 40% 60% MII_MDC peri od

MII_TX_CLK (Input)

MII_TXD [3:0] (Outputs)

MII_TX_EN

MII_TX_ER

MI I_ C R S, MI I_ C OL

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

70 Freescale Semiconductor

FEC Electrical Characteristics

Figure 68 shows the MII serial mana gem ent channel timing diagram.

Figure 68. MII Serial Management Channel Timing Diagram

M11

MII_MDC (Out put)

MII_MD IO (Output)

M12 M13

MII_MD IO (I nput)

M10

M14

MM15

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 71

Mec han ic al Data and Or deri ng Info r ma tion

16 Mechani cal Data and Ordering Information

Table 35 identifies the packages and oper ating frequencies available for the MPC875/MPC870.

Table 35. Available MPC875 /M PC 870 Packages/Freq uencie s

P ackage Type Temper ature (TJ) Frequency (MHz) Order Number

Plast i c ball gr i d array

ZT suffix—Leaded

VR suffix—L ead-Free are available as needed

0°C to 95°C 66 KMPC875ZT66

KMPC870ZT66

MPC875ZT66

MPC870ZT66

80 KMPC875ZT80

KMPC870ZT80

MPC875ZT80

MPC870ZT80

133 KMPC875ZT133

KMPC870ZT133

MPC875ZT133

MPC870ZT133

Plast i c ball gr i d array

CZT suffix—Leaded

CVR suffix—L ead-Free are available as needed

-40°C to 1 00°C 66 KMPC875CZT66

KMPC870CZT66

MPC875CZT66

MPC870CZT66

133 KMPC875CZT133

KMPC870CZT133

MPC875CZT133

MPC870CZT133

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

72 Freescale Semiconductor

Mec han ic al Data and Ord eri ng Informa tion

16.1 Pin Assignments

Figure 69 s hows the JEDEC pinout of the PBGA package as viewed from the t op surface. For additional

information, see the MPC885 PowerQUICC Family User’s Manual.

NOTE

The pin numbering starts with B2 in order to conform to the JEDEC standard for

23-mm body size using a 16 ×16 arra y.

NOTE: This is the top view of the device.

Figur e 69. Pinout of the PBGA Package—JEDE C Standard

MODCK2

IPA7

IPA4

D31

D29

D18

D11

D10

N/C

EXTCLK MODCK1 OP0 ALEA IPB0 BURST IRQ6 BR TEA BI CS0 CS3 CS5 N/C

RSTCONFSRESET BADDR29 OP1

XTAL

IPA2 WAITA PORESET EXTAL BADDR30 IPB1 BG GPLA4 GPLA5 WR CE2A CS7 WE2

IPA5 IPA3 VDDSYN

AS ALEB IRQ2 BB

HRESETBADDR28 IRQ3

D30 IPA6

TS TA BDIP CS2 CE1A GPLAB3 GPLA0

CS1 GPLB4 CS4 GPLAB2 WE0 BSA1 BSA2

D28 CLKOUT

D22 D6 D24

D19 D20

D15 D16

D2 D27

D9 D12

D23 D17 PE22

D4 D8 PE25

TSIZ0 A31

A22 A18

A25 A24

A20 A29

A27 A17

A15 A16

A11 A13

A7 A9

A5 A4

A0 PB29

VDDH

PE26 PD8 PA1 N/C PB30PE27

PE20 PE23 MII-TX-EN

PE17 PE21 PC7 PB19 PB24 TDI TMS PC12

PA14 N/C

PE15

PE29 PE24 PC13 MII-CRS PC10 PB23 PB25 TRST GND

PE16

234567 8910111213141516

IPA1

D26

D25

D14

PE18

IRQ7

IRQ1

PA3

PB31

PA0 PE14 PE31 PC6 PA6 PC11 TDO PA15 A3PA4

PE28 PE30 PA11 MII_COL PA7 TCK PB28 PC15PE19

BSA0 BSA3

TSIZ1 A26

A28 A30

A23 A21

A14 A19

A10 A12

A2 A8

A1 A6

IRQ4VSSSYN

WE1

PA10

D13

D21

VSSSYN1 CS6 OE

PA2 PB26 PB27

TEXP

IRQ0

IPA0

MII_MDIO

WE3

VDDH VDDH

VDDH

VDDL VDDL

VDDL

VDDL GND

GND

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 73

Mec han ic al Data and Or deri ng Info r ma tion

Table 36 contains a list of the MPC875/MPC870 input and output signals and s hows multiplexing and pin

assignments.

Table 36. Pin Assignments—J EDEC Stand ard

Name Pi n Numb er Type

A[0:31] R16, N14, M14, P15, P17, P16 , N15, N16, M15, N17, L14, M16,

L15, M17, K14, L16, L17, K17, G1 7, K15, J16, J15, G16, J14, H17,

H16, G15, K16, H14, J17, H15, F17

Bidirectional

Three-state (3.3 V only)

TSIZ0, REG F16 Bidirectional

Three-state (3.3 V only)

TSIZ1 G14 Bidirectional

Three-state (3.3 V only)

RD/WR D13 Bidirectional

Three-state (3.3 V only)

BURST B9 Bidirectional

Three-state (3.3 V only)

BDIP, GPL_B5 C13 Output

TS C11 Bidirectional

Activ e pull-up (3.3 V only)

TA C12 Bidirectional

Activ e pull-up (3.3 V only)

TEA B12 Open-drain

BI B13 Bidirectional

Activ e pull-up (3.3 V only)

IRQ2, RS V C9 Bidirectional

Three-state (3.3 V only)

IRQ4, K R , R ET RY,

SPKROUT E9 Bidirectional

Three-state (3.3 V only)

D[0:31] L5, N3, L3, L2, R2, K2, H3, G2, R3, M3, N2, M2, M4, N4, K5, K3, K4,

P3, J2, J3, J4, J5, H2, P2, H4, H5, G5, L4, G3, F2, F3, E2 Bidirectional

Three-state (3.3 V only)

CR, IRQ3 E10 Input

FRZ, IRQ6 B10 Bidirectional

Three-state (3.3 V only)

BR B11 Bi directional (3.3 V only)

BG D10 Bidirectional (3.3 V only)

BB C10 Bidirectional

Activ e pull-up (3.3 V only)

IRQ0 M6 Input (3 .3 V only)

IRQ1 P5 Input (3.3 V o n ly)

IRQ7 N5 Inpu t (3.3 V o n ly)

CS[0:5] B14, E11, C14, B15, E13, B16 Out put

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

74 Freescale Semiconductor

Mec han ic al Data and Ord eri ng Informa tion

CS6, CE1_B F12 Output

CS7, CE2_B D15 Output

WE0, BS_B0, IORD E15 Output

WE1, BS_B1, IOWR D17 Output

WE2, BS_B2, PCOE D16 Output

WE3, BS_B3, PCWE G13 Output

BS_A[0:3] F14, E16, E17, F15 Output

GPL_A0, GPL _B 0 C17 Output

OE, GPL_A1, GPL _B 1 F13 Output

GPL_A[2:3], GPL_B[2:3],

CS[2–3] E14, C16 Output

UPWAITA, GPL_A4 D11 Bidirectional (3.3 V only)

UPWAITB, GPL_B4 E12 Bidirectional

GPL_A5 D12 Output

PORESET D5 Input ( 3 .3 V only )

RSTCONF C3 Input ( 3 .3 V only )

HRESET E7 Open-drain

SRESET C4 Open-drain

XTAL D6 Analog output

EXTAL D7 Anal og input (3.3 V only)

CLKOUT G4 Output

EXTCLK B4 Input ( 3.3 V onl y)

TEXP B3 Output

ALE_A B7 Output

CE1_A C15 Output

CE2_A D14 Output

WAIT_A D4 Input (3 .3 V only )

IP_A0 G6 Input (3.3 V only)

IP_A1 F5 Input ( 3.3 V onl y)

IP_A2, IOI S 16_A D3 Input ( 3 .3 V only )

IP_A3 E4 Input (3.3 V onl y)

IP_A4 D2 Input (3.3 V onl y)

IP_A5 E3 Input (3.3 V onl y)

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pi n Numb er Type

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 75

Mec han ic al Data and Or deri ng Info r ma tion

IP_A6 F4 Input ( 3.3 V onl y)

IP_A7 C2 Input (3.3 V onl y)

ALE_B, DSCK C8 Bidirectional

Three-state (3.3 V only)

IP_B[0:1], IWP[0:1],

VFLS[0:1] B8, D9 Bidirectional (3.3 V only)

OP0 B6 Bidirectional (3.3 V only)

OP1 C6 Output

OP2, MODCK1, STS B5 Bidirectional (3.3 V only)

OP3, MODCK2, DSDO B2 Bidirectional (3.3 V only)

BADDR[28:29] E8, C5 Output

BADDR30, REG D8 Output

AS C7 Input ( 3 .3 V only )

PA15, USBRXD P14 Bid ir ectional

PA14, USBOE U16 Bidirect ional

(Opti onal: open-drain)

PA11 , RXD4, MII1-TXD0,

RMII1-TXD0 R9 Bidirectional

(Opti onal: open-drain)

(5-V tolerant)

PA10 , MII1- TXERR, TIN4,

CLK7 R12 Bidirectional

(Opti onal: open-drain)

(5-V tolerant)

PA7, CLK1, BRGO1, TIN1 R11 Bi directional

PA6, CLK2, TOUT1 P11 Bidirectional

PA4, CTS4, MII1-TXD1,

RMII-TXD1 P7 Bidirectional

PA3, MII1-RXER,

RMII1-RXER, BRGO3 R5 Bidirectional

(5-V tolerant)

PA2, MII1-RXDV,

RMII1-CRS_DV, TXD4 N6 Bidirectional

(5-V tolerant)

PA1, MII1-RXD0,

RMII1-RXD0, BRGO4 T4 Bidirectional

(5-V tolerant)

PA0, MII1-RXD1,

RMII1-RXD1, T O UT4 P6 Bidirectional

(5-V tolerant)

PB31, SPI SEL, MII1-TXCLK,

RMII1-REFCLK T5 Bidirectional

(Opti onal: open-drain)

(5-V tolerant)

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pi n Numb er Type

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

76 Freescale Semiconductor

Mec han ic al Data and Ord eri ng Informa tion

PB30, SPICLK T17 Bidirectional

(Opti onal: open-drain)

(5-V tolerant)

PB29, SPIMOSI R17 Bidirectional

(Opti onal: open-drain)

(5-V tolerant)

PB28, SPIMISO, BRGO4 R14 Bidi rectional

(Opti onal: open-drain)

(5-V tolerant)

PB27, I2CSDA, BRGO1 N13 Bi directional

(Opti onal: open-drain)

PB26, I2CSCL, BRGO2 N12 Bidirectional

(Opti onal: open-drain)

PB25, SMTXD1 U13 Bidirectional

(Opti onal: open-drain)

(5-V tolerant)

PB24, SMRXD1 T12 Bidirectional

(Opti onal: open-drain)

(5-V tolerant)

PB23, SDACK1, SMSYN1 U12 Bidirectional

(Opti onal: open-drain)

PB19, MII1-RXD3, RTS4 T11 Bidirectional

(Opti onal: open-drain)

PC15, DREQ0, L1ST1 R15 Bidirectional

(5-V tolerant)

PC13, MII1-TXD3, SDACK1 U9 Bi directional

(5-V tolerant)

PC12, MII1-TXD2, TOUT1 T15 Bidirectional

(5-V tolerant)

PC11, USBRXP P12 Bidi rectional

PC10, USBRXN, TGATE1 U11 Bidirectional

PC7, CTS4, L1TSYNCB ,

USBTXP T10 Bidirectional

(5-V tolerant)

PC6, CD4, L1 RSYNCB,

USBTXN P10 Bidirectional

(5-V tolerant)

PD8, RXD4, MII-MDC,

RMII-MDC T3 Bidirectional

(5-V tolerant)

PE31, CLK8, L1TCLKB,

MII1-RXCLK P9 Bidirectional

(Opti onal: open-drain)

PE30, L1RXDB, M II1-RXD2 R8 Bidi rectional

(Opti onal: open-drain)

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pi n Numb er Type

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 77

Mec han ic al Data and Or deri ng Info r ma tion

PE29, MII2-CRS U7 Bidirectional

(Opti onal: open-drain)

PE28, TOUT3, MII2-COL R7 Bidi rectional

(Opti onal: open-drain)

PE27, L1RQB , MII2-RXERR,

RMII2-RXERR T6 Bidirectional

(Opti onal: open-drain)

PE26, L1CLKOB,

MII2-RXDV, RMII2-CRS_DV T2 Bidirectional

(Opti onal: open-drain)

PE 2 5 , RX D 4 , M II2 - R X D3 ,

L1ST2 R4 Bidirectional

(Opti onal: open-drain)

PE24, SMRXD1, BRGO1,

MII2-RXD2 U8 Bidirectional

(Opti onal: open-drain)

PE23, TXD4, MII2-RXCLK,

L1ST1 U4 Bidirectional

(Opti onal: open-drain)

PE22, TOUT2, MII2-RXD1,

RMII2-RXD1, SDACK1 P4 Bidirectional

(Opti onal: open-drain)

PE21, TOUT1, M II 2-RX D 0 ,

RMII2-RXD0 T9 Bidirectional

(Opti onal: open-drain)

PE20, MII2-TXER U3 Bidirectional

(Opti onal: open-drain)

PE19, L1TXDB, MII2-TXEN,

RMII2-TXEN R6 Bidirectional

(Opti onal: open-drain)

PE18, SMTXD1, MII2-TXD3 M5 Bidirectional

(Opti onal: open-drain)

PE17, TIN3, CLK5, BRGO3,

SMSYN1, MII2-TXD2 T8 Bidirectional

(Opti onal: open-drain)

PE16, L1RCLKB, CLK6,

MII2-TXCLK, RMII2-REFCLK U6 Bidirectional

(Opti onal: open-drain)

PE15, TGATE1, MII 2 -T X D 1 ,

RMII2-TXD1 T7 Bidirectional

PE14, MII2-TXD0,

RMII2-TXD0 P8 Bidirectional

TMS T14 Input

(5-V tolerant)

TDI, DSDI T13 Input

(5-V tolerant)

TCK, DSCK R13 Input

(5-V tolerant)

TRST U14 Input

(5-V tolerant)

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pi n Numb er Type

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

78 Freescale Semiconductor

Mec han ic al Data and Ord eri ng Informa tion

TDO, DSDO P13 Output

(5-V tolerant)

MII1_CRS U10 Input

MII_MDIO M13 Bidirectional

(5-V tolerant)

MII1_TX_EN, RMII 1_TX_EN U5 Output

(5-V tolerant)

MII1_COL R10 Input

VSSSYN E5 PLL analog GND

VSSSYN1 F6 PLL analog GND

VDDSYN E6 PLL analog VDD

GND H8, H9, H10, H11, J8, J9, J10, J11, K8, K9, K10, K11, L8, L9, L10,

L11, U15 Power

VDDL F7, F8, F9, F10, F11, H6, H13, J6, J13 , K6, K13, L6, L13, N7, N8,

N9, N10, N11 Power

VDDH G7, G8, G9, G10, G11, G12, H7, H12, J7, J12, K7, K12, L7, L12, M7,

M8, M9, M10, M11, M12 Power

N/C B17, T16, U2, U17 No connect

Table 36. Pin Assignments—JEDEC Standard (continued)

Name Pi n Numb er Type

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 79

Mec han ic al Data and Or deri ng Info r ma tion

16.2 Mechanical Dimensions of the PBGA Package

Figure 70 shows the mechanical dimensions of the PBGA package.

Figure 70. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package

Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC875/MPC870VRXXX.

Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC875/MPC870ZTXXX.

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994.

3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

NOTES:

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

80 Freescale Semiconductor

Docume nt Revision Hist ory

17 D ocument Revision H istory

Table 37 lists significant changes between revisions of this hardwar e specification.

Table 37. Documen t Revision History

Revision

Number Date Changes

0 2/2003 Initial release.

0.1 3/2003 Took out the tim e-slot assigner and changed the SCC for SCC3 to SCC4.

0.2 5/2003 Changed the package drawing, removed all references to Data P arity. Changed the SPI Master Timing

Specs. 1 62 and 164. Added the RMII and USB tim ing. Added the 80-MHz timi ng.

0.3 5/2003 Made sure the pin types were correct. Changed the Features list to agree with the MPC885.

0.4 5/2003 Corrected the signals that had overlines on them. Made corrections on two pins that were typos.

0.5 5/2003 Changed the pi n descri ptions for PD8 and PD9.

0.6 5/2003 Changed a few typos. Put bac k the I2C. Put in the ne w reset configurat ion, corrected the USB timing.

0.7 6/2003 Changed the pi n descriptions per the June 22 spec, removed Utopia from the pin descri pti ons,

changed PADIR, PBDIR, PCDIR and PDDIR to be 0 in the M andatory Reset Config.

0.8 8/2003 Added the referenc e to USB 2.0 to the F eatures list and remov ed 1. 1 from USB on the b lock diagrams.

0.9 8/2003 Changed the USB description to full-/low-speed compatible.

1.0 9/2003 Added the DSP informa ti on in the Featur es li st.

Put a new sentence under Mechanical Dimensions.

Fixed tab le formattin g.

Nontechnical edits .

Released to the external web.

1.1 10/2003 Added TDMb to the MPC875 Featur es li st, the MPC875 Blo ck Diagram, added 13.5 Serial Interfa ce

AC Electrical Specifications, and removed TDMa from the pin descripti ons.

2.0 12/2003 Changed DBGC i n the Mandatory Reset Configurati on to X1.

Changed the maximum operating frequency to 133 MHz.

Put the timing in the 80 MHz column.

Put in the orderable part numbers.

Rounded the timings to hundredths in the 80 MHz column.

Put the pi n num bers in footnotes by the maximum currents in Tabl e 6.

Changed 22 and 41 in the Timing.

Put TBD in the Thermal table.

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 81

Document Revision History

3.0 1/07/2004

7/19/2004 • Added senten ce to Spec B1A about EXTCLK and CLKOUT being in alignment for integer values .

• Added a footnote to Spec 41 specifying th at EDM = 1.

• Added the thermal numbers to Table 4.

• Added RMII1_EN under M1II_EN in Table 36, Pin Assignments.

• Added a table footnote to Table 6, DC Electrica l Specificat ions, about meeti ng the VIL Max of the

I2C Standard.

• Put the new par t num bers in the Ordering Information Section.

4 08/2007 • Updated t emplate.

• On page 1, updated first paragraph and added a second paragr aph.

• After Table 2, inserted a new figure showing the undershoot/overshoot voltage (Figure 3) and

renumbered the rest of the figures.

•In Table 10, f or reset ti mings B29f and B29g added f ootnote indicat ing that the f ormula only applies

to bus operati on up to 50 MHz.

•In Figure 5, cha nged all reference v oltage measure me nt poi nts from 0.2 and 0.8 V to 50% leve l.

•In Table 18, changed num 46 description to read, “TA assertion to rising edge ...”

•In Figure 43, changed TA to reflect the rising ed ge of t he clock.

Table 37. Document Revisi on History (continued)

Revision

Number Date Changes

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

82 Freescale Semiconductor

Docume nt Revision Hist ory

THIS PAGE INTENTIONALLY LEFT BLANK

MPC875 /MPC870 Power Q UICC™ Har dware Specif ications, Re v. 4

Freescale Semiconductor 83

Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

Document Number: MPC875EC

Rev. 4

08/2007

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