Z80C30/Z85C30 CMOS SCC Serial Communications Controller Product Specification PS011705-0608 Copyright (c)2008 by Zilog(R), Inc. All rights reserved. www.Zilog.com CMOS SCC Serial Communications Controller Product Specification ii Warning: DO NOT USE IN LIFE SUPPORT LIFE SUPPORT POLICY Zilog'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF Zilog CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer (c)2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. Zilog, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. Zilog ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS011705-0608 CMOS SCC Serial Communications Controller Product Specification iii Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. PS011705-0608 Date Revision Level Description Page No June 2008 05 Updated Zilog logo, Zilog Text, Disclaimer as per latest template. All September 2004 01 Original issue All Revision History CMOS SCC Serial Communications Controller Product Specification iv Table of Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Other Features for Z85C30 Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30/Z80C30 Common Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 9 9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Interface Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30/Z80C30 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 27 27 28 28 34 37 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30/Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 Read/Write Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 41 41 42 43 43 43 44 44 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 PS011705-0608 Table of Contents CMOS SCC Serial Communications Controller Product Specification 1 Overview The features of Zilog's Z80C30 and Z85C30 devices include: * * * * PS011705-0608 Z85C30 -- Optimized for Non-Multiplexed Bus Microprocessors. Z80C30 -- Optimized for Multiplexed Bus Microprocessors. Pin Compatible to NMOS Versions. Two Independent, 0 to 4.1 Mbit/Second, Full-Duplex Channels. Each channel with Separate Crystal Oscillator, Baud Rate Generator (BRG), and Digital Phase-Locked Loop (DPLL) for Clock Recovery. * Multi-Protocol Operation under Program Control; Programmable for NRZ, NRZI, or FM Data Encoding. * Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two Stop Bits Per Character, Programmable Clock Factor, Break Detection and Generation; Parity, Overrun, and Framing Error Detection. * Synchronous Mode with Internal or External Character Synchronization on One or Two Synchronous Characters and CRC Generation and Checking with CRC-16 or CRC-CCITT Preset to either 1s or 0s. * SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero Insertion and Deletion, I-Field Residue Handling, Abort Generation and Detection, CRC Generation and Checking, and SDLC Loop. * * * * Software Interrupt Acknowledge Feature (not available with NMOS). * Speeds: - Z85C3O -- 8.5, 10, 16.384 MHz - Z80C3O -- 8, 10 MHz Local Loopback and Auto Echo Modes. Supports T1 Digital Trunk. Enhanced DMA Support (not available with NMOS) 10 x 19-Bit Status FIFO 14-Bit Byte Counter. Overview CMOS SCC Serial Communications Controller Product Specification 2 Other Features for Z85C30 Only Some of the features listed below are available by default. Some of them (features with *) are disabled on default to maintain compatibility with the existing Serial Communications Controller (SCC) design, and "program to enable through WR7": PS011705-0608 * * New programmable WR7 (Write register 7 prime) to enable new features. * Improved AC timing: - 3 to 3.6 PCLK access recovery time. - Programmable DTR/REQ timing.* - Write data to falling edge of WR setup time requirement is now eliminated. - Reduced INT timing. * Other features include: - Extended Read function to read back the written value to the Write registers.* - Latching RRO during read. - RRO, bit D7 and RR10, bit D6 now has reset default value. Improvements to support SDLC mode of synchronous communication: - Improve functionality to ease sending back-to-back frames. - Automatic SDLC opening Flag transmission.* - Automatic Tx Underrun/EOM Latch reset in SDLC mode.* - Automatic RTS deactivation.* - TxD pin forced High in SDLC NRZI mode after closing flag.* - Complete CRC reception.* - Improved response to Abort sequence in status FIFO. - Automatic Tx CRC generator preset/reset. - Extended Read for Write registers.* - Write data set-up timing improvement. Overview CMOS SCC Serial Communications Controller Product Specification 3 PS011705-0608 Overview CMOS SCC Serial Communications Controller Product Specification 4 General Description The Z80C30/Z85C30 Serial Communications Controller (SCC), is a pin and software compatible CMOS member of the SCC family introduced by Zilog(R) in 1981. It is a dual channel, multi-protocol data communications peripheral that easily interfaces with CPU's with either multiplexed or non-multiplexed address/data buses. The advanced CMOS process offers lower power consumption, higher performance, and superior noise immunity. The programming flexibility of the internal registers allow the SCC to be configured to various serial communications applications. Figure 1 displays a block diagram of the SCC. The many on-chip features such as Baud Rate Generators (BRG), Digital Phase Locked Loops (DPLL), and crystal oscillators reduce the need for an external logic. Additional features include a 10 x 19-bit status FIFO and 14-bit byte counter to support high speed SDLC transfers using DMA controllers. The SCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This device supports virtually any serial data transfer application (for example, cassette, diskette, tape drives, etc.). The device generates and checks CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The SCC also contains facilities for modem controls in both channels. In applications where these controls are not required, the modem controls can be used for general-purpose I/O. The daisy-chain interrupt hierarchy is also supported. PS011705-0608 General Description CMOS SCC Serial Communications Controller Product Specification 5 Transmit Logic Transmit MUX Transmit Buffer TxDA Data Encoding & CRC Generation Channel A Exploded View Receive and Transmit Clock Multiplexer TRxCA RTxCA Crystal Oscillator Amplifier Digital Baud Rate Phase-Locked Generator Loop CTSA DCDA Modem/Control Logic SYNCA RTSA DTRA/REQA Receive Logic Rec. Status Rec. Status FIFO 3 Byte FIFO 3 Byte SDLC Frame Status FIFO 10 X 19 Databus Receive MUX RxDA CRC Checker Data Decode & Sync Character Detection Interrupt Control Logic Channel A Register Interrupt Control Logic Channel B Register Channel A CPU & DMA Bus Interface Control Interrupt Control INT INTACK IEI IEO Channel B Figure 1. SCC Block Diagram PS011705-0608 General Description CMOS SCC Serial Communications Controller Product Specification 6 Pin Descriptions Z85C30/Z80C30 Common Pin Functions The following sections describe the pin functions common to Z85C30 and Z80C30 devices: * * * * * * * * * * * * * * * CTSA, CTSB DCDA, DCDB DTR/REQA, DTR/REQB IEI IEO INT INTACK PCLK RxDA, RxDB RTxCA, RTxCB RTSA, RTSB SYNCA, SYNCB TxDA, TxDB TRxCA, TRxCB W/REQA, W/REQB Each pin function is described below. CTSA, CTSB Clear To Send (inputs, active Low) -- If these pins are programmed for Auto Enable, a Low on the inputs enables the respective transmitters. If not programmed as Auto Enable, these pins can be used as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate slow rise-time inputs. The SCC detects pulses on these inputs and can interrupt the CPU on both logic level transitions. DCDA, DCDB Data Carrier Detect (inputs, active Low) -- These pins function as receiver enables if programmed for Auto Enable. Otherwise, these pins are used as general-purpose input pins. Both pins are Schmitt-trigger buffered to accommodate slow rise-time signals. The SCC detects pulses on these pins and can interrupt the CPU on both logic level transitions. PS011705-0608 General Description CMOS SCC Serial Communications Controller Product Specification 7 DTR/REQA, DTR/REQB Data Terminal Ready/Request (outputs, active Low) -- These outputs follow the state programmed into the DTR bit. They can also be used as general-purpose outputs or as Request lines for a DMA controller. IEI Interrupt Enable In (input, active High) -- IEI is used with IEO to form an interrupt daisy-chain when there is more than one interrupt driven device. A high IEI indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. IEO Interrupt Enable Out (output, active High) -- IEO is High only if IEI is High and the CPU is not servicing the SCC interrupt or the SCC is not requesting an interrupt (interrupt Acknowledge cycle only). IEO is connected to the next lower priority device's IEI input and thus inhibits interrupts from lower priority devices. INT Interrupt Request (output, open-drain, active Low) -- This signal activates when the SCC requests an interrupt. INTACK Interrupt Acknowledge (input, active Low) -- This signal indicates an active Interrupt Acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When RD is active, the SCC places an interrupt vector on the data bus (if IEI is High). INTACK is latched by the rising edge of PCLK. PCLK Clock (input) -- This is the master SCC clock used to synchronize internal signals. PCLK is a TTL level signal. PCLK is not required to have any phase relationship with the master system clock. The maximum transmit rate is 1/4 PCLK. RxDA, RxDB Receive Data (inputs, active High) -- These signals receive serial data at standard TTL levels. RTxCA, RTxCB Receive/Transmit Clocks (inputs, active Low) -- These pins can be programmed in several different operating modes. In each channel, RTxC can supply the receive clock, the transmit clock, clock for the Baud Rate Generator, or the clock for the Digital PhaseLocked Loop. These pins can also be programmed for use with the respective SYNC pins as a crystal oscillator. The receive clock can be 1, 16, 32, or 64 times the data rate in Asynchronous modes. PS011705-0608 General Description CMOS SCC Serial Communications Controller Product Specification 8 RTSA, RTSB Request To Send (outputs, active Low) -- When the Request To Send (RTS) bit in Write Register 5 (see Figure 9 on page 19) is set, the RTS signal goes Low. When the RTS bit is reset in the Asynchronous mode and Auto Enable is ON, the signal goes High after the transmitter is empty. In Synchronous mode, it strictly follows the state of the RTS bit. When Auto Enable is OFF, the RTS pins can be used as general-purpose outputs. SYNCA, SYNCB Synchronization (inputs or outputs, active Low) -- These pins function as inputs, outputs, or part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal oscillator option not selected), these pins are inputs similar to CTS and DCD. In this mode, transitions on these lines affect the state of the Synchronous/Hunt status bits in Read Register 0 (see Figure 8 on page 17) but have no other function. In External Synchronization mode with the crystal oscillator not selected, these lines also act as inputs. In this mode, SYNC must be driven Low for two receive clock cycles after the last bit in the synchronous character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of SYNC. In the Internal Synchronization mode (Monosync and Bisync) with the crystal oscillator not selected, these pins act as outputs and are active only during the part of the receive clock cycle in which synchronous characters are recognized. This synchronous condition is not latched. These outputs are active each time a synchronization pattern is recognized (regardless of character boundaries). In SDLC mode, these pins act as outputs and are valid on receipt of a flag. TxDA, TxDB Transmit Data (outputs, active High) -- These output signals transmit serial data at standard TTL levels. TRxCA, TRxCB Transmit/Receive Clocks (inputs or outputs, active Low) -- These pins can be programmed in several different operating modes. TRxC may supply the receive clock or the transmit clock in the input mode or supply the output of the Digital Phase-locked loop, the crystal oscillator, the Baud Rate Generator, or the transmit clock in the output mode. W/REQA, W/REQB Wait/Request (outputs, open-drain when programmed for a Wait function, driven High or low when programmed for a Request function) -- These dual-purpose outputs can be programmed as Request lines for a DMA controller or as Wait lines to synchronize the CPU to the SCC data rate. The reset state is Wait. PS011705-0608 General Description CMOS SCC Serial Communications Controller Product Specification 9 Z85C30 A/B Channel A/Channel B (input) -- This signal selects the channel in which the Read or Write operation occurs. CE Chip Enable (input, active Low) -- This signal selects the SCC for a Read or Write operation. D7-D0 Data Bus (bidirectional, tri-state) -- These lines carry data and command to and from the SCC. D/C Data/Control Select (input) -- This signal defines the type of information transferred to or from the SCC. A High indicates a data transfer; a Low indicates a command. RD Read (input, active Low) -- This signal indicates a Read operation and when the SCC is selected, enables the SCC's bus drivers. During the Interrupt Acknowledge cycle, this signal gates the interrupt vector onto the bus if the SCC is the highest priority device requesting an interrupt. WR Write (input, active Low) -- When the SCC is selected, this signal indicates a Write operation. The coincidence of RD and WR is interpreted as a reset. Z80C30 AD7-AD0 Address/Data Bus (bidirectional, active High, Tri-state) -- These multiplexed lines carry register addresses to the SCC as well as data or control information. AS Address Strobe (input, active Low) -- Addresses on AD7-AD0 are latched by the rising edge of this signal. CS0 Chip Select 0 (input, active Low) -- This signal is latched concurrently with the addresses on AD7-AD0 and must be active for the intended bus transaction to occur. PS011705-0608 General Description CMOS SCC Serial Communications Controller Product Specification 10 CS1 Chip Select 1 (input, active High) -- This second select signal must also be active before the intended bus transaction can occur. CS1 must remain active throughout the transaction. DS Data strobe (input, active Low) -- This signal provides timing for the transfer of data into and out of the SCC. If AS and DS coincide, this confluence is interpreted as a reset. R/W Read/Write (input) -- This signal specifies whether the operation to be performed is a Read or a Write. Figure 2 displays the pin assignments for Z85C30 and Z80C30 DIP package. D1 1 40 D0 AD1 1 40 AD0 D3 2 39 D2 AD3 2 39 AD2 D5 3 38 D4 AD5 3 38 AD4 D7 4 37 D6 AD7 4 37 AD6 INT 5 36 RD INT 5 36 DS IEO 6 35 WR IEO 6 35 AS IEI 7 34 A/B IEI 7 34 R/W INTACK 8 33 CE INTACK 8 33 CS0 +5v 9 32 D/C +5v 9 32 CS1 31 GND W/REQA 10 SYNCA Z85C30 Z80C30 W/REQA 10 W/REQB SYNCA 11 30 W/REQB 29 SYNCB RTxCA 12 29 SYNCB 13 28 RTxCB RxDA 13 28 RTxCB TRxCA 14 27 RxDB TRxCA 14 27 RxDB TxDA 15 26 TRxCB TxDA 15 26 TRxCB DTR/REQA 16 25 TxDB DTR/REQA 16 25 TxDB RTSA 17 24 DTR/REQB RTSA 17 24 DTR/REQB CTSA 18 23 RTSB CTSA 18 23 RTSB DCDA 19 22 CTSB DCDA 19 22 CTSB PCLK 20 21 DCDB PCLK 20 21 DCDB 31 GND 11 30 RTxCA 12 RxDA Figure 2. Z85C30 and Z80C30 DIP Pin Assignments PS011705-0608 General Description CMOS SCC Serial Communications Controller Product Specification 11 IEI INTACK 8 1 44 43 42 41 40 39 38 9 6 5 AS DS AD6 AD4 2 AD2 3 4 AD0 INT AD7 AD5 WR RD D6 D4 D2 D0 2 7 AD1 4 3 IEO AD3 5 D1 6 D3 INT D7 D5 Figure 3 displays the pin assignments for Z85C30 and Z80C30 PLCC package. A/B IEO 7 IEI INTACK 8 37 CE D/C 1 44 43 42 41 40 39 38 9 37 CS0 CS1 R/W +5V 10 36 NC +5V 10 36 NC W/REQA SYNCA 11 35 11 35 34 W/REQA GND W/REQB SYNCA 34 GND W/REQB RTxCA 13 33 SYNCB RTxCA 13 33 SYNCB RxDA 14 32 RTxCB RxDA 14 32 RTxCB TRxCA 15 31 RxDB TRxCA 15 31 RxDB TxDA 16 30 TRxCB TxDA 16 30 TRxCB NC 17 29 18 19 20 21 22 23 24 25 26 27 28 NC 17 29 18 19 20 21 22 23 24 25 26 27 28 TxDB NC DTR/REQB RTSB CTSB DCDB PCLK CTSA DCDA Z80C30 12 NC DTR/REQA RTSA TxDB NC DTR/REQB RTSB CTSB DCDB PCLD CTSA NC DTR/REQA RTSA DCDA Z85C30 12 Figure 3. Z85C30 and Z80C30 PLCC Pin Assignments Figure 4 displays the pin functions for the Z85C30 device. Data Bus Bus Timing and Reset Control Interrupt D7 TxDA D6 RxDA D5 TRxCA D4 RTxCA D3 SYNCA D2 W/REQA D1 DTR/REQA D0 RTSA CTSA RD WR Z85C30 TxDB CE RxDB D/C TRxCB INT RTxCB IEI IEO Channel Clocks Channel Controls for Modem, DMA and Other CH-A DCDA A/B INTACK Serial Data Serial Data Channel Clocks SYNCB W/REQB DTR/REQB RTSB CTSB CH-B Channel Controls for Modem, DMA and Other DCDB Figure 4. Z85C30 Pin Functions PS011705-0608 General Description CMOS SCC Serial Communications Controller Product Specification 12 Figure 5 displays the pin functions for the Z80C30 device. Data Bus Bus Timing and Reset Control Interrupt AD7 TxDA AD6 RxDA AD5 TRxCA AD4 RTxCA AD3 SYNCA AD2 W/REQA AD1 DTR/REQA AD0 RTSA CTSA AS DS Z80C30 TxDB CS1 RxDB CS0 TRxCB INT RTxCB IEI IEO Channel Clocks Channel Controls for Modem, DMA and Other CH-A DCDA R/W INTACK Serial Data Serial Data Channel Clocks SYNCB W/REQB DTR/REQB RTSB CTSB CH-B Channel Controls for Modem, DMA and Other DCDB Figure 5. Z80C30 Pin Functions PS011705-0608 General Description CMOS SCC Serial Communications Controller Product Specification 13 Functional Description The architecture of the SCC is described below: * As a data communications device which transmits and receives data in various protocols. * As a microprocessor peripheral in which the SCC offers valuable features such as vectored interrupts and DMA support. The SCC's peripheral and data communication are described in the following sections. Figure 1 on page 5 displays the SCC block diagram. Figure 6 and Figure 7 display the details of the communications between the receive and transmit logic to the system bus. The features and data path for each of the SCC's A and B channels are identical. Internal Data Bus To Other Channel WR6 WR7 SYNC Register SYNC WRB TX Buffer 1 Byte Internal TXD Register Final TX MUX 20-Bit TX Shift Register TXD Sync Sync Zero Insert (5 Bits) CRC-Gen SDLC Transmit MUX & 2-Bit Delay NRZ Encode Transmit Clock From Receiver Figure 6. SCC Transmit Data Path PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 14 CPU/I/O I/O Data buffer Internal Data Bus Upper Byte (WR13) Time Constant BRG Input Status FIFO 10 X 19 Frame Lower Byte (WR12) Time Constant 16-Bit Down Counter Rec. Error FIFO 3 Byte Deep Rec. Error FIFO 3 Byte Deep BRG Output DIV 2 14-Bit Counter Rec. Error Logic Hunt Mode (BISYNC) DPLL IN DPLL OUT DPLL SYNC Register & Zero Delete 3-Bit Receive Shift Register Internal TXD RXD 1-Bit MUX NRZI Decode CRC Delay Register (8 bits) MUX To Transmit Section SDLC-CRC CRC Checker SYNC CRC CRC Result Figure 7. SCC Receive Data Path I/O Interface Capabilities System communication to and from the SCC is performed through the SCC's register set. There are sixteen Write registers and eight Read registers. Table 1 and Table 2 list the SCC registers and provide a brief description of their functions. Throughout this document, Write and Read registers are referenced with the following notation: * * `WR' for Write Register `RR' for Read Register For example, WR4A Write Register 4 for channel A RR3 Read Register 3 for either/both channels PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 15 Table 1. SCC Read Register Functions Register Function RR0 Transmit/Receive buffer status and External status RR1 Special Receive Condition status RR2 Modified interrupt vector (Channel B only) Unmodified interrupt vector (Channel A only) RR3 Interrupt Pending bits (Channel A only) RR8 Receive Buffer RR10 Miscellaneous status RR12 Lower byte of Baud Rate Generator time constant RR13 Upper byte of Baud Rate Generator time constant RR15 External/Status interrupt information Table 2. SCC Write Register Functions PS011705-0608 Register Function WR0 CRC initialize, initialization commands for the various modes, register pointers WR1 Transmit/Receive interrupt and data transfer mode definition WR2 Interrupt vector (accessed through either channel) WR3 Receive parameters and control WR4 Transmit/Receive miscellaneous parameters and modes WR5 Transmit parameters and controls WR6 Sync characters or SDLC address field WR7 Sync character or SDLC flag WR7* Extended Feature and FIFO Control (WR7 Prime) 85C30 Only WR8 Transmit buffer WR9 Master interrupt control and reset (accessed through either channel) WR10 Miscellaneous transmitter/receiver control bits Functional Description CMOS SCC Serial Communications Controller Product Specification 16 Table 2. SCC Write Register Functions (continued) Register Function WR11 Clock mode control WR12 Lower byte of Baud Rate Generator time constant WR13 Upper byte of Baud Rate Generator time constant WR14 Miscellaneous control bits WR15 External/Status interrupt control Following three methods move data, status, and control information in and out of the SCC: * * * Polling Interrupts (vectored and non-vectored) CPU/DMA Block Transfer -- The BLOCK TRANSFER mode can be implemented under CPU or DMA control. Polling When polling, all interrupts are disabled. Three status registers in the SCC are automatically updated when any function is performed. For example, End-Of-Frame in SDLC mode sets a bit in one of these status registers. The purpose of polling is for the CPU to periodically read a status register until the register contents indicate the need for data to be transferred. Only one register is read, and depending on its contents, the CPU either writes data, reads data, or continues. Two bits in the register indicate the need for data transfer. An alternative is a poll of the Interrupt Pending register to determine the source of an interrupt. The status for both channels resides in one register. Interrupts The SCC's interrupt structure supports vectored and nested interrupts. Nested interrupts are supported with the interrupt acknowledge feature (INTACK pin) of the SCC. This allows the CPU to recognize the occurrence of an interrupt, and re-enable higher priority interrupts. Because an INTACK cycle releases the INT pin from the active state, a higher priority SCC interrupt or another higher priority device can interrupt the CPU. When an SCC responds to an Interrupt Acknowledge signal (INTACK) from the CPU, an interrupt vector can be placed on the data bus. This vector is written in WR2 and can be read in RR2A or RR2B. To speed interrupt response time, the SCC can modify three bits in this vector to indicate status. If the vector is read in Channel A, status is never included. If the vector is read in Channel B, status is always included. Each of the six sources of interrupts in the SCC (Transmit, Receive, and External/Status interrupts in both channels) has three bits associated with the interrupt source. PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 17 Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). Operation of the IE bit is straight forward. If the IE bit is set for a given interrupt source, then that source can request interrupts. The exception is when the MIE (Master Interrupt Enable) bit in WR9 is reset and no interrupts can be requested. The IE bits are Write only. The other two bits are related to the interrupt priority chain (see Figure 8). As a microprocessor peripheral, the SCC can request an interrupt only when no higher priority device is requesting one, that is, when IEI is High. If the device in question requests an interrupt, it pulls down INT. The CPU responds with INTACK, and the interrupting device places the vector on the data bus. Peripheral Peripheral IEI D7-D0 INT INTACK IEO IEI D7-D0 INT INTACK IEO +5 V Peripheral IEI D7-D0 INT INTACK +5 V D7-D0 INT INTACK Figure 8. SCC Interrupt Priority Schedule The SCC can also execute an interrupt acknowledge cycle through software. In some CPU environments, it is difficult to create the INTACK signal with the necessary timing to acknowledge interrupts and allow the nesting of interrupts. In these cases, the INTACK signal can be created with a software command to the SCC. In the SCC, the Interrupt Pending (IP) bit signals a need for interrupt servicing. When an IP bit is 1 and the IEI input is High, the INT output is pulled Low, requesting an interrupt. In the SCC, if the IE bit is not set by enabling interrupts, then the IP for that source is never set. The IP bits are readable in RR3A. The IUS bits signal that an interrupt request is being serviced. If an IUS is set, all interrupt sources of lower priority in the SCC and external to the SCC are prevented from requesting interrupts. The internal interrupt sources are inhibited by the state of the internal daisy chain, while lower priority devices are inhibited by the IEO output of the SCC being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an Interrupt Acknowledge cycle, if there are no higher priority devices requesting interrupts. There are three types of interrupts: * * PS011705-0608 Transmit Receive Functional Description CMOS SCC Serial Communications Controller Product Specification 18 * External/Status Each interrupt type is enabled under program control with Channel A having higher priority than Channel B, and with Receiver, Transmit, and External/Status interrupts prioritized in that order within each channel. When enabled, the receiver interrupts the CPU in one of three ways: * * * Interrupt on First Receive Character or Special Receive Condition Interrupt on All Receive Characters or Special Receive Conditions Interrupt on Special Receive Conditions Only Interrupt on First Character or Special Condition and Interrupt on Special Condition Only are typically used with the Block Transfer mode. A special Receive Condition is one of the following. receiver overrun, framing error in Asynchronous mode, end-of-frame in SDLC mode and, optionally, a parity error. The Special Receive Condition interrupt is different from an ordinary receive character available interrupt only by the status placed in the vector during the Interrupt Acknowledge cycle. In Interrupt on First Receive Character, an interrupt occurs from Special Receive Conditions anytime after the first receive character interrupt. The main function of the External/Status interrupt is to monitor the signal transitions of the CTS, DCD, and SYNC pins, however, an External/Status interrupt is also caused by a Transmit Underrun condition; a zero count in the Baud Rate Generator; by the detection of a Break (Asynchronous mode), Abort (SDLC mode) or EOP (SDLC Loop mode) sequence in the data stream. The interrupt caused by the Abort or EOP has a special feature allowing the SCC to interrupt when the Abort or EOP sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the Abort condition in external logic in SDLC mode. In SDLC Loop mode, this feature allows secondary stations to recognize the primary station regaining control of the loop during a poll sequence. Software Interrupt Acknowledge On the CMOS version of the SCC, the SCC interrupt acknowledge cycle can be initiated through software. If Write Register 9 (WR9) bit D5 is set, Read Register 2 (RR2) results in an interrupt acknowledge cycle to be executed internally. Like a hardware INTACK cycle, a software acknowledge causes the INT pin to return High, the IEO pin to go low and set the IUS latch for the highest priority interrupt pending. Similar to using the hardware INTACK signal, a software acknowledge cycle requires that a Reset Highest IUS command be issued in the interrupt service routine. Whenever an interrupt acknowledge cycle is used, hardware or software, a reset highest IUS command is required. If RR2 is read from channel A, the unmodified vector is returned. If RR2 is read from channel B, then the vector is modified to indicate the source of the interrupt. The Vector Includes Status (VIS) and No Vector (NV) bits in WR9 are ignored when bit 05 is set to 1. PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 19 When the INTACK and IEI pins are not being used, they should be pulled up to VCC through a resistor (10 K typical). CPU/DMA Block Transfer The SCC provides a Block Transfer mode to accommodate CPU block transfer functions and DMA controllers. The Block Transfer mode uses the WAIT/REOUEST output in conjunction with the Wait/Request bits in WR1. The WAIT/REOUEST output can be defined under software control as a WAIT line in the CPU Block Transfer mode or as a REQUEST line in the DMA Block Transfer mode. To a DMA controller, the SCC REQUEST output indicates that the SCC is ready to transfer data to or from memory To the CPU, the WAIT line indicates that the ESCC is not ready to transfer data, thereby requesting that the CPU extend the I/O cycle. The DTR/ REQUEST line allows full-duplex operation under DMA control. SCC Data Communications Capabilities The SCC provides two independent full-duplex programmable channels for use in any common asynchronous or synchronous data communication protocols (see Figure 9 on page 19). Each data communication channel has identical feature and capabilities. Parity Start Stop Marking Line Data Data Marking Line Data Asynchronous SYNC Data Data CRC1 CRC2 Data CRC1 CRC2 Data CRC1 CRC2 CRC1 CRC2 Monosync SYNC SYNC Data Signal Bisync Data External Sync Flag Address Information Information Flag SDLC/HDLC/X.25 Figure 9. Some SCC Protocols PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 20 Asynchronous Modes Send and Receive is accomplished independently on each channel with five to eight bits per character, plus optional even or odd parity. The transmitters can supply one, one-anda-half, or two stop bits per character and can provide a break output at any time. The receiver break-detection logic interrupts the CPU both at the start and at the end of a received break. Reception is protected from spikes by a transient spike-rejection mechanism that checks the signal one-half a bit time after a Low level is detected on the receive data input (RxDA or RxDB pins). If the Low does not persist (a transient), the character assembly process does not start. Framing errors and overrun errors are detected and buffered together with the partial character on which they occur. Vectored interrupts allow fast servicing or error conditions using dedicated routines. A built-in checking process avoids the interpretation of a framing error as a new start bit. A framing error results in the addition of one-half a bit time to the point at which the search for the next start bit begins. The SCC does not require symmetric transmit and receive clock signals - a feature allowing use of the wide variety of clock sources. The transmitter and receiver handle data at a rate supplied to the receive and transmit clock inputs. In Asynchronous modes, the SYNC pin can be programmed as an input used for functions such as monitoring a ring indicator. Synchronous Modes The SCC supports both byte and bit-oriented synchronous communication. Synchronous byte-oriented protocols are handled in several modes. They allow character synchronization with a 6-bit or 8-bit sync character (Monosync), and a 12-bit or 16-bit synchronization pattern (Bisync), or with an external sync signal. Leading sync characters are removed without interrupting the CPU. 5- or 7-bit synchronous characters are detected with 8- or 16-bit patterns in the SCC by overlapping the larger pattern across multiple incoming synchronous characters as displayed in Figure 10. 7 Bits SYNC SYNC SYNC Data Data Data Data 8 16 Figure 10. Detecting 5- or 7-Bit Synchronous Characters CRC checking for Synchronous byte-oriented modes is delayed by one character time so that the CPU can disable CRC checking on specific characters. This feature permits the implementation of protocols such as IBM Bisync. PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 21 Both CRC-16 (X16 + X15 + X12 +1) and CCITT (X16 + X12 + X5 + 1) error-checking polynomials are supported. Either polynomial can be selected in all Synchronous modes. You can preset the CRC generator and checker to all 1's or all 0's. The SCC also provides a feature that automatically transmits CRC data when no other data is available for transmission. This feature allows for high speed transmissions under DMA control, with no need for CPU intervention at the end of a message. When there is no data or CRC to send in Synchronous modes, the transmitter inserts 6-,8-, or 16-bit sync characters, regardless of the programmed character length. SDLC Mode The SCC supports Synchronous bit-oriented protocols, such as SDLC and HDLC, by performing automatic flag sending, zero insertion, and CRC generation. A special command is used to abort a frame in transmission. At the end of a message, the SCC automatically transmits the CRC and trailing flag when the transmitter underruns. The transmitter can also be programmed to send an idle line consisting of continuous flag characters or a steady marking condition. If a transmit underrun occurs in the middle of a message, an external/status interrupt warns the CPU of this status change, issuing an abort. The SCC can also be programmed to send an abort itself in case of an underrun, relieving the CPU of this task. One to eight bits per character can be sent, allowing reception of a message with no prior information about the character structure in the information field of a frame. The receiver automatically acquires synchronization on the leading flag of a frame in SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can also be programmed). The receiver can be programmed to search for frames addressed by a single byte (or four bits within a byte) of a user-selected address or to a global broadcast address. In this mode, frames not matching either the user-selected or broadcast address are ignored. The number of address bytes are extended under software control. For receiving data, an interrupt on the first received character, or an interrupt on every character, or on special condition only (end-of-frame) can be selected. The receiver automatically deletes all 0's inserted by the transmitter during character assembly CRC is also calculated and is automatically checked to validate frame transmission. At the end of transmission, the status of a received frame is available in the status registers. In SDLC mode, the SCC must be programmed to use the SDLC CRC polynomial, but the generator and checker can be preset to all 1's or all 0's. The CRC inverts before transmission and the receiver checks against the bit pattern 0001110100001111. NRZ, NRZI or FM coding can be used in any 1 x mode. The parity options available in Asynchronous modes are available in Synchronous modes. SDLC Loop Mode The SCC supports SDLC Loop mode in addition to normal SDLC. In an SDLC Loop, a primary controller station manages the message traffic flow on the loop and any number of secondary stations. In SDLC Loop mode, the SCC performs the functions of a secondary PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 22 station while an SCC operating in regular SDLC mode acts as a controller (see Figure 11 on page 22). The SDLC loop mode can be selected by setting WR10 bit D1. Controller Secondary #1 Secondary #2 Secondary #4 Secondary #3 Figure 11. An SDLC Loop A secondary station in an SDLC Loop is always listening to the messages sent around the loop and passes these messages to the rest of the loop by retransmitting them with a onebit-time delay. The secondary station places its own message on the loop only at specific times. The controller signals that secondary stations can transmit messages by sending a special character, called an End Of Poll (EOP), around the loop. The EOP character is the bit pattern 11111110. Because of zero insertion during messages, this bit pattern is unique and easily recognized. When a secondary station contains a message to transmit and recognizes an EOP on the line, it changes the last binary 1 of the EOP to a 0 before transmission. This change has the effect of turning the EOP into a flag sequence. The secondary station now places its message on the loop and terminates the message with an EOP. Any secondary stations further down the loop with messages to transmit append their messages to the message of the first secondary station by the same process. Any secondary stations without messages to send echo the incoming message and are prohibited from placing messages on the loop (except when recognizing an EOP). In SDLC Loop mode, NRZ, NRZI, and FM coding can be used. The SCC's ability to receive high speed back-to-back SDLC frames is maximized by a 10deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides the DMA the ability to continue to transfer data into memory so that the CPU can examine the message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored. The byte count and status bits are accessed through Read Registers 6 and 7. Read Registers 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10 x 19 status FIFO is separate from the 3-byte receive data FIFO. PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 23 Baud Rate Generator Each channel in the SCC contains a programmable Baud Rate Generator (BRG). Each generator consists of two 8-bit time constant registers that form a 16-bit time constant, a 16-bit down counter, and a flip-flop on the output producing a square wave. On startup, the output flip-flop is set in a High state, the value in the time constant register is loaded into the counter, and the counter starts counting down. The output of the BRG toggles when reaching 0, the value in the time constant register is loaded into the counter, and the process is repeated. The time constant can be changed at any time, but the new value does not take effect until the next load of the counter. The output of the BRG can be used as either the transmit clock, the receive clock, or both. It can also drive the Digital Phase-locked loop (see Digital Phase-Locked Loop). If the receive clock or transmit clock is not programmed to come from the TRxC pin, the output of the BRG can be echoed out through the TRxC pin. The following formula relates the time constant to the baud rate where PCLK or RTxC is the BRG input frequency in Hertz. The clock mode is 1, 16, 32, or 64, as selected in Write Register 4, bits D6 and D7. Synchronous operation modes select 1 and Asynchronous modes select 16, 32 or 64. Time Constant = PCLK or RTxC Frequency -2 2(Baud Rate)(Clock Mode) Digital Phase-Locked Loop The SCC contains a Digital Phase-Locked Loop (DPLL) to recover clock information from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is nominally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with the data stream, to construct a clock for the data. This clock is used as the SCC receive clock, the transmit clock, or both. When the DPLL is selected as the transmit clock source, it provides a jitter-free clock output that is the DPLL input frequency divided by the appropriate divisor for the selected encoding technique. For NRZI encoding, the DPLL counts the 32x clock to create nominal bit times. As the 32x clock is counted, the DPLL is searching the incoming data stream for edges (either 1 to 0, or 0 to 1). Whenever an edge is detected, the DPLL makes a count adjustment (during the next counting cycle), producing a terminal count closer to the center of the bit cell. For FM encoding, the DPLL again counts from 0 to 31, but with a cycle corresponding to two bit times. When the DPLL is locked, the clock edges in the data stream occur between counts 15 and 16 and between counts 31 and 0. The DPLL looks for edges only during a time centered on the 15 to 16 counting transition. The 32x clock for the DPLL can be programmed to come from either the RTxC input or the output of the BRG. The DPLL output can be programmed to be echoed out of the SCC through the TRxC pin (if this pin is not being used as an input). PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 24 Data Encoding The SCC can be programmed to encode and decode the serial data in four different methods (Figure 12). In NRZ encoding, a 1 is represented by a High level and a 0 is represented by a Low level. In NRZI encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. In FM1 (more properly, bi-phase mark), a transition occurs at the beginning of every bit cell. A 1 is represented by an additional transition at the center of the bit cell and a 0 is represented by no additional transition at the center of the bit cell. In FM0 (bi-phase space), a transition occurs at the beginning of every bit cell. A 0 is represented by an additional transition at the center of the bit cell, and a 1 is represented by no additional transition at the center of the bit cell. In addition to these four methods, the SCC can be used to decode Manchester (bi-phase level) data by using the DPLL in the FM mode and programming the receiver for NRZ data. Manchester encoding always produces a transition at the center of the bit cell. If the transition is 0 to 1, the bit is a 0. If the transition is 1 to 0, the bit is a 1. Data 1 1 0 0 1 0 NRZ NRZI FM1 FM0 Manchester Figure 12. Data Encoding Methods Auto Echo and Local Loopback The SCC is capable of automatically echoing everything it receives. This feature is useful mainly in Asynchronous modes, but works in Synchronous and SDLC modes as well. Auto Echo mode (Tx0 is Rx0) is used with NRZI or FM encoding with no additional delay because the data stream is not decoded before retransmission. In Auto Echo mode, the CTS input is ignored as a transmitter enable (although transitions on this input can still cause interrupts if programmed to do so). In this mode, the transmitter is actually bypassed and the programmer is responsible for disabling transmitter interrupts and WAIT/ REQUEST on transmit. The SCC is also capable of local loopback. In this mode, TxD or RxD is similar to Auto Echo mode. However, in Local Loopback mode the internal transmit data is tied to the PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 25 internal receive data and RxD is ignored (except to be echoed out through TxD). The CTS and DCD inputs are also ignored as transmit and receive enables. However, transitions on these inputs can still cause interrupts. Local Loopback works in Asynchronous, Synchronous and SDLC modes with NRZ, NRZI or FM coding of the data stream. SDLC FIFO Frame Status FIFO Enhancement The SCC's ability to receive high speed back-to-back SDLC frames is maximized by a 10-deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides the DMA the ability to continue to transfer data into memory so that the CPU can examine the message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored. The byte count and status bits are accessed through Read Registers 6 and 7. Read Registers 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10x19 status FIFO is separate from the 3-byte receive data FIFO. When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for the SDLC frame are stored in the 10 x 19 bit status FIFO. This arrangement allows the DMA controller to transfer the next frame into memory while the CPU verifies that the message was properly received. Summarizing the operation; data is received, assembled, and loaded into the eight byte FIFO before being transferred to memory by the DMA controller. When a flag is received at the end of an SDLC frame, the frame byte count from the 14-bit counter and five status bits are loaded into the status FIFO for verification by the CPU. The CRC checker automatically resets in preparation for the next frame which can begin immediately. Since the byte count and status are saved for each frame, the message integrity is verified at a later time. The status information for up to 10 frames is stored before a status FIFO overrun occurs. If a frame is terminated with an ABORT, the byte count is loaded to the status FIFO and the counter resets for the next frame. FIFO Detail For more details on the FIFO operation details, see Figure 13 on page 26. Enable/Disable This FIFO is implemented is enabled when WR15, bit D2, is set and the SCC is in the SDLC/HDLC mode. Otherwise, the status register contents bypass the FIFO and go directly to the bus interface (the FIFO pointer logic is reset either when disabled or through a channel or Power-On Reset). When the FIFO mode is disabled, the SCC is downward compatible with the NMOS Z8530. The FIFO mode is disabled on power-up (WR15 D2 is set to 0 on reset). The effects of backward compatibility on the register set are that RR4 is an image of RR0, RR5 is an image of RR1, RR6 is an image of RR2 and RR7 is an image of RR3. For more details on the added registers, see Figure 16 on page 30. The status of the FIFO Enable signal is obtained by reading RR15, bit D2. If the FIFO is enabled, the bit is set to 1; otherwise, it resets. PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 26 Read Operation When WR15 bit D2 sets and the FIFO is not empty, the next read to status register RR1 or registers RR7 and RR6, is from the FIFO. Reading status register RR1 causes one location of the FIFO to become empty. Status is read after reading the byte count, otherwise the count is incorrect. Before the FIFO underflows, it is disabled. In this case, the multiplexer is switched allowing status to read directly from the status register. Reads from RR7 and RR6 contain bits that are undefined. Bit D6 of RR7 (FIFO Data Available) determines if status data is coming from the FIFO or directly from the status register, which sets to 1 when the FIFO is not empty. Not all status bits are stored in the FIFO. The All Sent, Parity, and EOF bits bypass the FIFO. Status bits sent through the FIFO are Residue Bits (3), Overrun, and CRC Error. Frame Status FIFO Circuitry RR1 Reset on Flag Detect SCC Status Reg Residue Bits (3) Overrun, CRC Error Byte Counter Increment on Byte Detection Enable Count in SDLC 5 Bits End of Frame Signal Status Read Comp 14 Bits FIFO Array 10 Deep by 19 Bits Wide Tail Pointer 4-Bit Counter Head Pointer 4-Bit Counter 4-Bit Comparator Over EOF = 1 5 Bits 6 Bits 8 Bits EN 6-Bit MUX 2 Bits 6 Bits RR1 Equal Bit 7 Bit 6 Bits 5-0 RR6 RR7 D5-D0 + RR6 D7-D0 Byte Counter Contains 14 bits for a 16 KByte maximum count Interface to SCC FIFO Enable WR(15) Bit 2 Set Enables Status FIFO RR7 D6 FIFO Data available status bit Status Bit set to 1 When reading from FIFO RR7 D7 FIFO Overflow Status Bit MSB pf RR(7) is set on Status FIFO overflow In SDLC Mode the following definitions apply - All Sent bypasses MUX and equals contents of SCC Status Register - Parity Bits bypasses MUX and does the same - EOF is set to 1 whenever reading from the FIFO Figure 13. SDLC Frame Status FIFO PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 27 The sequence for operation of the byte count and FIFO logic is to read the registers in the following order. RR7, RR6, and RR1 (reading RR6 is optional). Additional logic prevents the FIFO from being emptied by multiple reads from RR1. The read from RR7 latches the FIFO empty/full status bit (D6) and steers the status multiplexer to read from the SCC megacell instead of the status FIFO (since the status FIFO is empty). The read from RR1 allows an entry to be read from the FIFO (if the FIFO was empty, logic was added to prevent a FIFO underflow condition). Write Operation When the end of an SDLC frame (EOF) is received and the FIFO is enabled, the contents of the status and byte-count registers are loaded into the FIFO. The EOF signal is used to increment the FIFO. If the FIFO overflows, RR7, bit D7 (FIFO Overflow) sets to indicate the overflow. This bit and the FIFO control logic is reset by disabling and re-enabling the FIFO control bit (WR15, bit 02). For details of FIFO control timing during an SDLC frame, see Figure 14. 0 F A D D D D C 7 0 0 C F F Internal Byte Strobe Increments Counter Don't Load Counter On 1st Flag Reset Byte Counter Here A D D D D C 7 0 C F Internal Byte Strobe Increments Counter Reset Byte Counter Load Counter Into FIFO and Increment PTR Reset Byte Counter Reset Byte Counter Load Counter Into FIFO and Increment PTR Figure 14. SDLC Byte Counting Detail Programming The SCC contains Write registers in each channel that are programmed by the system separately to configure the functional personality of the channels. Z85C30 In the SCC, the data registers are directly addressed by selecting a High on the D/C pin. With all other registers (except WR0 and RR0), programming the Write registers requires two Write operations and reading the read registers requires both a Write and a Read operation. The first write is to WR0 and contains three bits that point to the selected register. The second write is the actual control word for the selected register, and if the second operation is read, the selected Read register is accessed. All the SCC registers, including the data registers, can be accessed in this fashion. The pointer bits are automatically cleared after the Read or Write operation so that WR0 (or RR0) is addressed again. PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 28 Z80C30 All SCC registers are directly addressable. A command issued in WR0B controls how the SCC decodes the address placed on the address/data bus at the beginning of a Read or Write cycle. In the Shift Right mode, the channel select A/B is taken from AD0 and the state of AD5 is ignored. In the Shift Left mode, the channel select A/B is taken from AD5 and the state of AD0 is ignored. AD7 and AD6 are always ignored as address bits and the register address occupies AD4-AD1. Z85C30/Z80C30 Setup Initialization The system program first issues a series of commands to initialize the basic mode of operation. This is followed by other commands to qualify conditions within the selected mode. For example, in the Asynchronous mode, character length, clock rate, number of stop bits, and even or odd parity must be set first. The interrupt mode is set, and finally, the receiver and transmitter are enabled. Write Registers The SCC contains 15 Write registers for the 80C30, while there are 16 for the 85C30 (one more additional Write register if counting the transmit buffer) in each channel. These Write registers are programmed separately to configure the functional `personality' of the channels. There are two registers (WR2 and WR9) shared by the two channels that are accessed through either of them. WR2 contains the interrupt vector for both channels, while WR9 contains the interrupt control bits and reset commands. Figure 15 through Figure 18 display the format of each Write register. PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 29 Write Register 0 (non-multiplexed bus mode) Write Register 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Ext Int Enable 0 0 0 Register 0 0 0 1 Register 1 0 1 0 Register 2 0 1 1 Register 3 1 0 0 Register 4 1 0 1 Register 5 1 1 0 Register 6 1 1 1 Register 7 0 0 0 Register 8 0 0 1 Register 9 0 1 0 Register 10 0 1 1 Register 11 * 1 0 0 Register 12 1 0 1 Register 13 1 1 0 Register 14 1 1 Register 15 Null Code Point High Reset Ext/Status Interrupts Send Abort (SDLC) Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS 0 0 1 1 0 1 0 1 Tx Int Enable Parity is Special Condition 0 0 1 1 0 1 0 1 Rx Int Disable Rx Int on First Character or Special Condition Int on all Rx Characters or Special Condition Rx Int on Special Condition Only WAIT/DMA Request on Receive /Transmit WAIT/DMA Request Function WAIT/DMA Request 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Null Code Reset Rx CRC Checker Reset Tx CRC Generator Reset Tx Underrun/EOM Latch Write Register 2 D7 D6 D5 D4 D3 D2 D1 D0 V0 V1 V2 V3 V4 * With Point High Command Interrupt Vector V5 V6 Write Register 0 (multiplexed bus mode) V7 D7 D6 D5 D4 D3 D2 D1 D0 Write Register 3 0 0 1 1 0 1 0 1 Null Code Null Code Select Shift Left Mode Select Shift Right Mode D7 D6 D5 D4 D3 D2 D1 D0 * Rx Enable Sync Character Load Inhibit 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Null Code Null Code Reset Ext/Status Interrupts Send Abort Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS Null Code Reset Rx CRC Checker Reset Tx CRC Checker Reset Tx Underrun/EOM Latch Address Search Mode (SDLC) Rx CRC Enable Enter Hunt Mode Auto Enables 0 0 1 1 0 1 0 1 Rx 5 Bits/Character Rx 7 Bits/Character Rx 6 Bits/Character Rx 8 Bits/Character * B Channel Only Figure 15. Write Register Bit Functions PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 30 Write Register 4 Write Register 5 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Parity Enable Tx CRC Enable Parity EVEN/ODD RTS SDLC/CRC-16 Sync Modes Enable 1 Stop Bit/Character 1 1/2 Stop Bits/Character 2 Stop Bits/Character 8-Bit Sync Character 16-Bit Sync Character SDLC Mode (01111110 Flag) External Sync Mode Tx Enable Send Break 0 0 1 1 0 1 0 1 Tx 5 Bits (or Less)/Character Tx 7 Bits/Character Tx 6 Bits/Character Tx 8 Bits/Character DTR 0 0 1 1 0 X1 Clock Mode 1 X16 Clock Mode 0 X32 Clock Mode 1 X64 Clock Mode Figure 16. Write Register Bit Functions PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 31 Write Register 6 D7 D6 D5 D4 D3 D2 D1 D0 Sync7 Sync1 Sync7 Sync3 ADR7 ADR7 Sync6 Sync0 Sync6 Sync2 ADR6 ADR6 Sync5 Sync5 Sync5 Sync1 ADR5 ADR5 Sync4 Sync4 Sync4 Sync0 ADR4 ADR4 Sync3 Sync3 Sync3 1 ADR3 x Sync2 Sync2 Sync2 1 ADR2 x Sync1 Sync1 Sync1 1 ADR1 x Sync0 Sync0 Sync0 1 ADR0 x Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC SDLC (Address Range) Write Register 7 D7 D6 D5 D4 D3 D2 D1 D0 Sync7 Sync6 Sync5 Sync4 Sync15 Sync14 Sync11 Sync10 1 0 Sync5 Sync3 Sync13 Sync9 1 Sync4 Sync2 Sync12 Sync8 1 Sync3 Sync1 Sync11 Sync7 1 Sync2 Sync1 Sync0 x Sync0 x Sync10 Sync9 Sync8 Sync6 Sync5 Sync4 1 1 0 Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC WR 7' Prime (85C30 only) D7 D6 D5 D4 D3 D2 D1 D0 Auto Tx Flag Auto EOM Reset Auto RTS Deactivation Force TxD High DTR/REQ Fast Mode Complete CRC Reception Extended Read Enable Reserved (Program as 0) Figure 17. Write Register Bit Functions PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 32 Write Register 12 Write Register 9 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 VIS TC0 NV TC1 DLC TC2 MIE TC3 Status High/Status Low TC4 Software INTACK Enable 0 0 1 1 0 1 0 1 Lower Byte of Time Constant TC5 TC6 No Reset Channel Reset B Channel Reset A Force Hardware Reset TC7 Write Register 13 D7 D6 D5 D4 D3 D2 D1 D0 Write Register 10 D7 D6 D5 D4 D3 D2 D1 D0 TC8 TC9 0 0 1 1 6-Bit/8-Bit Sync TC10 Loop Mode TC11 Abort/Flag on Underrun TC12 Mark/Flag Idle TC13 Go Active on Poll TC14 Upper Byte of Time Constant TC15 0 NRZ 1 NRZI 0 FM1 (Transition = 1) 1 FM1 (Transition = 0) Write Register 14 D7 D6 D5 D4 D3 D2 D1 D0 CRC Preset I/O BR Generator Enable Write Register 11 BR Generator Source D7 D6 D5 D4 D3 D2 D1 D0 DTR/Request Function Auto Echo 0 0 1 1 0 1 0 1 TRxC Out = Xtal Output TRxC Out = Transmit Clock TRxC Out = BR Generator Output TRxC Out = DPLL Output TRxC O/I 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Transmit Clock = RTxC Pin Transmit Clock = TRxC Pin Transmit Clock = BR Generator Output Transmit Clock = DPLL Output Receive Clock = RTxC Pin Receive Clock = TRxC Pin Receive Clock = BR Generator Output Receive Clock = DPLL Output Local Loopback 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Null Command Enter Search Mode Reset Missing Clock Disable DPLL Set Source = BR Generator Set Source = RTxC Set FM Mode Set NRZI Mode Write Register 15 D7 D6 D5 D4 D3 D2 D1 D0 RTxC Xtal/No Xtal 0 Zero Count IE SDLC FIFO Enable DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE Figure 18. Write Register Bit Functions Read Registers The SCC contains ten Read registers (eleven, counting the receive buffer (RR8) in each channel). Four of these can be read to obtain status information (RR0, RR1, RR10, and RR15). Two registers (RR12 and RR13) are read to learn the Baud Rate Generator time constant. RR2 contains either the unmodified interrupt vector (Channel A) or the vector modified by status information (Channel B). RR3 contains the Interrupt Pending (IP) bits (Channel A only - Figure 19). RR6 and RR7 contain the information in the SDLC Frame Status FIFO, but is only read when WR15 D2 is set (see Figure 19 and Figure 20). PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 33 Read Register 3 Read Register 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Rx Character Available Channel B Ext/Status IP Zero Count Channel B Tx IP Tx Buffer Empty Channel B Rx IP DCD Channel A Ext/Status IP Sync/Hunt Channel A Tx IP CTS Channel A Rx IP Tx Underrun/EOM 0 Break/Abort 0 * * Always 0 in B Channel Read Register 1 D7 D6 D5 D4 D3 D2 D1 D0 Read Register 10 D7 D6 D5 D4 D3 D2 D1 D0 All Sent Residue Code 2 0 Residue Code 1 On Loop Residue Code 0 0 Parity Error 0 Rx Overrun Error Loop Sending CRC/Framing Error 0 End of Frame (SDLC) Two Clocks Missing One Clocks Missing Read Register 2 Read Register 12 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 V0 TC0 V1 TC1 V2 V3 V4 TC2 Interrupt Vector * TC3 V5 TC4 V6 TC5 Lower Byte of Time Constant TC6 V7 TC7 * Modified in B Channel Figure 19. Read Register Bit Functions Read Register 13 Read Register 15 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TC8 0 TC9 Zero Count IE TC10 TC11 TC12 0 Upper Byte of Time Constant TC13 DCD IE Sync/Hunt IE CTS IE TC14 Tx Underrun/EOM IE TC15 Break/Abort IE Figure 20. Read Register Bit Functions PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 34 Z85C30 Timing The SCC generates internal control signals from the WR and RD that are related to PCLK. PCLK has no phase relationship with WR and RD, the circuitry generating the internal control signals provides time for meta-stable conditions to disappear. This gives rise to a recovery time related to PCLK. The recovery time applies only between bus transactions involving the SCC. The recovery time required for proper operation is specified from the falling edge of WR or RD in the first transaction involving the SCC to the falling edge of WR or RD in the second transaction involving the SCC. This time must be at least 3 PCLKs regardless of which register or channel is being accessed. The Z85C30 timings are described below: * * * PS011705-0608 Read Cycle Timing Write Cycle Timing Interrupt Acknowledge Cycle Timing Functional Description CMOS SCC Serial Communications Controller Product Specification 35 Read Cycle Timing Figure 21 displays Read cycle timing. Addresses on A/ B and D/C and the status on INTACK must remain stable throughout the cycle. If CE falls after RD falls, or if CE rises before RD rises, the effective RD is shortened. A/B, D/C Address Valid INTACK CE RD Data Valid D7-D0 Figure 21. Read Cycle Timing PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 36 Write Cycle Timing Figure 22 displays Write cycle timing. Addresses on A/B and D/C and the status on INTACK must remain stable throughout the cycle. If CE falls after WR falls, or if CE rises before WR rises, the effective WR is shortened. Data must be valid before the rising edge of WR. A/B, D/C A AdAdd Address Valid INTACK CE WR D7-D0 Data Valid Figure 22. Write Cycle Timing PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 37 Interrupt Acknowledge Cycle Timing Figure 23 displays an Interrupt Acknowledge cycle timing. Between the time INTACK goes Low and the falling edge of RD, the internal and external IEI/IEO daisy chains settle. If there is an interrupt pending in the SCC and IEI is High when RD falls, the Acknowledge cycle is intended for the SCC. In this case, the SCC can be programmed to respond to RD Low by placing its interrupt vector on D7-D0. It then sets the appropriate InterruptUnder-Service latch internally. If the external daisy chain is not used, AC parameter #38 is required to settle the interrupt priority daisy chain internal to the SCC. If the external daisy chain is used, you must follow the equation in AC Characteristics, Read/Write Timing Table 6 on page 47, Note 5 for calculating the required daisy-chain settle time. INTACK RD D7-D0 Vector Figure 23. Interrupt Acknowledge Cycle Timing Z80C30 Timing The SCC generates internal control signals from AS and DS that are related to PCLK. Because PCLK has no phase relationship with AS and DS, the circuitry generating these internal control signals must provide time for metastable conditions to disappear. This gives rise to a recovery time related to PCLK. The recovery time applies only between bus transactions involving the SCC. The recovery time required for proper operation is specified from the falling edge of DS in the first transaction involving the SCC to the falling edge of DS in the second transaction involving the SCC. The timings for Z80C30 device is described below: * * * PS011705-0608 Read Cycle Timing Write Cycle Timing Interrupt Acknowledge Cycle Timing Functional Description CMOS SCC Serial Communications Controller Product Specification 38 Read Cycle Timing Figure 24 displays the Read cycle timing. The address on AD7-AD0 and the state of CS0 and INTACK are latched by the rising edge of AS. R/W must be High to indicate a Read cycle. CS1 must also be High for the Read cycle to occur. The data bus drivers in the SCC are then enabled while DS is Low. AS CS0 INTACK AD7-AD0 Address Data Valid R/W CS1 DS Figure 24. Read Cycle Timing PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 39 Write Cycle Timing Figure 25 displays the Write cycle timing. The address on AD7-AD0 and the state of CS0 and INTACK are latched by the rising edge of AS. R/W must be Low to indicate a Write cycle. CS1 must be High for the Write cycle to occur DS Low strobes the data into the SCC. AS CS0 INTACK AD7-AD0 Address Data R/W CS1 DS Figure 25. Write Cycle Timing PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 40 Interrupt Acknowledge Cycle Timing Figure 26 displays the Interrupt Acknowledge cycle timing. The address on AD7-AD0 and the state of CS0 and INTACK are latched by the rising edge of AS. If INTACK is Low, the address and CS0 are ignored. The state of the R/W and CS1 are also ignored for the duration of the Interrupt Acknowledge cycle. Between the rising edge of AS and the falling edge of DS, the internal and external IEI/IEO daisy chains settle. If there is an interrupt pending in the SCC, and IEI is High when DS falls, the Acknowledge cycle was intended for the SCC. In this case, the SCC is programmed to respond to RD Low by placing its interrupt vector on D7-D0 and internally setting the appropriate InterruptUnder-Service latch. AS CS0 (Ignored) INTACK AD7-AD0 (Ignored) Vector DS Figure 26. Interrupt Acknowledge Cycle Timing PS011705-0608 Functional Description CMOS SCC Serial Communications Controller Product Specification 41 Electrical Characteristics The electrical characteristics of the Z80C30 and the Z85C30 devices are described in the following sections. Absolute Maximum Ratings Stresses greater than those listed in Table 3 may cause permanent damage to the device This is a stress rating only. Operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Vcc Supply Voltage range -0.3 V to +7.0 V Voltages on all pins with respect to GND -3 V to VCC +0.3 V TA Operating Ambient Temperature See Ordering Information Storage Temperature -65 C to +150 C Standard Test Conditions The DC Characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin. See Figure 27 and Figure 28. * * * PS011705-0608 +4.50 V Vcc + 5.50 V GND = 0 V TA as specified in Ordering Information Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 42 2.1 K From Output Under Test 250 A 100 pF Figure 27. Standard Test Load 2.2 K From Output 50 pF Figure 28. Open-Drain Test Load Capacitance Table 4 lists the input, output, and bidirectional capacitance. PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 43 Table 4. Capacitance Symbol Parameter CIN Min Max Unit Test Condition Input Capacitance 10 pF1 COUT Output Capacitance 15 pF Unmeasured Pins Returned to Ground2 CI/O Bidirectional Capacitance 20 pF Notes 1. pF = 1 MHz, over specified temperature range. 2. Unmeasured pins returned to Ground. Miscellaneous The Gate Count is 6800. DC Characteristics Z80C30/Z85C30 Table 5 lists the DC characteristics for the Z80C30/Z85C30 devices. PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 44 Table 5. Z80C30/Z85C30 DC Characteristics Symbol Parameter Min VIH Input High Voltage VIL Typ Max Unit Condition 2.2 VCC +0.31 V Input Low Voltage -0.3 0.8 V VOH1 Output High Voltage 2.4 V IOH = -1.6 mA VOH2 Output High Voltage VCC 0.8 V IOH = -250 A VOL Output Low Voltage 0.4 V IOL = +2.0 mA IIL Input Leakage 10.0 A 0.4 VIN + 2.4 V IOL Output Leakage 10.0 A 0.4 VOUT + 2.4 V ICC1 VCC Supply Current2 7 12 (10 MHz) mA VCC = 5 V VIH = 4.8 VIL = 0 9 15 (16.384 MHz) mA ICCOSC Crystal OSC Current3 4 mA Crystal Oscillator off Current for each OSC in addition to ICC1 Notes 1. VCC = SV t10% unless otherwise specified, over specified temperature range. 2. Typical ICC was measured with oscillator off. 3. No ICC (OSC) max is specified due to dependency on external circuit and frequency of oscillation. AC Characteristics Z85C30 Read/Write Timing Diagrams Figure 29 through Figure 32 display the Z85C30 Read/Write timing diagrams. Table 6 lists the Z85C30 Read/Write timing parameters. PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 45 1 PCLK 2 4 3 5 6 A/B, D/C 10 7 9 12 INTACK 11 10 15 14 13 CE 18 16 RD 19 D7-D0 Read 21 20 22 Active Valid 23 17 24 26 25 27 WR 28 D7-D0 Write 31 29 W/REQ Wait 30 32 35 W/REQ Request DTR/REQ Request 33 34 36 INT 37 Figure 29. Z85C30 Read/Write Timing Diagram PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 46 PCLK 15 10 INTACK 38 10 14 RD 24 38 23 D7-D0 Valid Active 26 40 41 42 IEI 44 43 IEO 45 INT Figure 30. Z85C30 Interrupt Acknowledge Timing Diagram 49b 49b PCLK CE 49a RD or WR Figure 31. Z85C30 Cycle Timing Diagram WR 48 47 48 RD Figure 32. Z85C30 Reset Timing Diagram PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 47 Table 6. Z85C30 Read/Write Timing 8.5 MHz 10 MHz 16 MHz No Symbol Parameter Min Max Min Max Min Max 1 TwPCI PCLK Low Width 45 2000 40 2000 26 2000 2 TwPCh PCLK High Width 45 2000 40 2000 26 2000 3 TfPC PCLK Fall Time 10 10 5 4 TrPC PCLK Rise Time 10 10 5 5 TcPC PCLK Cycle Time 118 6 TsA(WR) Address to WR Fall Setup Time 66 50 35 7 ThA(WR) Address to WR Rise Hold Time 0 0 0 8 TsA(RD) Address to RD Fall Setup Time 66 50 35 9 ThA(RD) Address to RD Rise Hold Time 0 0 0 INTACK to PCLK Rise 20 Setup Time 20 15 INTACK to WR Fall Setup Time 140 120 70 12 ThIA(WR) INTACK to WR Rise Hold Time 0 0 0 13 TsiAi(RD)1 INTACK to RD Fall Setup Time 140 120 70 14 ThIA(RD) INTACK to RD Rise Hold Time 0 0 0 15 ThIA(PC) INTACK to PCLK Rise 38 Hold Time 30 15 16 TsCEI(WR) CE Low to WR Fall Setup Time 0 0 0 17 ThCE(WR) CE to WR Rise Hold Time 0 0 0 18 TsCEh(WR) CE High to WR Fall Setup Time 58 50 30 10 TsiA(PC) 11 TsiAi(WR)a PS011705-0608 4000 100 4000 61 4000 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 48 Table 6. Z85C30 Read/Write Timing (continued) 8.5 MHz No Symbol 10 MHz Parameter Min CE Low to RD Fall Setup Time 0 0 0 20 ThCE(RD)1 CE to RD Rise Hold Time 0 0 0 21 TsCEh(RD)1 CE High to RD Fall Setup Time 58 50 22 TwRDI1 RD Low Width 145 125 70 23 TdRD(DRA) RD Fall to Read Data Active Delay 0 0 0 24 TdRDr(DR) RD Rise to Data Not Valid Delay 0 0 0 25 TdRDI(DR) RD Fall to Read Data Valid Delay 135 120 70 26 TdRD(DRz) RD Rise to Read Data Float Delay 38 35 30 27 TdA(DR) Addr to Read Data Valid Delay 210 160 100 28 TwWRI WR Low Width 29 TdWR(DW) WR Fall to Write Data Valid Delay 30 ThDW(WR) Write Data to WR Rise 0 Hold Time 31 TdWR(W)b WR Fall to Wait Valid Delay 168 100 50 32 TdRD(W)2 RD Fall to Wait Valid Delay 168 100 50 33 TdWRf(REQ) WR Fall to W/REQ Not Valid Delay 168 120 70 34 TdRDf(REQ)c RD Fall to W/REQ Not Valid Delay 168 120 70 35a TdWRr(REQ) 4TcPc 4TcPc 4TcPc 168 100 70 19 TsCEI(RD) 1 WR Fall to DTR/REQ Not Valid 35b TdWRr(REQ)3 WR Fall to DTR/REQ Not Valid PS011705-0608 Max 145 Min 16 MHz Max Max 30 125 35 Min 75 35 20 0 0 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 49 Table 6. Z85C30 Read/Write Timing (continued) 8.5 MHz Max Parameter 36 TdRDrrREQ) RD Rise to DTR/REQ Not Valid Delay NA NA NA 37 TdPC(INT) PCLK Fall to INT Valid Delay 500 320 175 38 TdIAi(RD)d INTACK to RD Fall (Ack) Delay 145 90 50 39 TwRDA RD (Acknowledge) Width 145 125 75 40 TdRDA(DR) RD Fall (Ack) to Read Data Valid Delay 135 120 70 41 TsiEI(RDA) IEI to RD Fall (Ack) Setup Time 95 80 50 42 ThIEI(RDA) IEI to RD Rise (Ack) Hold Time 0 0 0 43 TdIElrIEO) IEI to IEO Delay Time 95 80 45 44 TdPC(IEO) PCLK Rise to IEO Delay 195 175 80 45 TdRDA(INT)2 RD Fall to INT Inactive Delay 480 320 200 46 TdRDrWRQ) RD Rise to WR Fall Delay for No Reset 15 15 10 47 TdWRQ(RD) WR Rise to RD Fall Delay for No Reset 15 15 10 48 TwRES WR and RD Low for Reset 145 100 75 49a Trce Valid Access Recovery 3.5TcPc Time 3.5TcPc Min 16 MHz No Symbol PS011705-0608 Min 10 MHz Max Min Max 3.5TcPc Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 50 Table 6. Z85C30 Read/Write Timing (continued) 8.5 MHz No Symbol 49b Trci f Parameter Min RD or WR Fall to PC Fall Setup Time 0 10 MHz Max Min 0 16 MHz Max Min Max 0 a. Parameter does not apply to Interrupt Acknowledge transactions. b. Open-drain output, measured with open-drain test load. c. Parameter applies to enhanced Request mode oniy (WR7' D4 = 1). d. Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each device separating them in the daisy chain. e. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc. f. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK. Figure 33 displays the Z85C30 general timing diagram. Table 7 lists the Z85C30 general timing characteristics. Figure 34 displays the Z85C30 system timing. Table 8 lists the Z85C30 system timing characteristics . Table 9 provides the Z85C30 Read/Write timing characteristics. Figure 35 through Figure 37 display the Z80C30 Read/Write timing, interrupt acknowledge timing, and reset timing, respectively. Table 10 provides the Z80C30 Read/Write timing characteristics. PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 51 PCLK 1 W/REQ Request 2 W/REQ Wait 3 CTS/TRxC, RTxC Receive 4 6 5 7 RxD 9 SYNC External 8 CTS/TRxC, RTxC Transmit 10 11 12 TxD 13 CTS/TRxC Output 14 15 RTxC 16 17 CTS/TRxC 19 18 20 CTS/TRxC DCD 22 22 22 22 SYNC Input Figure 33. Z85C30 General Timing Diagram Table 7. Z85C30 General Timing Table No Symbol Parameter 1 TdPC(REQ) PCLK to W/REQ Valid 2 TdPC(W) PCLK to Wait Inactive 3 TsRXC(PC) RxC to PCLK Setup Timea,b 4 TsRXD(RXCr) RxD to RxC Setup Time1 ThRXD(RxCr) 1 5 PS011705-0608 RxD to /RXC Hold Time 8.5 MHz 10 MHz Min Min Max Max Min Max 250 150 80 350 250 180 N/A N/A 0 150 16 MHz N/A 0 125 0 50 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 52 Table 7. Z85C30 General Timing Table (continued) No Symbol Parameter 1,c 6 TsRXD(RXCf) RxD to /RXC Setup Time 7 ThRXD(RXCf) RxD to /RXC Hold Time1,3 8 TsSY(RXC) SYNC to RxC Setup Time 9 ThSY(RXC) SYNC to RxC Hold Time1 10 TsTXC(PC) TxC to PCLK Setup Time 11 TdTXCf(TXD) TxC to TxD Delay4 1 d,e 8.5 MHz 10 MHz Min Min TdTxCr(TXD) TxC to TxD Delay 13 TdTXD(TRX) TxD to TRxC Delay f 14a TwRTXh RTxC High Width 14b TwRTXh(E) RTxC High Widthg 6 15a TwRTXI TRxC Low Width 15b TwRTXI(E) RTxC Low Width7 6,h 16a TcRTX RTxC Cycle Time 16b TcRTX(E) RTxC Cycle Time7 i Max Min 0 0 0 150 1 25 50 -200 -150 -100 5TcPc 5TcPc 5TcPc N/A N/A N/A 4,3 12 Max 16 MHz Max 200 150 80 200 150 80 200 140 80 150 120 80 50 40 15.6 150 120 80 50 40 15.6 488 400 244 125 100 31.25 17 TcRTXX Crystal Osc. Period 125 18 TwTRXh TRxC High Width6 150 120 180 19 TwTRXI TRxC Low Width 6 150 120 80 20 TcTRX TRxC Cycle Time6,8 488 400 244 21 TwEXT DCD or CTS Pulse Width 200 120 70 22 TwSY SYNC Pulse Width 200 120 70 1000 100 1000 62 1000 a. RxC is RTxC or TRxC, whichever is supplying the receive clock. b. Synchronization of RxC to PCLK is eliminated in divide by four operation. c. Parameter applies only to FM encoding/decoding. d. TxC is TRxC or /RTxC, whichever is supplying the transmit clock. e. External PCLK to RTxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation.TRxC and RTxC rise and fall times are identical to PCLK. Reference timing specs TfPC and TrPC.Tx and Rx input clock slew rates should be kept to a maximum of 30 nsec. All parameters related to input CLK edges must be referenced at the point at which the transition begins or ends, whichever is worst case. f. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are identical to case PCLK requirements. g. Enhanced Feature -- RTxC used as input to internal DPLL only. h. The maximum receive or transmit data rate is 1/4 PCLK. i. Both RTxC and SYNC have 30 pF capacitors to ground connections. PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 53 RTxC, TRxC Receive W/REQ Request 1 W/REQ Wait 2 SYNC Output 3 INT 4 TRxC, RTxC Transmit W/REQ Request 6 W/REQ Wait 6 DTR/REQ Request 7 INT 8 CTS, DCD SYNC Input 9 INT 10 Figure 34. Z85C30 System Timing Diagram Table 8. Z85C30 System Timing Table No Symbol Parameter a,b 1 TdRXC(REQ) RxC High to W/REQ Valid 2 TdRXC(W) RxC High to Wait Inactive1,2,c 3 TdRdXC(SY) PS011705-0608 1,2 RxC High to SYNC Valid 8.5 MHz 10 MHz 16 MHz Min Max Min Max Min Max 8 12 8 12 8 12 8 14 8 14 8 14 4 7 4 7 4 70 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 54 Table 8. Z85C30 System Timing Table (continued) No Symbol 8.5 MHz 10 MHz Min Max Min Max Min Max 10 16 10 16 10 16 5 8 5 8 5 8 5 11 5 11 5 11 4 7 4 7 4 7 TxC Low to INT Valid 6 10 6 10 6 10 SYNC to INT Valid 2,3 2 6 2 6 2 6 2 3 2 3 2 3 2 6 2 6 2 6 Parameter 1,2,3 4 TsRXC(INT) RxC High to INT Valid 5 TdTXC(REQ) TxC Low to W/REQ Valid2,d 2,3,4 6 TdTXC(W) TxC Low to Wait Inactive 7 TdTXC(DRQ) TxC Low to DTR/REQ Valid3,4 8 TdTXC(INT) 9a TdSY(INT) 2,3,4 2,3,e 9b TdSY(INT) SYNC to INT Valid 10 TdEXT(INT) DCD or CTS to INT Valid2,3 16 MHz a. RxC is RTxC or TRxC, whichever is supplying the receive clock. b. Units equal to TcPc. c. Open-drain output, measured with open-drain test load. d. TxC is TRxC or RTxC whichever is supplying the transmit clock. e. Units equal to AS. Table 9. Z85C30 Read/Write Timing 8.5 MHz 10 MHz 16 MHz No Symbol Parameter Min Max Min Max Min Max 1 TwPCI PCLK Low Width 45 2000 40 2000 26 2000 2 TwPCh PCLK High Width 45 2000 40 2000 26 2000 3 TfPC PCLK Fail Time 10 10 5 4 TrPC PCLK Rise Time 10 10 5 5 TcPC PCLK Cycle Time 118 6 TsA(WR) Address to WR Fail Setup Time 66 50 35 7 ThA(WR) Address to WR Rise Hold Time 0 0 0 8 TsA(RD) Address to RD Fall Setup Time 66 50 35 9 ThA(RD) Address to RD Rise Hold Time 0 0 0 10 TsiA(PC) INTACK to PCLK Rise Setup Time 20 20 15 PS011705-0608 4000 100 4000 61 4000 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 55 AS 2 4 CS0 7 CS1 4 6 14 INTACK 7 8 R/W Read 9 10 R/W Write 12 10 DS 12 AD7-AD0 Write 13 18 16 15 17 AD7-AD0 Read 20 16 19 15 23 21 22 24 W/REQ Wait 25 W/REQ Request 26 DTR/REQ Request 27 INT 44 PCLK 41 40 43 42 44 Figure 35. Z80C30 Read/Write Timing Diagram PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 56 AS 7 INTACK 8 DS 30 29 20 19 AD7-AD0 31 22 32 33 IEI 35 34 IEO 36 INT Figure 36. Z80C30 Interrupt Acknowledge Timing Diagram AS 37 38 35 DS Figure 37. Z80C30 Reset Timing Diagram Table 10. Z80C30 Read/Write Timinga 8 MHz 10 MHz No Symbol Parameter Min 1 TwAS AS Low Width 35 30 2 TdDS(AS) DS Rise to AS Fall Delayb 15 10 2 Max Min 3 TsCSO(AS) CS0 to AS Rise Setup Time 0 0 4 ThCSO(AS) CS0 to AS Rise Hold Time2 30 20 PS011705-0608 Max Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 57 Table 10. Z80C30 Read/Write Timinga (continued) 8 MHz No Symbol Parameter Min 10 MHz Max Min 2 65 50 5 TsCS1(DS) CS1 to DS Fall Setup Time 6 ThCS1(DS) CS1 to DS Rise Hold Time2 30 20 7 TsiA(AS) INTACK to AS Rise Setup Time 10 10 8 ThIA(AS) INTACK to AS Rise Hold Time 150 125 9 TsRWR(DS) R/W (Read) to DS Fall Setup Time 65 50 10 ThRW(DS) R/W to DS Rise Hold Time 0 0 11 TsRWW(DS) R/W (Write) to DS Fall Setup Time 0 0 12 TdAS(DS) AS Rise to DS Fall Delay 30 20 13 TwDSI DS Low Width 150 125 14 TrC Valid Access Recovery Timec 4TcPC 4TcPC 2 Max 15 TsA(AS) Address to AS Rise Setup Time 10 10 16 ThA(AS) Address to AS Rise Hold Time2 25 20 17 TsDW(DS) Write Data to DS Fall Setup Time 15 10 18 ThDW(DS) Write Data to DS Rise Hold Time 0 0 19 TdDS(DA) DS Fall to Data Active Delay 0 0 20 TdDSr(DR) DS Rise to Read Data Not Valid Delay 0 0 21 TdDSf(DR) DS Fall to Read Data Valid Delay 140 120 22 TdAS(DR) AS Rise to Read Data Valid Delay 250 190 23 TdDS(DRz) DS Rise to Read Data Float Delayd 40 35 24 TdA(DR) Address Required Valid to Read Data Valid Delay 260 210 25 TdDS(W) DS Fall to Wait Valid Delaye 170 160 26 TdDSf(REQ) DS Fall to W/REQ Not Valid Delay 170 160 27 TdDSr(REQ) DS Fall to DTR/REQ Not Valid Delay 4TcPC 4TcPC 28 TdAS(INT) AS Rise to INT Valid Delay5 500 500 29 TdAS(DSA) AS Rise to DS Fall (Acknowledge) Delayf 250 225 30 TwDSA DS (Acknowledge) Low Width 150 125 PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 58 Table 10. Z80C30 Read/Write Timinga (continued) 8 MHz Min 10 MHz No Symbol Parameter Max Min 31 TdDSA(DR) DS Fall (Acknowledge) to Read Data Valid Delay 32 TsiEI(DSA) IEI to DS Fall (Acknowledge) Setup Time 80 80 33 ThIEI(DSA) IEI to DS Rise (Acknowledge) Hold Time 0 0 34 TdIEI(IEO) IEI to IEO Delay 140 g 120 90 90 200 175 450 450 35 TdAS(IEO) AS Rise to IEO Delay 36 TdDSA(INT) DS Fall (Acknowledge) to INT Inactive Delay5 37 TdDS(ASQ) DS Rise to AS Fall Delay for No Reset 15 15 38 TdASQ(DS) AS Rise to DS Fall Delay for No Reset 20 15 h Max 39 TwRES AS and DS Coincident Low for Reset 40 TwPCI PCLK Low Width 50 1000 40 1000 41 TwPCh PCLK High Width 50 1000 40 1000 42 TcPC PCLK Cycle Time 125 2000 100 2000 43 TrPC PCLK Rise Time 10 10 44 TfPC PCLK Fall Time 10 10 150 100 a. Units in nanoseconds (ns) unless otherwise noted. b. Parameter does not apply to Interrupt Acknowledge transactions. c. Parameter applies only between transactions involving the SCC. d. Float delay is defined as the time required for a 0.5 V change in the output with a maximum DC load and a minimum AC load. e. Open-drain output, measured with open-drain test load. f. Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of TdAS(IEO) for the highest priority device in the daisy chain TsiEI(DSA) for the Z-SCC, and TdIElf(IEO) for each device separating them in the daisy chain. g. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction. h. Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the Z-SCC. All timing references assume 20 V for a logic "1" and 08 V for a logic "0". Figure 38 displays Z80C30 general timing and Table 11 lists the associated general timing characteristics. Figure 39 displays the Z80C30 system timing with the associated parameters listed in Table 12. PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 59 PCLK 1 W/REQ Request 2 W/REQ Wait 3 RTxC, TRxC Receive 5 4 6 7 RxD 8 9 SYNC External 10 TRxC, RTxC Transmit 12 11 TxD 13 TRxC Output 14 15 RTxC 16 17 TRxC 18 19 20 CTS, DCD 22 22 22 22 SYNC Input Figure 38. Z80C30 General Timing Diagram Table 11. Z80C30 General Timinga 8 MHz No Symbol Parameter 1 TdPC(REQ) PCLK Low to W/REQ Valid 250 200 2 TsPC(W) PCLK Low to Wait Inactive 350 300 3 TsRXC(PC) RxC High to PCLK High Setup Time b,c PS011705-0608 Min 10 MHz NA Max NA Min NA Max NA Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 60 Table 11. Z80C30 General Timinga (continued) 8 MHz 10 MHz No Symbol Parameter Min 4 TsRXD(RXCr) RxD to RxC High Setup Time 0 0 5 ThRXD(RxCr) RxD to RxC High Hold Time2 150 125 0 0 150 125 -200 -150 5TcPc 5TcPc NA NA 2,d 6 TsRXD(RXCf) RxD to RxC Low Setup Time 7 ThRXD(RXCf) RxD to RxC Low Hold Time2,4 2 8 TsSY(RXC) SYNC to RxC High Setup Time 9 ThSY(RXC) SYNC to RxC High Hold Time2 10 TsTXC(PC) TxC Low to PCLK High Setup Time 11 TdTXCf(TXD) TxC Low to TxD Delay5 12 TdTxCr(TXD) TxC High to TxD Delay 13 TdTXD(TRX) TxD to TRxC Delay e,3 5,4 Max Min 190 150 190 150 200 140 f 130 120 130 120 472 400 59 50 14 TwRTXh RTxC High Width 15 TwRTXI TRxC Low Width6 6,g 16a TcRTX RTxC Cycle Time 16b TxRx (DPLL) DPLL Cycle Time Min7,h i 17 TcRTXX Crystal Osc. Period 18 TwTRXh TRxC High Width6 130 120 6 130 120 118 Max 1000 100 19 TwTRXI TRxC Low Width 20 TcTRX TRxC Cycle Time6,7 472 400 21 TwEXT DCD or CTS Pulse Width 200 120 22 TwSY SYNC Pulse Width 200 120 1000 a. Units in nanoseconds (ns) otherwise noted. b. RxC is RTxC or (TRxC, whichever is supplying the receive clock. c. Synchronization of RxC to PCLK is eliminated in divide by four operation. d. Parameter applies only to FM encoding/decoding. e. TxC is TRxC or RTxC, whichever is supplying the transmit clock. f. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are identical to case PCLK requirements. g. The maximum receive or transmit data rate is 1/4 PCLK. h. Applies to DPLL clock source oniy Maximum data rate of 1/4 PCLK still applies DPLL clock should have a 50% duty cycle. i. Both RTxC and SYNC have 30 pf capacitors to ground connected to them. PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 61 PCLK 1 W/REQ Request 2 W/REQ Wait 3 RTxC, TRxC Receive 4 6 5 7 RxD 9 8 SYNC External 10 TRxC, RTxC Transmit 11 12 TxD 10 TRxC Output 15 14 RTxC 18 17 TRxC 19 18 20 CTS, DCD 21 21 22 22 SYNC Input Figure 39. Z80C30 System Timing Diagram Table 12. Z80C30 System Timing 8 MHz 10 MHz No Symbol Parameter Min Max Min Max 1 TdRXC(REQ) RxC High to W/REQ Valid a,b 8 12 8 12 2 TdRXC(W) RxC High to Wait Inactive 1,2,c 8 14 8 14 3 TdRdXC(SY) RxC High to SYNC Valid1,2 4 7 4 7 TdRXC(INT) RxC High to INT Valid1,2,3 8 12 8 12 4 PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 62 Table 12. Z80C30 System Timing (continued) 8 MHz No Symbol Parameter Note 5 TdTXC(REQ) d,2 TxC Low to W/REQ Valide,2 1,2,3 10 MHz Min Max Min Max 2 3 2 3 5 8 5 8 6 TdTXC(W) TxC Low to Wait Inactive 5 11 5 11 7 TdTXC(DRQ) TxC Low to DTR/REQ Valid2,3 4 7 4 7 4 6 4 6 2 3 2 3 2 6 2 6 2 3 2 3 2 3 2 3 8 TdTXC(INT) TxC Low to INT Valid 1,2 Note2,4 2,3 9a TdSY(INT) SYNC to INT Valid 9b TdSY(INT) SYNC to INT Valid2,3,4 10 TdEXT(INT) Note 2,3,4 a. RxC is RTxC or TRxC whichever is supplying the receive clock. b. Units equal to TcPc. c. Open-drain output, measured with open-drain test load. d. Units equal to AS. e. TxC is TRxC or RTxC, whichever is supplying the transmit clock. PS011705-0608 Electrical Characteristics CMOS SCC Serial Communications Controller Product Specification 63 Packaging Figure 40 displays the 40-pin DIP package available for Z80C30 and Z85C30 devices. Figure 40. 40-Pin DIP Package Diagram PS011705-0608 Packaging CMOS SCC Serial Communications Controller Product Specification 64 Figure 41 displays the 44-pin Plastic Leaded Chip Carriers (PLCC) package diagram available for Z80C30 and Z85C30 devices. Figure 41. 44-Pin PLCC Package Diagram PS011705-0608 Packaging CMOS SCC Serial Communications Controller Product Specification 65 Ordering Information Table 13 provides ordering information for the Z80C30 and the Z85C30 devices. Table 13. Z80C30/Z85C30 Ordering Information 8 MHz 10 MHz 16 MHz Z80C3008PSC Z80C3010PSC Z85C3016PSC Z80C3008VSC Z80C3010VSC Z85C3016VSC Z85C3008PSC/PEC Z85C3010PSC/PEC Z85C3008VSCNEC Z85C3010VSCNEC For complete details on Z80C30 and Z85C30 devices, development tools and downloadable software, visit www.zilog.com. PS011705-0608 Packaging CMOS SCC Serial Communications Controller Product Specification 66 Part Number Suffix Designations Zilog(R) part numbers consist of a number of components, as indicated in the following example: Example Part number Z80C3016PSG is a Z80C30, 16 MHz, PLCC, 0 C to +70 C, Lead Free Z 80C30 16 P S G Environmental Flow G = Lead Free Temperature Range S = 0 C to +70 C E = Extended, -40 C to +100 C Package P = Plastic DIP V = Plastic Leaded Chip Carrier D = Ceramic DIP Speed 8 = 8 MHz 10 = 10 MHz 16 = 16 MHz Product Number Zilog(R) Prefix PS011705-0608 Packaging CMOS SCC Serial Communications Controller Product Specification 67 Customer Support For answers to technical questions about the product, documentation, or any other issues with Zilog's offerings, please visit Zilog's Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog's Technical Support at http://support.zilog.com. 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