PIC16F887-I/PT - Microchip Technology

PIC16F882/883/884/886/887

Data Sheet

28/40/44-Pin, Enhanced Flash-Based 8-Bit

CMOS Microcontrollers with

nanoWatt Technology

Information contained in this publication regarding device

applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce

and may be supers eded by up dates. I t is you r r es ponsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Prog ra m ming , IC SP, ICEPI C , M i n di , MiWi , MPASM, MP L AB

Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,

PICkit, PICDEM, P ICDEM.net, PICtail , PIC32 logo, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Total Endurance, TSHARC, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microch ip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

PIC16F882/883/884/886/887

High-Performance RISC CPU:

• Only 35 Instructions to Lea rn:

- All single-cycle instructions except branches

• Ope rati ng Speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Interrupt Capability

• 8-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

S pecial Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%

- Software selectable frequency range of

8 MHz to 31 kHz

- Softwa re tunab le

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for

power saving s

• Power-Saving Sleep mode

• Wide Operating Voltage Range (2.0V-5.5V)

• Indus tri al and Extended Tem pe r atu re Ra nge

• Power-on Reset (P OR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-ou t Reset (BOR) with Softwa re Control

Option

• Enhanced Low-Current Watchdog Timer (WDT)

with On-Ch ip Os ci ll ator (software sele ctable

nominal 268 seconds wit h full prescaler) with

software enable

• Multiplexed Master Clear with Pull-up/Input Pin

• Programmable Code Protection

• High Endurance Flash/EEPROM Cell:

- 10 0,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

• Program Memory Read/Write during run time

• In-Circuit Debugger (on board)

Low-Power Features:

• Standby Current:

- 50 nA @ 2.0V, typical

• Ope rati ng Curren t:

-11μA @ 32 kHz, 2.0V, typical

-220μA @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

Peripheral Feat ures:

• 24/35 I/O Pins with Individual Direction Control:

- High current source/sink for direct LED drive

- Interrupt-on-Change pin

- Individually programmable weak pull-ups

- Ultra Low-Power Wa ke-up (ULPWU)

• Analog Comparator Mo dule with:

- Two analog comparators

- Programmable on-chip voltage reference

(CVREF) module (% of VDD)

- F ixed voltage reference (0.6V)

- Comparator inputs and outputs externally

accessible

- SR Latch mode

- External Timer1 Ga te (c ou nt enab le )

• A/D Converter:

- 10-bit resolution and 11/14 channels

• Timer0: 8-bit Timer/Counter with 8-bit

Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Dedicated low-power 32 kHz oscillator

• Timer2: 8-bit Timer/Counter with 8-bit Period

• Enhanced Capture, Compare, PWM+ Module:

- 1 6-bit Capture, max. resolution 12.5 n s

- Compare, max. resolution 200 ns

- 10-bit PWM with 1, 2 or 4 output channels,

programmable “dead time”, max. frequency

20 kHz

- PWM output steering control

• Cap ture , Comp a r e, PWM Mo dul e:

- 1 6-bit Capture, max. resolution 12.5 ns

- 16-bit Compare, max. resolution 200 ns

- 10-bit PWM, max. frequency 20 kHz

• Enhanced USART Module:

- Supports RS-485, RS-232, and LIN 2.0

- Auto-Baud Detect

- Auto-Wake-Up on Start bit

• In-C ircuit Seri al Prog ram mingTM (ICSPTM) via T wo

Pins

• Master Synchronous Serial Port (MSSP) Module

supporting 3-wire SPI (all 4 modes) and I2C™

Master and Slave Modes with I2C Address Mask

28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

nanoWatt Technology

PIC16F882/883/884/886/887

Device

Program

Memory Dat a Memory I/O 10-bit A/D

(ch) ECCP/

CCP EUSART MSSP Comparators Timers

8/16-bit

Flash

(words) SRAM

(bytes) EEPROM

(bytes)

PIC16F882 2048 128 128 24 11 1/1 1 1 2 2/1

PIC16F883 4096 256 256 24 11 1/1 1 1 2 2/1

PIC16F884 4096 256 256 35 14 1/1 1 1 2 2/1

PIC16F886 8192 368 256 24 11 1/1 1 1 2 2/1

PIC16F887 8192 368 256 35 14 1/1 1 1 2 2/1

PIC16F882/883/884/886/887

Pin Diagrams – PIC16F882/883/886, 28- Pin PDIP, SOIC, SSOP

TABLE 1: PIC16F882/883/886 28-PIN SUMMARY (PDIP, SOIC, SSOP)

I/O Pin Analog Comparators Timers ECCP EUSART MSSP Interrupt Pull-up Basic

RA0 2AN0/ULPWU C12IN0- — — — — — — —

RA1 3 AN1 C12IN1- — — — — — — —

RA2 4AN2 C2IN+ — — — — — — VREF-/CVREF

RA3 5 AN3 C1IN+ — — — — — — VREF+

RA4 6 — C1OUT T0CKI — — — — — —

RA5 7 AN4 C2OUT — — — SS —— —

RA6 10 — — — — — — — — OSC2/CLKOUT

RA7 9 — — — — — — — — OSC1/CLKIN

RB0 21 AN12 — — — — — IOC/INT Y —

RB1 22 AN10 C12IN3- — P1C — — IOC Y —

RB2 23 AN8 — — P1B — — IOC Y —

RB3 24 AN9 C12IN2- — — — — IOC Y PGM

RB4 25 AN11 — — P1D — — IOC Y —

RB5 26 AN13 — T1G — — — IOC Y —

RB6 27 — — — — — — IOC YICSPCLK

RB7 28 — — — — — — IOC Y ICSPDAT

RC0 11 — — T1OSO/T1CKI — — — — — —

RC1 12 — — T1OSI CCP2 — — — — —

RC2 13 — — — CCP1/P1A — — — — —

RC3 14 — — — — — SCK/SCL — — —

RC4 15 — — — — — SDI/SDA — — —

RC5 16 — — — — — SDO — — —

RC6 17 — — — — TX/CK — — — —

RC7 18 — — — — RX/DT — — — —

RE3 1 — — — — — — — Y(1) MCLR/VPP

—20 — — — — — — — — VDD

— 8 — — — — — — — — VSS

—19 — — — — — — — — VSS

Note 1: Pull-up activated only with external MCLR configuration.

14 15

PIC16F882/883/886

RE3/MCLR/VPP

RA0/AN0/ULPWU/C12IN0-

RA1/AN1/C12IN1-

RA2/AN2/VREF-/CVREF/C2IN+

RA3/AN3/VREF+/C1IN+

RA4/T0CKI/C1OUT

RA5/AN4/SS/C2OUT

VSS

RA7/OSC1/CLKIN

RA6/OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/P1A/CCP1

RC3/SCK/SCL

RB7/ICSPDAT

RB6/ICSPCLK

RB5/AN13/T1G

RB4/AN11/P1D

RB3/AN9/PGM/C12IN2-

RB2/AN8/P1B

RB1/AN10/P1C/C12IN3-

RB0/AN12/INT

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

28-pin PDIP, SOIC, SSOP

PIC16F882/883/884/886/887

Pin Diagrams – PIC16F882/883/886, 28-Pin QFN

PIC16F882/883/886

RA1/AN1/C12IN1-

RA0/AN0/ULPWU/C12IN0-

RE3/MCLR/VPP

RB7/ICSPDAT

RB6/ICSPCLK

RB5/AN13/T1G

RB4/AN11/P1D

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/P1A/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RA2/AN2/VREF-/CVREF/C2IN+

RA3/AN3/VREF+/C1IN+

RA4/T0CKI/C1OUT

RA5/AN4/SS/C2OUT

VSS

RA7/OSC1/CLKIN

RA6/OSC2/CLKOUT

RB3/AN9/PGM/C12IN2-

RB2/AN8/P1B

RB1/AN10/P1C/C12IN3-

RB0/AN12/INT

VDD

VSS

RC7/RX/DT

28-pin QFN

PIC16F882/883/884/886/887

TABLE 2: PIC16F882/883/886 28-PIN SUMMARY (QFN)

I/O Pin Analog Comparators Timers ECCP EUSART MSSP Interrupt Pull-up Basic

RA0 27 AN0/ULPWU C12IN0- — — — — — — —

RA1 28 AN1 C12IN1- — — — — — — —

RA2 1AN2 C2IN+ — — — — — — VREF-/CVREF

RA3 2 AN3 C1IN+ — — — — — — VREF+

RA4 3 — C1OUT T0CKI — — — — — —

RA5 4 AN4 C2OUT — — — SS —— —

RA6 7 — — — — — — — — OSC2/CLKOUT

RA7 6 — — — — — — — — OSC1/CLKIN

RB0 18 AN12 — — — — — IOC/INT Y —

RB1 19 AN10 C12IN3- — P1C — — IOC Y —

RB2 20 AN8 — — P1B — — IOC Y —

RB3 21 AN9 C12IN2- — — — — IOC Y PGM

RB4 22 AN11 — — P1D — — IOC Y —

RB5 23 AN13 — T1G — — — IOC Y —

RB6 24 — — — — — — IOC YICSPCLK

RB7 25 — — — — — — IOC Y ICSPDAT

RC0 8 — — T1OSO/T1CKI — — — — — —

RC1 9 — — T1OSI CCP2 — — — — —

RC2 10 — — — CCP1/P1A — — — — —

RC3 11 — — — — — SCK/SCL — — —

RC4 12 — — — — — SDI/SDA — — —

RC5 13 — — — — — SDO — — —

RC6 14 — — — — TX/CK — — — —

RC7 15 — — — — RX/DT — — — —

RE3 26 — — — — — — — Y(1) MCLR/VPP

—17 — — — — — — — — VDD

— 5 — — — — — — — — VSS

—16 — — — — — — — — VSS

Note 1: Pull-up activated only with external MCLR configuration.

PIC16F882/883/884/886/887

Pin Diagrams – PIC16F884/887, 40-Pin PDIP

PIC16F884/887

RE3/MCLR/VPP

RA0/AN0/ULPWU/C12IN0-

RA1/AN1/C12IN1-

RA2/AN2/VREF-/CVREF/C2IN+

RA3/AN3/VREF+/C1IN+

RA4/T0CKI/C1OUT

RA5/AN4/SS/C2OUT

RE0/AN5

RE1/AN6

RE2/AN7

VDD

VSS

RA7/OSC1/CLKIN

RA6/OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/P1A/CCP1

RC3/SCK/SCL

RD0

RD1

RB7/ICSPDAT

RB6/ICSPCLK

RB5/AN13/T1G

RB4/AN11

RB3/AN9/PGM/C12IN2-

RB2/AN8

RB1/AN10/C12IN3-

RB0/AN12/INT

VDD

VSS

RD7/P1D

RD6/P1C

RD5/P1B

RD4

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3

RD2

40-pin PDIP

PIC16F882/883/884/886/887

TABLE 3: PIC16F884/887 40-PIN SUMMARY (PDIP)

I/O Pin Analog Comparators Timers ECCP EUSART MSSP Interrupt Pull-up Basic

RA0 2AN0/ULPWU C12IN0- — — — — — — —

RA1 3 AN1 C12IN1- — — — — — — —

RA2 4AN2 C2IN+ — — — — — — VREF-/CVREF

RA3 5 AN3 C1IN+ — — — — — — VREF+

RA4 6 — C1OUT T0CKI — — — — — —

RA5 7 AN4 C2OUT — — — SS —— —

RA6 14 — — — — — — — — OSC2/CLKOUT

RA7 13 — — — — — — — — OSC1/CLKIN

RB0 33 AN12 — — — — — IOC/INT Y —

RB1 34 AN10 C12IN3- — — — — IOC Y —

RB2 35 AN8 — — — — — IOC Y —

RB3 36 AN9 C12IN2- — — — — IOC Y PGM

RB4 37 AN11 — — — — — IOC Y —

RB5 38 AN13 — T1G — — — IOC Y —

RB6 39 — — — — — — IOC YICSPCLK

RB7 40 — — — — — — IOC Y ICSPDAT

RC0 15 — — T1OSO/T1CKI — — — — — —

RC1 16 — — T1OSI CCP2 — — — — —

RC2 17 — — — CCP1/P1A — — — — —

RC3 18 — — — — — SCK/SCL — — —

RC4 23 — — — — — SDI/SDA — — —

RC5 24 — — — — — SDO — — —

RC6 25 — — — — TX/CK — — — —

RC7 26 — — — — RX/DT — — — —

RD0 19 — — — — — — — — —

RD1 20 — — — — — — — — —

RD2 21 — — — — — — — — —

RD3 22 — — — — — — — — —

RD4 27 — — — — — — — — —

RD5 28 — — — P1B — — — — —

RD6 29 — — — P1C — — — — —

RD7 30 — — — P1D — — — — —

RE0 8AN5 — — — — — — — —

RE1 9 AN6 — — — — — — — —

RE2 10 AN7 — — — — — — — —

RE3 1 — — — — — — — Y(1) MCLR/VPP

—11 — — — — — — — — VDD

—32 — — — — — — — — VDD

—12 — — — — — — — — VSS

—31 — — — — — — — — VSS

Note 1: Pull-up activated only with external MCLR configuration.

PIC16F882/883/884/886/887

Pin Diagrams – PIC16F884/887, 44-Pin QFN

44-pin QFN

PIC16F884/887

RA6/OSC2/CLKOUT

RA7/OSC1/CLKIN

VSS

VDD

RE2/AN7

RE1/AN6

RE0/AN5

RA5/AN4/SS/C2OUT

RA4/T0CKI/C1OUT

RC7/RX/DT

RD4

RD5/P1B

RD6/P1C

RD7/P1D

VSS

VDD

RB0/AN12/INT

RB1/AN10/C12IN3-

RB2/AN8

RB3/AN9/PGM/C12IN2-

RB4/AN11

RB5/AN13/T1G

RB6/ICSPCLK

RB7/ICSPDAT

RE3/MCLR/VPP

RA0/AN0/ULPWU/C12IN0-

RA1/AN1/C12IN1-

RA2/AN2/VREF-/CVREF/C2IN+

RA3/AN3//VREF+/C1IN+

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3

RD2

RD1

RD0

RC3/SCK/SCL

RC2/P1A/CCP1

RC1/T1OSCI/CCP2

RC0/T1OSO/T1CKI

PIC16F882/883/884/886/887

TABLE 4: PIC16F884/887 44-PIN SUMMARY (QFN)

I/O Pin Analog Comparators Timers ECCP EUSART MSSP Interrupt Pull-up Basic

RA0 19 AN0/ULPWU C12IN0- — — — — — — —

RA1 20 AN1 C12IN1- — — — — — — —

RA2 21 AN2 C2IN+ — — — — — — VREF-/CVREF

RA3 22 AN3 C1IN+ — — — — — — VREF+

RA4 23 —C1OUT T0CKI — — — — — —

RA5 24 AN4 C2OUT — — — SS —— —

RA6 33 — — — — — — — — OSC2/CLKOUT

RA7 32 — — — — — — — — OSC1/CLKIN

RB0 9AN12 — — — — — IOC/INT Y —

RB1 10 AN10 C12IN3- — — — — IOC Y —

RB2 11 AN8 — — — — — IOC Y —

RB3 12 AN9 C12IN2- — — — — IOC Y PGM

RB4 14 AN11 — — — — — IOC Y —

RB5 15 AN13 — T1G — — — IOC Y —

RB6 16 — — — — — — IOC YICSPCLK

RB7 17 — — — — — — IOC Y ICSPDAT

RC0 34 — — T1OSO/T1CKI — — — — — —

RC1 35 — — T1OSI CCP2 — — — — —

RC2 36 — — — CCP1/P1A — — — — —

RC3 37 — — — — — SCK/SCL — — —

RC4 42 — — — — — SDI/SDA — — —

RC5 43 — — — — — SDO — — —

RC6 44 — — — — TX/CK — — — —

RC7 1 — — — — RX/DT — — — —

RD0 38 — — — — — — — — —

RD1 39 — — — — — — — — —

RD2 40 — — — — — — — — —

RD3 41 — — — — — — — — —

RD4 2 — — — — — — — — —

RD5 3 — — — P1B — — — — —

RD6 4 — — — P1C — — — — —

RD7 5 — — — P1D — — — — —

RE0 25 AN5 — — — — — — — —

RE1 26 AN6 — — — — — — — —

RE2 27 AN7 — — — — — — — —

RE3 18 — — — — — — — Y(1) MCLR/VPP

— 7 — — — — — — — — VDD

—8 — — — — — — — — VDD

—28 — — — — — — — — VDD

—6 — — — — — — — — VSS

—30 — — — — — — — — VSS

—31 — — — — — — — — VSS

—13 — — — — — — — — NC (no connect)

— 29 — — — — — — — — NC (no co nnec t)

Note 1: Pull-up activated only with external MCLR configuration.

PIC16F882/883/884/886/887

Pin Diagrams – PIC16F884/887, 44-Pin TQFP

44-pin TQFP

PIC16F884/887

RC0/T1OSO/T1CKI

RA6/OSC2/CLKOUT

RA7/OSC1/CLKIN

VSS

VDD

RE2/AN7

RE1/AN6

RE0/AN5

RA5/AN4/SS/C2OUT

RA4/T0CKI/C1OUT

RC7/RX/DT

RD4

RD5/P1B

RD6/P1C

RD7/P1D

VSS

VDD

RB0/AN12/INT

RB1/AN10/C12IN3-

RB2/AN8

RB3/AN9/PGM/C12IN2-

RB4/AN11

RB5/AN13/T1G

RB6/ICSPCLK

RB7/ICSPDAT

RE3/MCLR/VPP

RA0/AN0/ULPWU/C12IN0-

RA1/AN1/C12IN1-

RA2/AN2/VREF-/CVREF/C2IN+

RA3/AN3//VREF+/C1IN+

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3

RD2

RD1

RD0

RC3/SCK/SCL

RC2/P1A/CCP1

RC1/T1OSCI/CCP2

PIC16F882/883/884/886/887

TABLE 5: PIC16F884/887 44-PIN SUMMARY (TQFP)

I/O Pin Analog Comparators Timers ECCP EUSART MSSP Interrupt Pull-up Basic

RA0 19 AN0/ULPWU C12IN0- — — — — — — —

RA1 20 AN1 C12IN1- — — — — — — —

RA2 21 AN2 C2IN+ — — — — — — VREF-/CVREF

RA3 22 AN3 C1IN+ — — — — — — VREF+

RA4 23 —C1OUT T0CKI — — — — — —

RA5 24 AN4 C2OUT — — — SS —— —

RA6 31 — — — — — — — — OSC2/CLKOUT

RA7 30 — — — — — — — — OSC1/CLKIN

RB0 8AN12 — — — — — IOC/INT Y —

RB1 9 AN10 C12IN3- — — — — IOC Y —

RB2 10 AN8 — — — — — IOC Y —

RB3 11 AN9 C12IN2- — — — — IOC Y PGM

RB4 14 AN11 — — — — — IOC Y —

RB5 15 AN13 — T1G — — — IOC Y —

RB6 16 — — — — — — IOC YICSPCLK

RB7 17 — — — — — — IOC Y ICSPDAT

RC0 32 — — T1OSO/T1CKI — — — — — —

RC1 35 — — T1OSI CCP2 — — — — —

RC2 36 — — — CCP1/P1A — — — — —

RC3 37 — — — — — SCK/SCL — — —

RC4 42 — — — — — SDI/SDA — — —

RC5 43 — — — — — SDO — — —

RC6 44 — — — — TX/CK — — — —

RC7 1 — — — — RX/DT — — — —

RD0 38 — — — — — — — — —

RD1 39 — — — — — — — — —

RD2 40 — — — — — — — — —

RD3 41 — — — — — — — — —

RD4 2 — — — — — — — — —

RD5 3 — — — P1B — — — — —

RD6 4 — — — P1C — — — — —

RD7 5 — — — P1D — — — — —

RE0 25 AN5 — — — — — — — —

RE1 26 AN6 — — — — — — — —

RE2 27 AN7 — — — — — — — —

RE3 18 — — — — — — — Y(1) MCLR/VPP

— 7 — — — — — — — — VDD

—28 — — — — — — — — VDD

— 6 — — — — — — — — VSS

— 13 — — — — — — — — NC (no co nnec t)

—29 — — — — — — — — VSS

— 34 — — — — — — — — NC (no co nnec t)

—33 — — — — — — — — NC (no connect)

— 12 — — — — — — — — NC (no co nnec t)

Note 1: Pull-up activated only with external MCLR configuration.

PIC16F882/883/884/886/887

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 Memory Organizati on................................................................................................................................................................. 21

3.0 I/O Ports.............................. ........................... ............................ ..................... ........................................................................... 39

4.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 61

5.0 Timer0 Module ........................................................................................................................................................................... 73

6.0 Timer1 Module with Gate Control............................................................................................................................................... 76

7.0 Timer2 Module ........................................................................................................................................................................... 81

8.0 Comparator Module....................................................... .... .... ......... .... .... .... ......... .... .... .... ........................................................... 83

9.0 Analog-to-Digital Converter (ADC) Module . ............................................................................................................................... 99

10.0 Data EEPROM and Flash Program Memory Control...................................................... ................. ...... .................................. 111

11.0 Enhanced Capture/Compare/PWM Module.................. .... .... ......... .. .... .... .... ......... .. .... .... ......... .. .... .... . ..................................... 123

12.0 Enhanced Universal Sync hronous As ynchr onous Receiver Transmitter (EUSART)............................................................... 151

13.0 Master Sy nchronous Serial Port (M SSP ) Module .................................................................................................................... 179

14.0 Special Features of the CPU........................ ..................... ..................... ........................... ....................................................... 209

15.0 Instruction Set Summary.......................................................................................................................................................... 231

16.0 Development Support. .............................................................................................................................................................. 241

17.0 Electrical Specifications............................................................................................................................................................ 245

18.0 DC and AC Characteristics Graphs and Tables............................. .... .... .... ........... .... .... .... ........... .... ........................................ 273

19.0 Packa g i n g In fo rmation............................ ..................... ........................... ..................... ............................................................. 301

Appendix A: Data Sheet Revision History........................................................ .... ........... .... ...... ......................................................... 313

Appendix B: Migrating from other PIC® Devices................................................................................. .............................................. 313

Index .................................................................................................................................................................................................. 315

The Micro chip Web Site... ..................... ............................ ........................... .......................... ............................................................ 323

Customer Change Notification Service .............................................................................................................................................. 323

Customer Support................................. ................. ...... ................. ................. ...... .............................................................................. 323

Reader Response.............................................................................................................................................................................. 324

Product Identification System............................................................................................................................................................. 325

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Customer No tific atio n Syst em

PIC16F882/883/884/886/887

1.0 DEVICE OVERVIEW

The PIC16F882/883/884/886/887 is covered by this

data she et. The P IC16F882/883/88 6 is avai lable in 28-

pin PDIP, SOIC, SSOP and QFN packages. The

PIC16F884/887 is available in a 40-pin PDIP and 44-

pin QFN and TQFP packages. Figure 1-1 shows the

block diagram of PIC16F882/883/886 and Figure 1-2

shows a block diagram of the PIC16F884/887 device.

Table 1-1 and Table 1-2 show the corresponding pinout

descriptions.

PIC16F882/883/884/886/887

FIGURE 1-1: PIC16F882/883/886 BLOCK DIAGRAM

Flash

Program

Memory

13 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

RAM

File

Registers

Direct Ad dr 7

RAM Addr 9

Addr MU X

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Instruction

Decode and

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

8-Level Stack 128(2)/256(1)/

2K(2)/4K(1)/

(13-Bit)

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR VSS

Brown-out

Reset

Timer0 Timer1

Data

EEPROM

128(2)/

EEDATA

EEADDR

T0CKI T1CKI

Configuration

Internal

Oscillator

T1G

VDD

Timer2 ECCP

Block

2 Analog ComparatorsVREF+and Reference

Analog-To-Digital Converter

(ADC)

AN0

AN1

AN2

AN3

AN4

AN8

AN9

AN10

AN11

AN12

AN13

C1IN+

C12IN0-

C12IN1-

C12IN2-

C12IN3-

C1OUT

C2IN+

C2OUT

CCP1/P1A

P1B

P1C

P1D

PORTA

PORTC RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

PORTB

EUSART

TX/CK

RX/DT

PORTE

RE3

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RA7

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

Timer1

32 kHz

Oscillator

Master Synchronous

Serial Port (MSSP)

CCP2

SDO

SDI/SDA

SCK/SCL

VREF-

Note 1: PIC16F883 only.

2: PIC16F882 only.

VREF+

VREF-

CVREF

In-Circuit

Debugger

(ICD)

T1OSI

T1OSO

8K X 14

368 Bytes

256 Bytes

PIC16F882/883/884/886/887

FIGURE 1-2: PI C16F 88 4/PIC16F887 BLOCK DIAGRAM

PORTD RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

Flash

Program

Memory

13 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

RAM

File

Registers

Direct Addr 7

RAM Addr 9

Addr MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Instruction

Decode and

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

8-Level Stack 256(1)/368 Bytes

4K(1)/8K X 14

(13-Bit)

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR VSS

Brown-out

Reset

Timer0 Timer1

Data

EEPROM

256 Bytes

EEDATA

EEADDR

T0CKI T1CKI

Configuration

Internal

Oscillator

T1G

VDD

Timer2 ECCP

Block

2 Analog Comparators

and Reference

Analog-To-Digital Converter

(ADC)

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

PORTA

PORTC RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

PORTB

EUSART

PORTE

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RA7

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

Timer1

32 kHz

Oscillator

Master Synchronous

Serial Port (MSSP)

CCP2

Note 1: PIC16F 884 only.

RE0

RE1

RE2

RE3

SDO

SDI/SDA

SCK/SCL

CCP1/P1A

P1B

P1C

P1D

TX/CK

RX/DT

VREF+

VREF-

VREF+

VREF-

CVREF

C1IN+

C12IN0-

C12IN1-

C12IN2-

C12IN3-

C1OUT

C2IN+

C2OUT

In-Circuit

Debugger

(ICD)

T1OSI

T1OSO

PIC16F882/883/884/886/887

TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/AN0/ULPWU/C12IN0- RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

ULPWU AN — Ultra Low-Power Wake-up input.

C12IN0- AN — Comparator C1 or C2 negative input.

RA1/AN1/C12IN1- RA1 TTL CMOS Gener al purpose I/O.

AN1 AN — A/D Channel 1 input.

C12IN1- AN — Comparator C1 or C2 negative input.

RA2/AN2/VREF-/CVREF/C2IN+ RA2 TTL CMOS General purpose I/O.

AN2 AN — A/D Channel 2.

VREF- AN — A/D Negative Voltage Reference input.

CVREF — AN C omparator Voltage Reference output.

C2IN+ AN — Comparator C2 positive input.

RA3/AN3/VREF+/C1IN+ RA3 TTL — General purpose I/O.

AN3 AN — A/D Channel 3.

VREF+ AN — Programming voltage.

C1IN+ AN — Comparator C1 positive input.

RA4/T0CKI/C1OUT RA4 TTL CMOS General purpose I/O.

T0CKI ST — Timer0 clock input.

C1OUT — CMOS Comparator C1 output.

RA5/AN4/SS/C2OUT RA5 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel 4.

SS ST — Slave Select input.

C2OUT — CMOS Comparator C2 output.

RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O.

OSC2 — XTAL Master Clear with internal pull-up.

CLKOUT — CMOS FOSC/4 output.

RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O.

OSC1 XTAL — Crystal/Resonator.

CLKIN ST — External clock input/RC oscillator connection.

RB0/AN12/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN12 AN — A/D Channel 12.

INT ST — External interrupt.

RB1/AN10/P1C/C12IN3- RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN10 AN — A/D Channel 10.

P1C — CMOS PWM output.

C12IN3- AN — Comparator C1 or C2 negative input.

RB2/AN8/P1B RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN8 AN — A/D Channel 8.

P1B — CMOS PWM output.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels

HV = High Voltage XTAL = Crystal

PIC16F882/883/884/886/887

RB3/AN9/PGM/C12IN2- RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN9 AN — A/D Channel 9.

PGM ST — Low-voltage ICSP™ Programming enable pin.

C12IN2- AN — Comparator C1 or C2 negative input.

RB4/AN11 /P1D RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN11 AN — A/D Channel 11.

P1D — CMOS PWM output.

RB5/AN13/T1G RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN13 AN — A/D Channel 13.

T1G ST — Timer1 Gate input.

RB6/ICSPCLK RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

ICSPCLK ST — Serial Programming Clock.

RB7/ICSPDAT RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

ICSPDAT ST CMOS ICSP™ D a ta I/O.

RC0/T1OSO/T1CKI RC0 ST CMOS General purpose I/O.

T1OSO — CMOS Timer1 oscillator output.

T1CKI ST — Timer1 clock input.

RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O.

T1OSI ST — Timer1 oscillator input.

CCP2 ST CMOS Capture/Compare/PWM2.

RC2/P1A/CCP1 RC2 ST CMOS General purpose I/O.

P1A — CMOS PWM output.

CCP1 ST CMOS Capture/Compare/PWM1.

RC3/SCK/SCL R C3 ST CMOS General purpose I/O.

SCK ST CMOS SPI cl ock.

SCL ST OD I2C™ clock.

RC4/SDI/SDA RC4 ST CMOS General purpose I/O.

SDI ST — SPI data input.

SDA ST OD I2C data input/output.

RC5/SDO RC5 ST CMOS General purpose I/O.

SDO — CMOS SPI data output.

RC6/TX/CK RC6 ST CMOS General purpose I/O.

TX — CMOS EUSART asynchronous transmit.

CK ST CMOS EUSART synchronous clock.

RC7/RX/DT RC7 ST CMOS General purpose I/O.

RX ST — EU SART asynchronous input.

DT ST CMOS EUSART synchronous data.

RE3/MCLR/VPP RE3 TTL — G eneral purpose inpu t.

MCLR ST — Master Clear with internal pull-up.

VPP HV — Programming voltage.

VSS VSS Power — Ground reference.

VDD VDD Power — Positive supply.

TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels

HV = High Voltage XTAL = Crystal

PIC16F882/883/884/886/887

TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/AN0/ULPWU/C12IN0- RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

ULPWU AN — Ultra Low-Power Wake-up input.

C12IN0- AN — Comparator C1 or C2 negative input.

RA1/AN1/C12IN1- RA1 TTL CM O S General purpose I/O.

AN1 AN — A/D Channel 1 input.

C12IN1- AN — Comparator C1 or C2 negative input.

RA2/AN2/VREF-/CVREF/C2IN+ RA2 TTL CMOS General purpose I/O.

AN2 AN — A/D Channel 2.

VREF- AN — A/D Negative Voltage Reference input.

CVREF — AN Comparator Voltage Reference output.

C2IN+ AN — Comparator C2 positive input.

RA3/AN3/VREF+/C1IN+ RA3 TTL CM O S General purpose I/O.

AN3 AN — A/D Channel 3.

VREF+ AN — A/D Positive Voltage Reference input.

C1IN+ AN — Comparator C1 positive input.

RA4/T0CKI/C1OUT RA4 TTL CMOS General purpose I/O.

T0CKI ST — Timer0 clock input.

C1OUT — CMOS Comparator C1 output.

RA5/AN4/SS/ C 2OU T RA5 TTL CM O S General purpose I/O.

AN4 AN — A/D Channel 4.

SS ST — Slave Select input.

C2OUT — CMOS Comparator C2 output.

RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator.

CLKOUT — CMOS FOSC/4 output.

RA7/OSC1/CLKIN RA7 T TL CM O S G eneral purpose I/O.

OSC1 XTAL — Crystal/Resonator.

CLKIN ST — External clock input/RC oscillator connection.

RB0/AN12/INT RB0 T TL CM OS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN12 AN — A/D Channel 12.

INT ST — External in te rrupt.

RB1/AN10/C12IN3- RB1 TTL CMO S G eneral purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN10 AN — A/D Channel 10.

C12IN3- AN — Comparator C1 or C2 negative input.

RB2/AN8 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN8 AN — A/D Channel 8.

RB3/AN9/PGM /C12 IN2- RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN9 AN — A/D Channel 9.

PGM ST — Low-voltage ICSP™ Programming enable pin.

C12IN2- AN — Comparator C1 or C2 negative input.

Legend: AN = Analog input or output CMO S = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Sc hmit t Trigger input with CMOS levels

HV = High Voltage XTA L = Crystal

PIC16F882/883/884/886/887

RB4/AN11 RB4 TTL CM O S G eneral purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN11 AN — A/D Channel 11.

RB5/AN13/T1G RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN13 AN — A/D Channel 13.

T1G ST — Timer1 Gate input.

RB6/ICSPC LK RB6 TTL CM O S G eneral purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

ICSPCLK ST — Serial Programming Clock.

RB7/ICSPD AT RB7 TTL CM OS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

ICSPDAT ST TTL ICSP™ Data I/O.

RC0/T1OSO/T1CKI RC0 ST CMOS G eneral purpose I/O.

T1OSO — XTAL Timer1 oscillator output.

T1CKI ST — Timer1 clock input.

RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O.

T1OSI X TAL — Timer1 oscillator input.

CCP2 ST CMOS Capture/Compare/PWM2.

RC2/P1A/CCP1 RC2 ST CMOS G eneral purpose I/O.

P1A ST CMO S P W M output.

CCP1 — CMOS Capture/Compare/PWM1.

RC3/SCK/SCL RC3 ST CMOS General purpose I/O.

SCK ST CMOS SPI clock.

SCL ST OD I2C ™ clock.

RC4/SDI/SDA RC4 ST CMOS General purpose I/O.

SDI ST — SPI data input.

SDA ST OD I2C data input/output.

RC5/SDO RC5 ST CMOS G eneral purpose I/O.

SDO — CMOS SPI data output.

RC6/TX/CK RC6 ST CMOS G eneral purpose I/O.

TX — CMO S E USA RT asynchronous transmit.

CK ST CMO S EUSART synchronous clock.

RC7/RX/DT RC7 ST CMOS G eneral purpose I/O.

RX ST — EUSART asynchronous input.

DT ST CMOS E U SA RT synchronous data.

RD0 RD0 TTL CM O S G eneral purpose I/O.

RD1 RD1 TTL CM O S G eneral purpose I/O.

RD2 RD2 TTL CM O S G eneral purpose I/O.

RD3 RD3 TTL CM O S G eneral purpose I/O.

RD4 RD4 TTL CM O S G eneral purpose I/O.

RD5/P1B RD5 TTL CM O S G eneral purpose I/O.

P1B — CM O S P W M output.

RD6/P1C RD6 TTL CM O S G eneral purpose I/O.

P1C — CMOS P W M output.

TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMO S = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Sc hmit t Trigger input with CMOS levels

HV = High Voltage XTA L = Crystal

PIC16F882/883/884/886/887

RD7/P1D RD7 TTL CM O S G eneral purpose I/O.

P1D AN — PWM output.

RE0/AN5 RE0 TTL CMOS General purpose I/O.

AN5 AN — A/D Channel 5.

RE1/AN6 RE1 TTL CMOS General purpose I/O.

AN6 AN — A/D Channel 6.

RE2/AN7 RE2 TTL CMOS General purpose I/O.

AN7 AN — A/D Channel 7.

RE3/MCLR/VPP RE3 T TL — G eneral purpose input.

MCLR ST — Master Clear with internal pull-up.

VPP HV — P rogramming voltage.

VSS VSS Power — G round reference.

VDD VDD Power — Positive supply.

TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMO S = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Sc hmit t Trigger input with CMOS levels

HV = High Voltage XTA L = Crystal

PIC16F882/883/884/886/887

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F882/883/884/886/887 has a 13-bit program

counter cap able of addressing a 2K x 14 (0000h-07FFh)

for the PIC16F882, 4K x 14 (0000h-0FFFh) for the

PIC16F883/PIC16F884, and 8K x 14 (0000h-1FFFh) for

the PIC16F886/PIC16F887 program memory space.

Accessing a locati on above these boundaries will c ause

a wrap-around within th e first 8K x 1 4 sp ac e. The Reset

vector is at 0000h and the interrupt vector is at 0004h

(see Figures 2-2 and 2-3).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F882

FIGURE 2-2: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F883/PIC16F884

FIGURE 2-3: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F886/PIC16F887

PC<12:0>

0000h

0004h

0005h

07FFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Page 0

On-Chip

Program

Memory

PC<12:0>

0000h

0004h

0005h

07FFh

0800h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Page 0

Page 1 0FFFh

On-Chip

Program

Memory

PC<12:0>

0000h

0004h

0005h

07FFh

0800h

17FFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Page 0

Page 1

Page 2

Page 3

0FFFh

1000h

1FFFh

1800h

On-Chip

Program

Memory

PIC16F882/883/884/886/887

2.2 Dat a Memor y Organization

The data memory (see Figures 2-2 and 2-3) is

partitioned into four banks which contain the General

Purpose Registers (GPR) and the Special Function

Registers (SFR). The Special Function Registers are

located in the first 32 locations of each bank. The

General Purpose Registers, implemented as static RAM,

are located in the last 96 locations of each Bank.

Bank 2 and 1F0h-1FFh in Bank 3, point to addresses

70h-7Fh in Bank 0. The actual number of General

Purpose Resisters (GPR) implemented in each Bank

depends on the devi ce. Details are sho wn in Figures 2-5

and 2-6. All other RAM is unimplemented and returns ‘0’

when read. RP<1:0> of the STATUS register are the

bank sele ct bits:

RP1 RP0

00→Bank 0 is selected

01→Bank 1 is selected

10→Bank 2 is selected

11→Bank 3 is selected

2.2.1 GENERAL PURPOSE REGISTER

FILE

The register file is organized as 128 x 8 in the

PIC16F882, 256 x 8 in the PIC1 6F883/PIC16F884, and

368 x 8 i n th e PIC16 F886/PIC16F887. Each regist er i s

accessed, either directly or indirectly, through the File

Select Register (FSR) (see Section 2.4 “Indirect

Addressing, INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-1). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

assoc iated with th e “core” are described in this sec tion.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

PIC16F882/883/884/886/887

FIGURE 2-4: PI C16F 88 2 SPECIA L FUNCTION REGISTERS

File File File File

Address Address Address Address

Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h In direct addr. (1) 180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h WDTCON 105h SRCON 185h

PORTB 06h TRISB 86h PORTB 106h TRISB 186h

PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h

08h 88h CM2CON0 108h ANSEL 188h

PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch

PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh

TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh

TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh

T1CON 10h OSCTUNE 90h 110h 190h

TMR2 11h SSPCON2 91h 111h 191h

T2CON 12h PR2 92h 112h 192h

SSPBUF 13h SSPADD 93h 113h 193h

SSPCON 14h SSPSTAT 94h 114h 194h

CCPR1L 15h WPUB 95h 115h 195h

CCPR1H 16h IOCB 96h 116h 196h

CCP1CON 17h VRCON 97h 117h 197h

RCSTA 18h TXSTA 98h 118h 198h

TXREG 19h SPBRG 99h 119h 199h

RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah

CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh

CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch

CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh

ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General

Purpose

Registers

96 Bytes

20h General

Purpose

Registers

32 Bytes

A0h

BFh

120h 1A0h

C0h

EFh 16Fh 1EFh

accesses

70h-7Fh F0h accesses

70h-7Fh 170h accesses

70h-7Fh 1F0h

7Fh FFh 17Fh 1FFh

Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

PIC16F882/883/884/886/887

FIGURE 2-5: PI C16F 88 3/PIC16F884 SPECIAL FUNCTION REGISTERS

File File File File

Address Address Address Address

Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h WDTCON 105h SRCON 185h

PORTB 06h TRISB 86h PORTB 106h TRISB 186h

PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h

PORTD(2) 08h TRISD(2) 88h CM2CON0 108h ANSEL 188h

PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch

PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh

TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh

TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh

T1CON 10h OSCTUNE 90h 110h 190h

TMR2 11h SSPCON2 91h 111h 191h

T2CON 12h PR2 92h 112h 192h

SSPBUF 13h SSPADD 93h 113h 193h

SSPCON 14h SSPSTAT 94h 114h 194h

CCPR1L 15h WPUB 95h 115h 195h

CCPR1H 16h IOCB 96h 116h 196h

CCP1CON 17h VRCON 97h 117h 197h

RCSTA 18h TXSTA 98h 118h 198h

TXREG 19h SPBRG 99h 119h 199h

RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah

CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh

CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch

CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh

ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General

Purpose

Registers

96 Bytes

20h General

Purpose

Registers

80 Bytes

A0h General

Purpose

Registers

80 Bytes

120h 1A0h

EFh 16Fh 1EFh

accesses

70h-7Fh F0h accesses

70h-7Fh 170h accesses

70h-7Fh 1F0h

7Fh FFh 17Fh 1FFh

Bank 0Bank 1Bank 2Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: PIC16F884 only.

PIC16F882/883/884/886/887

FIGURE 2-6: PI C16F 88 6/PIC16F887 SPECIAL FUNCTION REGISTERS

File File File File

Address Address Address Address

Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h WDTCON 105h SRCON 185h

PORTB 06h TRISB 86h PORTB 106h TRISB 186h

PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h

PORTD(2) 08h TRISD(2) 88h CM2CON0 108h ANSEL 188h

PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch

PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh

TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh

TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh

T1CON 10h OSCTUNE 90h

General

Purpose

Registers

16 Bytes

110h

General

Purpose

Registers

16 Bytes

190h

TMR2 11h SSPCON2 91h 111h 191h

T2CON 12h PR2 92h 112h 192h

SSPBUF 13h SSPADD 93h 113h 193h

SSPCON 14h SSPSTAT 94h 114h 194h

CCPR1L 15h WPUB 95h 115h 195h

CCPR1H 16h IOCB 96h 116h 196h

CCP1CON 17h VRCON 97h 117h 197h

RCSTA 18h TXSTA 98h 118h 198h

TXREG 19h SPBRG 99h 119h 199h

RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah

CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh

CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch

CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh

ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General

Purpose

Registers

96 Bytes

20h

3Fh General

Purpose

Registers

80 Bytes

A0h General

Purpose

Registers

80 Bytes

120h General

Purpose

Registers

80 Bytes

1A0h

40h

6Fh EFh 16Fh 1EFh

70h accesses

70h-7Fh F0h accesses

70h-7Fh 170h accesses

70h-7Fh 1F0h

7Fh FFh 17Fh 1FFh

Bank 0Bank 1Bank 2Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: PIC16F887 only.

PIC16F882/883/884/886/887

TABLE 2-1: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Page

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 37,217

01h TM R0 Timer0 Module Register xxxx xxxx 73,217

02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 37,217

03h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 29,217

04h FSR Indirect Data Memory Address Pointer xxxx xxxx 37,217

05h PORTA(3) RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx 39,217

06h PORTB(3) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 48,217

07h PORTC(3) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 53,217

08h PORTD(3,4) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 57,217

09h PORTE(3) — — — —RE3RE2

(4) RE1(4) RE0(4) ---- xxxx 59,217

0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 37,217

0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 31,217

0Ch PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 34,217

0Dh PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF —CCP2IF0000 00-0 35,217

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 76,217

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 76,217

10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 79,217

11h TMR2 Timer2 Module Register 0000 0000 81,217

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 82,217

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 183,217

14h SSPCON(2) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 181,217

15h CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx 126,217

16h CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) xxxx xxxx 126,217

17h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 124,217

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 161,217

19h TXREG EUSART Transmit Data Register 0000 0000 153,217

1Ah RCREG EUSART Receive Data Register 0000 0000 158,217

1Bh CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) xxxx xxxx 126,217

1Ch CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) xxxx xxxx 126,218

1Dh CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 125,218

1Eh ADRESH A/D Result Register High Byte xxxx xxxx 99,218

1Fh ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 104,218

Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the

mismatch exists.

2: When SS P CON r e gis t er b it s S SP M<3 : 0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK

3: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the

data latches are either undefined (POR) or unchanged (other Resets).

4: PIC16F884/PIC16F887 only.

PIC16F882/883/884/886/887

TABLE 2-2: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Page

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 37,217

81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 30,218

82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 37,217

83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 29,217

84h FSR Indirect Data Memory Address Pointer xxxx xxxx 37,217

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 39,218

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 48,218

87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 53,218

88h TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 57,218

89h TRISE — — — — TRISE3 TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 59,218

8Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 37,217

8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 31,217

8Ch PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 32,218

8Dh PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 0000 00-0 33,218

8Eh PCON —— ULPWUE SBOREN ——PORBOR --01 --qq 36,218

8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 62,218

90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 66,218

91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 181,218

92h PR2 Time r2 Pe rio d Re gist e r 1111 1111 81,218

93h SSPADD(2) S yn c hr ono us Seri al Po rt (I2C mode) Address Register 0000 0000 189,218

93h SSPMSK(2) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 189,218

94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 189,218

95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 49,218

96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 49,218

97h VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 0000 0000 97,218

98h TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 160,218

99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 163,218

9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 163,218

9Bh PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 145,218

9Ch ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 142,218

9Dh PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 146,218

9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 99,218

9Fh ADCON1 ADFM —VCFG1VCFG0— — — — 0-00 ---- 105,218

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the

mismatch exists.

2: Accessible only when SSPCON register bits SSPM<3:0> = 1001.

3: PIC16F884/PIC16F887 only.

PIC16F882/883/884/886/887

TABLE 2-3: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

TABLE 2-4: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Page

Bank 2

100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 37,217

101h TMR0 Timer0 Module Reg is ter xxxx xxxx 73,217

102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 37,217

103h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 29,217

104h FSR Indirect Data Memory Address Pointer xxxx xxxx 37,217

105h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 225,218

106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 48,217

107h CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 88,218

108h CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 89,218

109h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL —— T1GSS C2SYNC 0000 --10 91,219

10Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 37,217

10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 31,217

10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 112,219

10Dh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 112,219

10Eh EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 112,219

10Fh EEADRH — — — EEADRH4(2) EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 112,219

Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the

mismatch exists.

2: PIC16F886/PIC16F887 only.

AddrName Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0Value on

POR, BOR Page

Bank 3

180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 37,217

181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 30,218

182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 37,217

183h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 29,217

184h FSR Indirect Data Memory Address Pointer xxxx xxxx 37,217

185h SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — FVREN 0000 00-0 93,219

186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 48,218

187h BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 162,219

188h ANSEL ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 40,219

189h ANSELH —— ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 99,219

18Ah PCLATH ——— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 37,217

18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 31,217

18Ch EECON1 EEPGD ——— WRERR WREN WR RD x--- x000 113,219

18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 111,219

Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the

mismatch exists.

2: PIC16F884/PIC16F887 only.

PIC16F882/883/884/886/887

2.2.2.1 STATUS Register

The S TATUS registe r, shown in R e gis ter 2-1, co nt a ins :

• the arithmetic s tatus of the ALU

• the Reset status

• the bank select bits for data memory (GPR and

SFR)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For exam ple, CLRF STATUS, will clear the uppe r three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not affect-

ing any Status b it s , s ee Se ction 15.0 “Instruction Set

Summary”

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDC

(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: Register Bank Select bi t (use d for indirect addressing)

1 = Bank 2, 3 (100h-1FFh)

0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h-7Fh)

01 = Bank 1 (80h-FFh)

10 = Bank 2 (100h-17Fh)

11 = Bank 3 (180h-1FFh)

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rot ate (RRF, RLF) instructi ons, this b it is loa ded with ei ther the hi gh-order or low-orde r

bit of the source register.

PIC16F882/883/884/886/887

2.2.2.2 OPTION Register

The OPTION register, shown in Register 2-2, is a

readable and writable register, which contains various

control bits to configure:

• Timer0/WDT prescaler

• Extern al IN T inter rupt

•Timer0

• Weak pu ll-ups on P ORTB

Note: To achieve a 1:1 prescaler assignment fo r

T imer0, assign the prescaler to the WDT by

setting PSA bit of the OPTION register to

‘1’. See Section 6.3 “Timer1 Prescaler”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

bit 5 T0CS: Timer0 Clock Sou rce Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clo ck (FOSC/4)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assig nment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value Timer0 Rate WDT Rate

PIC16F882/883/884/886/887

2.2.2.3 INTCON Register

The INTCON register, shown in Register 2-3, is a

readable and writable register , which contains the various

enable and fl ag bits f or TMR 0 re gi ster ov er fl ow, PORTB

change and external INT pin interrupts.

Note: Interru pt flag bi ts are s et when an interrupt

conditi on occ urs, regar dless o f the s tate of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE(1) T0IF(2) INTF RBIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: Timer0 Ov erfl ow Interru pt E nab le bit

1 = Enables the Timer0 interrupt

0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt

0 = Disables the INT external interrupt

bit 3 RBIE: PORTB Change Interrupt Enable bit(1)

1 = Enables the PORTB change interrupt

0 = Disables the PORTB change interrupt

bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)

1 = TM R0 register has overflowed (must be cleare d in so ftwa re)

0 = TM R0 register did no t overfl ow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred (must be cleared in software)

0 = The INT external interrupt did not occur

bit 0 RBIF: PORTB Change Interrupt Flag bit

1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in

software)

0 = None of the PORTB general purpose I/O pins have changed state

Note 1: IOCB register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

PIC16F882/883/884/886/887

2.2.2.4 PIE 1 Regi st er

The PIE1 regis te r con t ai ns th e in terrupt enable bi t s, a s

shown in Register 2-4.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt

0 = Disables the ADC interrupt

bit 5 RCIE: EUSART Receive Interrupt Enable bit

1 = Enables the EUSART receive interrupt

0 = Disables the EUSART receive interrupt

bit 4 TXIE: EUSART Transmit Interrupt Enable bit

1 = Enables the EUSART transmit interrupt

0 = Disables the EUSART transmit interrupt

bit 3 SSPIE: Master Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt

0 = Disables the MSSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt

0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt

0 = Disables the Timer1 overflow interrupt

PIC16F882/883/884/886/887

2.2.2.5 PI E2 Regi st er

The PIE2 regis te r con t ai ns th e in terrupt enable bi t s, a s

shown in Register 2-5.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables oscillator fail interrupt

0 = Disables oscillator fail interrupt

bit 6 C2IE: Comparator C2 Interrupt Enable bit

1 = Enables Comparator C2 interrupt

0 = Disables Comparator C2 interrupt

bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables Comparator C1 interrupt

0 = Disables Comparator C1 interrupt

bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit

1 = Enables EEPROM write operation interrupt

0 = Disables EEPROM write operation interrupt

bit 3 BCLIE: Bus Collision Interrupt Enable bit

1 = Enables Bus Collision interrupt

0 = Disable s Bus Collision interru pt

bit 2 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable bit

1 = Enables Ultra Low-Power Wake-up interrupt

0 = Disables Ultra Low-Power Wake-up interrupt

bit 1 Unimplemented: Read as ‘0’

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables CC P2 inte rrup t

0 = Disables CCP2 interrupt

PIC16F882/883/884/886/887

2.2.2.6 PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-6.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the

appropriate int errupt fla g bits are clear prior

to enabling an interrupt.

U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

—ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = A/D conversion comp lete (must be cleared in software)

0 = A/D conversion has not completed or has not been started

bit 5 RCIF: EUSART Receive Interrupt Flag bit

1 = The EUSART receive buffer is full (cleared by reading RCREG)

0 = The EUSART receive buffer is not full

bit 4 TXIF: EUSART Transmit Interrupt Flag bit

1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)

0 = The EUSART transmit buffer is full

bit 3 SSPIF: Master Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = The MSSP interrupt condition has occurred, and must be cleared in software before returning from the

Interrupt Service Routine. The conditions that will set this bit are:

SPI A transmission/reception has taken place

I2 C Slave/Master

A transmission/reception has taken place

I2 C Master

The initiated St art condition was completed by the MSSP module

The initiated Stop condition was completed by the MSSP module

The initiated restart condition was completed by the MSSP module

The initiated Acknowledge condition was completed by the MSSP module

A Start condition occurred while the MSSP module was idle (Multi-master system)

A Stop condition occurred while the MSSP module was idle (Multi-master system)

0 = No MSSP interrupt condition has occurred

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurr ed

PWM mode:

Unused in this mode

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = A Timer2 to PR2 match occurred (mus t be cleared in software)

0 = No Timer2 to PR2 match occur red

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = The TMR1 register overflowed (must be cleared in software)

0 = The TMR1 register did not overflow

PIC16F882/883/884/886/887

2.2.2.7 PIR2 Register

The PIR2 register contains the interrupt flag bits, as

shown in Register 2-7.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bit s are clear prior

to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0 = System clock operating

bit 6 C2IF: Comparator C2 Interrupt Flag bit

1 = Comparator output (C2OUT bit) has changed (must be cleared in software)

0 = Comparator output (C2OUT bit) has not changed

bit 5 C1IF: Comparator C1 Interrupt Flag bit

1 = Comparator output (C1OUT bit) has changed (must be cleared in software)

0 = Comparator output (C1OUT bit) has not changed

bit 4 EEIF: EE Write Operation Interrupt Flag bit

1 = Write operation completed (must be cleared in software)

0 = Write operation has not completed or has not started

bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred in the MSSP when configured for I2C Ma ster mode

0 = No bus collision has occurred

bit 2 ULPWUIF: Ultra Low-Po wer Wake -up Inte rrupt Flag bit

1 = Wake-up condition has occurred (must be cleared in software)

0 = No Wake-up condition has o ccurred

bit 1 Unimplemented: Read as ‘0’

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (m ust be cleared in software )

0 = No TM R1 regist er capture occu rred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode

PIC16F882/883/884/886/887

2.2.2.8 PCON Regi st er

The Power Control (PCON) register (see Register 2-8)

cont ains flag bits to differentiat e betwe en a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON register also controls the Ultra Low-Power

Wake-up and software enable of the BOR.

U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x

—— ULPWUE SBOREN(1) ——PORBOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit

1 = Ultra Low-Power Wake-up enabled

0 = Ultra Low-Power Wake-up disabled

bit 4 SBOREN: Software BOR Enable bit(1)

1 = BOR enabled

0 = BOR disabled

bit 3-2 Unimplemented: Read as ‘0’

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: BOREN<1:0> = 01 in the Configuration Word Register 1 for this bit to control the BOR.

PIC16F882/883/884/886/887

2.3 PCL and PCLATH

The Program Counte r (PC) is 13 bit s wide. The lo w byte

comes from the PCL register, which is a readable and

writable register . The high byte (PC<12:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 2-7 shows the two

situ at i o ns fo r t he l o ad i n g of t h e PC . T he u p per e x am pl e

in Figure 2-7 shows how the PC is loaded on a write to

PCL (PCLATH<4:0> → PCH). The lower example in

Figure 2-7 show s how the PC is loaded during a CALL or

GOTO instructi on (PC L ATH<4:3> → PCH).

FIGURE 2-7: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

content s of th e PCLATH register. Th is allo ws the enti re

contents of the program counter to be changed by

writing the desire d upper 5 bit s to the PCLATH register.

When th e lower 8 bits are w ritten to the PCL register, all

13 bit s of the program cou nter will chang e to the values

contained in the PCLATH register and those being

written to the PCL register.

A comput ed GOTO is acc om pli sh ed by adding a n offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions or if the lower 8 bits of the memory

address rolls over from 0xFF to 0x00 in the middle of

the table, then PCLATH must be incremented for each

address rollover that occurs between the table

beginning and the target location within the table.

For more information refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

2.3.2 STACK

The PIC16F882/883/884/886/887 devices have an

8-level x 13-bit wide hardware stack (see Figures 2-2

and 2-3). The stack s pace is not part of eit her program

or data space and the Stack Pointer is not readable or

writable. The PC is PUSHed onto the stack when a

CALL instruction is executed or an interrupt causes a

branch. The stack i s POPed i n the e vent o f a RETURN,

RETLW or a RETFIE inst ructio n executi on. PC LATH is

not affected by a PUSH or POP operation.

The st ack operates as a circular buf fer . This means that

af ter the st ack ha s be en PUSHed ei ght time s, th e nin th

push ove rwr ites the va lu e that was s tored fro m the firs t

push. The tenth pus h ov erw ri tes the second pus h (an d

so on).

2.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is no t a physica l register . Addr essing

the INDF register will caus e indirect addressing.

Indirect addressing is possible by using the INDF

accesses data pointed to by the File Select Register

(FSR) . Reading INDF itself in directly w ill produc e 00h.

Writing to the INDF register indirectly results in a no

operation (although Status bits may be affected). An

eff ectiv e 9-bi t address is obta ined by concat enatin g the

8-bit FSR and the IRP bit of the STATUS register, as

shown in Figure 2-8.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESS ING

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE<10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interr upt add res s.

MOVLW 0x20 ;initialize pointer

MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer

BTFSS FSR,4 ;all done?

GOTO NEXT ;no clear next

CONTINUE ;yes continue

PIC16F882/883/884/886/887

FIGURE 2-8: DIRECT/INDIRECT ADDRE SSING PIC16F882/883/884/886/887

Note: Fo r mem ory map deta il, see Fi gures 2-2 and 2- 3.

Data

Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1 RP0 6 0

From Opcode IRP File Select Register

Bank Select Location Select

00 01 10 11 180h

1FFh

00h

7Fh

Bank 0 Ban k 1 Bank 2 Bank 3

PIC16F882/883/884/886/887

3.0 I/O PORTS

There are as many as thirty-five general purpose I/O

pins available. Depending on which peripherals are

enabled , some or all of the pins may not be a vailable as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

3.1 PORTA and the TRISA Registers

PORTA is a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 3-2). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a T RISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). Example 3-1 shows how to

initialize PORTA.

Reading the PORTA register (Register 3-1) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch.

The TRISA register (Register 3-2) controls the PORTA

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISA register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

EXAMPLE 3-1: INITIALI ZING PORTA

Note: The ANSEL register must be initialized to

configure an analog channel as a digital

input. Pi ns configu red as analo g inputs will

read ‘0’.

BANKSEL PORTA ;

CLRF PORTA ;Init PORTA

BANKSEL ANSEL ;

CLRF ANSEL ;digital I/O

BANKSEL TRISA ;

MOVLW 0Ch ;Set RA<3:2> as inputs

MOVWF TRISA ;and set RA<5:4,1:0>

;as outputs

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RA<7:0>: PORTA I/O Pin bit

1 = Port pin is > VIH

0 = Port pin is < VIL

R/W-1(1) R/W-1(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

Note 1: TRISA<7:6> always reads ‘1’ in XT, HS and LP Oscillator modes.

PIC16F882/883/884/886/887

3.2 Additional Pin Functions

RA0 also has an Ultra Low-Power W ake-up option. The

next three sections descr ibe thes e functio ns.

3.2.1 ANSEL REGISTER

The ANSEL reg ister (Regist er 3-3 ) is us ed to conf igu re

the Input mode of an I/O pin to analog. Setting the

appropriate ANSEL bit high will cause all digital reads

on the pin to be read as ‘0’ and allow analog functions

on the pin to operate correctly.

The st ate of the ANSEL bit s has no af fect on digit al out-

put functi ons. A pin with TRIS clea r and ANSEL set will

still operate as a digital output, but the Input mode will

be analog. This can cause unexpected behavior when

executing read-modify-write instructions on the

affec ted port.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANS<7:0>: Analog Select bits

Analog select between analog or digital function on pins AN<7:0>, respectively.

1 = Analog input. Pin is assigned as analog input(1).

0 = Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and

interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow

external control of the voltage on the pin.

2: Not implemented on PIC16F883/886.

PIC16F882/883/884/886/887

3.2.2 ULTRA LOW-POWER WAKE-UP

The Ultra Low-Power Wake-up (ULPWU) on RA0 allows

a slow falling voltage to generate an interrupt-on-change

on RA0 without exces s current c onsum ption. The m ode

is selected by setting the ULPWUE bit of the PCON

used to discharge a cap ac itor on RA0.

Follow these steps to use this feature:

a) Charge the capacitor on RA0 by configuring the

RA0 pin to output (= 1).

b) Configure RA0 as an input.

c) Set the ULPWUIE bit of the PIE2 register to

enable inte rrupt.

d) Set the ULPWUE bit of the PCON register to

begin the capacitor discharge.

e) Execute a SLEEP instruction.

When the v olt ag e on RA0 dro p s below VIL, an interrupt

will be generated which will cause the device to

wake-u p and exec ute the next instru ction . If the GIE b it

of the INTCON register is set, the device will then call

the interrupt vector (0004h).

This feature provides a low-power technique for

periodically waking up the device from Sleep. The

time-out is dependent on the discharge time of the RC

circuit on RA0. See Example 3-2 for initializing the

Ultra Low-Power Wake-up module.

A series resistor between RA0 and the external

capacitor provides overcurrent protection for the

RA0/AN0/ULPWU/C12IN0- pin and can allow for

software calibration of the time-out (see Figure 3-1). A

timer can be used to measure the charge time and

discharge time of the capacitor. The charge time can

then be ad jus t ed to pro vi de th e de si red i nterrupt delay.

This technique will compensate for the affects of

temperature, voltage and component accuracy. The

Ultra Low-Power Wake-up peripheral can also be

configured as a simple Programmable Low Voltage

Detect or temperature sensor.

EXAMPLE 3-2: ULTRA LOW-POWER

WAKE-UP INITIALIZATION

Note: For more information, refer to AN879,

“Using the Microchip Ultra Low-Power

Wake-up Module” Application Note

(DS00879).

BANKSEL PORTA ;

BSF PORTA,0 ;Set RA0 data latch

BANKSEL ANSEL ;

BCF ANSEL,0 ;RA0 to digital I/O

BANKSEL TRISA ;

BCF TRISA,0 ;Output high to

CALL CapDelay ;charge capacitor

BANKSEL PIR2 ;

BCF PIR2,ULPWUIF ;Clear flag

BANKSEL PCON

BSF PCON,ULPWUE ;Enable ULP Wake-up

BSF TRISA,0 ;RA0 to input

BSF PIE2, ULPWUIE ;Enable interrupt

MOVLW B’11000000’ ;Enable peripheral

MOVWF INTCON ;interrupt

SLEEP ;Wait for IOC

NOP ;

PIC16F882/883/884/886/887

3.2.3 PIN DESCRIPTIONS AND

DIAGRAMS

Each PORT A pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the comparator or the A/D Converter (ADC),

refer to the appropriate section in this dat a shee t.

3.2.3.1 RA0/AN0/ULPWU/C12IN0-

Figure 3-1 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• an analog input for the ADC

• a negative analog input to Comparator C1 or C2

• an analog input for the Ultra Low-Power Wake-up

FIGURE 3-1: BLOCK DIAGRAM OF RA0

I/O Pin

VDD

VSS

To Comparator

Analog(1)

Input Mode

IULP

Data Bus

PORTA

TRISA

PORTA

Note 1: ANSEL determines Analog Input mode.

TRG

ULPWUE

To A/D Converter

VSS

PIC16F882/883/884/886/887

3.2.3.2 RA1/AN1/C12IN1-

Figure 3-2 shows the diagram for this pin. This pin is

configurable to function as one of the fol lowing:

• a general purpose I/O

• an analog input for the ADC

• a negative analog input to Comparator C1 or C2

FIGURE 3-2: BLOCK DIAGRAM OF RA1

3.2.3.3 RA2/AN2/VREF-/CVREF/C2IN+

Figure 3-3 shows the diagram for this pin. This pin is

confi gu rab le to func ti on a s one o f t he following :

• a genera l purpo se I/O

• an analog input for the ADC

• a negative voltage reference input for the ADC

and CVREF

• a comparator voltage reference output

• a positive analog input to Comparator C2

FIGURE 3-3: BLOCK DIAGRAM OF RA2

I/O Pin

VDD

VSS

Analog(1)

Input Mode

Data Bus

PORTA

TRISA

To A/D Converter

Note 1: ANSEL determines Analog Input mode.

To Comparator

I/O Pin

VDD

VSS

Analog(1)

Input Mode

Data Bus

PORTA

TRISA

To Comparator (V REF-)

Note 1: ANSEL determines Analog Input mode.

To Comparator (positive input)

CVREF

VROE

To A/D Converter (VREF-)

To A/D Converter (analog channel)

PIC16F882/883/884/886/887

3.2.3.4 RA3/AN3/VREF+/C1IN+

Figure 3-4 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose input

• an analog input for the ADC

• a pos itive vo ltage reference i nput for the ADC and

CVREF

• a positive analog input to Comparator C1

FIGURE 3-4: BLOCK DIAGRAM OF RA3

3.2.3.5 RA4/T0CKI/C1OUT

Figure 3-5 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• a clock input for Timer0

• a di gital output from Comparator C1

FIGURE 3-5: BLOCK DIAGRAM OF RA4

I/O Pin

VDD

VSS

Analog(1)

Input Mode

Data Bus

PORTA

TRISA

Note 1: ANSEL determines Analog Input mode.

To Comparator (VREF+)

To Comparator (positive input)

To A/D Converter (VREF+)

To A/D Converter (analog channel)

I/O Pin

VDD

VSS

Data Bus

PORTA

TRISA

C1OUT

Enable

To Timer0

PIC16F882/883/884/886/887

3.2.3.6 RA5/AN4/SS/C2OUT

Figure 3-6 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a slave select input

• a digital output from Comparator C2

FIGURE 3-6: BLOCK DIAGRAM OF RA5

3.2.3.7 RA6/OSC2/CLKOUT

Figure 3-7 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• a crystal/reso na tor con nec tio n

• a clock output

FIGURE 3-7: BLOCK DIAGRAM OF RA6

I/O Pin

VDD

VSS

Analog(1)

Input Mode

Data Bus

PORTA

TRISA

C2OUT

Enable

To SS Input

To A/D Converter

Note 1: ANSEL determines Analog Input mode.

I/O Pin

VDD

VSS

Data Bus

PORTA

TRISA

FOSC/4

OSC2

CLKOUT

Enable

INTOSCIO/

EXTRCIO/EC(1)

CLKOUT

Enable

Note 1: With I/O option.

Circuit

Oscillator

PIC16F882/883/884/886/887

3.2.3.8 RA7/OSC1/CLKIN

Figure 3-8 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• a crystal/resonator connection

• a clock input

FIGURE 3-8: BLOCK DIAGRAM OF RA7

TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

I/O Pin

VDD

VSS

Data Bus

PORTA

TRISA

INTOSC

Mode

OSC1

CLKIN

Circuit

Oscillator

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all ot her

Resets

ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000

ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000

CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000

CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL —— T1GSS C2SYNC 0000 --10 0000 --10

PCON —— ULPWUE SBOREN ——PORBOR --01 --qq --0u --uu

OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

PIC16F882/883/884/886/887

3.3 PORTB and TRISB Registers

PORTB is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISB

(Register 3-6). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., put the

corresponding output driver in a High-Imped ance mode).

Clea ring a TRI SB bi t (= 0) will make the corresponding

PORTB pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 3-3 shows how to ini tialize POR TB.

Reading the PORTB register (Register 3-5) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, th is value is modifi ed and the n written

to the PORT dat a lat ch.

The TRISB register (Register 3-6) controls the PORTB

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISB register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’. Example 3-3 shows how to initiali ze PORTB.

EXAMPLE 3-3: INITIALIZING PORTB

3.4 Additional PORTB Pin Functions

PORT B pins RB<7 :0> on the dev ice family device hav e

an interrupt-on-change option and a weak pull-up

option. The following three sections describe these

PORTB pin functions.

Every PORTB pin on this device family has an

interrupt-on-change option and a weak pull-up option.

3.4.1 ANSELH REGISTER

The ANSELH register (Register 3-4) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELH bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELH bits has no affect on digital

output functions. A pin with TRIS clear and ANSELH

set will still operate as a digital output, but the Input

mode will be analog. This can cause unexpected

behavior when executing read-modify-write

inst ruct ion s on the af f ected port.

3.4.2 WEAK PULL-UPS

Each of the PORTB pi ns has an ind ividually co nfigurable

internal weak pull-up. Control bit s WPUB<7:0> enable or

disable each pull-up (see Register 3-7). Each weak

pull-up is automatically turned off when the port pin is

configured as an output. All pull-ups are disabled on a

Power-on Reset by the RBPU bit of the OPTION register .

3.4.3 INTERRUPT-ON-CHANGE

All of the PORTB pins are individually configurable as an

interrupt-on-change pin. Control bits IOCB<7:0> enable

or disable the interrupt function for each pin. Refer to

disabled on a Power-on Reset.

For enabled interrupt-on-change pins, the present value

is compared with the old va lue l atch ed on the last rea d

of PORTB to determine which bits have changed or

mismatched the old value. The ‘mismatch’ outputs of

the last read are OR’d together to set the PORTB

Change Interrupt flag bit (RBIF) in the INTCON register .

This interrupt can wake the device from Sleep. The user,

in the Interrupt Service Routine, clears the inte rrupt by:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear the flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading or writing PORTB will end the mismatch

condition and allow flag bit RBIF to be cleared. The latch

holding the last read value is not affected by a MCLR nor

Brown-out Reset. After these Resets, the RBIF flag will

continue to be set if a mismatch is present.

Note: The ANSELH register must be initialized

to config ure an analog c hannel as a dig ital

input. Pi ns configured as analog inputs w ill

read ‘0’.

BANKSEL PORTB ;

CLRF PORTB ;Init PORTB

BANKSEL TRISB ;

MOVLW B‘11110000’;Set RB<7:4> as inputs

;and RB<3:0> as outputs

MOVWF TRISB ;

Note: If a change on the I/O pin should occur when

the read operation is being executed (start of

the Q2 cycle), then the RBIF interrupt flag

may not get set. Fur thermore, since a read

or write on a port affects all bits of that port ,

care must be taken when using multiple pins

in Interrupt-on-Change mode. Changes on

one pin may not be seen while servicing

changes on another pin.

PIC16F882/883/884/886/887

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

—— ANS13 ANS12 ANS11 ANS10 ANS9 ANS8

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 ANS<13:8>: Analog Select bits

Analog select between analog or digital function on pins AN<13:8>, respectively.

1 = Analog input. Pin is assigned as analog input(1).

0 = Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and

interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow

external control of the voltage on the pin.

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RB<7:0>: PORTB I/O Pin bit

1 = Port pin is > VIH

0 = Port pin is < VIL

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit

1 = PORTB pin configured as an input (tri-stated)

0 = PORTB pin configured as an output

PIC16F882/883/884/886/887

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 WPUB<7:0>: Weak Pull-up Register bit

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bit

1 = Interrupt-on-change enabled

0 = Interrupt-on-change disabled

PIC16F882/883/884/886/887

3.4.4 PIN DESCRIPTIONS AND

DIAGRAMS

Each PORTB pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the SSP, I2C or interrupts, refer to the appropriate

section in this data sheet.

3.4.4.1 RB0/AN12/INT

Figure 3-9 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• an external edge triggered interrupt

3.4.4.2 RB1/AN10/P1C(1)/C12IN3-

Figure 3-9 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a PWM output(1)

• an analog input to Comparator C1 or C2

3.4.4.3 RB2/AN8/P1B(1)

Figure 3-9 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a PWM output(1)

3.4.4.4 RB3/AN9/PGM/C12IN2-

Figure 3-9 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• Low-voltage In-Circuit Serial Programming enable

• an analog input to Comparator C1 or C2

FIGURE 3-9: BLOCK DIAGRAM OF

RB<3:0>

Note 1: P1C is available on PIC16F882/883/886

only.

Note 1: P1B is available on PIC16F882/883/886

only.

I/O Pin

VDD

VSS

VDD

Weak

Analog(1)

Input Mode

Data Bus

WPUB

PORTB

TRISB

To A/D Converter

RB0/INT

Analog(1)

Input Mode

RBPU

Note 1: ANSELH determines Analog Input mode.

RB3/PGM

To Comparator (RB1, RB3)

RD PORTB

PORTB

IOCB

Interrupt-on-

Change

CCP1OUT Enable

CCP1OUT

PIC16F882/883/884/886/887

3.4.4.5 RB4/AN11/P1D(1)

Figure 3-10 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a PWM output(1)

3.4.4.6 RB5/AN13/T1G

Figure 3-10 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a Timer1 gate input

3.4.4.7 RB6/ICSPCLK

Figure 3-10 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• In-Circuit Serial Programming clock

3.4.4.8 RB7/ICSPDAT

Figure 3-10 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• In-Circ uit Ser ial Program ming data

FIGURE 3-10: BLOCK DIAGRAM OF RB<7:4>

Note 1: P1D is available on PIC16F882/883/886

only.

I/O Pin

VDD

VSS

VDD

Weak

Data Bus

WPUB

RD PORTB

PORTB

TRISB

IOCB

Interrupt-on-

Analog(1) Input Mode

RBPU

Change

Available on PIC16F882/PIC16F883/PIC16F886 only.

Note 1: ANSELH determines Analog Input mode.

2: Applies to RB<7:6> pins only).

3: Applies to RB5 pin only.

To A/D Converter

CCP1OUT Enable

CCP1OUT 0

Analog(1)

Input Mode

To Timer1 T1G(3)

ICSP™(2)

To ICSPCLK (RB6) and ICSPDAT (RB7)

PIC16F882/883/884/886/887

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

ANSELH —— ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 --11 1111

CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL ——T1GSSC2SYNC 0000 --10 0000 --10

IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by PORTB.

PIC16F882/883/884/886/887

3.5 PORTC and TRISC Registers

PORTC is a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISC

(Register 3-10). Setting a TRISC bit (= 1) will make the

corresponding PORTC pin an input (i.e., put the

corr esponding o utput dr iver in a Hi gh-Impeda nce mode).

Clearing a TRISC bit (= 0) will make the corresponding

PORTC pi n an outp ut ( i.e. , enab le th e out put dri ver and

put th e co nte nts of t he ou tp ut l atc h on t h e se le cted pi n) .

Example 3-4 show s h ow t o ini ti al iz e PORTC.

Reading the PORTC register (Register 3-9) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pin s are read, thi s value is modi fied and the n written

to the PORT data latch.

The TRISC register (Register 3-10 ) contr ols the PORTC

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISC register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

EXAMPLE 3-4: INITIALIZI NG PORTC

BANKSEL PORTC ;

CLRF PORTC ;Init PORTC

BANKSEL TRISC ;

MOVLW B‘00001100’ ;Set RC<3:2> as inputs

MOVWF TRISC ;and set RC<7:4,1:0>

;as outputs

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bit

1 = Port pin is > VIH

0 = Port pin is < VIL

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1(1) R/W-1(1)

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISC<7:0>: PORTC Tri-State Control bit

1 = PORTC pin configured as an input (tri-stated)

0 = PORTC pin configured as an output

Note 1: TRISC<1:0> always reads ‘1’ in LP Oscillator mode.

PIC16F882/883/884/886/887

3.5.1 RC0/T1OSO/T1CKI

Figure 3-11 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• a Ti mer1 oscillator output

• a Timer1 clock input

FIGURE 3-11: BLOCK DIAGRAM OF RC0

3.5.2 RC1/T1OSI/CCP2

Figure 3-12 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• a Ti mer1 oscillator input

• a Capture input and Compare/PWM output for

Comparator C2

FIGURE 3-12: BLOCK DIAGRAM OF RC1

3.5.3 RC2/P1A/CCP1

Figure 3-13 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• a PWM output

• a Capture input and Compare output for

Compar ator C1

FIGURE 3-13: BLOCK DIAGRAM OF RC2

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

To Timer1 clock input

T1OSCEN Circuit

Timer1 Oscillator

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

To CCP2

CCP2

CCP2CON

T1OSCEN

T1OSCEN Circuit

Timer1 Oscillator

T1OSI

VDD

VSS

Data bus

PORTC

TRISC

To Enhance d CCP1

PORTC

CCP1/P1A

CCP1CON

0I/O Pin

PIC16F882/883/884/886/887

3.5.4 RC3/SCK/SCL

Figure 3-14 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• a SPI clock

•an I

2C™ clock

FIGURE 3-14: BLOCK DIAGRAM OF RC3

3.5.5 RC4/SDI/SDA

Figure 3-15 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• a SPI data I/O

•an I

2C data I/O

FIGURE 3-15: BLOCK DIAGRAM OF RC4

3.5.6 RC5/SDO

Figure 3-16 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• a serial data output

FIGURE 3-16: BLOCK DIAGRAM OF RC5

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

To SSPSR

SSPEN

SCK

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

To SSPSR

SSPEN

SDI/SDA

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

Port/SDO

SDO

Select

PIC16F882/883/884/886/887

3.5.7 RC6/TX/CK

Figure 3-17 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an asynchronous serial output

• a synchronous clock I/O

FIGURE 3-17: BLOCK DIAGRAM OF RC6

3.5.8 RC7/RX/DT

Figure 3-18 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• an asynchronous serial input

• a sync hron ou s seri al data I/O

FIGURE 3-18: BLOCK DIAGRAM OF RC7

TABLE 3-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

SPEN

TXEN

SYNC

EUSART

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

SPEN

SYNC

EUSART

EUSART RX/DT

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Va lue on

all other

Resets

CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

PIC16F882/883/884/886/887

3.6 PORTD and TRISD Registers

PORTD(1) is a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISD

(Register 3-12). Setting a TRISD bit (= 1) will make the

corresponding PORTD pin an input (i.e., put the

corr esponding o utput dr iver in a Hi gh-Impeda nce mode).

Clearing a TRISD bit (= 0) will make the corresponding

PORTD pi n an outp ut ( i.e. , enab le th e out put dri ver and

put th e co nte nts of t he ou tp ut l atc h on t h e se le cted pi n) .

Example 3-5 shows how to initialize PORTD.

Reading the PORTD register (Register 3-11) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pin s are read, thi s value is modi fied and the n written

to the PORT data latch.

The TRISD register (Register 3-12 ) contr ols the PORTD

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISD register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

EXAMPLE 3-5: INITIALIZI NG PORTD

Note 1: PORTD is available on PIC16F884/887

only.

BANKSEL PORTD ;

CLRF PORTD ;Init PORTD

BANKSEL TRISD ;

MOVLW B‘00001100’ ;Set RD<3:2> as inputs

MOVWF TRISD ;and set RD<7:4,1:0>

;as outputs

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bit

1 = Port pin is > VIH

0 = Port pin is < VIL

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISD<7:0>: PORTD Tri-State Control bit

1 = PORTD pin configured as an input (tri-stated)

0 = PORTD pin configured as an output

PIC16F882/883/884/886/887

3.6.1 RD<4:0>

Figure 3-19 shows the diagram for these pins. These

pins are configured to function as general purpose

I/O’s.

FIGURE 3-19: BLOCK DIAGRAM OF

RD<4:0>

3.6.2 RD5/P1B(1)

Figure 3-20 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• a PWM output

3.6.3 RD6/P1C(1)

Figure 3-20 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• a PWM output

3.6.4 RD7/P1D(1)

Figure 3-20 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• a PWM output

FIGURE 3-20: BLOCK DIAGRAM OF

RD<7:5>

TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Note: RD<4:0> is available on PIC16F884/887

only.

Note 1: RD5/P1B is available on PIC16F884/887

only. See RB2/AN8/P1B for this f unc tio n

on PIC16F882/883/886.

VDD

VSS

Data Bus

PORTD

TRISD

PORTD

I/O Pin

Note 1: RD6/P1C is available on PIC16F884/887

only. See RB1/AN10/P1C/C12IN3- for

this functi on on PIC16F 882 /883/886.

Note 1: RD7/P1D is available on PIC16F884/887

only. See RB4/AN11/P1D for this functio n

on PIC16F882/883/886.

VDD

VSS

Data Bus

PORTD

TRISD

PORTD

CCP1

PSTRCON

0I/O Pin

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Va lue on

all other

Resets

PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu

PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001

TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.

PIC16F882/883/884/886/887

3.7 PORTE and TRISE Registers

PORTE(1) is a 4-bit wide, bidirectional port. The

corres pond ing d ata direc tion regis ter is TRISE. Se tting a

TRISE bit (= 1) will make the corresponding PORTE pin

an input (i.e., put the corresponding output driver in a

High-Impedance mode). Clearing a TRISE bit (= 0) will

make the corresponding PORTE pin an output (i.e.,

enable the output driver and put the contents of the

output latch on th e s el ected pin). The exception is RE3,

which is input only and its TRIS bit will always read as

‘1’. Example 3-6 show s how to initia lize PORT E.

Readi ng t he PO R T E register (Reg is ter 3-13) reads th e

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch. RE3 reads ‘0’ when

MCLRE = 1.

The TR IS E r e gist er (R eg ist er 3-1 4 ) c ontr o ls t he P ORTE

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISE register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

EXAMPLE 3-6: INITIALIZI NG PORTE

Note 1: RE<2:0> pins are available on

PIC16F884/887 only.

Note: The ANSEL register must be initialized to

configure an analog channel as a digital

input. Pi ns configu red as analo g inputs will

read ‘0’.

BANKSEL PORTE ;

CLRF PORTE ;Init PORTE

BANKSEL ANSEL ;

CLRF ANSEL ;digital I/O

BCF STATUS,RP1 ;Bank 1

BANKSEL TRISE ;

MOVLW B‘00001100’ ;Set RE<3:2> as inputs

MOVWF TRISE ;and set RE<1:0>

;as outputs

U-0 U-0 U-0 U-0 R-x R/W-x R/W-x R/W-x

— — — — RE3 RE2 RE1 RE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 RD<3:0>: PORTE General Purpose I/O Pin bit

1 = Port pin is > VIH

0 = Port pin is < VIL

U-0 U-0 U-0 U-0 R-1(1) R/W-1 R/W-1 R/W-1

— — — — TRISE3 TRISE2 TRISE1 TRISE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 TRISE<3:0>: PORTE Tri-State Control bit

1 = PORTE pin configured as an input (tri-stated)

0 = PORTE pin configured as an output

Note 1: TRISE<3> always reads ‘1’.

PIC16F882/883/884/886/887

3.7.1 RE0/AN5(1)

This pin is configurable to function as one of the

following:

• a general purpose I/O

• an analog input for the ADC

3.7.2 RE1/AN6(1)

This pin is configurable to function as one of the

following:

• a general purpose I/O

• an analog input for the ADC

3.7.3 RE2/AN7(1)

This pin is configurable to function as one of the

following:

• a general purpose I/O

• an analog input for the ADC

FIGURE 3-21: BLOCK DIAGRAM OF

RE<2:0>

3.7.4 RE3/MCLR/VPP

Figure 3-22 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se inp ut

• as Master Clear Reset with weak pull-up

FIGURE 3-22: BLOCK DIAGRAM OF RE3

TABLE 3-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Note 1: RE0/AN5 is available on PIC16F884/887

only.

Note 1: RE1/AN6 is available on PIC16F884/887

only.

Note 1: RE2/AN7 is available on PIC16F884/887

only.

I/O Pin

VDD

VSS

Analog(1)

Input Mode

Data Bus

PORTE

TRISE

To A/D Converter

Note 1: ANSEL determines Analog Input mode.

Input

VSS

Data Bus

PORTE

Reset MCLRE

TRISE VSS

MCLRE

VDD

Weak

MCLRE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Value on

all other Resets

ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

PORTE ———— RE3 RE2 RE1 RE0 ---- xxxx ---- uuuu

TRISE ———— TRISE3 TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE

PIC16F882/883/884/886/887

4.0 OSCILLAT OR M ODULE (WITH

FAIL-SAFE CLOCK MONITOR)

4.1 Overview

The oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applicati ons while maximizing perfor-

mance and minimizing power consumption. Figure 4-1

illustrates a block diagram of the oscillator module.

Clock sources can be configured from external

oscilla tors, quartz crystal resonators , ceramic resonators

and Resistor-Capacitor (RC) circuits. In addition, the

system clock source can be configured from one of two

internal oscillators, with a choice of speeds selectable via

softw are . Add itio nal clo ck feat ures inc lud e:

• Selectable system clock source between external

or internal via so ftwa re.

• Two-Speed Start-up mode, w hich min im iz es

latency between external oscillator start-up and

code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch

automatically to the internal oscillator.

The osc illat or mod ule c an be config ured i n one of eig ht

clock modes.

1. EC – External clock with I/O on OSC2/CLK OUT.

2. LP – 32 kHz Low-Power Crystal mode.

3. XT – Medium Gain Crystal or Ceramic Resonator

Oscillator mode.

4. HS – High Gain Crystal or Ceramic Resonator

mode.

5. RC – External Resistor-Capacitor (RC) with

FOSC/4 output on OSC2/CLKOUT.

6. RCIO – Exte rnal R es ist or-Capacito r (RC ) with I/

O on OSC2/CLKOUT.

7. INTOSC – Internal oscillator with FOSC/4 output

on OSC2 and I/O on OSC1/CLKIN.

8. INTOSCIO – Internal oscillator with I/O on

OSC1/CLKIN and OSC2/CLKOUT.

Clock Source modes are configured by the FOSC<2:0>

bits in the Configuration Word Register 1 (CONFIG1).

The internal clock can be generated from two internal

oscillators. The HFINTOSC is a calibrated high-

frequenc y osci llator. The LFINT OSC is an unca librate d

low-frequency oscillator.

FIGURE 4-1: SIMPLI FIED P IC® MCU CLOCK SOURCE BLOCK DIAGRAM

(CP U and Peripherals)

OSC1

OSC2

Sleep

External Oscillator

LP, XT, HS, RC, RCIO, EC

System Clock

Postscaler

MUX

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

IRCF<2:0>

111

110

101

100

011

010

001

000

31 kHz

Power-up Timer (PWRT)

FOSC<2:0>

(Configuration Word Register 1)

SCS<0>

(OSCCON Register)

Internal Oscillator

(OSCCON Register)

Watchdog Timer (WDT)

Fail-Safe Clock Monitor (FSCM)

HFINTOSC

8 MHz

LFINTOSC

31 kHz

INTOSC

PIC16F882/883/884/886/887

4.2 Oscillator Control

The Oscillator Control (OSCCON) register (Figure 4-1)

controls the system clock and frequency selection

options. The OSCCON register contains the following

bits:

• Frequency selection bits (IRCF)

• Frequency Status bits (HTS, LTS)

• System clock control bits (OSTS, SCS)

U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0

— IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits

111 = 8 MHz

110 = 4 MHz (defaul t)

101 = 2 MHz

100 = 1 MHz

011 = 500 kHz

010 = 250 kHz

001 = 125 kHz

000 = 31 kHz (LFINTOSC)

bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)

1 = Device is running from the c lock defined b y FOSC<2:0> of the CONFIG1 register

0 = Device is r unning f rom the in ternal oscillator (HFINTOSC o r LFI NTOSC)

bit 2 HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)

1 = HFINTOSC is stable

0 = HFINTOSC is not stable

bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)

1 = LFINT OSC is stable

0 = LFINTOSC is not st abl e

bit 0 SCS: System Cl ock Se lect bit

1 = Internal oscillator is used for system clock

0 = Clock source defined by FOSC<2:0> of the CONFIG1 register

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled.

PIC16F882/883/884/886/887

4.3 Clock Source Modes

Clock Source modes can be classified as external or

internal.

• Extern al C lock m odes re ly on exte rnal c ircuitry fo r

the clock source. Examples are: oscillator mod-

ules (EC mode), quartz crystal resonators or

ceramic resonators (LP, XT and HS modes) and

Resistor-Capacitor (RC) mode circuits.

• Internal clock sources are contained internally

within the oscil lator module. The oscillator mod ule

has two internal oscillators: the 8 MHz High-

Frequency Internal Oscillator (HFINTOSC) and

the 31 kHz Low-Frequency Internal Oscillator

(LFINTOSC).

The syste m cl oc k can be selected betw ee n ex tern al or

internal clock sources via the System Clock Select

(SCS) bit of the OSCCON register. See Section 4.6

“Clock Switching” for additional information.

4.4 External Clock Modes

4.4.1 OSCILLATOR START-UP TIMER (OST)

If the oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR) and when the Power-up Ti mer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

cryst al res onator o r ce ramic res onator, has st arted an d

is providing a stable system clock to the oscillator

module. When switching between clock sources, a

delay is required to allow the new clock to stabilize.

These oscillator delays are shown in Table 4-1.

In order to mi nimize laten cy between externa l oscillator

start-up and code execution, the Two-Speed Clock

S tart -up mode can be s elected (see Section 4.7 “T wo-

Speed Clock Start-up Mode”).

TABLE 4-1: OSCILLATOR DELAY EXAMPLES

4.4.2 EC MODE

The External Clock (EC) mode allows an externally

generated logic level as the system clock source. When

operating in this mode, an external clock source is

connected to the OSC1 input and the OSC2 is available

for general purpose I/O. Figure 4-2 shows the pin

connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC® MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

FIGURE 4-2: EXTERNAL CLOCK (EC)

MODE OPERATION

Switch From Switch To Frequency Oscillator Delay

Sleep/POR LFINTOSC

HFINTOSC 31 kHz

125 kHz to 8 MHz Oscillator Warm-up Delay (TWARM)

Sleep/POR EC, RC DC – 20 MHz 2 cycles

LFINTOSC (31 kHz) EC, RC DC – 20 MHz 1 cycle of each

Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)

LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz 1 μs (approx.)

OSC1/CLKIN

OSC2/CLKOUT(1)

I/O

Clock from

Ext. System PIC® MCU

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

PIC16F882/883/884/886/887

4.4.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 a nd OSC2 (Figur e 4-3). The mod e selects a low ,

medium or high gain setting of the internal inverter-

amplifi er to support vari ous resonator typ es and spee d.

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier . LP mode current consumption

is the least of the three mo des. This mode is designed to

drive only 32.768 kHz tuning-fork type crystals (watch

crystals).

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current c onsumption is the medium of the three mo des.

This mode is best suited to drive resonators with a

medium drive level specification.

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifie r. HS mode current consumption

is the highest of the three modes. This mode is best

suited fo r reso nato rs that require a h igh driv e s ettin g.

Figure 4-3 and Figure 4-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

FIGURE 4-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 4-4: CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ to 10 MΩ).

Quartz

RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: Quartz crystal characteristics vary according

to type, package and manufacturer. The

user should consult the manufacturer data

sheet s fo r spec ifica tions and re comm ende d

application.

2: Always veri fy os ci lla tor performance ov er

the VDD and temperature range that is

expected for the application.

3: For oscillator de sign assistance, re ference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC® and PIC®

Devices” (DS00826)

• AN849, “Basic PIC® Oscillator Design”

(DS00849)

• AN943, “Practical PIC® Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ to 10 MΩ).

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

C2 Ceramic RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

RP(3)

Resonator OSC2/CLKOUT

PIC16F882/883/884/886/887

4.4.4 EXTERNAL RC MODES

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes: RC and RCIO.

In RC mode, the RC circuit connects to OSC1. OSC2/

CLKOUT outputs the RC oscillator frequency divided

by 4. This signal may be used to provide a clock for

external circuitry, synchronization, calibration, test or

other application requirements. Figure 4-5 shows the

external RC mode connections.

FIGURE 4-5: EXTERNAL RC MODES

In RCIO mode, the RC circuit is connected to OSC1.

OSC2 becomes an additional general purpose I/O pin.

The RC oscillator frequency is a function of the supply

voltage, the resis tor (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packa ging vari ations in c apacitance

The user also needs to take into account variation due

to tolerance of external RC components used.

4.5 Internal Cloc k Modes

The oscillator module has two independent, internal

oscillators that can be configured or selected as the

system clock source.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

8 MHz. The f requenc y o f the HFINTOSC c an b e

user-adjusted via software using the OSCTUNE

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at

31 kHz.

The sy stem clock s peed can be selecte d via software

using the Internal Oscillator Frequency Select bits

IRCF<2:0> of the OSCCON register.

The syste m cl oc k can be selected between ext erna l or

inte rnal cloc k sources via the S ystem Clo ck Select ion

(SCS) bit of the OSCCON register. See Section 4.6

“Clock Switching” for more information.

4.5.1 INTOSC AND INTOSCIO MODES

The INTOSC and INTOSCIO modes configure the

internal oscillators as the system clock source when

the devi ce is pr ogrammed using the o scillato r selectio n

or the FOSC<2:0> bits in the Configuration Word

In INTOSC mode, OSC1/ CLKIN is av ailable for general

purpose I/O. OSC2/CLKOUT outputs the selected

internal oscillator fre quency divide d by 4. The CLKO UT

signal may be used to provide a clock for external

circuitry, synchronization, calibration, test or other

application requirements.

In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT

are available for general purpose I/O.

4.5.2 HFINTOSC

The Hig h-Frequency Int ernal Oscil lator (HFINT OSC) i s

a factory calibrated 8 MHz internal clock source. The

frequency of the HFINTOSC can be altered via

software using the OSCTUNE register (Register 4-2).

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 4-1). One of seven

frequencies can be selected via software using the

IRCF<2:0> bits of the OSCCON register. See

Section 4.5.4 “Frequency Select Bits (IRCF)” for

more information.

The HFINTOSC is enabled by selecting any frequency

betwee n 8 MHz and 125 kHz b y set ting th e IRCF <2:0>

bits of the OSCCON register ≠000. Then, set the

System Clock Source (SCS) bit of the OSCCON

the IESO bit in the Configuration Word Register 1

(CONFIG1) to ‘1’.

The HF Internal Oscillator (HTS) bit of the OSCCON

OSC2/CLKOUT(1)

CEXT

REXT

PIC® MCU

OSC1/CLKIN

FOSC/4 o r

Internal

Clock

VDD

VSS

Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V

3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V

CEXT > 20 pF, 2-5V

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

2: Output depend s upon RC or RCIO Clock

mode.

I/O(2)

PIC16F882/883/884/886/887

4.5.2.1 OSCTUNE Register

The HFINTOSC is factory calibrated but can be

adjusted in software by writing to the OSCTUNE

The default value of the OSCTUNE register is ‘0’. The

value is a 5-bit two’s complement number.

When the OSCTUNE register is modified, the

HFINTOSC frequency will begin shifting to the new

frequency. Code execution continues during this shift.

There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and p eripherals, are not affected by the

change in frequency.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 TUN<4:0>: Frequency Tuning bits

01111 = Maximu m frequency

01110 =

•

00001 =

00000 = Oscillator module is running at the factory-calibrated frequency.

11111 =

•

10000 = Minimum fre quency

PIC16F882/883/884/886/887

4.5.3 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 4-1). Select 31 kHz, via

software, using the IRCF<2:0> bits of the OSCCON

(IRCF)” for more inform ation. The LFINTOSC is also the

frequency for the Power-up Timer (PWRT), Watchdog

Timer (WDT) and Fail-Safe Clock Mo nitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<2:0> bit s of the OSCCON regis ter = 000) as the

system clock source (SCS bit of the OSCCON

• Two-Speed St a rt-up IESO bi t of the C on fig urati on

Word Register 1 = 1 and IRCF<2:0> bit s of th e

OSCCON regis ter = 000

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The LF Internal Oscillator (LTS) bit of the OSCCON

not.

4.5.4 FREQUENCY SELECT BITS (IRCF)

The output of the 8 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 4-1). The Internal Oscillator Frequency

Select bits IRCF<2:0> of the OSCCON register select

the frequency output of the internal oscillators. One of

eight frequencies can be selected via software:

•8 MHz

• 4 MHz (Default after Reset)

•2 MHz

•1 MHz

• 500 kHz

• 250 kHz

• 125 kHz

• 31 kHz (LFINTOSC)

4.5.5 HFINTOSC AND LFINTOSC CLOCK

SWITCH TIMING

When switching between the LFINTOSC and the

HFINTOSC, the new oscillator may already be shut

down to save power (see Figure 4-6). If th is is the cas e,

there is a delay after the IRCF<2:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The LTS and HTS bits of the

OSCCON register will reflect the current active status

of the LFINTOSC and HFINTOSC oscillators. The

timing of a frequency selection is as follows:

1. IRCF<2:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Cl ock switch ci rcuitry waits for a fal ling edge of

the cu rrent clock.

4. CLKOUT is held low and the clock switch

circuit ry w ai t s for a rising edg e in the new clock.

5. CLKOUT is now connected with the new clock.

LT S and HTS bits of th e OSCCON registe r are

updated as require d.

6. Clock switch is complete.

See Figure 4-1 for more details.

If the internal oscillator speed selected is between

8 MHz and 125 kHz, there is no start-up delay before

the new frequency is selected. This is because the old

and new frequencies are derived from the HFINTOSC

via the post s ca ler and multiplexer.

Start-up delay specifications are located in the

oscillator tables of Section 17.0 “Electrical

Specifications”.

Note: Following any Reset, the IRC F<2:0> bits of

the OSCCON register are set to ‘110’ and

the frequency selection is set to 4 MHz.

The user can modify the IRCF bits to

select a different frequency.

PIC16F882/883/884/886/887

FIGURE 4-6: INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC

LFINTOSC

IRCF <2:0>

System Clock

HFINTOSC

LFINTOSC

IRCF <2:0>

System Clock

≠ 0= 0

Start-up Time 2-cycle Sync Running

2-cycle Sync Running

HFINTOSC LFINTOSC (FSCM and WDT disabled)

HFINTOSC LFINTOSC (Either FSCM or WDT enabled)

LFINTOSC

HFINTOSC

IRCF <2:0>

System Clock

= 0¼ 0

Start-up Time 2-cycle Sync Running

LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled

PIC16F882/883/884/886/887

4.6 Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bit of the OSCCON

4.6.1 SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit of the OSCCON

the CPU and peripherals.

• Whe n the SCS bit of the OSCCON register = 0,

the system clock source is determined by

configuration of the FOSC<2:0> bits in the

Conf igur ation Word Register 1 (CONFIG1).

• Whe n the SCS bit of the OSCCON register = 1,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<2:0>

bits of the OSCCON register. After a Reset, the

SCS bit of the OSCCON register is always

cleared.

4.6.2 OSCIL LAT OR START-UP TIME-OU T

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of

the OSCCON register indicates whether the system

clock is running from the external clock source, as

defined by the FOSC<2:0> bits in the Configuration

Word Regis te r 1 (CONFI G1 ), or from the inte rna l cl oc k

source. In particular , OSTS indicates that the Oscillator

Start-up Timer (OST) has timed out for LP, XT or HS

modes.

4.7 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device.

This mode allows the application to wake-up from

Sleep, perform a few instructions using the INTOSC

as the clock source and go back to Sleep without

waiting for the primary oscillator to become stable.

When the oscillat or module is configured for LP, XT or

HS modes, the Oscillator Start-up Timer (OST) is

enabled (see Section 4.4.1 “Oscillator Start-up Timer

(OST)”). The OST will suspend program execution until

1024 oscillations are counted. Two-Speed Start-up

mode minimizes the delay in code execution by

operating from the internal oscillator as the OST is

counting. When the OST count reaches 1024 and the

OSTS bit of the OSCCON register is set, program

executi on switches to the external oscillator.

4.7.1 TWO-SPEED START-UP MODE

CONFIGURATION

Two-Speed Start-up mode is configured by the

following settings:

• IESO (of the Configuration Word Register 1) = 1;

Internal/ E xte rnal Switc hov er b it (Two-Speed St a rt-

up mode enabled).

• SCS (of the OSCCON register) = 0.

• FOSC<2:0> bits in the Configuration Word

HS mode.

Two-Speed Start-up mode is entered after:

• Pow er-on Reset (POR) and, if enabl ed, after

Power-up Ti mer (PWRT) has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be

anything other than LP, XT or HS mode, then Two-

speed S tart-up is disabled. This is because the external

clock oscillator does not require any stabilization time

after POR or an ex it from Sleep.

4.7.2 TWO-SPEED START-UP

SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<2:0>

bits of th e O SCCON re giste r.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System c lock he ld low until the next fal ling edg e

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

Note: Any automatic clock switch, which may

occur from Two-S peed Start-up or Fail-Safe

Clock Monito r , does not update the SCS bit

of the OSCCON register. The user can

monitor the OSTS bit of the OSCCON

clock sour ce.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCCON register to

remain clear.

PIC16F882/883/884/886/887

4.7.3 CHECKING TWO-SPEED CLOCK

STATUS

Checking the state of the OSTS bit of the OSCCON

from the external clock source, as defined by the

FOSC<2:0> bits in the Configuration Word Register 1

(CONFIG1), or the internal oscillator.

FIGURE 4-7: TWO-SPEED START-UP

0 1 1022 1023

PC + 1

TOSTT

HFINTOSC

OSC1

OSC2

Program Counter

System Clock

PC - N PC

PIC16F882/883/884/886/887

4.8 Fail-Safe Clock Monitor

The Fail-Saf e Cl oc k Mo nit or (FSC M) al lows the dev ic e

to continue operat ing should th e external os ci ll ator fail.

The FSCM can detect oscillator failure any time after

the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

Config uration W ord Reg ister 1 (C ONFIG1). The F SCM

is applicable to all external Oscillator modes (LP, XT,

HS, EC, RC and RCIO).

FIGURE 4-8: FSCM BLOCK DIAGRAM

4.8.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

compari ng the extern al osci llat or to the FSCM sa mple

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 4-8. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock cle ars the latch on each ris ing edge of th e

sample c loc k. A fail ure is d ete cte d w h en an entire half-

cycle of the sample clock elapses before the primary

clock goes low.

4.8.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

devi ce clock to an interna l clock s ource and s ets the b it

flag OSFIF of the PIR2 register. Setting this flag will

generate an interrupt if the OSFIE bit of the PIE2

steps to mitigate the problems that may arise from a

failed clock. The system clock will continue to be

sourced from the internal clock source until the device

firmware successfully restarts the external oscillator

and switches back to external operation.

The internal clock source chosen by the FSCM is

determined by the IRCF<2:0> bits of the OSCCON

configured before a failure occurs.

4.8.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset,

executing a SLEEP instruction or toggling the SCS bit

of the OSCCON register. Wh e n th e SC S b i t i s t o g gl ed ,

the OST is restarted. While the OST is running, the

device co ntinue s to op erate fro m the I NT OSC sele cted

in OSCCON. When the OST times out, the Fail-Safe

condition is cleared and the device will be operating

from the ex ternal cl ock s ource. The Fai l-Saf e condi tion

must be c le ared bef ore th e O SFIF flag can be cle are d.

4.8.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC or

RC Clock modes so that the FSCM will be active as

soon as the Reset or wake-up has completed. When

the FSCM is enabled, the Two-Speed Start-up is also

enabled . Therefore, the device will alway s be executing

code while the OST is operating.

External

LFINTOSC ÷ 64

31 kHz

(~32 μs) 488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit of the OSCCON register to verify

the oscillator start-up and that the system

clock switchover has successfully

completed.

PIC16F882/883/884/886/887

FIGURE 4-9: FSCM TIMING DIAGRAM

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note: The syste m clock is normally at a m uch higher frequency than the sam ple clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Test Test Test

Clock Monitor Output

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets(1)

CONFIG1(2) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000

OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE —CCP2IE 0000 00-0 0000 00-0

PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF —CCP2IF 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: See Configuration Word Register 1 (Register 14-1) for operation of all register bits.

PIC16F882/883/884/886/887

5.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on over flow

Figure 5-1 is a block diagram of the Timer0 module.

5.1 Timer0 Operation

When use d as a tim er, the T imer0 modul e can be used

as either an 8-bit timer or an 8-bit counter.

5.1.1 8-BIT TIMER MODE

When used as a timer, the Timer0 module will

increment every instruction cycle (without prescaler).

Timer mode is selected by clearing the T0CS bit of the

OPTION register to ‘0’.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

5.1.2 8-BIT COUNTER MODE

When used as a counter, the Timer0 module will

increment on every rising or falling edge of the T0CKI

pin. The incrementing edge is determined by the T0SE

bit of the OPTION register . Counter mode is selected by

setting the T0CS bit of the OPTION register to ‘1’.

FIGURE 5-1: TIMER0/WDT PRESCALER BLOCK DIAGRAM

Note: The value writ ten to the T MR0 register can

be adju sted, in o rder to ac count for th e two

instruction cycle delay when TMR0 is

written.

T0CKI

T0SE

TMR0

Watchdog

Timer

WDT

Time-out

PS<2:0>

WDTE

Data Bus

Set Flag bi t T0 IF

on Overflow

T0CS

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.

2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.

3: WDTE bit is in the Configuration Word Register1.

8-bit

Prescaler

FOSC/4

PSA

16-bit

Prescaler 16

WDTPS<3:0>

31 kHz

INTOSC

SWDTEN

Sync

2 Tcy

PIC16F882/883/884/886/887

5.1.3 SOFTWARE PROGRAMMABLE

PRESCALER

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignme nt is contro lled by the PSA bit o f the OPTION

must be cleared to a ‘0’.

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

select able via th e PS<2:0> bits of the OPTION registe r .

In order to have a 1:1 prescaler value for the Timer0

module, the prescaler must be assigned to the WDT

module.

The prescaler is not readable or writable. When

assigned to the T im er0 module, all instructions writing to

the TMR0 register will clear the prescaler.

When the prescaler is assigned to WDT, a CLRWDT

instruction will clear the prescaler along with the WDT.

5.1.3.1 Switching Prescaler Between

Timer0 and WDT Modules

As a result of having the prescaler assigned to either

Timer0 or the WDT, it is possible to generate an

unintended device Reset when switching prescaler

values . When chan gin g th e presca le r ass ig nme nt fro m

Timer0 to the WDT module, the instruction sequence

shown in Example 5-1, must be executed.

EXAMPLE 5-1: CHANGING PRESCALER

(TIMER0 →WDT)

When changing the prescaler assignment from the

WDT to the Timer0 module, the following instruction

sequence must be execute d (see Example 5-2).

EXAMPLE 5-2: CHANGING PRESCA LER

(WDT →TIMER0)

5.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

flag bit of the INTCON register is set every time the

TMR0 register overflows, regardless of whether or not

the Timer0 interrupt is enabled. The T0IF bit must be

cleared in software. The Timer0 interrupt enable is the

T0IE bit of the INTCON register.

5.1.5 USING TIMER0 WITH AN

EXTERNAL CLOCK

When Timer 0 is in Coun ter mode, t he synchronizatio n

of the T0CKI input and the Timer0 register is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, the

high and low peri od s of the ex tern al cl oc k so urc e mus t

meet the timing requirements as shown in the

Section 17.0 “Electrical Specifications”.

BANKSEL TMR0 ;

CLRWDT ;Clear WDT

CLRF TMR0 ;Clear TMR0 and

;prescaler

BANKSEL OPTION_REG ;

BSF OPTION_REG,PSA ;Select WDT

CLRWDT ;

;

MOVLW b’11111000’ ;Mask prescaler

ANDWF OPTION_REG,W ;bits

IORLW b’00000101’ ;Set WDT prescaler

MOVWF OPTION_REG ;to 1:32

Note: The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

CLRWDT ;Clear WDT and

;prescaler

BANKSEL OPTION_REG ;

MOVLW b’11110000’ ;Mask TMR0 select and

ANDWF OPTION_REG,W ;prescaler bits

IORLW b’00000011’ ;Set prescale to 1:16

MOVWF OPTION_REG ;

PIC16F882/883/884/886/887

TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

bit 5 T0CS: TMR0 Cloc k Sourc e Sele ct bit

1 = Transit ion on T0CKI pin

0 = Internal instruction cycle clo ck (FOSC/4)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assig nme nt bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

Note 1: A dedicated 16-bit WDT postscaler is available. See Section 14.5 “Watchdog Timer (WDT)” for more

information.

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

BIT VALUE TMR 0 RA TE WDT RATE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: – = Un im pl em ente d l oc ati ons, read as ‘ 0’, u = unc ha nge d, x = unknown. Shad ed ce lls are not used by the

Timer0 module .

PIC16F882/883/884/886/887

6.0 TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit timer/counter with the

following features:

• 16-bi t timer/c ounter reg ister pai r (TMR1 H:TMR1 L)

• Programmable internal or external clock source

• 3-bit prescaler

• Optional LP oscillator

• Synchronous or asynchronous operation

• Timer1 gate (count enable) via comparator or

T1G pin

• Interrupt on over flow

• Wak e-up on ov erfl ow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with ECCP)

• Comparator output synchronization to Timer1

clock

Figure 6-1 is a block diagram of the Timer1 module.

6.1 Timer1 Operation

The Timer1 module is a 16-bit incrementing counter

which is acces sed through the TMR 1H:TMR1L reg ister

pair. Writes to TMR1H or TMR1L directly update the

counter.

When us ed with an interna l clock so urce, the module i s

a time r. When us ed wit h an ex terna l clock sourc e, the

module can be used as either a timer or counter.

6.2 Clock Source Selection

The TMR1CS bit of the T1CON register is used to select

the clock source. When TMR1CS = 0, the clock source

is FOSC/4. When TMR1CS = 1, the clock source is

supplied exte rnally.

FIGURE 6-1: TIMER1 BLOCK DIAGRAM

Clock Source TMR1CS

FOSC/4 0

T1CKI pin 1

Note 1: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI.

2: Timer1 register increm ents on rising edge.

3: Synchronize does not operate while in Sleep.

4: SYNCC2OUT is synchronized when the C2SYNC bit of the CM2CON1 register is set.

TMR1H TMR1L

Oscillator T1SYNC

T1CKPS<1:0>

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronized

clock input

Set flag bit

TMR1IF on

Overflow TMR1(2)

TMR1GE

TMR1ON

T1OSCEN

SYNCC2OUT(4)

T1GSS

T1GINV

To C2 Comparator Module

Timer1 Clock

TMR1CS

T1OSI

T1OSO/T1CKI (1)

INTOSC

Without CLKOUT

Synchronize(3)

det

T1G

PIC16F882/883/884/886/887

6.2.1 INTERNAL CLOCK SOURCE

When the internal clock source is selected the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

6.2.2 EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may wo rk as a timer or a cou nter.

When counting, Timer1 is incremented on the rising

edge of the external clock input T1CKI. In addition, the

Counter mode clock can be synchronized to the

microcontroller system clock or run async hronously.

If an external clock oscillator is needed (and the

microc ontroller is using the INT OSC withou t CLKOUT),

Timer1 can use the LP oscillator as a clock source.

In Counter mode, a falling edge must be registered by

the counter prior to the first incrementing rising edge

after one or more of the following conditions (see

Figure 6-2):

• Timer1 is enabled after POR or BOR Reset

• A write to TMR1H or TMR1L

• T1CKI is high when Timer1 is disabled and when

Timer1 is reenabled T1CKI is low.

6.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however , the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

6.4 Timer1 Oscillator

A low-power 32.768 kHz oscillator is built-in between

pins T1OSI (input) and T1OSO (amplifier output). The

oscillator is enabled by setting the T1OSCEN control

bit of th e T1CON register. The oscil lator wi ll contin ue to

run during Sleep.

The Timer1 oscillator is identical to the LP oscillator.

The user m us t prov id e a so ftware tim e de lay to en su re

proper oscillator start-up.

TRISC0 and TRISC1 bits are set when the Timer1

oscill ator is enable d. RC0 an d RC 1 bit s read as ‘0’ an d

TRISC0 and TRISC 1 bits read as ‘1’.

6.5 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

continues to increment asynchronous to the internal

phase clocks. The timer will continue to run during

Sleep and can generate an interrupt on overflow,

which will wake-up the processor. However, special

precautions in software are needed to read/write the

timer (see Section 6.5.1 “Reading and Writing

Timer1 in Asynchronous Counter Mode”).

6.5.1 READING AND WRITING T IMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an e xternal asyn chronous cl ock will ens ure a valid

read (taken care of in hardware). However, the user

should keep i n mind that rea ding t he 16-bi t time r in tw o

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For writes , it is re commend ed that th e user s imply sto p

the timer and write the desired values. A write

conte ntion may occ ur by w ritin g to th e timer regist ers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TTMR1L register

pair.

6.6 Timer1 Gate

Timer1 gate source is software configurable to be the

T1G pin or the output of Comparator C2. This allows the

device to directly time external events using T1G or

analog events using Comparator C2. See the

CM2CON1 register (Register 8-3) for selecting the

Timer1 gate source. This feature can simplify the

software for a Delta-Sigma A/D converter and many

other applications. For more informatio n on Delt a-Sigma

A/D converters, see the Microchip web site

(www.microchip.com).

Timer1 gate can be inverted using the T1GINV bit of

the T1CON register, whether it orig inates from the T1G

pin or Comparato r C2 output. T his configures T imer1 to

measure either the active-high or active-low time

between events.

Note: The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

Note: When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce a single spurious

increment.

Note: TMR1GE bit of the T1CON register must be

set to use the Timer1 gate.

PIC16F882/883/884/886/887

6.7 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Ti mer1 in terrupt fl ag bit of th e PIR1 regis ter is

set. To enable the interrupt on rollover, you must set

these bits:

• Timer1 interrupt enable bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

6.8 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynch ronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

The device will wake-up on an overflow and execute

the next instruction. If the GIE bit of the INTCON

Routine (0004h).

6.9 ECCP Capture/Compare Time Base

The ECCP module uses the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

In Compare mode, an event is triggered when the value

CCPRxH:CCPRxL register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

See Section 11.0 “Capture/Compare/PWM Modules

(CCP1 and CCP2)” for more information.

6.10 ECCP Special Event Trigger

If an ECCP is confi gure d to trigg er a spe ci al ev ent , the

trigger will clear the TMR1H:TMR1L register pair. This

special event does not cause a Timer1 interrupt. The

ECCP module may still be configured to generate a

ECCP interrupt.

In this mode of operation, the CCPRxH:CCPRxL

Timer1.

Timer1 should be synchronized to the FOSC to utilize

the Special Event Trigger. Asynchronous operation of

Timer1 can cause a Special Event Trigger to be

missed.

In the eve nt that a wri te to TMR1H or TMR1L coi ncides

with a Special Event Trigger from the ECCP, the write

will take precedence.

For more information, see Section 11.0 “Capture/

Compare/PWM Modules (CCP1 and CCP2)”.

6.11 Comparator Synchronization

The same cloc k used to increment Timer1 can also be

used to synchronize the comparator output. This

feature is enabled in the Comparator module.

When using the comparator for Timer1 gate, the

comparator output should be synchronized to Timer1.

This ensures Timer1 does not miss an increment if the

comp ara tor changes.

For more information, see Section 8.0 “Comparator

Module”.

FIGURE 6-2: TIMER1 INCREMENTING EDGE

Note: The T MR1H:TTMR1L register p air and th e

TMR1IF bit should be cleared before

enabling interrupts.

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be re gistered by the counter prior to t he first incrementing rising edge of

the clock.

PIC16F882/883/884/886/887

6.12 Timer1 Control Register

The Timer1 Control register (T1CON), shown in

various features of the Timer1 module.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 T1GINV: Timer1 Gate Invert bit(1)

1 = Timer1 gate is active-high (Timer1 counts when gate is high)

0 = Timer1 gate is active-low (Timer1 counts when gate is low)

bit 6 TMR1GE: Timer1 Gate Enable bit(2)

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1 = Timer1 counting is controlled by the Timer1 Gate function

0 = Timer1 is always counting

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale Value

10 = 1:4 Prescale Value

01 = 1:2 Prescale Value

00 = 1:1 Prescale Value

bit 3 T1OSCEN: LP Oscillator Enable Contro l bit

1 = LP oscillator is enabled for Timer1 clock

0 = LP oscillator is off

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1 = Do not synchroniz e exte rnal cloc k inp ut

0 = Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock

bit 1 TMR1CS: Timer1 Clock Sourc e Sele ct bit

1 = External clock from T1CKI pin (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE b it must be set to us e eithe r T1G pin or C2OUT, as se lecte d by t he T1G SS bit o f the CM 2CON 1

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TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL —— T1GSS C2SYNC 0000 --10 0000 --10

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

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7.0 TIMER2 MODULE

The Timer2 module is an eight-bit timer with the

following features:

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

See Figure 7-1 for a block diagram of Timer2.

7.1 Timer2 Operation

The clock input to the Timer2 module is the system

instruction clock (FOSC/4). The clock is fed into the

Timer2 prescaler, which has prescale options of 1:1,

1:4 or 1:16. The output of the prescal er is the n use d to

increm ent the TM R2 regis ter.

The val ues of T MR2 and PR2 are co nstan tly com pared

to determine when they match. TMR2 will increment

from 00h until it matches the value in PR2. When a

match occurs, two things happen:

• TMR2 is reset to 00h on the next increment cycle

• The Timer2 postscaler is incremented

The match output of the Timer2/PR2 comparator is

then fed into th e T i mer2 post sca ler. The post s caler has

post scal e options of 1:1 to 1: 16 inclus ive. The output of

the Timer2 postscaler is used to set the TMR2IF

interrupt flag bit in the PIR1 register.

The TMR2 and PR2 registers are both fully readable

and w rita ble. O n any Rese t, the TMR2 regis ter is set to

00h and the PR2 register is set to FFh.

Timer2 is turned on by setting the TMR2ON bit in the

T2CON register to a ‘1’. Tim er2 is turned off by clearing

the TMR2ON bit to a ‘0’.

The Timer2 presc ale r is contro lle d by the T2CKPS bits

in the T2CON register. The Timer2 postscaler is

controlled by the TOUTPS bits in the T2CON register.

The prescaler and postscaler counters are cleared

when:

• A write to TMR2 occurs.

• A write to T2CON occurs.

• Any device Reset occurs (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset).

FIGURE 7-1: TIMER2 BLOCK DIAGRAM

Note: TMR2 is not cleared when T2CON is

written.

Comparator

TMR2 Sets Flag

TMR2

Output

Reset

Postscaler

Prescaler

PR2

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

bit TMR2IF

TOUTPS<3:0>

T2CKPS<1:0>

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TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2 REGISTERS

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits

0000 = 1:1 Pos tscaler

0001 = 1:2 Pos tscaler

0010 = 1:3 Pos tscaler

0011 = 1:4 Pos tscaler

0100 = 1:5 Pos tscaler

0101 = 1:6 Pos tscaler

0110 = 1:7 Pos tscaler

0111 = 1:8 Pos tscaler

1000 = 1:9 Pos tscaler

1001 = 1:10 Postscaler

1010 = 1:11 Postscaler

1011 = 1:12 Postscaler

1100 = 1:13 Postscaler

1101 = 1:14 Postscaler

1110 = 1:15 Postscaler

1111 = 1:16 Postscaler

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00 =Prescaler is 1

01 =Prescaler is 4

1x = Prescaler is 16

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all ot her

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

PR2 Timer2 Module Period Register 1111 1111 1111 1111

TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

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8.0 COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

The comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of the program execution. The analog

comparator module includes the following features:

• Independent comparator control

• Programmable input selection

• Comp arator ou tput is avail able internall y/externally

• Programmable output polarity

• Interrupt-on-change

• Wake-up from Sleep

•PWM shutdown

• Time r1 gate (co unt enable)

• Output synchronization to Timer1 clock input

•SR Latch

• Programmable and fixed volt age reference

8.1 Comparator Overview

A single comparator is shown in Figure 8-1 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of th e comp arator is a digita l high leve l.

FIGURE 8-1: SINGLE COMPARATOR

Note: Only Comparator C2 can be linked to

Timer1.

–

VIN+

VIN-Output

Output

VIN+

VIN-

Note: The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

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FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM

FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM

Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).

3: Q1 is held high during Sleep mode.

C1POL

C1OUT

To PWM Logic

RD_CM1CON0

Set C1IF

Q1 Data Bus

C1POL

Q3*RD_CM1CON0

Reset

C1OUT (to SR Latch)

MUX

C1ON(1)

C1CH<1:0> 2

C1R

MUX

C1VIN-

C1VIN+

C12IN0-

C12IN1-

C12IN2-

C12IN3-

C1IN+ +

MUX

CVREF

C1RSEL

FixedRef

C1VREF

MUX C2

C2POL

C2OUT

C2ON(1)

C2CH<1:0> 2

C2R

From Timer1

Clock

Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).

3: Q1 is held high during Sleep mode.

MUX

RD_CM2CON0

Q3*RD_CM2CON0

Set C 2 IF

Reset

C2VIN-

C2VIN+

SYNCC2OUT

C2IN+

C12IN0-

C12IN1-

C12IN2-

C12IN3-

C2SYNC

C2POL Data Bus

MUX To Timer1 Gate, SR Latch,

MUX

CVREF

C2RSEL

FixedRef

C2VREF

PWM Logic, and other

peripherals

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8.2 Comparator Control

Each comparator has a separate control and

Configuration register: CM1CON0 for Comparator C1

and CM2CON0 for Comparator C2. In addition,

Comparator C2 has a second control register,

CM2CON1, for controlling the interaction with Timer1 and

simultaneous reading of both comparator outputs.

The CM1CON0 and CM2CON0 registers (see Registers

8-1 and 8-2, respectively) contain the control and Status

bits for the followi ng:

• Enable

• Input selection

• Reference selection

•Output selection

• Outp ut pol arit y

8.2.1 COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

8.2.2 COMPARATOR INPUT SELECTION

The CxCH<1:0> bits of the CMxCON0 register direct

one of four analog input pins to the comparator

inverting input.

8.2.3 COMPARATOR REFERENCE

SELECTION

Setting the CxR bit of the CMxCON0 register directs an

internal voltage reference or an analog input pin to the

non-inverting input of the comparator. See

Section 8.10 “Comparator Voltage Reference” for

more information on the internal voltage reference

module.

8.2.4 COMPARATOR OUTPUT

SELECTION

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CM2CON1 register. In order

to make the output available for an external connection,

the following conditions must be true:

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set

8.2.5 COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit result s in a non-inverted output.

Table 8-1 shows the output state versus input

conditions, including polarity control.

8.3 Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new refe rence volta ge. This period is refer red to as

the response time. The response time of the

comparator differs from the settling time of the voltage

reference. Therefore, both of these times must be

considered when determining the total response time

to a comparator input change. See the Comparator and

Voltage Reference specifications in Section 17.0

“Electrical Specifications” for more details.

Note: To use CxIN+ and CxIN- pins as analog

inputs, the appropriate bits must be set in

the ANSEL an d ANSELH registers and the

corresponding TRIS bits must also be set

to disable the output drivers.

Note 1: The CxOE bit overrides the PORT data

latch. Setting the CxON has no impact on

the port overrid e.

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

TABLE 8-1: COMPARATOR OUTPUT

STATE VS. IN PUT

CONDITIONS

Input Condition CxPOL CxOUT

CxVIN- > CxVIN+00

CxVIN- < CxVIN+01

CxVIN- > CxVIN+11

CxVIN- < CxVIN+10

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8.4 Comparator Interrupt Operation

The comparator interrupt flag can be set whenever

there is a chang e in the o utput val ue of the compa rator.

Changes are recognized by means of a mismatch

circuit which consists of two latches and an exclusive-

or gate (see Figures 8-2 and 8-3). One latch is updated

with the compa rator o utp ut leve l when th e CMxCON 0

next read of the CMxCON0 register or the occurrence

of a Reset. The other latch of the mismatch circuit is

updated on every Q1 system clock. A mismatch

condition will occur when a comparator output change

is clocked through the second latch on the Q1 clock

cycle. At this point the two mismatch latches have

opposite output levels which is detected by the

exclusive-or gate and fed to the interrupt circuitry. The

mismatch condition persists until either the CMxCON0

previous state.

The comparator interrupt is set by the mismatch edge

and not the mismatch level. This means that the inter-

rupt flag can be reset without the additional step of

reading or writing the CMxCON0 register to clear the

mismatch registers. When the mismatch registers are

cleared, an interrupt will oc cur upon the comparator ’s

return to the previous state, otherwise no interrupt will

be generated.

Software will need to maintain information about the

status of the comparator output, as read from the

CMxCON0 register , or CM2CON1 register, to determine

the actual change that has occ urred.

The CxIF bit of the PIR2 register is the comparator

interrupt flag. This bit must be reset in software by

clearing it to ‘0’. Since i t i s also po ssib le t o writ e a ‘1’ to

this register, an interrupt can be generated.

The CxIE bi t of the PIE2 re gister and the PEIE and G IE

bits of the INTCON register must all be set to enable

comparator interrupts. If any of these bits are cleared,

the interru pt is not en abled, alt hough the Cx IF bit of the

PIR2 register will still be set if an interrupt condition

occurs.

FIGURE 8-4: COMPARATOR

INTERRUPT TIMING W/O

CMxCON0 READ

FIGURE 8-5: COMPARATOR

INTERRUPT TIMING WITH

CMxCON0 READ

Note 1: A write operation to the CMxCON0

condition because all writes include a read

operation at the beginning of the write

cycle.

2: Comparator interrupts will operate correctly

regardless of the state of CxOE. Note 1: If a change in the CMxCON0 register

(CxOUT) s hould occu r when a read op er-

ation is being executed (start of the Q2

cycle), then the CxIF of the PIR2 register

interrupt flag may not get set.

2: When either comparator is first enabled,

bias circuitry in the comparator module

may cause an invalid output from the

comparator until the bias circuitry is stable.

Allow about 1 μs for bias settling then clear

the mismatch condition and interrupt flags

before enabling comparator interrupts.

CIN+

CxOUT

Set CxIF (level)

CxIF

TRT

reset by software

CxIN+

CxOUT

Set CxIF (level)

CxIF

TRT

reset by software

cleared by CMxCON0 read

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8.5 Operation During Sleep

The compa rator , if enabled b efore entering Sleep mode,

remains active during Sleep. The additional current

consumed by the comp arator is show n separately in the

Section 17.0 “Electrical Specifications”. If the

comparator is not used to wake the device, power

consumption can be minimized while in Sleep mode by

turning off the comp arator. Each comparator is turned of f

by clearing the CxON bit of the CMxC ON0 register.

A change to the comparator output can wake-up the

device from Sleep. To enable the comparator to wake

the devic e from Sle ep, the CxIE bit of the PIE2 reg ister

and the PEIE bit of the INTCON register must be set.

The instruction following the Sleep instruction always

executes following a wake from Sleep. If the GIE bit of

the INTCON register is also set, the device will then

execute the Interrupt Service Routine.

8.6 Effects of a Reset

A device Reset forces the CMxCON0 and CM2CON1

registers to their Reset states. This forces both

comparators and the voltage references to their Off

states.

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R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

C1ON C1OUT C1OE C1POL —C1R C1CH1 C1CH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C1ON: Comparator C1 Enable bit

1 = Comparator C1 is enabled

0 = Comparator C1 is disabled

bit 6 C1OUT: Comparator C1 Output bit

If C1POL = 1 (inverted polarity):

C1OUT = 0 when C1VIN+ > C1VIN-

C1OUT = 1 when C1VIN+ < C1VIN-

If C1POL = 0 (non-inverted polarity):

C1OUT = 1 when C1VIN+ > C1VIN-

C1OUT = 0 when C1VIN+ < C1VIN-

bit 5 C1OE: Comparator C1 Output Enable bit

1 = C1OUT is present on the C1OUT pin(1)

0 = C1OUT is internal only

bit 4 C1POL: Comparator C1 Output Polarity Select bit

1 = C1OUT logic is inverted

0 = C1OUT logic is not inverted

bit 3 Unimplemented: Read as ‘0’

bit 2 C1R: Comparator C1 Refere nce Select bit (non-inverting input)

1 = C1VIN+ connects to C1VREF output

0 = C1VIN+ connects to C1IN+ pin

bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit

00 = C12IN0- pin of C1 connects to C1VIN-

01 = C12IN1- pin of C1 connects to C1VIN-

10 = C12IN2- pin of C1 connects to C1VIN-

11 = C12IN3- pin of C1 connects to C1VIN-

Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port

TRIS bit = 0.

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R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

C2ON C2OUT C2OE C2POL —C2R C2CH1 C2CH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C2ON: Comparator C2 Enable bit

1 = Compar ator C2 is enab led

0 = Comparator C2 is disabled

bit 6 C2OUT: Comparator C2 Output bit

If C2POL = 1 (inverted polarity):

C2OUT = 0 when C2VIN+ > C2VIN-

C2OUT = 1 when C2VIN+ < C2VIN-

If C2POL = 0 (non-inverted polarity):

C2OUT = 1 when C2VIN+ > C2VIN-

C2OUT = 0 when C2VIN+ < C2VIN-

bit 5 C2OE: Comparator C2 Output Enable bit

1 = C2OUT is present on C2OUT pin(1)

0 = C2OUT is internal only

bit 4 C2POL: Comparator C2 Output Polarity Select bit

1 = C2OUT logic is inverted

0 = C2OUT logic is not inverted

bit 3 Unimplemented: Read as ‘0’

bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input)

1 = C2VIN+ connects to C2VREF

0 = C2VIN+ connects to C2IN+ pin

bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits

00 = C12IN0- pin of C2 connects to C2VIN-

01 = C12IN1- pin of C2 connects to C2VIN-

10 = C12IN2- pin of C2 connects to C2VIN-

11 = C12IN3- pin of C2 connects to C2VIN-

Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port

TRIS bit = 0.

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8.7 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 8-6. Since the analog i nput pins share thei r con-

nection with a digital input, they have reverse biased

ESD protection diodes to VDD and VSS. The analog

input, therefore, must be between VSS and VDD. If the

input voltage deviates from this range by more than

0.6V in either direction, one of the diodes is forward

biased and a latch-up may occur.

A maximum source impedance of 10 kΩ is recommended

for the analog sources. Also, any external component

connected to an anal og inpu t pin, such as a capacitor or

a Zener diode, should h ave very little leakage curr ent to

minimize inaccuracies introduced.

FIGURE 8-6: ANALOG INPUT MODEL

Note 1: When reading a PORT register, all pins

configu red a s anal og inp uts will read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

2: Analog levels on any pin defined as a

digit al input, may ca use the input buff er to

consume more current than is specified.

Rs < 10K

CPIN

5 pF

VDD

VT ≈ 0.6V

RIC

ILEAKAGE(1)

±500 nA

Vss

AIN

Legend: CPIN = Input Capaci tance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC = Interconnect Resistance

RS= Source I mpedance

VA= Analog Voltage

VT= Threshold Voltage

To ADC Input

Note 1: See Section 17.0 “Electrical Specifications”.

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8.8 Additional Comparator Features

There are three additional comparator features:

• Timer1 count enable (gate)

• Synchronizing output with Timer1

• Simultaneous read of comparator outputs

8.8.1 COMPARATOR C2 GATING TIMER1

This feat ure can be used to time the d uration or inte rval

of analog events. Clearing the T1GSS bit of the

CM2CON1 register will enable Timer1 to increment

based on the output of Comparator C2. This requires

that Timer1 is on and gating is enabled. See

Section 6.0 “Timer1 Module with Gate Control” for

details.

It is recommended to synchronize the comparator with

Timer1 by setting the C2SYNC bit when the comparator

is us ed as t he T imer1 gate sou rce. Thi s ensur es T imer1

does not miss a n incr eme nt if the compar a tor ch an ges

during an increment.

8.8.2 SYNCHRONIZING COMPARATOR

C2 OUTPUT TO TIMER1

The Comparator C2 output can be synchronized with

Timer1 by setting the C2SYNC bit of the CM2CON1

falling edge of the Timer1 clock source. If a prescaler is

used with T imer1, the comparator output is latched after

the prescaling function. To prevent a race condition, the

comparator o utput is latch ed on the falling e dge of th e

Timer1 clock source and Timer1 increments on the

rising edge of its clock source. See the Comparator

Block Diagram (Figures 8-2 and 8-3) and the Timer1

Block Diagram (Figure 6-1) for more infor m ation.

8.8.3 SIMULTANEOUS COMPARATOR

OUTPUT READ

The MC1OUT and MC2OUT bits of the CM2CON1

The ability to read both outputs simultaneously from a

single register eliminates the timing skew of reading

separate registers.

Note 1: Obtaining the status of C1OUT or C2OUT

by readi ng C M2CON 1 do es not af fect th e

comparator interrupt mism atch registers.

R-0 R-0 R/W-0 R/W-0 U-0 U-0 R/W-1 R/W-0

MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 MC1OUT: Mirror Copy of C1OUT bit

bit 6 MC2OUT: Mirror Copy of C2OUT bit

bit 5 C1RSEL: Comparator C1 Refe rence Select bit

1 = CVREF routed to C1VREF input of Comparator C1

0 = Absolute voltage reference (0.6) routed to C1VREF input of Comparator C1 (or 1.2V precision

reference on parts so equipped)

bit 4 C2RSEL: Comparator C2 Refe rence Select bit

1 = CVREF routed to C2VREF input of Comparator C2

0 = Absolute voltage reference (0.6) routed to C2VREF input of Comparator C2 (or 1.2V precision

reference on parts so equipped)

bit 3-2 Unimplemented: Read as ‘0’

bit 1 T1GSS: Timer1 Gate Source Select bit

1 = Timer1 gate source is T1G

0 = Timer1 gate source is SYNCC2OUT.

bit 0 C2SYNC: Comparator C2 Output Synchronization bit

1 = Output is synchronous to falling edge of Timer1 clock

0 = Output is asynchronous

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8.9 Comparator SR Latch

The SR latch module provides additional control of the

comparator outputs. The module consists of a single

SR latch and output multiplexers. The SR latch can be

set, reset or toggled by the comparator outputs. The SR

latch may also be set or reset, independent of

comparator output, by control bit s in the SRCON control

whether the latch output s or the com p arator output s are

directed to the I/O port log ic for ev entual outpu t to a pin.

8.9.1 LATCH OPERATION

The latch is a Set-Reset latch that does not depend o n a

clock source. Each of the Set and Reset inputs are

active-high. Each latch input is connected to a

comparator output and a software controlled pulse

generator . The latch can be set by C1OUT or the PULSS

bit of the SRCON register. The latch can be reset by

C2OUT or the PULSR bit of the SRCON register. The

latch is reset-dominant, therefore, if both Set and Reset

inputs are high the latch will go to the Reset state. Both

the PULSS and PULSR bits are self resetting which

means that a single write to either of the bits is all that is

necessary to compl e te a latch se t or Reset op eration.

8.9.2 LATCH OUTPUT

The SR<1:0> bits of the SRCON register control the

latch output multiplexers and determine four possible

output configurations. In these four configurations, the

CxOUT I/O port logic is connected to:

• C1OUT and C2OUT

• C1OUT an d SR latch Q

• C2OUT an d SR latch Q

• SR latch Q and Q

After any Reset, the default output configuration is the

unlatched C1OUT and C2OUT mode. This maintains

compatibility with devices that do not have the SR latch

feature.

The applicable TRIS bits of the corresponding ports

must be cleared to enable the port pin output drivers.

Additionally, the CxOE comparator output enable bits of

the CMxCON0 registers must be set in order to make the

comparator or latch output s available on the output pins.

The latch configuration enable states are completely

independent of the enable states for the comparators.

FIGURE 8-7: SR LATCH SIMPLIFIED BLOCK DIAGRAM

C1SEN

SR0

PULSS

C2REN

PULSR SR1

Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q =1

2: Pulse generator causes a 1/2 Q-state (1 Tosc ) pulse width.

3: Output shown for reference only. See I/O port pin block diagram for more detail.

Pulse

Gen(2)

Pulse

Gen(2)

SYNCC2OUT (from comparator)

C1OUT (from comparator)

C2OE

C2OUT pin(3)

C1OE

C1OUT pin(3)

MUX

Latch(1)

PIC16F882/883/884/886/887

R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 R/W-0

SR1(2) SR0(2) C1SEN C2REN PULSS PULSR — FVREN

bit 7 bit 0

Legend: S = Bit is set only -

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SR1: SR Latch Configuration bit(2)

1 = C2OUT pin is the latch Q output

0 = C2OUT pin is the C2 comparator output

bit 6 SR0: SR Latch Configuration bits(2)

1 = C1OUT pin is the latch Q output

0 = C1OUT pin is the C1 Comparator output

bit 5 C1SEN: C1 Set Enable bit

1 = C1 comparator output sets SR latch

0 = C1 comparator output has no effect on SR latch

bit 4 C2REN: C2 Reset Enable bit

1 = C2 comparator output resets SR latch

0 = C2 comparator output has no effect on SR latch

bit 3 PULSS: Pulse the SET Input of the SR Latch bit

1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.

0 = Does not trigger pulse generator

bit 2 PULSR: Pulse the Reset Input of the SR Latch bit

1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.

0 = Does not trigger pulse generator

bit 1 Unimplemented: Read as ‘0’

bit 0 FVREN: Fixed Voltage Reference Enable bit

1 = 0.6V Reference FROM INTOSC LDO is enabled

0 = 0.6V Reference FROM INTOSC LDO is disabled

Note 1: The CxOUT bit in the CMxCON0 register will always reflect the actual c omp arator output (not the lev el on

the pin), regardless of the SR latch operation.

2: To enable an SR Latch output to the pin, the appropriate CxOE and TRIS bits must be properly

configured.

PIC16F882/883/884/886/887

8.10 Comparator Voltage Reference

The comparator voltage reference module pr ovides an

internally generated voltage reference for the compara-

tors. The following features are available:

• Independent from Comparator operation

• Two 16-level voltage ranges

• Output clamped to VSS

• Ratiometric with VDD

• Fix ed Reference (0.6 V)

The VRCON register (Register 8-5) controls the

voltage reference module shown in Figure 8-8.

The voltage source is selectable through both ends of

the 16 co nne ction resis tor l add er ne tw ork. Bit VRSS of

the VRCON register selects either the internal or

external voltage source.

The PIC16F882/883/884/886/887 allows the CVREF

signal to be output to the RA2 pin of PORTA under

certain configurations only. For more details, see

Figure 8-9.

8.10.1 INDEPENDENT OPERATION

The comparator voltage reference is independent of

the comparator configuration. Setting the VREN bit of

the VRCON register will enable the voltage reference.

8.10.2 OUTPUT VOLTAGE SELECTION

The CVREF voltage reference has 2 ranges with 16

voltage levels in each range. Range selection is

controlled by the VRR bit of the VRCON register. The

16 levels are set with the VR<3:0> bits of the VRCON

The CVREF output voltage is determined by the following

equations:

EQUATION 8-1: CVREF OUTPUT VOLTAGE

The full range of VSS to VDD cannot be realized due to

the construction of the module. See Figure 8-8.

8.10.3 OUTPUT CLAMPED TO VSS

The CVREF output voltage can be set to Vss with no

power consumption by clearing the FVREN bit of the

VRCON register.

This allows the comparator to detect a zero-crossing

while not consuming additional CVREF module current.

8.10.4 OUTPUT RATIOMETRIC TO VDD

The comparator voltage reference is VDD derived and

therefore, the CVREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Comparator

Voltage Reference can be found in Section 17.0

“Electrical Specifications”.

8.10.5 FIXED VOLTAGE REFERENCE

The fixed volta ge reference is ind ependent of VDD, with

a nomina l output volt age of 0.6V. This reference can be

enabled by setting the FVREN bit of the SRCON

the HFINTOSC oscillator is active.

8.10.6 FIXED VOLTAGE REFERENCE

STABILIZATION PERIOD

When the fixe d vol tage refe re nce mo dul e is enabled , it

will require some time for the reference and its amplifier

circuits to stabilize. The user program must include a

small delay routine to allow the module to settle. See

Section 17.0 “Electrical Specifications” for the

minimum delay requirement.

8.10.7 VOLTAGE REFERENCE

SELECTION

Multiplexers on the output of the voltage reference

module enable selection of either the CVREF or fixed

voltage reference for use by the comparators.

Setting the C1RSEL bit of the CM2CON1 register

enables current to flow in the CVREF voltage divider

and selects the CVREF volta ge f or us e b y C1 . C l ear i ng

the C1RSEL b it sel ect s the fixed volt age for use b y C1.

Setting the C2RSEL bit of the CM2CON1 register

enables current to flow in the CVREF voltage divider

and selects the CVREF volta ge f or us e b y C2 . C l ear i ng

the C2RSEL b it sel ect s the fixed volt age for use b y C2.

When bo th the C1RSEL an d C2RSEL bits a r e cle are d,

current flow in the CVREF voltage divider is disabled

minimizing the power drain of the voltage reference

peripheral.

VRR 1 (low range):=

VRR 0 (high range):=

CVREF (VLADDER/4) + =

CVREF (VR<3:0>/24) VLADDER×=

(VR<3:0> VLADDER/32)×

VLADDER VDD=or ([VREF+] - [VREF-]) or VREF+

Note: Depending on the application, additional

components may be required for a zero

cross circuit. Reference TB3013, “Using

the ESD Parasiti c Dio des on Mix ed Signa l

Microcontrollers” (DS93013), for more

information.

PIC16F882/883/884/886/887

FIGURE 8-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

FIGURE 8-9: COMPARATOR AND ADC VOLTAGE REFERENCE BLOCK DIAGRAM

VRR

VR<3:0>

Analog

8RRR RR

16 Stages

MUX

Fixed Voltage

VREN

CVREF

Reference

FVREN

Sleep

HFINTOSC enable

0.6V

FixedRef

To Comparators

and ADC Module

To Comparators

and ADC Module

VREF+

VDD

VRSS = 0

VRSS = 1

VREF-

VRSS = 0

VRSS = 1

CVREF

VROE

C1RSEL

C2RSEL

VREF+

VCFG0

AVDD

VREF-

VCFG1

AVSS

VROE

VCFG1

CVREF

Comparator ADC

AVDD

AVSS

Voltage

Reference Voltage

Reference

VRSS

PIC16F882/883/884/886/887

TABLE 8-2: COMPARATOR AND ADC VOLTAGE REFERENCE PRIORITY

RA3 RA2 Comp.

Reference (+) Comp.

Reference (-) ADC

Reference (+) ADC

Reference (-) CFG1 CFG0 VRSS VROE

I/O I/O AVDD AVSS AVDD AVSS 0000

I/O CVREF AVDD AVSS AVDD AVSS 0001

VREF+VREF-VREF+VREF-AVDD AVSS 0010

VREF+CVREF VREF+AVSS AVDD AVSS 0011

VREF+I/O AVDD AVSS VREF+AVSS 0100

VREF+CVREF AVDD AVSS VREF+AVSS 0101

VREF+VREF-VREF+VREF-VREF+AVSS 0110

VREF+CVREF VREF+AVSS VREF+AVSS 0111

I/O VREF-AVDD AVSS AVDD VREF-1000

I/O VREF-AVDD AVSS AVDD VREF-1001

VREF+VREF-VREF+VREF-AVDD VREF-1010

VREF+VREF-VREF+VREF-AVDDVREF-1011

VREF+VREF-AVDD AVSS VREF+VREF-1100

VREF+VREF-AVDD AVSS VREF+VREF-1101

VREF+VREF-VREF+VREF-VREF+VREF-1110

VREF+VREF-VREF+VREF-VREF+VREF-1111

PIC16F882/883/884/886/887

T ABLE 8-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE

REFERENCE MODULES

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

VREN VROE VRR VRSS VR3 VR2 VR1 VR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 VREN: Comparator C1 Voltage Reference Enable bit

1 =CV

REF circuit powered on

0 =CV

REF circuit powered down

bit 6 VROE: Comparator C2 Voltage Reference Enable bit

1 =CV

REF voltage level is also output on the RA2/AN2/VREF-/CVREF/C2IN+ pin

0 =CV

REF voltage is disconnected from the RA2/AN2/VREF-/CVREF/C2IN+ pin

bit 5 VRR: CVREF Range Selection bit

1 = Low range

0 = High range

bit 4 VRSS: Comparator VREF Range Selection bit

1 = Comparato r Reference Source, C VRSRC = (VREF+) - (VREF-)

0 = Comparato r Reference Source, C VRSRC = VDD - VSS

bit 3-0 VR<3:0>: CVREF Value Selection 0 ≤ VR<3:0> ≤ 15

When VRR = 1: CVREF = (VR<3:0> /24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR<3:0> /32) * VDD

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

ANSELH — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 --11 1111

CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000

CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000

CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL —— T1GSS C2SYNC 0000 --10 0000 --10

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE —CCP2IE 0000 00-0 0000 00-0

PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF —CCP2IF 0000 00-0 0000 00-0

PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

SRCON SR1 SR0 C1SEN C2SEN PULSS PULSR —FVREN 0000 00-0 0000 00-0

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator.

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

9.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESL and ADRESH).

The ADC voltage reference is software selectable to be

either internally gene rated or externally s upplied.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt ca n be used to wake-up the

device from Sleep.

Figure 9-1 shows the block diagram of the ADC.

FIGURE 9-1: ADC BLOCK DIAGRAM

AN0

AN1

AN2

AN4

AVDD

VREF+

ADON

GO/DONE

VCFG0 = 1

VCFG0 = 0

CHS<3:0>

VSS

AN5

AN6

AN7

AN3

AN8

AN9

AN10

AN11

AN12

AN13

AVSS

VREF-VCFG1 = 1

VCFG1 = 0

CVREF

FixedRef

0000

0001

0010

0011

0100

0101

0111

0110

1000

1001

1010

1011

1100

1101

1110

1111

ADRESH ADRESL

ADFM 0 = Le ft Ju stify

1 = Right Justify

ADC

PIC16F882/883/884/886/887

9.1 ADC Configuration

When configuring and using the ADC the following

functio ns must be considere d:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conv ersion clock sour ce

• Interrupt control

• Results formatting

9.1.1 PORT CONFIGURATION

The ADC can be used to convert both analog and digital

signals. When converting analog signals, the I/O pin

should be configured for analog by setting the associated

TRIS and ANSEL bits. See the corresponding Port

section for more information.

9.1.2 CHANNEL SELECTION

The CHS bits of the ADCON0 r egister det ermine whic h

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 9.2

“ADC Operation” for more information.

9.1.3 ADC VOLTAGE REFERENCE

The VCFG bits of the ADCON0 register provide

independent control of the positive and negative

voltage re ferences. The positive voltage reference can

be either VDD or an external voltage source. Likewise,

the negativ e vo ltage referen ce ca n be ei ther V SS or an

external voltage source.

9.1.4 CONVERSION CLOCK

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON0 register. There

are four possible clock options:

•F

OSC/2

•FOSC/8

•F

OSC/32

•FRC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 1 0-b it c on ve rsion require s 11 TAD periods

as shown in Figure 9-2.

For correct conversion, the appropriate TAD specificatio n

must be met. See A/D conversion requirements in

Section 17.0 “Electrical Specifications” for more

information. Table 9-1 gives examples of appropriate

ADC clock selections.

Note: Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

Note: Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

PIC16F882/883/884/886/887

TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)

FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

9.1.5 INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC interrupt flag is th e ADIF bit in the

PIR1 reg ister. The ADC inte rrupt en able i s the ADIE bit

in the PIE1 register. The ADIF bit must be cleared in

software.

This interrupt can be generated while the device is

operatin g or while in Sle ep. If the device is in Sle ep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruc tio n is always executed. If the user is attem ptin g

to wake-up from Sleep and resume in-line code

execution, the global interrupt must be disabled. If the

global interrupt is enabled, execution will switch to the

Interr u pt Service Routine.

Please see Section 14.3 “Interrupts” for more

information.

ADC Clock Period (TAD) Device Freque ncy (FOSC)

ADC Clock Source ADCS<1:0> 20 MHz 8 MHz 4 MHz 1 MHz

FOSC/2 00 100 ns(2) 250 ns(2) 500 ns(2) 2.0 μs

FOSC/8 01 400 ns(2) 1.0 μs(2) 2.0 μs8.0 μs(3)

FOSC/32 10 1.6 μs4.0 μs8.0 μs(3) 32.0 μs(3)

FRC 11 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be perf ormed during S leep.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9

Set GO/DONE bit

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

b9 b8 b7 b6 b5 b4 b3 b2

TAD10 TAD11

b1 b0

TCY to TAD

Conversion Starts

ADRESH and ADRESL registers are loaded,

GO bit is cleared,

ADIF bit is set,

Holding capacitor is connected to analog input

Note: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

PIC16F882/883/884/886/887

9.1.6 RESULT FORMATTING

The 10-bit A/D conversion res ult can be supplied in two

formats, left justified or right justified. The ADFM bit of

the ADCON0 register controls the output format.

Figure 9-3 shows the two output formats.

FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT

9.2 ADC Operation

9.2.1 STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

9.2.2 COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF flag bit

• Update the AD RESH:ADRESL reg isters with new

conversion result

9.2.3 TERMINATING A CONVERSION

If a co nver sion must b e term ina ted be fore comp leti on,

the GO/DONE bit can be cleared in software. The

ADRESH:ADRESL registers will not be updated with

the partially complete Analog-to-Digital conversion

sample. Instead, the ADRESH:ADRESL register pair

will retain the value of the previous conversion. Addi-

tionall y, a 2 TAD delay is required before ano ther acqui-

sition can be initiated. Following this delay, an input

acquisition is automatically started on the selected

channel.

9.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC wa its on e addition al instru ction bef ore sta rting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

9.2.5 SPECIAL EVEN T TRIGGER

The E CCP Spec ial Ev ent Trigg er allow s peri odic A DC

measurements without software intervention. When

this trigger occurs, the GO/DONE bit is set by hardware

and the Timer1 counter resets to zero.

Using the S pecial Event T rigger does not assure proper

ADC timi ng. I t is the user’s resp onsib ility t o ensu re that

the ADC timing requirements are met.

See Section 11.0 “Capture/Compare/PWM Modules

(CCP1 and CCP2)” for more information.

ADRESH ADRESL

(ADFM = 0)MSB LSB

bit 7 bit 0 bit 7 bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1)MSB LSB

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit A/D Result

Note: The GO/DONE bit shou ld not be se t in the

same instruction that turns on the ADC.

Refer to Section 9.2.6 “A/D Conversion

Procedure”.

Note: A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

PIC16F882/883/884/886/887

9.2.6 A/D CONVERSION PROCEDURE

This is an example procedure for using the ADC to

perform an Analog-to-Digit al conve rsion:

1. Conf igure Port:

• Disable pin output driver (See TRIS register)

• Configure pin as analog

2. Conf igure the ADC module:

• Select AD C conversion clock

• Configure voltage reference

• Select ADC input channel

• Select result format

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt(1)

4. Wait the required acquisition time(2).

5. Start conversion by setting the GO/DONE bit.

6. Wait f or ADC conv ers ion to com ple te by o ne of

the following:

• Po lli ng the GO/DONE bit

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result

8. Clear the AD C interrupt fl ag (required if interrupt

is enabled).

EXAMPLE 9-1: A/D CONVE RSI ON

Note 1: The global int errupt can be d isabl ed if th e

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: See Section 9.3 “A/D Acquisition

Requirements”.

;This code block configures the ADC

;for polling, Vdd and Vss as reference, Frc

clock and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

BANKSEL ADCON1 ;

MOVLW B’10000000’ ;right justify

MOVWF ADCON1 ;Vdd and Vss as Vref

BANKSEL TRISA ;

BSF TRISA,0 ;Set RA0 to input

BANKSEL ANSEL ;

BSF ANSEL,0 ;Set RA0 to analog

BANKSEL ADCON0 ;

MOVLW B’11000001’ ;ADC Frc clock,

MOVWF ADCON0 ;AN0, On

CALL SampleTime ;Acquisiton delay

BSF ADCON0,GO ;Start conversion

BTFSC ADCON0,GO ;Is conversion done?

GOTO $-1 ;No, test again

BANKSEL ADRESH ;

MOVF ADRESH,W ;Read upper 2 bits

MOVWF RESULTHI ;store in GPR space

BANKSEL ADRESL ;

MOVF ADRESL,W ;Read lower 8 bits

MOVWF RESULTLO ;Store in GPR space

PIC16F882/883/884/886/887

9.2.7 ADC REGISTER DEFINITIONS

The following registers are used to control the opera-

tion of the ADC.

Note: For ANSEL and ANSELH registers, see

Regist er 3-3 and Regis ter 3-4, resp ectively.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits

00 = FOSC/2

01 = FOSC/8

10 = FOSC/32

11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)

bit 5-2 CHS<3:0>: Analog Channel Select bits

0000 = AN0

0001 = AN1

0010 = AN2

0011 = AN3

0100 = AN4

0101 = AN5

0110 = AN6

0111 = AN7

1000 = AN8

1001 = AN9

1010 = AN10

1011 = AN11

1100 = AN12

1101 = AN13

1110 = CVREF

1111 = Fixed Ref (0.6V fixed voltage reference)

bit 1 GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0 = A/D conversion completed/not in progress

bit 0 ADON: ADC Enable bit

1 = ADC is enabled

0 = ADC is disabled and consumes no operating current

PIC16F882/883/884/886/887

R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

ADFM —VCFG1VCFG0— — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Conversion Result Format Select bit

1 = Right justif ied

0 = Left justi fied

bit 6 Unimplemented: Read as ‘0’

bit 5 VCFG1: Voltage Reference bit

1 = V REF- pin

0 = VSS

bit 4 VCFG0: Voltage Reference bit

1 = V REF+ pin

0 = VDD

bit 3-0 Unimplemented: Read as ‘0’

PIC16F882/883/884/886/887

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2

bit 7 bit 0

Legend:

R = Readable bit W = Writ able bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ADRES1 ADRES0 — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writ able bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 ADRES<1:0>: ADC Result Register bits

Lower 2 bits of 10-bit conversion result

bit 5-0 Reserved: Do not use.

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — — — — — ADRES9 ADRES8

bit 7 bit 0

Legend:

R = Readable bit W = Writ able bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Reserved: Do not use.

bit 1-0 ADRES<9:8>: ADC Result Register bits

Upper 2 bits of 10-bit conversion result

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0

bit 7 bit 0

Legend:

R = Readable bit W = Writ able bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES<7:0>: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

PIC16F882/883/884/886/887

9.3 A/D Acquisition Requirements

For the A DC t o meet i ts specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 9-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 9-4.

The maximum recommended impedance for analog

sources is 10 kΩ. As the source impedance is

decreased, the acquisition time may be decreased.

After the analog input channel is selected (or changed),

an A/D acquisition must be done before the conversion

can be started. To calculate the minimum acquisition

time, Equation 9-1 may be used. This equation

assumes that 1/2 LSb error is used (1024 steps for the

ADC). The 1/2 LSb erro r is the maximum er ror allow ed

for the ADC to meet its specified resolution.

EQUATION 9-1: ACQUISITION TIME EXAMPLE

TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient++=

TAMP TCTCOFF++=

2µs TCTemperature - 25°C()0.05µs/°C()[]++=

TCCHOLD RIC RSS RS++() ln(1/2047)–=

10pF 1k

10k

++()– ln(0.0004885)=

1.37

=µs

TACQ 2ΜS1.37ΜS50°C- 25°C()0.05ΜS/°C()[]++=

4.67ΜS=

VAPPLIED 1e

Tc–

---------

–

⎝⎠

⎜⎟

⎛⎞

VAPPLIED 11

2n1+

()1–

--------------------------–

⎝⎠

⎛⎞

VAPPLIED 11

2n1+

()1–

--------------------------–

⎝⎠

⎛⎞

VCHOLD=

VAPPLIED 1e

TC–

----------

–

⎝⎠

⎜⎟

⎛⎞

VCHOLD=

;[1] VCHOLD charged to within 1/2 lsb

;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]

The value for TC can be approximated with the following equations:

Solving for TC:

Therefore:

Temperature 50°C and external impedance of 10k

5.0V VDD=

Assumptions:

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

PIC16F882/883/884/886/887

FIGURE 9-4: ANALOG INPUT MODEL

FIGURE 9-5: ADC TRANSFER FUNCTION

CPIN

Rs ANx

5 pF

VDD

VT = 0.6V

VT = 0.6V I LEAKAGE(1)

RIC ≤ 1k

Sampling

Switch

SS Rss

CHOLD = 10 pF

VSS/VREF-

Sampling Switch

567891011

(kΩ)

VDD

± 500 nA

Legend: CPIN

I LEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

various junctions

RSS

Note 1: See Section 17.0 “Electrical Specifications”.

3FFh

3FEh

ADC Output Code

3FDh

3FCh

004h

003h

002h

001h

000h

Full-Scale

3FBh

1 LSB ideal

VSS/VREF-Zero-Scale

Transition VDD/VREF+

Transition

1 LSB ideal

Full-Scale Range

Analog Input Voltage

PIC16F882/883/884/886/887

TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Va lue on

all other

Resets

ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000

ADCON1 ADFM —VCFG1VCFG0— — — — 0-00 ---- -000 ----

ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

ANSELH —— ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 --11 1111

ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu

ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 —ADIERCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIR1 —ADIFRCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

PORTE ————RE3 RE2 RE1 RE0 ---- xxxx ---- uuuu

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 111

TRISE ———— TRISE3 TRISE2 TRISE1 TRISE0 ---- 1111 ---- 111

Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

10.0 DAT A EEPROM AND FLASH

PROGRAM MEMORY

CONTROL

The Data EEPROM and Flash program memory are

readable and w ritab le durin g no rmal op eration ( full VDD

range). Th ese memorie s are not di rectly m apped in the

addressed through the Special Function Registers

(SFRs). There are six SFRs used to access these

memories:

• EECON1

• EECON2

• EEDAT

•EEDATH

• EEADR

• EEADRH (bit 4 on PIC16F886/PIC16F887 only)

When interfacing the data memory block, EEDA T holds

the 8-bit data for read/write, and EEADR holds the

address o f the EEDAT loca tio n being ac ce ss ed . These

devices have 256 bytes of data EEPROM with an

address range from 0h to 0FFh.

When accessing the program memory block of the

PIC16F886/PIC16F887 devices, the EEDAT and

EEDATH registers form a 2-byte word that holds the

14-bit data for read/write, and the EEADR and

EEADRH registers form a 2-byte word that holds the

12-bit address of the EEPROM location being read.

The PIC16F882 devices have 2K words of program

EEPROM with an address range from 0h to 07FFh.

The PIC16 F88 3/PIC16F884 devi ces hav e 4K words of

program EEPROM with an address range from 0h to

0FFFh. The program memory allows one-word reads.

The EEPROM dat a memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write).

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge p ump rated to op erate over the v oltage ran ge of

the device for byte or word operations.

Depending on the setting of the Flash Program

Memory Self Write Enable bits WRT<1:0> of the

Configuration Word Register 2, the device may or may

not be able to write certain blocks of the program

memory. However, reads from the program memory

are allowed.

When the device is code-protected, the CPU may

continue to read and write the data EEPROM memory

and Flas h program memory. When code-prote cted, the

device programmer can no longer access data or

program memory .

10.1 EEADR and EEADRH Registers

The EEADR and EEADRH registers can address up to

a maximum of 256 bytes of data EEPROM or up to a

maximum of 8K words of program EEPROM.

When selecting a program address value, the MSB of

the address is written to the EEADRH register and the

LSB is w ritten to t he EEADR register. When sele cting a

data address value, only the LSB of the address is

written to the EEADR register.

10.1.1 EECON1 AND EECON2 REGISTERS

EECON1 is the control register for EE memory

accesses.

Control bit EEPGD determines if the access will be a pro-

gram or data memory access. When cle ar, as it is when

reset, any subsequent operations will operate on the data

memory . When set, any subsequent operations will oper-

ate on the program me mory. Progra m memory ca n only

be read.

Control bits RD and WR initiate read and write,

resp ec ti v el y. Thes e bi ts cann o t be clea r e d, on l y s et , in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, w ill all ow a write op eratio n to

data EEPROM. On power-up, the WREN bit is clear.

The WRERR bit is set when a write operation is

interrupted by a MCLR or a WDT Time-out Reset

during normal operation. In these situations , following

Reset, the user can check the WRERR bit and rewrite

the location.

Interrupt flag bit EEIF of the PIR2 register is set when

write is complete. It must be cleared in the software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

PIC16F882/883/884/886/887

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EEDAT<7:0>: 8 Least Significant A ddress bit s to Wr ite to or R ead from dat a EEPROM or Read fr om program memory

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EEADR<7:0>: 8 Least Significant Address bits for EEPROM Read/Write Operation(1) or Read from program memory

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 U nimplemented: Read as ‘0’

bit 5-0 EEDATH<5:0>: 6 Most Significant Data bits from program memory

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — EEADRH4(1) EEADRH3 EEADRH2 EEADRH1 EEADRH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 U nimplemented: Read as ‘0’

bit 4-0 EEADRH<4:0>: Specifies the 4 Most Significant Address bits or high bits for program memory reads

Note 1: PIC16F886/P IC16F887 only.

PIC16F882/883/884/886/887

R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD — — — WRERR WREN WR RD

bit 7 bit 0

Legend:

S = Bit can only be set

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Program/Dat a EEPROM Selec t bit

1 = Accesses program memory

0 = Accesses data memory

bit 6-4 Unimplemented: Read as ‘0’

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOR Reset)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a wri te cy cle (T he bit is cle ared by hardwa re onc e wri te is comp let e. The WR bit ca n only

be set, not cleared, in software.)

0 = Write cycle to the data EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in

software.)

0 = Does not initiate a memory read

PIC16F882/883/884/886/887

10.1.2 READING THE DATA EEPROM

MEMORY

To read a data memory loca tion, the user must write the

address to the EEADR register, clear the EEPGD

control bit of the EECON1 register, and then set contro l

bit RD. The data is available at the very next cycle, in

the EEDA T register; therefore, it can be read in the next

instruction. EEDAT will hold this value until another

read or until it is written to by the user (during a write

operation).

EXAMPLE 10-1: DATA EEPROM READ

10.1.3 WRITING TO THE DATA EEPROM

MEMORY

To write an EEPROM data location, the user must first

wri te t he addr ess to the E EADR regi ster an d the data

to the EEDAT register. Then the user must follow a

specific sequence to initiate the write for each byte.

The write will not initiate if the above sequence is not

followed exactly (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. Interrupts

should be disabled during this code segment.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

After a write sequence has been initiated, clearing the

WREN bit wil l not af fect this wr ite cycle. T he WR bit wil l

be inhib ited from bei ng s et unless the W R EN bit is se t.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

EXAMPLE 10-2: DATA EEPROM WRITE

BANKSEL EEADR ;

MOVLW DATA_EE_ADDR ;

MOVWF EEADR ;Data Memory

;Address to read

BANKSEL EECON1 ;

BCF EECON1, EEPGD ;Point to DATA memory

BSF EECON1, RD ;EE Read

BANKSEL EEDAT ;

MOVF EEDAT, W ;W = EEDAT

BCF STATUS, RP1 ;Bank 0

BANKSEL EEADR ;

MOVLW DATA_EE_ADDR ;

MOVWF EEADR ;Data Memory Address to write

MOVLW DATA_EE_DATA ;

MOVWF EEDAT ;Data Memory Value to write

BANKSEL EECON1 ;

BCF EECON1, EEPGD ;Point to DATA memory

BSF EECON1, WREN ;Enable writes

BCF INTCON, GIE ;Disable INTs.

BTFSC INTCON, GIE ;SEE AN576

GOTO $-2

MOVLW 55h ;

MOVWF EECON2 ;Write 55h

MOVLW AAh ;

MOVWF EECON2 ;Write AAh

BSF EECON1, WR ;Set WR bit to begin write

BSF INTCON, GIE ;Enable INTs.

SLEEP ;Wait for interrupt to signal write complete

BCF EECON1, WREN ;Disable writes

BCF STATUS, RP0 ;Bank 0

BCF STATUS, RP1

Required

Sequence

PIC16F882/883/884/886/887

10.1.4 READING THE FLASH PROGRAM

MEMORY

To read a program memory location, the user must

write the Least an d Most Si gnific ant add ress bit s to the

EEADR and EEADRH registers, set the EEPGD con-

trol bit of th e EEC ON 1 reg ist er, and then set c ont rol b it

RD. Once the read cont rol bit is set, the program mem-

ory Flash controller will use the second instruction

cycle to read th e data. This caus es the second ins t ru c-

tion immediately following the “BSF EECON1,RD”

instruction to be ignored. The data is available in the

very ne xt cycle, in the EEDAT and EED ATH reg ister s;

therefore, it can be read as two bytes in the following

instructions.

EEDAT and EEDATH registers will hold this value until

another read or until it is written to by the user.

EXAMPLE 10-3: FLASH PROGRAM READ

Note 1: The two instructions following a program

memory read are required to be NOPs.

This prevents the user from executing a

two-cycle instruction on the next

instruction after the RD bit is set.

2: If the WR bit is set when EEPGD = 1, it

will be immediately reset to ‘0’ and no

operation will take place.

BANKSEL EEADR ;

MOVLW MS_PROG_EE_ADDR ;

MOVWF EEADRH ;MS Byte of Program Address to read

MOVLW LS_PROG_EE_ADDR ;

MOVWF EEADR ;LS Byte of Program Address to read

BANKSEL EECON1 ;

BSF EECON1, EEPGD ;Point to PROGRAM memory

BSF EECON1, RD ;EE Read

;

;First instruction after BSF EECON1,RD executes normally

NOP

NOP ;Any instructions here are ignored as program

;memory is read in second cycle after BSF EECON1,RD

;BANKSEL EEDAT ;

MOVF EEDAT, W ;W = LS Byte of Program Memory

MOVWF LOWPMBYTE ;

MOVF EEDATH, W ;W = MS Byte of Program EEDAT

MOVWF HIGHPMBYTE ;

BCF STATUS, RP1 ;Bank 0

Required

Sequence

PIC16F882/883/884/886/887

FIGURE 10-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BSF EECON1,RD

execut ed her e INSTR(PC + 1)

executed here Forced NOP

execut ed her e

PC + 1 EEADRH,EEADR PC+3 PC + 5

Flash ADDR

RD bit

EEDATH,EEDAT

PC + 3 PC + 4

INSTR (PC + 1)

INSTR(PC - 1)

executed here INSTR(PC + 3)

executed here INSTR(PC + 4)

executed here

Flas h Data

EEDATH

EEDAT

EERHLT

INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)

PIC16F882/883/884/886/887

10.2 Writing to Flash Program Memory

Flash program memory may only be written to if the

desti nati on addr ess i s in a se gment of me mory th at is

not write -protec ted, as d efined i n bit s WR T<1: 0> of the

Config uration Wo rd Register 2. Fl ash program memo ry

must be written in eight-word blocks (four-word blocks

for 4K memory devices). See Figures 10-2 and 10-3 for

more details. A block consists of eight words with

sequential addresses, with a lower boundary defined

by an address, where EEADR<2:0> = 000. All block

writes to program memory are done as 16-word erase

by eight-word write operations. The write operation is

edge-aligned and cannot occur across boundaries.

To write program data, it must first be loaded into the

buff er registers (see Figure 10-2). This is accomplished

by first writing the destination address to EEADR and

EEADRH and then writing the data to EEDATA and

EEDATH. Af ter the address and data h ave been set u p,

then the following sequence of events must be

executed:

1. Set the EEPGD control bit of the EECON1

2. Write 55h, then AAh, to EECON2 (Flash

program ming sequence ).

3. Set the WR contr ol bit of the EECON1 register.

All eight buffer register locations should be written to

with correct dat a. If less than eight words are being writ-

ten to in the block of eight words, then a read from the

program memory location(s) not being written to must

be performed. This takes the data from the program

location(s) not being written and loads it into the

EEDAT A and EEDA TH reg isters. Then th e sequence of

events to transfer data to the buffer registers must be

executed.

To transfer data from the buffer registers to the program

memory , the EEADR and EEADRH must point to the last

location in the eight-word block (EEADR<2:0> = 111).

Then the following sequence of events must be

executed:

1. Set the EEPGD control bit of the EECON1

2. Write 55h, then AAh, to EECON2 (Flash

program ming sequence ).

3. Set control bit WR of the EECON1 register to

begin the write operation.

The user must follow the same specific sequence to

initiate the write for each word in the program block,

writing each program word in sequence (000, 001,

010, 011, 100, 101, 110, 111). When the write is

performed on the last word (EEADR<2:0> = 111), a

bloc k of s ix t ee n wor ds i s au t om ati ca l ly er ase d an d the

content of the eight word buffer registers are written

into the program memory.

After th e “BSF EECON1,WR” instruction, the processor

requires tw o c ycles to se t up the era se /w rite op era t io n.

The user must p lac e tw o NOP i nst ructions af ter the WR

bit is set. Sinc e dat a is being written to buf fe r registers,

the writing of the first seven words of the block appears

to occur immediately. The processor will halt internal

operat io ns for the typi ca l 4 ms, only during the cy cl e in

which the erase takes place (i.e., the last word of the

sixteen-word block erase). This is not Sleep mode as

the cloc ks and perip herals will co ntinue to run. Af ter the

eight-w ord w rite cy cl e, th e processor wi ll resume op er-

ation with the third instruction after the EECON1 write

instruction. The above sequence must be repeated for

the higher eight words.

PIC16F882/883/884/886/887

FIGURE 10-2: BLOCK WRITES TO 2K AND 4K FLASH PROGRAM MEMORY

FIGURE 10-3: BLOCK WRITES TO 8K FLASH PROGRAM MEMORY

14 14 14 14

Program Memory

Buffer Register

EEADR<1 :0 > = 00

Buffer Register

EEADR<1:0> = 01

Buffer Register

EEADR<1:0> = 10

Buffer Register

EEADR<1:0> = 11

EEDATAEEDATH

75 07 0

First word of block

to be written

Sixteen words of

to Flash

automatically

after this word

is wr itten

are transferred

Flash are eras ed,

then four buffers

14 14 14 14

Program Memory

Buffer Register

EEADR<2 :0 > = 000

Buffer Register

EEADR<2:0> = 001

Buffer Register

EEADR<2:0> = 010

Buffer Register

EEADR<2:0> = 111

EEDATAEEDATH

75 07 0

First word of block

to be written

Sixteen words of

to Flash

automatically

after this word

is wr itten

are transferred

Flash are eras ed,

then eight buffers

PIC16F882/883/884/886/887

An exampl e of the complete eight-w ord write sequenc e

is shown in Example 10-4. The initial address is loaded

into the EEADRH and EEADR register pair; the eight

words of data are loaded using indirect addressing.

EXAMPLE 10-4: WRITING TO FLASH PROGRAM MEMORY

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; This write routine assumes the following:

; A valid starting address (the least significant bits = '000')

; is loaded in ADDRH:ADDRL

; ADDRH, ADDRL and DATADDR are all located in data memory

;

BANKSEL EEADRH

MOVF ADDRH,W ; Load initial address

MOVWF EEADRH ;

MOVF ADDRL,W ;

MOVWF EEADR ;

MOVF DATAADDR,W ; Load initial data address

MOVWF FSR ;

LOOP MOVF INDF,W ; Load first data byte into lower

MOVWF EEDATA ;

INCF FSR,F ; Next byte

MOVF INDF,W ; Load second data byte into upper

MOVWF EEDATH ;

INCF FSR,F ;

BANKSEL EECON1

BSF EECON1,EEPGD ; Point to program memory

BSF EECON1,WREN ; Enable writes

BCF INTCON,GIE ; Disable interrupts (if using)

BTFSC INTCON,GIE ; See AN576

GOTO $-2

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Required Sequence

MOVLW 55h ; Start of required write sequence:

MOVWF EECON2 ; Write 55h

MOVLW 0AAh ;

MOVWF EECON2 ; Write 0AAh

BSF EECON1,WR ; Set WR bit to begin write

NOP ; Required to transfer data to the buffer

NOP ; registers

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

BCF EECON1,WREN ; Disable writes

BSF INTCON,GIE ; Enable interrupts (comment out if not using interrupts)

BANKSEL EEADR

MOVF EEADR, W

INCF EEADR,F ; Increment address

ANDLW 0x0F ; Indicates when sixteen words have been programmed

SUBLW 0x0F ; 0x0F = 16 words

; 0x0B = 12 words (PIC16F884/883/882 only)

; 0x07 = 8 words

; 0x03 = 4 words(PIC16F884/883/882 only)

BTFSS STATUS,Z ; Exit on a match,

GOTO LOOP ; Continue if more data needs to be written

PIC16F882/883/884/886/887

10.3 W rite Verify

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM should be verified ( see Exam ple 10-5) to the

des i red value to be written.

EXAMPLE 10- 5: WRITE VERI FY

10.3.1 USING THE DATA EEPROM

The data EEPROM is a high-endurance, byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated often).

When variables in one section change frequently, while

variables in another section do not change, it is possible

to exceed the total number of write cycles to the

EEPROM (specification D124) without exceeding the

total number of write cycles to a single byte

(specifications D120 and D120A). If this is the case,

then a refr esh of the array must be per form ed. F or th is

reason, variables that change infrequently (such as

constants, IDs, calibration, etc.) should be stored in

Flas h program me m ory.

10.4 Protection Against Spurious Writ e

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been buil t in. On power-u p, WREN is cleare d. Also, the

Power-up Timer (64 ms duration) prevents

EEPROM write.

The wri te in iti ate sequence an d the WR EN bi t tog eth er

help prevent an acciden tal write du ring:

• Brown-out

•Power Glitch

• Software Malfunction

10.5 Data EEPROM Operation During

Code-Protect

Data me mory can be co de-prot ected by program ming

the CPD bit in the Configuration Word Register 1

(Register 14-1) to ‘0’.

When the data memory is code-protected, only the

CPU is able to read and write data to the data

EEPROM. It is recommended to code-protect the pro-

gram memory when code-protecting data memory.

This prevents anyone from programming zeroes over

the exis ting c ode (whic h wi ll execu te as NOPs) to reach

an added routine, programmed in unused program

memory, which outputs the contents of data memory.

Programming unused locations in program memory to

‘0’ will also help prevent data memory code protection

from becom ing breached.

BANKSEL EEDAT ;

MOVF EEDAT, W ;EEDAT not changed

;from previous write

BANKSEL EECON1 ;

BSF EECON1, RD ;YES, Read the

;value written

BANKSEL EEDAT ;

XORWF EEDAT, W ;

BTFSS STATUS, Z ;Is data the same

GOTO WRITE_ERR ;No, handle error

: ;Yes, continue

BCF STATUS, RP1 ;Bank 0

PIC16F882/883/884/886/887

TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

Name Bit 7 B it 6 Bit 5 Bit 4 B i t 3 B it 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 0--- q000

EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----

EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

EEADRH — — — EEADRH4(1) EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---0 0000 ---0 0000

EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

EEDATH —— EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 0000 00-0 0000 00-0

PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 0000 00-0 0000 00-0

Legend: x = unknow n , u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by data EEPRO M module.

Note 1: PIC16F886/PIC16F887 only.

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

11.0 CAPTURE/COMP ARE/ PWM

MODULES (CCP1 AND CCP2)

This d evice con tai ns one Enh anced C apture/Com pare/

PWM (CCP1) and Capture/Compare/PWM module

(CCP2 ). The CC P1 and C CP2 m odule s are i dentic al in

operation, with the exception of the Enhanced PWM

features available on CCP1 only. See Section 11.6

“PWM (Enhanced Mode)” for more information.

Note: CCPRx and CCPx throughout this

document refer to CCPR1 or CCPR2 and

CCP1 or CCP2, respectively.

PIC16F882/883/884/886/887

11.1 Enhanced Capture/Comp are/ PWM

(CCP1)

The Enhanced Capture/Compare/PWM module is a

peripheral which allows the user to time and control

different events. In Capture mode, the peripheral

allows the timing of the duration of an event. The

Compare mode allows the user to trigger an external

event when a predetermined amount of time has

expired. The PWM mode can generate a Pulse-Width

Modulated signal of varying frequency and duty cycle.

Table 11-1 shows the timer resources required by the

ECCP module.

TABLE 11-1: ECCP MODE – TIMER

RESOURCES REQUIR ED

ECCP Mode Timer Resource

Capture Timer1

Compare Timer1

PWM Timer2

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 P1M<1:0>: PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:

xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins

If CCP1M<3 :2> = 11:

00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins

01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive

10 = Half-Bridge output; P1A, P1B modulated with dead-ban d control; P1C, P1D assigned as port pins

11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive

bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused.

Compare mode:

Unused.

PWM mo de:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0 CCP1M<3:0>: ECCP Mode Select bits

0000 = Capture/Compare/PWM off (resets ECCP module)

0001 = Unused (reserved)

0010 = Compare mode, toggle output on match (CCP1IF bit is set)

0011 = Unused (reserved)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, set output on match (CCP1IF bit is set)

1001 = Compare mode, clear output on mat ch (CC P1IF bit is set)

1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is

unaffected)

1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2

1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low

PIC16F882/883/884/886/887

11.2 Capture/Compare/PWM (CCP2)

The Capture/Compare/PWM module is a peripheral

which allows the user to time and control different

events. In Capture mode, the peripheral allows the

timing of the duration of an event. The Compare mode

allows the user to trigger an external event when a

predetermined amount of time has expired. The PWM

mode can generate a Pulse-Width Modulated signal of

varying frequency and duty cycle.

The timer resources used by the module are shown in

Table 11-2.

Additional information on CCP modules is available in

the Applic ation Not e AN594 , “Using the CCP M odule s”

(DS00594).

TABLE 11-2: CCP MODE – TIMER

RESOURCES REQUIR ED

CCP Mode Timer Resource

Capture Timer1

Compare Timer1

PWM Timer2

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DC2B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused.

Compare mode:

Unused.

PWM mo de:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR2L.

bit 3-0 CCP2M<3:0>: CCP2 Mode Select bits

0000 = Capture/Compare/PWM off (resets CCP2 module)

0001 = Unused (reserved)

0010 = Unused (reserved)

0011 = Unused (reserved)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, set output on match (CCP2IF bit is set)

1001 = Compare mode, clear output on match (CCP2IF bit is set)

1010 = Compare mode, generate software interrupt on match (CCP2IF bit is set, CCP2 pin

is unaffected)

1011 = Compare mode, trigger special event (CCP2IF bit is set, TMR1 is reset and A/D

conversion is started if the ADC module is enabled. CCP2 pin is unaffected.)

11xx = PWM mode.

PIC16F882/883/884/886/887

11.3 Capture Mode

In Capture mode, the CCPRxH, CCPRxL register pair

captures the 16-bi t value o f the TMR1 register w hen an

event occurs on pin CCPx. An event is defined as one

of the following and is configured by the CCP1M<3:0>

bits of the CCP1CON register:

• Every falling edge

• Every rising edge

• Ever y 4th rising edg e

• Every 16th rising edge

When a cap ture i s m ade, the I nterrupt Re quest Flag bit

CCPxIF of the PIRx register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPRxH, CCPRxL register pair

is read, the old captured value is overwritten by the new

captured value (see Figure 11-1).

11.3.1 CCP PIN CONFIGURATION

In Capture mode, the CCPx pin should be configured

as an input by setting the associated TRIS control bit.

FIGURE 11 -1: CAP TURE MODE

OPERATION BLOCK

DIAGRAM

11.3.2 TIMER1 MODE SELECTION

T imer1 must be running in T imer mode or Synchroni zed

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

11.3.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE inte rrupt enable bit of the PIEx regis ter clear to

avoid false interrupts. Additionally, the user should

clear the CCPxIF interrupt flag bit of the PIRx register

following any change in Operating mode.

11.3.4 CCP PRESCALER

There are four prescaler settings specified by the

CCPxM<3 :0> bits of the C CPxCON regis ter . Whenev er

the CCP module is turned off, or the CCP module is not

in Captu re mode, the presca ler count er is clea red. Any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCPxCON register before changing the

prescaler (see Example 11-1).

EXAMPLE 11-1: CHANGING BETWEEN

CAPTURE PRESCALERS

Note: If th e CCPx pin is c onfigu red as an o utput,

a write to the port can cause a capture

condition.

CCPRxH CCPRxL

TMR1H TMR1L

Set Flag bit CCPxIF

(PIRx register)

Capture

Enable

CCPxCON<3:0>

Prescaler

÷ 1, 4, 16

and

Edge Detect

CCPx

System Clock (FOSC)

BANKSEL CCP1CON ;Set Bank bits to point

;to CCP1CON

CLRF CCP1CON ;Turn CCP module off

MOVLW NEW_CAPT_PS;Load the W reg with

; the new prescaler

; move value and CCP ON

MOVWF CCP1CON ;Load CCP1CON with this

; value

PIC16F882/883/884/886/887

11.4 Compare Mode

In Compare mode, the 16-bit CCPRx register value is

constantly compared against the TMR1 register pair

value. When a match o ccurs, the C CPx module may :

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPx1CON register.

All Compare modes can generate an interrupt.

FIGURE 11 -2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

11.4.1 CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit.

11.4.2 TIMER1 MODE SELECTION

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

11.4.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the CCPx module does not

assert control of the CCPx pin (see the CCP1CON

11.4.4 SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen

(CCPxM<3:0> = 1011), the CCPx module does the

following:

• Resets Timer1

• Starts an ADC conversion if ADC is ena bled

The CCP x module does no t assert control of the C CPx

pin in this mode (see the CCPxCON register).

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPRxH, CCPRxL

reset until th e next r ising ed ge of the T imer1 clock. This

allows the CCPRxH, CCPRxL register pair to

effectively provide a 16-bit programmable period

Note: Clearing the CCP1CON register will force

the CCPx compare output latch to the

default lo w lev el. This is no t the PO R T I/O

data l atch.

CCPRxH CCPRxL

TMR1H TMR1L

Comparator

ROutput

Logic

Special Event Trigger

Set CCPxIF Interrupt Flag

(PIRx)

Match

TRIS

CCPxCON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

• Clear TMR1H and TMR1L registers.

• NOT set interrupt flag bit TMR1IF of the PIR1 register.

• Set the GO/DONE bit to start the ADC conversion.

CCPx 4

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMRxIF of the PIR1 register.

2: Removing the match condition by

changing the contents of the CCPRxH

and CCPRxL register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the T imer1 Reset, will p reclude

the Reset from occurring.

PIC16F882/883/884/886/887

11.5 PWM Mode

The PWM mode generates a Pulse-Width Modulated

signal on the CCPx pin. The duty cycle, period and

resolution are determined by the following registers:

•PR2

•T2CON

• CCPRxL

• CCPxCON

In Pulse-Width Modulation (PWM) mode, the CCP

module produce s up to a 10 -bit resol ution PWM outp ut

on the CCPx pin. Since the CCPx pin is multiplexed

with the POR T dat a latch, the TRIS for that pi n must be

cleared to enable the CCPx pin output driver.

Figure 11-3 shows a simplified block diagram of PWM

operation.

Figure 11-4 shows a typical waveform of the PWM

signal.

For a ste p-by-step proced ure on how t o set up the CCP

module for PWM operation, see Section 11.5.7

“Setup for PWM Operation”.

FIGURE 11-3: SIMPLIFIED PWM BLOCK

DIAGRAM

The PWM output (Figure 11-4) has a time base

(period) and a time that the output stays high (duty

cycle).

FIGURE 11-4: CCP PWM OUTPUT

Note: Clearing the CCPxCON register will

relinquish CCPx control of the CCPx pin.

CCPRxL

CCPRxH(2) (Slave)

Comparator

TMR2

PR2

(1)

Duty Cycle Registers CCPxCON<5:4>

Clear Timer2 ,

toggle CCPx pin and

latch duty cycle

Note 1: The 8-bit timer TMR2 register is concatenated

with the 2-bit internal system clock (FOSC), or

2 bits of the prescaler , to create the 10-bit time

base.

2: In PWM mode, CCPRxH is a read-only register.

TRIS

CCPx

Comparator

Period

Pulse Width

TMR2 = 0

TMR2 = CCPRxL:CCPxCON<5:4>

TMR2 = PR2

PIC16F882/883/884/886/887

11.5.1 PWM PERIOD

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 11-1.

EQUATION 11-1: PWM PERIOD

When TM R2 is equa l to PR2, t he followi ng three ev ents

occur on t he next inc rement cy cle:

• TMR 2 is cl eare d

• The CCPx pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

• The PW M duty c ycle is latc hed fro m CCPRx L int o

CCPRxH.

11.5.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit

value to multiple registers: CCPRxL register and

DCxB<1:0> bits of the CCPxCON register. The

CCPRxL contains the eight MSbs and the DCxB<1:0>

bits of the CCPxCON register contain the two LSbs.

CCPRxL and DCxB<1:0> bits of the CCPxCON

value is not latched into CCPRxH until after the period

completes (i.e., a match between PR2 and TMR2

registers occurs). While using the PWM, the CCPRxH

Equation 11-2 is used to calculate the PWM pulse

width.

Equation 11-3 is used to calculate the PWM duty cycle

ratio.

EQUATION 11-2: PULSE WIDTH

EQUATION 11-3: DUTY CYCLE RATIO

The CCPRxH register and a 2-bit internal latch are

used to dou ble buf fer th e PWM duty cycle. Thi s doubl e

buffering is essential for gl itchless PWM operation.

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or 2 bits of

the prescaler , to create the 10-bit time ba se. The system

clock is used if the Timer2 pres caler is s et to 1:1.

When the 10-bit time base matches the CCPRxH and

2-bit latch, then the CCPx pin is cleared (see

Figure 11-3).

Note: The Timer2 postscaler (see Section 7.1

“Timer2 Operation”) is not used in the

determination of the PWM frequency.

PWM Period PR2()1+[]4TOSC •••=

(TMR2 Prescale Value)

Note: TOSC = 1/FOSC

Pulse Width CCPRxL:CCPxCON<5:4>()

•

TOSC

•

(TMR2 Prescale Value)

Duty Cycle Ratio CCPRxL:CCPxCON<5:4>()

4PR2 1+()

-----------------------------------------------------------------------=

PIC16F882/883/884/886/887

11.5.3 PWM RESOLUTION

The r esolutio n determi nes th e number of avai lable dut y

cycles for a given period. For example, a 10-bit resolution

will r e sult in 10 24 di sc ret e d ut y c ycl es , wh er eas an 8- b it

resol uti on wi ll re su lt in 2 56 di s cre te du ty c ycl es .

The ma ximum P WM re solut ion i s 10 bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 11-4.

EQUATION 11-4: PWM RESOLUTION

TABLE 11-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

TABLE 11-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

Resolution 4PR2 1+()[]log

2()log

------------------------------------------ bits=

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09

Maximum Resolution (bits) 8 8 8 6 5 5

PIC16F882/883/884/886/887

11.5.4 OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment

and the state o f the mo dule will no t change. I f the CC Px

pin is dri ving a value , it wil l cont inue to d rive th at valu e.

When the device wakes up, TMR2 wil l continue from it s

previous state.

11.5.5 CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency. See

Section 4.0 “Oscillator Module (With Fail-Safe

Clock Monitor)” for ad ditiona l details.

11.5.6 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

11.5.7 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Disable the PWM pin (CCPx) output drivers as

an input by setting the associated TRIS bit.

2. Set the PWM period by loading the PR2 register .

3. Configure the CCP module for the PWM mode

by loading the CCPxCON register with the

appropriate values.

4. Set the PWM duty cycle by loading the CCPRxL

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the

PIR1 register.

• Set t he Timer2 presca le value by loading the

T2CKPS bits of the T2CON register.

• Enable Timer2 by setting the TMR2ON bit of

the T2CON register.

6. Enable PW M ou tput after a n ew PWM cyc le ha s

started:

• Wait until Timer2 overflows (TMR2IF bit of

the PIR1 register is set).

• En able the CCPx pin output d river by cleari ng

the associated TRIS bit.

PIC16F882/883/884/886/887

11.6 PWM (Enhanced Mode)

The Enhanced PWM Mode can generate a PWM signal

on up to four different output pins with up to 10-bits of

resolution. It can do this through four different PWM

output modes:

• Single PWM

• Half-Bridge PWM

• Full-Bridge PWM, Forward mode

• Full-Bridge PWM, Reverse mode

To select an Enhanced PWM mode, the P1M bits of the

CCP1CON register must be set appropriately.

The PWM outputs are multiplexed with I/O pins and are

designated P1A, P1B, P1C and P1D. The polarity of the

PWM pins is configurable and is selected by setting the

CCP1M bits in the CC P1CON register appropriately.

Table 11-5 shows the pin assignments for each

Enhanced PWM mode.

Figure 11-5 shows an example of a simplified block

diagram of the Enhanced PWM module .

FIGURE 11-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

TABLE 11-5: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES

Note: The PWM Enhanc ed mode is ava ilable on

the Enhanced Capture/Compare/PWM

module (CCP1) only.

Note: To prevent the generation of an

incomplete waveform when the PWM is

first enabl ed, the ECCP module w aits unti l

the start of a new PWM period before

generating a PWM signal.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(1)

Duty Cycle Registers DC1B<1:0>

Clear Timer2,

toggle PWM pin and

latch duty cycle

Note 1: The 8-b it ti m er TMR 2 re giste r is con cate na ted wi th the 2- bit interna l Q clock, or 2 bi ts of th e p res cal er to creat e t he 10- bi t

time base.

TRISn

CCP1/P1A

TRISn

P1B

TRISn

P1C

TRISn

P1D

Output

Controller

P1M<1:0> 2CCP1M<3:0>

PWM1CON

CCP1/P1A

P1B

P1C

P1D

Note 1: The TRIS register value for each PWM output must be configured appropriately.

2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins.

3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.

ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D

Single 00 Yes(1) Yes(1) Yes(1) Yes(1)

Half-Bridge 10 Yes Yes No No

Full-Bridg e, Forward 01 Yes Yes Yes Yes

Full-Bridg e, Reve rse 11 Yes Yes Yes Yes

Note 1: Pulse Steering enables outputs in Single mode.

PIC16F882/883/884/886/887

FIGURE 11 -6: E XAMP LE PW M (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH

STATE)

Period

Signal PR2+1

P1M<1:0>

P1A Modulated

P1B Modulated

P1A Active

P1B Inactive

P1C Inact ive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

P1D Inact ive

Pulse

Width

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay(1) Delay(1)

Relationships:

• Period = 4 * TOSC * (PR2 + 1) * (TM R2 Presca l e Value)

• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

• Delay = 4 * TOSC * (PWM1CON<6:0>)

Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.6.6 “Programmable Dead-Band Delay

Mode”).

PIC16F882/883/884/886/887

FIGURE 11 -7: EX AMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

Period

Signal PR2+1

P1M<1:0>

P1A Modulated

P1B Modulated

P1A Active

P1B Inactive

P1C Inact ive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

P1D Inact ive

Pulse

Width

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay(1) Delay(1)

Relationships:

• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

• Delay = 4 * TOSC * (PWM1CON<6:0>)

Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.6.6 “Programmable Dead-Band Delay

Mode”).

PIC16F882/883/884/886/887

11.6.1 HALF-BRIDGE MODE

In Half-Bridge mode, two pins are used as outputs to

drive push-p ull loa ds. The PW M outp ut sign al is output

on the CCPx/P1A pin, while the complementary PWM

output signal is output on the P1B pin (see Figure 1 1-9).

This mode can be used for Half-Bridge applications, as

shown in Figure 11-9, or for Full-Bridge applications,

where four power switches are being modulated with

two PWM signals.

In Half-Bridge mode, the programmable dead-band delay

can be used to prevent shoot-through current in Half-

Bridge power devices. The value of the PDC<6:0> bits of

the PWM1CON register sets the number of instruction

cycles before the output is driven active. If the value is

greater than the duty cycle, the corresponding output

remains inactive during the entire cycle. See

Section 11.6.6 “Programmable Dead-Band Delay

Mode” for more details of the dead-band delay

operations.

Since the P1A and P1B outputs are multiplexed with

the PORT data latches, the associated TRIS bits must

be cleared to configure P1A and P1B as outputs.

FIGURE 11-8: EXAMPLE OF HALF-

BRIDGE PWM OUTPUT

FIGURE 11 -9: EXAMP LE OF HALF-BRIDGE APPLICATIONS

Period

Pulse Width

(1)

P1A(2)

P1B(2)

td = Dead-B and Delay

Period

(1) (1)

Note 1: At this time, t he TM R2 register is equal to t he

PR2 register.

2: Output signals are shown as active-high.

P1A

P1B

FET

Driver

FET

Driver

Load

FET

Driver

FET

Driver

V+

Load

FET

Driver

FET

Driver

P1A

P1B

Standard Half-Bridge Circuit (“Push-P ull ”)

Half-Bridge Output Driving a Full-Bridge Circuit

PIC16F882/883/884/886/887

11.6.2 FULL-BRIDGE MODE

In Full-Bridge mode, all four pins are used as outputs.

An example of Full-Bridge application is shown in

Figure 11-10.

In the Forward mode, pin CCP1/P1A is driven to its active

state, p in P1 D is m odul ated, whil e P1B and P1C will be

driven to their inactive state as shown in Figure 11-11.

In the Reverse mode, P1C is driven to its active state,

pin P1B is modulated, while P1A and P1D wi l l be driv en

to th eir in ac t iv e s tate a s s h own Figure 11-11.

P1A, P1B, P1C and P1D outputs are multiplexed with

the POR T dat a latc hes. The a ssoc iated T RIS bit s mus t

be cleared to configure the P1A, P1B, P1C and P1D

pins as outputs.

FIGURE 11 -10: EXAMPL E OF FULL-BRIDGE APPLICAT ION

P1A

P1C

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

P1B

P1D

QB QD

PIC16F882/883/884/886/887

FIGURE 11-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT

Period

Pulse Width

P1A(2)

P1B(2)

P1C(2)

P1D(2)

Forw a r d M o de

(1)

Period

Pulse Width

P1A(2)

P1C(2)

P1D(2)

P1B(2)

Reverse Mode

(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.

2: Output signal is shown as active-high.

PIC16F882/883/884/886/887

11.6.2.1 Direction Change in Full-Bridge

Mode

In the F ull -B rid ge m ode , t he P 1M1 bit in th e CC P1C ON

direction. When the application firmware changes this

direction co ntrol bit, the modu le will change to the new

direction on the next PWM cycle.

A direction change is initiated in software by changing

the P1M1 bit of the CCP1CON register. The following

sequence occurs prior to the end of the current PWM

period:

• The mo dulated ou tputs (P1 B and P1D) are plac ed

in their inactive state.

• The associated unmodulated outputs (P1A and

P1C) are switched to drive in the opposite

direction.

• PW M modul ation res umes at the be gin ning of the

next period.

See Figure 11-12 for an illustration of this sequence.

The Full-Bridge mode does not provide dead-band

delay. As one outpu t is modulated at a tim e, dead-band

delay is generally not required. There is a situation

where dead-band delay is required. This situation

occurs when both of the following conditions are true:

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn off time of the power switch, including

the power device and driver circuit, is greater

than the turn on time.

Figure 11-13 shows an example of the PWM direction

chan gi ng from for w ar d to rev ers e , at a ne ar 100% duty

cycle. In this example, at time t1, the output P1A and

P1D become inactive, while output P1C becomes

active. Since the turn off time of the power devices is

longer than the turn on time, a shoot-through current

will flow through power devices QC and QD (see

Figure 11-10) for the duration of ‘t’. The same

phenomenon will occur to power devices QA and QB

for PWM di rec t io n ch an ge from reve rs e to forwa rd.

If changing PWM direction at high duty cycle is required

for an app lication, two possible solutions f or eliminatin g

the shoot-through current are:

1. Reduce PWM duty cycle for one PWM period

before changing directions.

2. Use switch drivers that can drive th e switches of f

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

FIGURE 11-12: EXAMPLE OF PWM DIRECTION CHANGE

Pulse Width

Period(1)

Signal

Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.

2: When changing directions, the P1A and P1C signals switch before the end of the current PWM c ycle. The

modulated P1B and P1D signals are inactive at this time. The length of this time is (1/Fosc) • TMR2 prescale

value.

Period

(2)

P1A (Active-High)

P1B (Active-High)

P1C (Active-High)

P1D (Active-High)

Pulse Width

PIC16F882/883/884/886/887

FIGURE 11 -1 3: EXAMPLE OF PW M DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Forward Period Reverse Period

P1A

TON

TOFF

T = TOFF – TON

P1B

P1C

P1D

External Switch D

Potential

Shoot-Through Current

Note 1: All signals are shown as active-high.

2: TON is the turn on delay of power switch QC and its driver.

3: TOFF is the turn off delay of power switch QD and its driver.

External Switch C

PIC16F882/883/884/886/887

11.6.3 START-UP CONSIDERATIONS

When any PWM mode is used, the application

hardware must use the proper external pull-up and/or

pull-down resistors on the PWM output pins.

The CCP1M<1:0> bits of the CCP1CON register allow

the us er t o ch oose whe the r th e P WM output si gna ls are

active-high or active-low for each pair of PWM output pins

(P1A/P1C and P1B/P1D). The PWM output polarities

must be selecte d bef ore the PWM pi n output driv ers ar e

enabled. Changing the polarity configuration while the

PWM pin outpu t dr ivers ar e enab le is no t recomme nde d

since it may result in damage to the application circuits.

The P1A, P1B, P1C and P 1D output latches may not be

in the proper states when the PWM module is

initialized. Enabling the PWM pin output drivers at the

same time as the Enhanced PWM modes may cause

damage to the applic ati on circuit. The En han ce d PWM

modes must be enabled in the proper Output mode and

complete a full PWM cycle before enabling the PWM

pin output drivers. The completion of a full PWM cycle

is indicated by the TMR2IF bit of the PIR1 register

being set as th e second PWM pe riod begins.

Note: When the microcontroller is released from

Reset, all of the I/O pins are in the

high-impedance state. The external cir-

cuits must keep t he power switch devic es

in the Off state until the microcontroller

drives the I/O pins with the proper signal

levels or activates the PWM output(s).

PIC16F882/883/884/886/887

11.6.4 ENHANCED PWM AUTO-

SH UTDOWN MODE

The PWM mode supports an Auto-Shutdow n m ode that

will disable the PWM outputs when an external

shutdown event occurs. Auto-Shutdown mode places

the PWM output pins into a predetermined state. This

mode is used to help prevent the PWM from damaging

the application.

The auto-shutdown sources are selected using the

ECCPAS<2:0> bits of the ECCP AS regi ster . A shutdown

event may be generated by:

•A logic ‘0’ on the INT pin

• Comparator C1

• Comparator C2

• Setting the ECCPASE bit in firmware

A shutdown condition is indicated by the ECCPASE

(Auto-Shutdown Event Status) bit of the ECCPAS

normally. If the bit is a ‘1’, the PWM outputs are in the

shutdown state.

When a shutdow n event oc curs, two things ha ppen:

The ECCPASE bit is set to ‘1’. The ECCPASE will

remain set until cleared in firmware or an auto-restart

occurs (see Section 1 1.6.5 “Auto-Restart Mode”).

The enabled PWM pins are asynchronously placed in

their shutdown states. The PWM output pins are

grouped into pairs [P1A/P1C] and [P1B/P1D]. The state

of each pin pair is determined by the PSSAC and

PSSBD bits of the ECCPAS register. Each pin pair may

be placed into one of three st ates:

• Drive logic ‘1’

• Drive logic ‘0’

• Tri-state (high-impedance)

FIGURE 11 -14: AUTO-SHUTDOWN BLOCK DIAGRAM

PSSAC<1>

TRISx P1A

P1A_DRV

PSSAC<0>

PSSBD<1>

TRISx P1B

PSSBD<0>

P1B_DRV

PSSAC<1>

TRISx P1C

PSSAC<0>

P1C_DRV

PSSBD<1>

TRISx P1D

PSSBD<0>

P1D_DRV

000

001

010

011

100

101

110

111

From Com parato r C2

From Com parat or C 1

ECCPAS<2:0>

ECCPASE

From Data Bus

Write to ECCPASE

PRSEN

INT

PIC16F882/883/884/886/887

CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit

1 = A shutdown event has occurred; ECCP outputs are in shutdown state

0 = ECCP outputs are operating

bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits

000 = Auto-Shutdown is disabled

001 = Comparator C1 output high

010 = Comparator C2 output high(1)

011 = Either Comp arato rs outp ut is high

100 =V

IL on INT pin

101 =V

IL on INT pin or Comparator C1 output high

110 =V

IL on INT pin or Comparator C2 output high

111 =VIL on INT pin or either Comparators output is high

bit 3-2 PSSACn: Pins P1A and P1C Shutdown State Control bits

00 = Drive pins P1A and P1C to ‘0’

01 = Drive pins P1A and P1C to ‘1’

1x = Pins P1A and P1C tri-state

bit 1-0 PSSBDn: Pins P1B and P1D Shutdown State Control bits

00 = Drive pins P1B and P1D to ‘0’

01 = Drive pins P1B and P1D to ‘1’

1x = Pins P1B and P1D tri-state

Note 1: If C2SYNC is enabled, the shutdown will be delayed by Timer1.

Note 1: The auto-shutdown condition is a level-

based signal, not an edge-based signal.

As long as the level is present, the auto-

shutdown will persist.

2: Writing to the ECCPASE bit is disabled

while an auto-shutdown condition

persists.

3: Once the auto-shutdown condition has

been removed and the PWM restarted

(either through firmware or auto-restart)

the PWM signal will always restart at the

beginning of the next PWM period.

PIC16F882/883/884/886/887

FIGURE 11-15: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)

11.6.5 AUTO -RESTART MODE

The Enhanced PWM can be configured to automati-

cally restart the PWM signal once the auto-shutdown

condition has been removed. Auto-restart is enabled by

setting the PRSEN bit in the PWM1CON register.

If auto-restart is enabled, the ECCPASE bit will remain

set as long as the auto-shutdown condition is active.

When the auto-shutdown condition is removed, the

ECCPASE bit will be cleared via hardware and normal

operation will resume.

FIGURE 11 -16: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)

Shutdown

PWM

ECCPASE bit

Activity

Event

Shutdown

Event Occurs Shutdown

Event Clears PWM

Resumes

Start of

PWM Period

ECCPASE

Cleared by

Firmware

PWM Period

Shutdown

PWM

ECCPASE bit

Activity

Event

Shutdown

Event Occurs Shutdown

Event Cle ars PWM

Resumes

PWM Period

Start of

PWM Period

PIC16F882/883/884/886/887

11.6.6 PROGRAMMABLE DEAD-BAND

DELAY MODE

In Half-Bridge applications where all power switches

are modulated at the PWM frequency, the power

switches normally require more time to turn off than to

turn on. If b oth the u pper and lowe r power swit ches ar e

switched at the same time (one turned on, and the

other turned off), both switches may be on for a short

period of time until one switch completely turns off.

During this brief interval, a very high current (shoot-

through c urre nt) wi ll flow throu gh bot h po w er sw itc hes ,

shorting the bridge supply. To avoid this potentially

destructive shoot-through current from flowing during

switching, turning on either of the power switches is

normally delayed to allow the other switch to

completely turn off.

In Half-Bridge mode, a digitally programmable dead-

band delay is available to avoid shoot-through current

from destroying the bridge power switches. The delay

occurs at the si gnal tra nsition fro m the no n-acti ve st ate

to the active state. See Figure 1 1-17 for illu stration. The

lower sev en b it s of th e as s oci ate d PWM 1CO N reg ist er

(Register 11-4) sets the delay period in terms of

microcontrolle r instruction cycles (TCY or 4 TOSC).

FIGURE 11-17: EXAMPLE OF HALF-

BRIDGE PWM OUTPUT

FIGURE 11 -1 8: EXAMPLE OF HALF-BRIDGE APPLICATIONS

Period

Pulse Width

(1)

P1A(2)

P1B(2)

td = Dead-B and Delay

Period

(1) (1)

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

P1A

P1B

FET

Driver

FET

Driver

V+

V-

Load

Standard Half-Bridge Circuit (“Push-P ull ”)

PIC16F882/883/884/886/887

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PRSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes

away; the PWM restarts automatically

0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM

bit 6-0 PDC<6:0>: PWM Delay Count bits

PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal

should transition active and the actual time it transitions active.

PIC16F882/883/884/886/887

11.6.7 PULSE STEERING MODE

In Sing le Output mode, pul se steering all ows any of the

PWM pins to be t he modulated sig nal . Addi tio nal ly, the

same PWM signal can be simultaneously available on

multiple pins.

Once the Single Output mode is selected

(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the

CCP1CON register), the user firmware can bring out

the same PWM signal to one, two, three or four output

pins by setting the appropriate STR<D:A> bits of the

PSTRCON register, as shown in Table 11-5.

While th e PWM Steering mode is ac ti ve, CCP1M<1:0 >

bits of the CCP1CON register select the PWM output

polarity for the P1<D:A> pins.

The PWM auto-shutdown operation also applies to

PWM Steering mode as described in Section 11.6.4

“Enhanced PWM Auto-shutdown mode”. An auto-

shutdown event will only affect pins that have PWM

outputs enabled.

Note: The associated TRIS bits must be set to

output (‘0’) to enable the pin output driver

in or der to s ee the PWM s ign al on the pi n.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1

— — — STRSYNC STRD STRC STRB STRA

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 STRSYNC: S t eeri ng Syn c bit

1 = Output steering update occurs on next PWM period

0 = Output steering update occurs at the beginning of the instruction cycle boundary

bit 3 STRD: S teering Enable bit D

1 = P1D pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = P1D pin is assigned to port pin

bit 2 STRC: S teering Enable bit C

1 = P1C pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = P1C pin is assigned to port pin

bit 1 STRB: S teering Enable bit B

1 = P1B pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = P1B pin is assigned to port pin

bit 0 STRA: S teering Enable bit A

1 = P1A pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = P1A pin is assigned to port pin

Note 1: The PWM Steering mode is available only wh en the CCP1CON regist er bits CCP1M<3:2> = 11 and

P1M<1:0> = 00.

PIC16F882/883/884/886/887

FIGURE 11-1 9: SIMPLIFIED STEE R ING

BLOCK DIAGRAM

0TRIS

P1A pin

PORT Data

P1A Signal

STRA

0TRIS

P1B pin

PORT Data

STRB

0TRIS

P1C pin

PORT Data

STRC

0TRIS

P1D pin

PORT Data

STRD

Note 1: Port outputs are configured as shown when

the CCP1CON register bits P1M<1:0> = 00

and CCP1M<3:2> = 11.

2: Single PWM output requires setting at least

one of the STRx bits.

CCP1M1

CCP1M0

CCP1M1

CCP1M0

PIC16F882/883/884/886/887

11.6.7.1 Steering Synchronization

The STRSYNC bit of the PSTRCON register gives the

user two selections of when the steering event will

happen. When the STRSYNC bit is ‘0’, the steering

event will happen at the end of the instruction that

writes to the PSTRCON register. In this case, the

output signal at the P1<D:A> pins may be an

incomplete PWM waveform. This operation is useful

when the user firmware needs to immediately remove

a PWM signal from the pin.

When the STRSYNC bit is ‘1’, the effective steering

update will happen at the beginning of the next PWM

period. In this case, steering on/off the PWM output will

always produce a complete PWM waveform.

Figur es 1 1-20 an d 1 1-21 ill ustrate the timi ng diagrams

of the PWM steering depending on the STRSYNC

setting.

FIGURE 11-20: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)

FIGURE 11 -2 1: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION

(STRSYNC = 1)

PWM

P1n = PWM

STRn

P1<D:A> PORT Data

PWM Period

PORT Data

PWM

PORT Data

P1n = PWM

STRn

P1<D:A> PORT Data

PIC16F882/883/884/886/887

TABLE 11-6: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1

TABLE 11-7: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

CCPR1L Capture/Compare/PWM Regist er 1 Low Byte (LSB) xxxx xxxx xxxx xxxx

CCPR1H Ca pture/Compare/PWM Register 1 High By te (MS B) xxxx xxxx xxxx xxxx

CCPR2L Capture/Compare/PWM Regist er 2 Low Byte (LSB) xxxx xxxx xxxx xxxx

CCPR2H Ca pture/Compare/PWM Register 2 High By te (MS B) xxxx xxxx xxxx xxxx

CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL ——T1GSSC2SYNC 0000 --10 0000 --10

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 0000 00-0 0000 00-0

PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 0000 00-0 0000 00-0

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx xxxx xxxx

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx xxxx xxxx

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture and

Compare.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PR2 Timer2 Perio d Regi ste r 1111 1111 1111 1111

PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001

PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 0000 0000

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

TMR 2 Timer2 Modul e Reg ist er 0000 0000 0000 0000

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111

Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

12.0 ENHANCED UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

system. Full-Duplex mode is useful for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These device s typ icall y do n ot have inter nal cl ocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

The EUSART m odule includes the follow ing capabilities:

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

• One -ch arac ter out put buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

• Input buffer overrun error detection

• Received character framing error detection

• Hal f-du ple x sy nc hron ous master

• Hal f-du ple x sy nc hron ous slave

• Programmable clock polarity in synchronous

modes

• Sleep operation

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

• Automa tic detection and c alibration of the baud rate

• Wak e-up on Break re ception

• 13-bi t Break character transm it

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 12-1 and Figure 12-2.

FIGURE 12-1: EUSART TRANSMIT BLOCK DIAGRAM

TXIF

TXIE

Interrupt

TXEN

TX9D

MSb LSb

Data Bus

TXREG Register

Transmit Shift Register (TSR)

(8) 0

TX9

TRMT SPEN

TX/CK pin

Pin Buffer

and Control

SPBRG

SPBRGH

BRG16

FOSC ÷ n

+ 1 Multiplier x4 x16 x64

SYNC 1X00 0

BRGH X110 0

BRG16 X101 0

Baud Rate Generator

•••

PIC16F882/883/884/886/887

FIGURE 12-2: EUSART RECEIVE BLOCK DIAGRAM

The operation of the EUSART module is controlled

through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCTL)

These registers are detailed in Register 12-1,

Regi st er 12 -2 an d R e gi s ter 12-3, respec ti v ely.

RX/DT pin

Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR

FERR

RSR Register

MSb LSb

RX9D RCREG Register FIFO

Interrupt

RCIF

RCIE

Data Bus

Stop START

(8) 7 10

RX9

• • •

SPBRGSPBRGH

BRG16

RCIDL

FOSC ÷ n

+ 1 Multiplier x4 x16 x64

SYNC 1X00 0

BRGH X110 0

BRG16 X101 0

Baud Rate Generato r

PIC16F882/883/884/886/887

12.1 EUSART Asynchronous Mode

The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH mark state which

represents a ‘1’ data bit, and a VOL space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output l evel of that bit wi thout returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the mark state. Each character

transmission consists of one Start bit followed by eig ht

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is 8 bits. Each transmitted bit persists for a period

of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud

Rate Generator is used to derive standard baud rate

frequencies from the system oscillator. See Table 12-5

for examples of baud rate configurations.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

indepen dent, but share th e sa me dat a format and bau d

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data b it.

12.1.1 EUSART ASYNCHRONOUS

TRANSMITTER

The EUSART transmitter block diagram is shown in

Figure 12-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

12.1.1.1 Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

•TXEN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the TXEN bit of the TXSTA register enables the

transmitter circuitry of the EUSART. Clearing the SYNC

bit of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCST A register enables the EUSART and automatically

configures the TX/CK I/O pin as an output. If the TX/CK

pin is shared with an analog peripheral the analog I/O

function must be disabled by clearing the corresponding

ANSEL bit.

12.1.1.2 Transmitting Data

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR re gister. If the T SR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then tran sferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bit s

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

12.1.1.3 Transmit Interrupt Flag

The TXIF interrupt flag bit of the PIR1 register is set

whenever the EUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new char acter ha s been

queued for transmission in the TXREG. The TXIF flag bit

is not cleared immediately upon writing TXREG. TXIF

becomes valid in the second instruction cycle following

the write execut ion. Polling TXIF immediately following

the TXREG write will return invalid results. The TXIF bit

is read-only, it cannot be set or cleared by software.

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF fla g bit will be set wheneve r the TXR EG is emp ty,

regardless of the state of TXIE enable bit.

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE i nterrupt en able bi t upon w riting the last charact er

of the transmission to the TXREG.

Note 1: When the SPEN bit is set the RX/DT I/O pin

is automatically configured as an input,

regardless of the state of the corresponding

TRIS bit and whether or not the EUSART

receiver is enabled. The RX/DT pin data

can be read via a normal PORT read but

PORT latch data output is precluded.

2: The TXIF transmitter interrupt flag is set

when the TXEN enable bit is set.

PIC16F882/883/884/886/887

12.1.1.4 T SR Status

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

12.1.1.5 Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set the

EUSART will shif t 9 bits out for each character transmit-

ted. The TX9D bit of the TXSTA register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the 8 Least Sig nificant bit s into the TXREG. All nine bit s

of data will be transferred to the TSR shift register

immediately after the TXREG is written.

A special 9-bit Address mode is available for use with

multiple receivers. See Section 12.1.2.7 “Address

Detection” for more inform ation on the Addre ss mode.

12.1.1.6 Asynchronous Transmission Set-up:

1. Initialize the SPBRGH, SPBRG register pair and

the BRGH and BRG16 bits to achieve the d esired

baud rate (see Section 12.3 “EUSART Baud

Rate Generator (BRG)”).

2. Enable the as y nch ron ous serial port by cle arin g

the SYNC bit and setting the SPEN bit.

3. If 9-bit tran sm is si on is d es ire d, s et th e TX9 con-

trol bit. A set nin th data bi t will indicat e that the 8

Least Significant data bits are an address when

the receiver is set for address detection.

4. Enable the transmission by setting the TXEN

contr ol bit . Thi s wi ll c aus e th e TXI F i nte rrup t bi t

to be set.

5. If interrupts are desired, set the TXIE interrupt

enable bit of the PIE1 register. An interrupt will

occur immediately provided that the GIE and

PEIE bits of the INTCON register are also set.

6. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

7. Load 8-bit data into the TXREG register. This

will start the transmission.

FIGURE 12-3: ASYNCHRONOUS TRANSMISSION

FIGURE 12-4: ASYNCHR ON OUS TRANSMISSION (BACK TO BACK)

Note: The TSR register is not mapped in data

memory, so it is not available to the user.

Word 1 Stop bit

Word 1

Transmit Shift Reg

Start bit bit 0 bit 1 bit 7/8

Write to TXREG Word 1

BRG Output

(Shift Clock)

TX/CK

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Tran s mit Sh ift

Reg. Empty Flag)

1 TCY

Transmit Shift Reg.

Write to TXREG

BRG Output

(Shift Clock)

TX/CK

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1 Word 2

Start bit Stop bit Start bit

Transmit Shift Reg.

Word 1 Word 2

bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram shows two consecutive transmissions.

1 TCY

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

PIC16F882/883/884/886/887

TABLE 12-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Va lue on

POR, BOR

Value on

all other

Resets

BAUDCTL ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 01-0 0-00 01-0 0-00

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

RCREG EUSART Receive Data Register 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXREG EUSART Transmit Data Register 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission.

PIC16F882/883/884/886/887

12.1.2 EUSART ASYNCHRONOUS

RECEIVER

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 12-2. The d ata is received on th e RX/DT pin and

drives the data recov ery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

bits of the character have been shifted in, they are

immediately transferred to a two character First-In-

First-Out (FIFO) memory. The FIFO buffering allows

receptio n of two complete characters and the s t art of a

third cha rac ter be fore software must start servi ci ng th e

EUSART receiver. The FIFO and RSR registers are not

direc tly ac cessible b y s oftwar e. Ac cess to the r e ce ived

data is via the RCREG register.

12.1.2.1 Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operatio n by configuring the fol lowing three control bits:

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCST A register enables the

receiver circuitry of the EUSART. Clearing the SYNC bit

of the TXSTA register configures the EUSART for asyn-

chronous operation. Setting the SPEN bit of the RCSTA

ures the RX/DT I /O pin as an in put. If t he RX/DT pin is

shared with an analog peripheral the analog I/O function

must be disabled by clearing the corresponding ANSEL

bit.

12.1.2.2 Receiving Data

The receiver data recovery circuit initiates character

receptio n on t he fallin g edge of the first bit. Th e f irst bit,

also known as the Start bit, is always a zero. The data

recovery circuit co unt s one-h alf bi t time to the c enter of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit c ounts a full bit time to the ce nter of the

next bit. The bit is then sampled by a majority detect

circuit and the resultin g ‘0’ or ‘1’ is sh ifted int o the RSR.

This repeats until all data bits have been sampled and

shif ted into the RSR. One final bit time is measured and

the le ve l samp le d . Thi s is th e Sto p bi t, wh ic h is alwa ys

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

charact er , otherwise th e framing error is c leared for thi s

character. See Section 12.1.2.4 “Receive Framing

Error” for more information on framing errors.

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

12.1.2.3 Receive Interrupts

The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSAR T receiver i s enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt fla g bit is read-o nly, it ca nnot b e set or cl eared

by software.

RCIF interrupts are enabled by setting all of the

following bits:

• RCIE interrupt enable bit of the PIE1 register

• PEIE peripheral interrupt enable bit of the INT-

CON register

• GIE global interrupt enable bit of the INTCON

The RCIF interrupt flag bit will be set when there is an

unread c haracter in the FIFO, regardless of the st ate of

interrupt enable bits.

Note: When the SPEN bit is set the TX/CK I/O

pin is automatically configured as an

output, regardless of the state of the

corresp onding TRI S bit and whe ther or not

the EUSART transmitter is enabled. The

PORT latch is disconnected from the

output driver so it is not possible to use the

TX/CK pin as a general purpose output.

Note: If the receive FIFO is overrun, no addi tional

characters will be received until the overrun

condition is cleared. See Section 12.1.2.5

“Receive Overrun Error” for more

information on overrun errors.

PIC16F882/883/884/886/887

12.1.2.4 Receive Framing Error

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indic ates t hat a Stop bit was not seen at the e xpect ed

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represen ts the s ta tus o f the top u nread charac ter in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.

The FERR bit is read-only and only applies to the top

unre ad char acter in the re ceive F IFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the EUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

12.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun erro r will be generated If a thi rd character, in its

entirety , is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTA register is set.

The characters already in the FIFO buffer can be read

but no additional characters will be received until the

error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

resetting the EUSART by clearing the SPEN bit of the

RCSTA register.

12.1.2.6 Rec ei vi ng 9-bit Chara cte rs

The EUS ART support s 9-bit c haracter rece ption. When

the RX9 bit of the RCSTA register is set the EUSART

will shift 9 bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

charact er in the recei ve FIFO. When read ing 9- bit dat a

from the receive FIFO buffer, the RX9D data bit must

be read befo re reading the 8 L east Signifi cant bits fro m

the RCREG.

12.1.2. 7 Addres s Detecti on

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

rece iv e FI F O bu ffe r, there by s et t i ng th e R CI F i nte r r up t

bit. All other characters will be ignored.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop b it oc cu rs. When use r s oftware de tec t s th e end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

Note: If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCREG will not clear the FERR bit.

PIC16F882/883/884/886/887

12.1.2.8 Asynchronous Reception Set-up:

1. Initialize the SPBRGH, SPBRG reg ister pair and

the BRGH and BRG16 bits to achieve the

des i red baud rate (see Section 12.3 “EUSART

Baud Rate Generator (BRG)”).

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

4. If 9-bit reception is desired, set the RX9 bit.

5. Enable reception by setting the CREN bit.

6. The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

7. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data b it.

8. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

9. If an overrun occurred, clear the OERR flag by

clearing the C REN r eceiver e nable bit.

12.1.2.9 9-bit Address Detection Mode Set-up

This m ode w o uld ty pi cally be us ed in RS-485 sy ste ms .

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH, SPBRG register p air and

the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 12.3 “EUSART

Baud Rate Generator (BRG)”).

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

4. Enable 9-bit reception by setting the RX9 bit.

5. Enable a ddress d etection by setti ng the ADD EN

bit.

6. Enable reception by setting the CREN bit.

7. The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will b e gener ated if t he RCIE inte rrupt en able b it

was also set.

8. R ead the RCS TA regi ste r to get th e err or f lag s.

The ninth data bit will always be set.

9. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

device’s address.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 12-5: ASYNCHRONOUS RECEPTION

Start

bit bit 7/8

bit 1bit 0 bit 7/8 bit 0Stop

bit

Start

bit Start

bit

bit 7/8 Stop

bit

RX/DT pin

Reg

Rcv Buffer Reg

Rcv Shift

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG Word 2

RCREG

Stop

bit

Note: This timin g diagram sho ws three words appearing on the RX input. The RCREG (receive buffer) is r ead after the third word,

causing the OERR (overrun) bit to be set.

RCIDL

PIC16F882/883/884/886/887

TABLE 12-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOR

Value on

all other

Resets

BAUDCTL ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 01-0 0-00 01-0 0-00

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

RCREG EUSART Receive Data Register 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXREG EUSART Transmit Data Register 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception.

PIC16F882/883/884/886/887

12.2 Clock Accuracy with

Asynchronous Operation

The factory calibrates the Internal Oscillator block out-

put (INTOSC). However, the INTOSC frequency may

drift as VDD or temperature changes, and this directly

af fects the asynch ronous baud rate. T wo methods ma y

be used to adjust the baud rate clock, but both require

a reference clock source of some kind.

The first (preferred) method uses the OSCTUNE

value in the OSCTUNE register allows for fine resolution

changes to the system clock source. See Section 4.5

“Internal Clock Modes” for more information.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see Section 12.3.1 “Auto-

Baud Detect”). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

bit 6 TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: EUSART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 SENDB: Send Break Character bit

Asynchronous mode:

1 = Send Sync Break on next transmission (cleared by hardware upon completion)

0 = Sync Break transmission co mpleted

Synchronous mode:

Don’t care

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode :

Unused in this mode

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC16F882/883/884/886/887

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0 = Serial port disabled (held in Reset)

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1 = Enables single receive

0 = Disables single r eceive

This bit is cleared after reception is complete.

Synchronou s mod e – Slave

Don’t care

bit 4 CREN: Conti nuous Receive Enab le bit

Asynchronous mode:

1 = Enables receiver

0 = Disables receiver

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables contin uou s r ece iv e

bit 3 ADDEN: Address Detect Enab le bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

bit 2 FERR: Framing Error bit

1 = Fra ming error (can be updated by reading RCREG register and receive next valid byte)

0 = No f raming error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: Ninth bit of Received D ata

This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC16F882/883/884/886/887

R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:

1 = Auto-baud timer overflowed

0 = Auto-baud timer did not overflow

Synchronous mode:

Don’t care

bit 6 RCIDL: Receive Idle Flag bit

Asynchronous mode:

1 = Receiver is Idle

0 = Start bit has been received and the receiver is receiving

Synchronous mode:

Don’t care

bit 5 Unimplemented: Read as ‘0’

bit 4 SCKP: Synchronou s Clock Polari ty Select bit

Asynchronous mode:

1 = Transmit inverted data to the RB7/TX/CK pin

0 = Transmit non-inverted data to the RB7/TX/CK pin

Synchronous mode:

1 = Data is clocked on rising edge of the clock

0 = Data is clocked on falling edge of the clock

bit 3 BRG16: 16-bit Baud Rate Generator bit

1 = 16-bit Baud Rate Ge ner ator is used

0 = 8-bit Baud Rate Generator is used

bit 2 Unimplemented: Read as ‘0’

bit 1 WUE: Wake-up Enable bit

Asynchronous mode:

1 = Receiv er is waiting fo r a falling ed ge. No charac ter will be rece ived byte RCIF will be se t. WUE will

automatically clear after RCIF is set.

0 = Receiv er is operatin g normally

Synchronous mode:

Don’t care

bit 0 ABDEN: Auto-Baud Dete ct Enab le bit

Asynchronous mode:

1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

0 = Auto-Baud Detect mode is disabled

Synchronous mode:

Don’t care

PIC16F882/883/884/886/887

12.3 EUSART Baud Rate Generator

(BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By defau lt, the BRG ope rates in 8-bit mode . Setting th e

BRG16 bit of the BAUDCTL register selects 16-bit

mode.

The SPBRGH, SPBRG register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the TXST A

Synchronous mode, the BRGH bit is ignored.

Table 12-3 contains the formulas for determining the

baud rate . Example 12-1 provides a s ample calcul ation

for determining the baud rate and baud rate error.

Typical baud rates and error values for various

asynchronous modes have been computed for your

convenience and are shown in Table 12-3. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to redu ce th e baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

Writing a new value to the SPBRGH, SPBRG register

pair c auses the BRG timer to be reset (or cleared). Thi s

ensures that the BRG do es not wait fo r a timer overflow

before outputting the new baud rate.

If the s ys tem c lo ck is changed duri ng an active r ece iv e

operation, a receive error or data loss may result. To

avoid thi s problem , check the status of the RCID L bit to

make sure that the receive operation is Idle before

changing the system clock.

EXAMPLE 12-1: CALCULATING BAUD

RATE ERROR

TABLE 12-3: BAUD RATE FORMULAS

TABLE 12-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

For a devi ce w ith FOSC of 16 MHz, desired baud rate

of 9600, Asynch rono us mode, 8-bit BRG:

Solving for SPBRGH:SPBRG:

FOSC

Desired Baud Rate

---------------------------------------------

--------------------------------------------- 1–=

Desired Baud Rate FOSC

64 [SPBRGH:SPBRG] 1+()

---------------------------------------------------------------------=

16000000

9600

------------------------

------------------------1–=

25.042[]25==

Calculated Baud Rate 16000000

64 25 1+()

---------------------------=

9615=

Error Calc. Baud Rate Desired Baud Rate –

Desired Baud Rate

--------------------------------------------------------------------------------------------=

9615 9600–()

9600

---------------------------------- 0 . 1 6 %==

Configuration Bits BRG/EUSART Mode Baud Rate Form ula

SYNC BRG16 BRGH

000 8-bit/Asynchronous FOSC/ [64 (n+1)]

001 8-bit/Asynchronous FOSC/[16 (n+1)]

010 16-bit/Asynchronous

011 16-bit/Asynchronous

FOSC/[4 (n+1)]10x 8-bit/Synchronous

11x 16-bit/Synchronous

Legend: x = Don’t car e , n = valu e of SPBR GH, SPBRG register p a ir

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOR

Value on

all other

Resets

BAUDCTL ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 01-0 0-00 01-0 0-00

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

PIC16F882/883/884/886/887

TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300—— — —— — —— — —— —

1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103

2400 2404 0.16 129 2400 0.00 119 2400 0.00 71 2404 0.16 51

9600 9470 -1.36 32 9600 0.00 29 9600 0.00 17 9615 0.16 12

10417 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 10417 0.00 11

19.2k 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 — — —

57.6k — — — 57.60k 0.00 7 57.60k 0.00 2 — — —

115.2k — — — — — — — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 300 0.16 207 300 0.00 191 300 0.16 103 300 0.16 51

1200 1202 0.16 51 1200 0.00 47 1202 0.16 25 1202 0.16 12

2400 2404 0.16 25 2400 0.00 23 2404 0.16 12 — — —

9600 — — — 9600 0.00 5 — — — — — —

10417 10417 0.00 5 — — — 10417 0.00 2 — — —

19.2k — — — 19.20k 0.00 2 — — — — — —

57.6k — — — 57.60k 0.00 0 — — — — — —

115.2k — — — — — — — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 —— — —— — —— — —— —

1200 — — — — — — — — — — — —

2400 — — — — — — —— —2404 0.16 207

9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51

10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47

19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19231 0.16 25

57.6k 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8

115.2k 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —

PIC16F882/883/884/886/887

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 — — — — — — — — — 300 0.16 207

1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51

2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25

9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — —

10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5

19.2k 19.23k 0.16 12 19.2k 0.00 11 — — — — — —

57.6k — — — 57.60k 0.00 3 — — — — — —

115.2k — — — 115.2k 0.00 1 — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 299.9 -0.02 1666

1200 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 1199 -0.08 416

2400 2399 -0.03 520 2400 0.00 479 2400 0.00 287 2404 0.16 207

9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51

10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47

19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19.23k 0.16 25

57.6k 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8

115.2k 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 300.1 0.04 832 300.0 0.00 767 299.8 -0.108 416 300.5 0.16 207

1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51

2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25

9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — —

10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5

19.2k 19.23k 0.16 12 19.20k 0.00 11 — — — — — —

57.6k — — — 57.60k 0.00 3 — — — — — —

115.2k — — — 115.2k 0.00 1 — — — — — —

TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

PIC16F882/883/884/886/887

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 300.0 0.00 6666

1200 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 1200 -0.02 1666

2400 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.04 832

9600 9597 -0.03 520 9600 0.00 479 9600 0.00 287 9615 0.16 207

10417 10417 0.00 479 10425 0.08 441 10433 0.16 264 10417 0 191

19.2k 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 19.23k 0.16 103

57.6k 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 57.14k -0.79 34

115.2k 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 117.6k 2.12 16

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 300.0 0.01 3332 300.0 0.00 3071 299.9 -0.02 1666 300.1 0.04 832

1200 1200 0.04 832 1200 0.00 767 1199 -0.08 416 1202 0.16 207

2400 2398 0.08 416 2400 0.00 383 2404 0.16 207 2404 0.16 103

9600 9615 0.16 103 9600 0.00 95 9615 0.16 51 9615 0.16 25

10417 10417 0.00 95 10473 0.53 87 10417 0.00 47 10417 0.00 23

19.2k 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 25 19.23k 0.16 12

57.6k 58.82k 2.12 16 57.60k 0.00 15 55.56k -3.55 8 — — —

115.2k 111.1k -3.55 8 115.2k 0.00 7 — — — — — —

TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

PIC16F882/883/884/886/887

12.3.1 AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a receiv ed 55h (ASCII “U ”) which is the Sync charac ter

for the LIN bus. The unique feature of this character is

that it has five rising edges in cluding the S top bit ed ge.

Setting the ABDEN bit of the BAUDCTL register starts

the auto-baud calibration sequence (Figure 12-6).

While the ABD sequence takes place, the EUSART

state machine is held in Idle. On the first rising edge of

the receive line, after the Start bit, the SPBRG begins

counting up using the BRG counter clock as shown in

Table 12-6. Th e fifth rising edge will occur on the RX pin

at the end of the eighth bit period. At that time, an

accumulated value totaling the proper BRG period is

left in the SPBRGH, SPBRG register pair, the ABDEN

bit is automatically cleared and the RCIF interrupt flag

is set. The value in the RCREG needs to be read to

clear the RCIF interrupt. RCREG content should be

discarded. When calibrating for modes that do not use

the SPBRGH register the user can verify that the

SPBRG register did not o verflow by check ing for 00h i n

the SPBRGH register.

The BRG au to-baud clock is d etermined by the BRG1 6

and BRGH bits as shown in Table 12-6. During ABD,

both the SPBRGH and SPBRG registers are used as a

16-bit counter, independent of the BRG16 bit setting.

While calibrating the baud rate period, the SPBRGH

and SPBRG registers are clocked at 1/8th the BRG

base clo ck rate. The resu lting byte meas urement is the

average bit time when clocked at full speed.

TABLE 12-6: BRG COUNTER CLOCK RATES

FIGURE 12-6: AUTOMATIC BAUD RATE CALIBRATION

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection w ill occur on the by te

following the Break character (see

Section 12.3.2 “Auto-Wake-up on

Break”).

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscill ator freq uency

and EUSART baud rates are not possible.

3: During the auto-baud process, the auto-

baud counter starts counting at 1. Upon

completion of the auto-baud sequence, to

achieve maximum accuracy, subtract 1

from the SPBRGH:SPBRG register pair.

BRG16 BRGH BRG Base

Clock BRG ABD

Clock

00FOSC/64 FOSC/512

01FOSC/16 FOSC/128

10FOSC/16 FOSC/128

11 FOSC/4 FOSC/32

Note: During the ABD sequence, SPBRG and

SPBRGH registers are both used as a 16-bit

counter , independent of BRG16 setting.

BRG Value

RX pin

ABDEN bit

RCIF bit

bit 0 bit 1

(Interrupt)

Read

RCREG

BRG Clock

Start

Auto Cleared

Set by User

XXXXh 0000h

Edge #1 bit 2 bit 3

Edge #2 bit 4 bit 5

Edge #3 bit 6 bit 7

Edge #4 Stop bit

Edge #5

001Ch

Note 1: The ABD sequen ce requ i re s the EUSART modul e to be configur ed in Asyn chr ono us mod e

SPBRG XXh 1Ch

SPBRGH XXh 00h

RCIDL

PIC16F882/883/884/886/887

12.3.2 AUTO-WAKE-UP ON BREAK

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controll er to w ake -up due to ac tiv ity on the R X/DT line.

This feature is available only in Asynchronous mode.

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDCTL regis ter. Onc e set, the normal

receive sequence on RX/DT is disabled, and the

EUSART remains in an Idle state, monitoring for a wake-

up event independent of the CPU mode. A wake-up

event consists of a high-to-low transition on the RX/DT

line. (This coincides with the start of a Sync Break or a

wake-up si gnal character fo r the LIN pro toc ol.)

The EUSART module generates an RCIF interrupt

coincident with the wake-up event. The interrupt is

generated s ynchronously to the Q clocks in normal CPU

operating modes (Figure 12-7), and asynchronously if

the device is in Sleep mode (Figure 12-8). The interrupt

condition is cleared by reading the RCRE G regis ter.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in Idle mode waiting to

receive the next character.

12.3.2.1 Special Considerations

Brea k Cha ract er

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

receive d, the low time from the S tar t bit to the firs t rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the ini tial cha racter in the transmi ssion mus t

be all ‘0’s. This must be 10 or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

Oscillator Startup Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval , to allow eno ugh ti me fo r the se lecte d osc illat or

to start and provide proper initialization of the EUSART.

WUE Bit

The wake-up event causes a receive interrupt by

setting the RCIF bit. The WUE bit is cleared in

hardware by a rising edge on RX/DT. The interrupt

condition is then cleared in software by reading the

RCREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before set ting the WU E bit. If a recei ve opera tion is not

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

FIGURE 12-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2Q3 Q4Q1 Q2Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1Q2 Q3Q4

OSC1

WUE bit

RX/DT Line

RCIF

Bit set by user Auto Cleared

Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

PIC16F882/883/884/886/887

FIGURE 12-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

12.3.3 BREAK CHARACTER SEQUENCE

The EUSART mod ule ha s t he c apabili ty of s en din g th e

special Break chara cter sequences that are required by

the LIN bus standard. A Break character consists of a

St ar t bit, follo w ed by 12 ‘0’ bits and a Stop bit.

To send a Break character, set the SENDB and TXEN

bits of the TXSTA register. The Break character trans-

mission is then initiated by a write to the TXREG. The

value of data written to TXREG will be ignored and all

‘0’s will be transmitted.

The SENDB bit is automatically reset by hardware af ter

the correspon din g Stop bit is s ent. This al lo w s t he us er

to preloa d the trans mit FIFO with the n ext transm it byte

following the Break character (typically, the Sync

character in the LIN specification).

The TRMT bit of the TXSTA register indicates when the

transmit operation is active or Idle, jus t as it does during

normal transmission. See Figure 12-9 for the timing of

the Break character sequence.

12.3.3.1 Bre a k and Sync Trans mit Seque nce

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART for the desire d mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transm it FIFO buf f er.

5. After the Break has been se nt, the SEN DB bit i s

reset by hardware and the Sync character is

then transm itte d.

When the TXREG bec omes em pty, as indica ted by th e

TXIF, the next data byte can be written to TXREG.

12.3.4 RECEIVING A BREAK CHARACTER

The Enhanced EUSART module can receive a Break

character in two ways.

The first method to detect a Break character uses the

FERR bit of the RCSTA regist er and the Rece ived data

as indicated by RCREG. The Baud Rate Generator is

assum ed to ha ve been initiali zed to the exp ec t ed bau d

rate.

A Break charac ter has been received when;

• RCIF bit is set

• FERR bit is set

• RCREG = 00h

The second method uses the Auto-Wake-up feature

described in Section 12.3.2 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART will

sample the next two transitions on RX/DT, cause an

RCIF interru pt, and recei ve th e n ext d ata byte fol lowe d

by another interrupt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUDCTL register before placing the EUSART in

Sleep mode.

Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4Q1Q2Q3 Q4 Q1Q2Q3Q4

OSC1

WUE bit

RX/DT Line

RCIF

Bit Set by User Auto Clear ed

Cleared due to User Read of RCREG

Sleep Command Executed

Note 1

Note 1: If the wake-up e vent requires long oscillator warm-up time, th e automatic cle aring of the WUE bit ca n occur wh ile the stposc sign al is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

Sleep Ends

PIC16F882/883/884/886/887

FIGURE 12-9: SEND BREAK CHARACTE R SEQUENCE

Write to TXREG Dummy Write

BRG Output

(Shift Clock)

S tart bit bit 0 bit 1 bit 11 Stop bit

Break

TXIF bit

(Transmit

Interrupt Flag)

TX (pin)

TRMT bit

(Transmit Shift

Empty Flag)

SENDB

(send Break

control bit)

SENDB Sam ple d Here Auto Cleared

PIC16F882/883/884/886/887

12.4 EUSART Synchronous Mode

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary cir-

cuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

There are t wo signal lines in Synchronous mode: a bidi-

rectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The EUSART can operate as either a master or slave

device.

Start and Stop bits are not used in synchronous

transmissions.

12.4.1 SYNCHRONOUS MASTER MODE

The following bits are used to configure the EUSART

for Synchronous Master operation:

• SYNC = 1

• CSRC = 1

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTA register configures

the de vi c e f or sy n ch ron ous opera tion. Setti ng the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCST A

regis ter ensures th at the dev ic e i s in th e Tra ns m it mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSAR T. If the RX/DT or TX/CK pins are shared with an

analog peripheral the analog I/O functions must be

disab le d by c le aring the co rre sp on ding ANSE L b its.

12.4.1.1 Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device config-

ured as a master transmit s the c lock on the TX/CK lin e.

The TX/CK pin output driver is automatically enabled

when the EUSART is configured for synchronous

transmit or receive operation. Serial data bits change

on the le ading edg e to ensure they are v alid at the trail-

ing edge of each clock. One clock cycle is generated

for each data bit. Only as many clock cycles are

generated as there are data bits.

12.4.1.2 Clock Polarity

A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the SCKP

bit of the BAUDCTL register. Setting th e SCKP bit sets

the clock Idle state as high. When the SCKP bit is set,

the data changes on the falling edge of each clock.

Clearing the SCKP bit sets the Idle state as low. When

the SCKP bit is cle ared, the da ta ch anges on the rising

edge of each clock.

12.4.1.3 Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/C K pi n outp ut driv ers ar e aut oma t-

ically enabled when the EUSART is configured for

synchronous master transmit operation.

A transmission is initiated by writing a character to the

TXREG reg is ter. If the TSR st ill co nt a ins al l or part of a

previous character the new character dat a is held in the

TXREG until the last bit of the previous character has

been tr ansmitted. If this is the first charac ter , or the pre-

vious character has been completely flushed from the

TSR, the d ata in th e TXREG is im mediatel y transferre d

to the TSR. The transmission of the character com-

mences immediately following the transfer of the data

to the TSR from the TXREG.

Each data bit changes on the leading edge of the

master clock and remains valid until the subsequent

leading clock edge.

12.4.1.4 Synchronous Master Transmission

Set-up:

1. Initialize the SPBRGH, SPBRG register p air and

the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 12.3 “EUSART

Baud Rate Generator (BRG)”).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

3. Disable Receive mode by clearing bits SREN

and CREN.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

8. S tart transmission b y loadin g data to the TXREG

Note: The TSR register is not mapped in data

memory, so it is not available to the user.

PIC16F882/883/884/886/887

FIGURE 12-10: SYNCHRONOUS TRANSMISSION

FIGURE 12-11: SYNCHRONOUS TRA NSM ISSION (THROUGH TXEN)

TABLE 12-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOR

Value on

all other

Resets

BAUDCTL ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 01-0 0-00 01-0 0-00

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

RCREG EUSART Receive Data Register 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXREG EUSART Transmit Data Register 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.

bit 0 bit 1 bit 7

Word 1 bit 2 bit 0 bit 1 bit 7

RX/DT

Write to

TXREG Reg

TXIF bit

(Interrupt Flag)

TXEN bit ‘1’ ‘1’

Word 2

TRMT bi t

Write Word 1 Write Word 2

Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

TX/CK p in

TX/CK pin

(SCKP = 0)

(SCKP = 1)

RX/DT pin

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

bit 0 bit 1 bit 2 bit 6 bit 7

TXEN bi t

PIC16F882/883/884/886/887

12.4.1.5 Synchronous Master Reception

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

EUSAR T is config ured fo r synch ronous master receiv e

operation.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the com pletio n of one c har acter. When CREN is set,

clocks are continuously generated until CREN is

cleared . If CREN is cleared in the middle of a c haracter

the CK clo ck sto p s imm ed iat ely and t he p a rtia l charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cl eared at the co mpletion of the first cha racter

and CREN takes precedence.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

receive d into the RSR, the RCI F bit is set and the ch ar-

acter is automatically transferred to the two character

receive FIFO. The Least Sign ificant e ight bit s of the to p

character in the receive FIFO are available in RCREG.

The RCIF bit remains set as long as there are un-read

characters in the receive FIFO.

12.4.1.6 Slave Clock

Synchronous data transfers use a separate clock line,

which is synchronous wi th the data. A device configured

as a slave receives the cloc k on the TX/CK line . The TX/

CK pin output driver is automatically disabled when the

device is configured for synchronous slave transmit or

receive operation. Serial dat a bits change on the leading

edge to ensure they are valid at the trailing edge of each

clock. One data bit is transferred for each clock cycle.

Only as many clock cycles should be received as there

are data bits.

12.4.1.7 Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be genera ted if a th ird charac ter , in it s

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be recei ved until the erro r is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set then th e error conditi on is cleared b y either clearin g

the CREN bit of the RCSTA register or by clearing the

SPEN bit which resets the EUSART.

12.4.1.8 Receiving 9-bit Characters

The EUSAR T support s 9-bit chara cter receptio n. When

the RX9 bit of the RCSTA register is set the EUSART

will shift 9-bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

charact er i n t he rec eiv e FIFO . Whe n r ead ing 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read befo re reading the 8 Le ast Signifi cant bit s from

the RCREG.

12.4.1.9 Synchronous Master Reception Set-

up:

1. Initialize the SPBRGH, SPBRG register pair for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Ensure bits CREN and SREN are clear.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit reception is desired, set bit RX9.

6. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

7. Interrupt fla g bit RCIF will be se t when recep tion

of a character is complete. An interrupt will be

generated if the enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG register.

10. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

the EUSART.

PIC16F882/883/884/886/887

FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOR

Value on

all other

Resets

BAUDCTL ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 01-0 0-00 01-0 0-00

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

RCREG EUSART Receive Data Register 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXREG EUSART Transmit Data Register 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

CREN bit

RX/DT

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

‘0’

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

‘0’

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TX/CK pin

(SCKP = 0)

(SCKP = 1)

PIC16F882/883/884/886/887

12.4.2 SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for Synchronous slave operation:

• SYNC = 1

• CSRC = 0

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TX STA reg ister configur es the device as a slave.

Clearing the SREN and CREN bits of the RCST A register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART. If the RX/DT or TX/CK pins are shared with an

analog peripheral the analog I/O functions must be

disabled by clearing the corresponding ANSEL bits.

12.4.2.1 EUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes are identical (see Section 12.4.1.3

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

1. The first character will immediately transfer to

the TSR register and transmit.

2. The seco nd word wil l remain in TXR EG registe r .

3. The TXIF bit will not be set.

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

5. If the PEIE and TXIE bits are set, the interrupt

will wa ke the dev ice from Sleep and e xecute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

12.4.2.2 Synchronous Slave Transmission

Set-up:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the CREN and SREN bits.

3. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

4. If 9-bit transmission is desired, set the TX9 bit.

5. Enable transmission by setting the TXEN bit.

6. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

7. Start transmission by writing the Least

Significant 8 bits to the TXREG register.

TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOR

Value on

all other

Resets

BAUDCTL ABDOVF RCIDL —SCKPBRG16 —WUE ABDEN 01-0 0-00 01-0 0-00

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

RCREG EUSART Receive Data Register 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXREG EUSART Transmit Data Register 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.

PIC16F882/883/884/886/887

12.4.2.3 EUSART Synchronous Slave

Reception

The operation of the Synchronous Master and Slave

modes is identical (Section 12.4.1.5 “Synchronous

Master Reception”), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is

nev er Idle

• SREN bit, whic h is a “don't ca re” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is rec eived, th e RSR regist er will tran sfer the da ta

to the RCREG register . If the RCIE enable bit is set, the

interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

12.4.2.4 Synchronous Slave Reception Set-

up:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

3. If 9-bit reception is desired, set the RX9 bit.

4. Set the CREN bit to enable reception.

5. The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

6. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

7. Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

8. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

the EUSART.

TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOR

Value on

all other

Resets

BAUDCTL ABDOVF RCIDL —SCKPBRG16 —WUE ABDEN 01-0 0-00 01-0 0-00

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

RCREG EUSART Receive Data Register 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXREG EUSART Transmit Data Register 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.

PIC16F882/883/884/886/887

12.5 EUSART Operation During Sleep

The EUSART WILL remain active during Sleep only in

the Synchronous Slave mode. All other modes require

the system clock and therefore cannot generate the

necessary signals to run the Transmit or Receive Shift

registers during Sleep.

Synchronous Slave mode uses an exte rnally generated

clock to run the Transmit and R eceive Shift regis ters.

12.5.1 SYNCHRONOUS RECEIVE DURING

SLEEP

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configu red for Synchron ous Slave Recep tion (see

Section 12.4.2.4 “Synchronous Slave

Reception Set-up:”).

• If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

• The RCIF interrupt flag must be cleared by read-

ing RCREG to unload any pending characters in

the receive buffer.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the da ta word has b een c om ple tel y

clocked in by the external device, the RCIF interrupt

flag bi t of th e PIR1 regis ter will be s et. The reb y, waking

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the GIE global

interrupt enable bit of the INTCON register is also set,

then the Interrupt Service Routine at address 004h will

be called.

12.5.2 SYNCHRONOUS TRANSMIT

DURING SLEEP

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Transmission

(see Section 12.4.2.2 “Synchronous Slave

Transmission Set-up:”).

• The TXIF interru pt flag must be c leared by writing

the output data to the TXREG, thereby filling the

TSR and transmit buffer.

9. If interrupts are desired, set the TXIE bit of the

PIE1 register and the PEIE bit of the INTCON

• Interru pt enable bits T XIE of the PIE1 re gister and

PEIE of the INTCON register must set.

Upon entering Sleep mode, the device will be ready to

accept clocks on TX/CK pin and transmit data on the

RX/DT pin. When the data word in the TSR has been

completely clocked out by the external device, the

pending byte in the TXREG will tra nsfer to the TSR an d

the TXIF flag will be set. Thereby, waking the processor

from Sleep. At this point, the TXREG is available to

accept another character for transmission, which will

clear the TXIF flag.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the GIE global

interrupt enable bit is also set th en the Interrupt Service

Routine at address 0004h will be called.

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

13.0 MASTE R SYNCHRONOUS

SERIAL PORT (MS SP)

MODULE

13.1 Master SSP (MSSP) Module

Overview

The Master Synchronous Serial Port (MSSP) module is

a serial interface useful for communicating with other

periphera l or m icroc ontroll er dev ices. Th ese p eriphera l

devices may be Serial EEPROMs, shift registers,

displa y drivers, A/D converte rs, etc. The MSSP modul e

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated CircuitTM (I2CTM)

- F ull Master mode

- Slave mode (with general address call).

The I2C interface supports the following modes in

hardware:

•Master mode

• Multi-Master mode

• Slave mode.

13.2 Control Registers

The MSSP module has three associated registers.

These include a STATUS register and two control

registers.

(SSPSTAT), Register 13-2 shows the MSSP Control

MSSP Control Register 2 (SSPCON2).

PIC16F882/883/884/886/887

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A PSR/WUA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Sample bit

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

In I2 C Master or Slave mode:

1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for high speed mode (400 kHz)

bit 6 CKE: SPI Clock Edge Select bit

CKP = 0:

1 = Data transmitted on rising edge of SCK

0 = Data transmitted on falling edge of SCK

CKP = 1:

1 = Data transmitted on falling edge of SCK

0 = Data transmitted on rising edge of SCK

bit 5 D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit

(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Res et)

0 = Stop bit was not detected last

bit 3 S: Start bit

(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Re set)

0 = Start bit was not detected last

bit 2 R/W: Read/Write bit information (I2C mode only)

This bit holds the R / W bi t i nformati on fo llow ing the las t addr ess match. T hi s bi t is on ly v alid from the ad dres s ma tch to

the next Start bit, Stop bit, or not ACK bi t.

In I2 C Slave mode:

1 = Read

0 = Write

In I2 C Master mode:

1 = Transmit is in progress

0 = Transmit is not in progress

OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in Idle mode.

bit 1 UA: Update Address bit (10-bit I2C mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

Receive (SPI and I2 C modes):

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Transmit (I2 C mode only):

1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full

0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

PIC16F882/883/884/886/887

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

Legend:

R = Rea da b l e bi t W = Writab l e b it U = Un i m pl e m e nted bi t , re ad as ‘ 0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

Master mode:

1 = A write to the SSPBUF register was attemp ted while the I 2C condition s were n ot valid f or a trans mission t o be star ted

0 = No collision

Slave mode:

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)

0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit

In SPI mode:

1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow , the data in SSPSR

is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting

data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is

initia ted by writ ing t o th e SS PBUF re gist er (must be cle ar ed in sof twar e).

0 = No overflow

In I2 C mode:

1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit

mode (must be cleared in software).

0 = No overflow

bit 5 SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly confi gured as input or output

In SPI mode:

1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins

0 = Disables serial port and configures these pins as I/O port pins

In I2 C mode:

1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: Clock Polarity Select bit

In SPI mode:

1 = Idle state for clock is a high lev el

0 = Idle state for clock is a low level

In I2 C Slave mode:

SCK release control

1 = Enable clock

0 = Holds clock low (clock stretch ). (Used to ensure data setup time.)

In I2 C Master mode:

Unused in this mode

bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000 = SPI Master mode, cloc k = FOSC/4

0001 = SPI Master mode, cloc k = FOSC/16

0010 = SPI Master mode, cloc k = FOSC/64

0011 = SPI Master mode, clock = TMR2 output/2

0100 = SPI Slave mode, clock = SC K pin, SS pin co ntrol enabled

0101 = SPI Slave mode, clock = SC K pin, SS pin co ntrol disabled, SS can be used as I/O pin

0110 = I2C Slave mode, 7-bit address

0111 = I2C Slave mode, 10-bit address

1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))

1001 = Load Mask function

1010 = Reserved

1011 = I2C firmware controlled Master mode (Slave idle)

1100 = Reserved

1101 = Reserved

1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

PIC16F882/883/884/886/887

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)

1 = Enable interrupt when a general call address (0000h) is received in the SSPSR

0 = General call address disabled

bit 6 ACKSTAT: Acknowledge Status bit (in I2C Master mode only)

In Master Transmit mode:

1 = Acknowledge was not received from slave

0 = Acknowledg e was receiv ed fr om slave

bit 5 ACKDT: Acknowledge Data bit (in I2C Master mode only)

In Master Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1 = Not Acknowl edge

0 = Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mo de only)

In Master Receive mode:

1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0 = Acknowledge sequence idle

bit 3 RCEN: Receive Enable bit (in I2C Master mode only)

1 = Enables Receive mode for I2C

0 = Receive idle

bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)

SCK Release Control:

1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Stop condition Idle

bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)

1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Repeated Start condition Idle

bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only)

In Master mode:

1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Start condition Idle

In Slave mode:

1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0 = Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be

set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

PIC16F882/883/884/886/887

13.3 SPI Mode

The SPI mode allows 8 bits of data to be sy nchronous ly

transmitted and received, simultaneously . All four modes

of SPI are supported. To accomplish communication,

typically thre e pins are use d:

• Serial Data Out (SDO) – RC5/SDO

• Serial Data In (SDI) – RC4/SDI/SDA

• Serial Clock (SCK) – RC3/SCK/SCL

Additionally, a fourth pin may be used when in any

Slave mode of operation:

• Slave Select (SS) – RA5/SS/AN4

13.3.1 OPERATION

When initializing the SPI, several options need to be

specif ied. This is done by progra mming the ap propriate

control bits SSPCON<5:0> and SSPSTAT<7:6>.

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock polarity (Idle state of SCK)

• Data input sample phase (middle or end of data

output time)

• Clock edge (output data on rising/falling edge of

SCK)

• Clock rate (Master mode only)

• Slave Select mode (Slave mode only)

Figure 13-1 shows the block diagram of the MSSP

module, when in SPI mode.

FIGURE 13-1: MSSP BLOCK DIAGRAM

(SPI MODE)

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buf fer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR,

until the received data is ready. Once the 8 bits of data

have bee n received, that byte is m oved to the SSPBUF

STAT register and the interrupt flag bit SSPIF of the

PIR1 register are set. This double buffering of the

received data (SSPBUF) allows the next byte to start

reception before reading the data that was just

received. Any write to the SSPBUF register during

transmission/reception of data will be ignored, and the

write coll ision detect bi t WCOL of the SSPCON register

will be set. User software must clear the WCOL bit so

that it can be determined if the following write(s) to the

SSPBUF register completed successfully.

( )

Read Write

Internal

Data Bus

SSPSR Reg

SSPM<3:0>

bit 0 Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 Output

TOSC

Prescaler

4, 16, 64

Edge

Select

Data to TX/RX in SSPSR

TRIS bit

SMP:CKE

SDI

SDO

SCK

Note: I/O pins have diode protection to VDD and VSS.

SSPBU F Reg

PIC16F882/883/884/886/887

When the application software is expecting to receive

valid da ta, the SSPBUF shoul d be read before th e next

byte of data to transfer is written to the SSPBUF. The

buffer full bit BF of the SSPSTAT register indicates

when SSPBUF has been loaded wi th the recei ved data

(transmi ssion is co mplete). When th e SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a tra nsmitter . Generally, the MSSP Interru pt

is used to determine when the transmission/reception

has completed. The SSPBUF must be read and/or

written. If the interrupt method is not going to be used,

then sof tware pol ling can be d one to ensure that a write

collision does not occur. Example 13-1 shows the

loading of the SSPBUF (SSPSR) for data transmission.

The SSPSR is not directly readable or writable, and

can only be accessed by addressing the SSPBUF

(SSPSTAT register) indicates the various status

conditions.

13.3.2 ENABLING SPI I/O

To enable the se rial port, SSP Enabl e bit SSPEN of the

SSPCON register must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON registers, and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port

function, some must have their data direction bits (in

the TRIS register) appropriately programmed. That is:

• SDI i s a utom atically c ont roll ed by the SPI module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit

cleared

• SCK (Slave mode) must have TRISC<3> bit set

•SS

must have TRISA<5> bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

EXAMPLE 13-1: LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?

GOTO LOOP ;No

MOVF SSPBUF, W ;WREG reg = contents of SSPBUF

MOVWF RXDATA ;Save in user RAM, if data is meaningful

MOVF TXDATA, W ;W reg = contents of TXDATA

MOVWF SSPBUF ;New data to xmit

PIC16F882/883/884/886/887

13.3.3 MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave is to broadcast data by the software

protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF registe r is written to. If the SPI is

only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSPSR register

will co ntinue to shift in the signal pre sent on the SDI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

a normal received byte (interrupts and Status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

The clock polarity is selected by appropri ately pro gram-

ming the CKP bit of the SSPCON register. This, then,

would give waveforms for SPI communication as

shown in Figure 13-2, Figure 13-4 and Figure 13-5,

where t he MSb is tra nsmitted first. In Ma ster mode, th e

SPI clock ra te (bit rate) is user programmable t o be one

of the fo llowing:

•F

OSC/4 (or TCY)

•FOSC/16 (or 4 • TCY)

•F

OSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 13-2 shows the waveforms for Master mode.

When the CKE bit of the SSPSTAT register is set, the

SDO dat a is val id befo re ther e is a cl ock edge on SCK.

The chang e of th e input sa mple is show n base d on the

state of the SM P bi t o f th e SSPSTAT register. T he time

when the SSPBUF is loaded with the received data is

shown.

FIGURE 13-2: SPI MODE WAVEFORM (MASTER MODE)

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit7 bit 0

SDI

SSPIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)

Next Q4 Cycle

after Q 2 ↓

PIC16F882/883/884/886/887

13.3.4 SLAVE MODE

In Slave m ode , the data is trans mi tted and rece iv ed as

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit of the

PIR1 register is set.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times, as

specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from Sleep.

13.3.5 SLAVE SELECT

SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control

enabled (SSPCON<3:0> = 04h). The pin must not

be driven low for the SS pin to function as an input.

The Data Latch must be high. When the SS pin is

low, transmission and reception are enabled and

the SDO pin is driven. When the SS pin goes high,

the SDO pin is no longer driven, even if in the mid-

dle of a transmitted byte, and becomes a floating

output. External pull-up/pull-down resistors may be

desirable, depending on the application.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level, or clearing the SSPEN bit.

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an in put. This d isables transmissi ons from th e SDO.

The SDI can always be left as an input (SDI function),

since it can not cre ate a bus con f li ct .

FIGURE 13-3: SLAVE SY NCHRONIZATION WAVEFORM

Note 1: When the SPI is in Slave mode with SS

pin control enabled (SSPCON<3:0> =

0100), the SPI module will reset if the SS

pin is set to VDD.

2: If the SPI is us ed in Slave mo de with CK E

set (SSPSTAT register), then the SS pin

control must be enabled.

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI bit 7

SDO bit 7 bit 6 bit 7

SSPIF

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

bit 0

bit 7 bit 0

Next Q4 Cycle

after Q2↓

PIC16F882/883/884/886/887

FIGURE 13-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 13-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPIF

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Optional

Next Q4 Cycle

after Q2↓

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPIF

(SMP = 0)

CKE = 1)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Required

Next Q4 Cycle

after Q2↓

PIC16F882/883/884/886/887

13.3.6 SLEEP OPERATION

In Master mode, all module clocks are halted, and the

transmission/reception will remain in that state until the

device wakes from Sleep. After the device returns to

normal mode, the module will continue to transmit/

receive data.

In Slave mode, the SPI transmit/receive shift register

operat es asy nchron ously to the devi ce. Th is al lows the

device to be placed in Sleep mode and data to be

shifted into the SPI transmit/receive shift register.

When all eight bits have been received, the MSSP

inter rupt flag bit wi ll be set and , if enabled, will wake th e

device from Sleep.

13.3.7 EFFECTS OF A RESET

A Reset disable s the MSSP module and termina tes the

current transfer.

13.3.8 BUS MODE COMPATIBILITY

Table 13-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 13-1: SPI BUS MODES

There is al so a SMP b it that co ntrols when the da t a will

be sampled.

TABLE 13-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Standard SPI Mode

Terminology Control Bits State

CKP CKE

0, 001

0, 100

1, 011

1, 110

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

RESETS

INTCON GIE/GIEH PEIE/GIEL T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 0000 0000

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: x = unknow n , u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.

Note 1: Bit 6 of PORTA, LA TA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and

read ‘0’.

PIC16F882/883/884/886/887

13.4 MSSP I2C Operation

The MSSP module in I2C mode, fully implements all

master and slave functions (including general call

support) and provides interrupts on S ta rt and S top bits in

hardware, to determine a free bus (Multi-Master mode).

The MSSP module implements the standard mode

specifications, as well as 7-bit and 10-bit addres sing.

T wo pins are used for dat a transfer . These are the RC3/

SCK/SCL pin, which is the clock (SCL), and the RC4/

SDI/S DA pin, which i s the data ( SDA). T he user mu st

configure these pins as inputs or outputs through the

TRISC<4:3> bits.

The MSSP module functions are enabled by setting

MSSP Enable bit SSPEN of the SSPCON register.

FIGURE 13-6: MSSP BLOCK DIAGRAM

(I2C MODE)

The MSSP module has these six registers for I2C

operation:

• MSSP Control Register 1 (SSPCON)

• MSSP Control Register 2 (SSPCON2)

• MSSP STATUS register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly

accessible

• MSSP Address register (SSPADD)

• MSSP Mask register (SSPMSK)

The SSPCON register allows control of the I2C

operation. The SSPM<3:0> mode selection bits

(SSPCON register) allow one of the following I2C modes

to be selected:

•I

2C Master mode, clock = OSC/4 (SS PADD +1)

•I

2C Slave mode (7-bit address)

•I

2C Slave mode (10-bit address)

•I

2C Slave mode (7-bit address), with Start and

Stop bit interrupts enabled

•I

2C Slave mode (10-bit address), with Start and

Stop bit interrupts enabled

•I

2C firmw are co ntrolle d master op erat ion, slav e is

idle

Selection of any I2C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open drain,

provided these pins are programmed to be inputs by

setting the appropriate TRISC bits.

13.4.1 SLAVE MODE

In Slave mode, the SCL and SDA pins must be

configured as inputs (TRISC<4:3> set). The MSSP

module will overrid e the input sta te with the ou tput dat a

when required (slave-transmitter).

When an address is m atc he d, or the data tra ns fer after

an address match is received, the hardware

automatically will generate the Acknowledge (ACK)

pulse and load the SSPBUF register with the received

value currently in the SSPSR register.

If either or b oth o f the followin g co nd itio ns are tru e, th e

MSSP module will not give this ACK pulse:

a) The buf fer full bit BF (SSPCON regis ter) was set

before the transfer was received.

b) The overflow bit SSPOV (SSPCON register)

was set before the transfer was received.

In this event, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF of the PIR1 register is

set. The BF bit is cleared by reading the SSPBUF

The SCL clock input must have a minimum high and

low fo r pro per ope rati on. The high an d l ow ti me s o f th e

I2C specification, as well as the requirement of the

MSSP module, are shown in timing parameter #100

and parameter #101.

Read Write

SSPSR Reg

Match Detect

SSPADD Reg

Start and

Stop bit Detect

SSPBUF Reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT Reg)

RC3/SCK/SCL

RC4/

Shift

Clock

MSb

SDI/ LSb

SDA

Note: I/O pins have diode protection to VDD and VSS.

SSPMSK Reg

PIC16F882/883/884/886/887

13.4.1.1 Addressing

Once the MSSP module has been enabled, it waits for

a Start cond ition to oc cur. Followin g the St art condi tion,

the eight bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

a) The SSPSR register value is loaded into the

SSPBUF register.

b) The buffer full bit BF is set.

c) An ACK pulse is generated.

d) MSSP interrupt flag bit, SSPIF of the PIR1

SCL pulse (interrupt is generated, if enabled).

In 10-bit address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSb) of the first address byte specify if this is a 10-bit

address. The R/W bit (SSPSTA T register) mu st specif y

a write so the slave device will receive the second

address by te. F or a 10 -bi t add res s, t he fi rst byt e woul d

equal ‘1111 0 A9 A8 0’, where A9 and A8 are the

two MSb’s of the address.

The sequence of events for 10-bit addressing is as

follows, with steps 7-9 for slave-transmitter:

1. Receive first (high) byte of address (bit SSPIF of

the PIR1 register and bits BF and UA of the

SSPSTAT register are set).

2. Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

4. Receive second (low) byte of address (bits

SSPIF, BF, and UA are set).

5. Update the SSPADD register with the firs t (high)

byte of address. If match releases SCL line, this

will clear bit UA.

6. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

7. Receive Repeated Start condition.

8. Receive first (high) byte of address (bits SSPIF

and BF are set).

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

13.4.1.2 Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overflow condition exists, then

no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPST AT register)

is set, or bit SSPOV (SSPCON register) is set.

An MSSP interrupt is generated for each data transfer

byte. Flag bit SSPIF of the PIR1 register must be

cleared in software. The SSPSTAT register is used to

determine the status of the byte.

13.4.1.3 Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RC3/SCK/SCL is held

low. The transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR regis-

ter. Then pin RC3/SC K/SC L s ho uld be e na ble d by se t-

ting bit CKP (SSPCON register). The master must

monitor the SCL pin prior to asserting another clock

pulse. T he slave devices may be h olding of f th e master

by stretching the clock. The eight data bits are shifted

out on the falling edge of the SCL input. This ensures

that the SDA signal is valid during the SCL high time

(Figure 13-8).

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

As a s lav e-t rans mi tte r, the ACK puls e from the mast er-

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line is high (not ACK), then the

data transfer is complete. When the ACK is latched by

the slave, the slave logic is reset and the slave moni-

tors for another occurrence of the Start bit. If the SDA

line was low (ACK), the transmit data must be loaded

into the S SPBUF register, which also lo ads the SSPSR

setting bit CKP.

PIC16F882/883/884/886/887

FIGURE 13-7: I2C™ SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

FIGURE 13-8: I2C™ SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

765

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1SDA

SCL 1234567891234567891234

Bus Master

Terminates

Transfer

Bit SSPOV is set because the SSPBUF register is still full

Cleared in software

SSPBUF register is read

ACK Receiving Data

Receiving Data D0

D3D4

D6D7

ACK

R/W = 0

Receiving Address

SSPIF

SSPOV

Not ACK

ACK is not sent

SDA

SCL

SSPIF

CKP

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 Not ACKTransmitting DataR/W = 1Receiving Address

123456789 123456789 P

Cleared in software

SSPBUF is written in software From SSP Interrupt

Service Routine

Set bit after writing to SSPBUF

SData in

Sampled

(the SSPBUF must be written to

before the CKP bit can be set)

R/W = 0

responds to SSPIF

SCL held low

while CPU

PIC16F882/883/884/886/887

13.4.2 GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I2C bus is such that,

the first byte after the Start condition usually deter-

mines which device will be the slave addressed by the

master. The exception is the general call address,

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all 0’s with R/W = 0.

The gene ral call add ress is recog nized (ena bled) when

the General Call Enable (GCEN) bit is set (SSPCON2

shifted into the SSPSR and the address is compared

agains t the SSP AD D. It is also c ompared to the genera l

call address and fixed in hardware.

If the general call address matches, the SSPSR is

transferre d to the SSPBUF, the BF bit is set (eigh th bit),

and on the falling edge of the ninth bit (ACK bit), the

SSPIF interrupt flag bit is set.

When the i nterrupt is serv iced, the source f or the inter-

rupt can be checked by reading the contents of the

SSPBUF. The value can be used to determine if the

address was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the secon d half of the address to match , and the UA

bit is set (SSPST A T register). If the general call address

is sampled when the GCEN bit is set, and while the

slave is configured in 10-bit address mode, then the

second half of th e address is not n ecessary. The UA bit

will not be set, and the slave will begin receiving data

after the Acknowledge (Figure 13-9).

FIGURE 13-9: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS)

SDA

SCL S

SSPIF

SSPOV

Cleared in software

SSPBUF is read

R/W = 0ACK

General Call Address

Address is compared to General Call Address

GCEN

Receiving Data ACK

123456789123456789

D7 D6 D5 D4 D3 D2 D1 D0

after ACK, set interru pt

‘0’

‘1’

PIC16F882/883/884/886/887

13.4.3 MASTER MODE

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared

from a Reset, or when the MSSP module is disabled.

Control of the I 2C bus may be taken when the P bit is

set, or the bus is idle, with both the S and P bits clear.

In Master mode, the SCL and SDA lines are manipu-

lated by the MSSP hardware.

The following events will cause SSP Interrupt Flag bit,

SSPIF, to be set (SSP Interrupt if enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

• Acknowledge t ransmit

• Repeated Start condition

13.4.4 I2C™ MASTER MODE SUPPORT

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON and by setting the

SSPEN bit. Once Master mode is enabled, the user

has the follow i ng six optio ns :

1. Assert a Start condition on SDA and SCL.

2. Assert a Repeated Start condition on SDA and

SCL.

3. Write to the SSPBUF register initiating

transmission of data/address.

4. Generate a Stop condition on SDA and SCL.

5. Config ure the I2C port to receive data.

6. Ge nera te an Ack nowl edge c ondit ion at t he end

of a received byte of data.

FIGURE 13-10: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)

Note: The MSSP modu le, when configured in I2C

Master mode, does not allow queueing of

events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPBUF register to

imitate transmission, before the Start

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, ind icating tha t a write

to the SSPBUF did not occur.

Read Write

SSPSR

Start bit, Stop bit,

SSPBUF

Internal

Data Bus

Set/Res e t, S, P, WCO L (SSPSTAT )

Shift

Clock

MSb LSb

SDA

Acknowledge

Generate

SCL

SCL In

Bus Collision

SDA In

Receive Enable

Clock Cntl

Clock Arbitrate/WCO L Detect

(hold off clock source)

SSPADD<6:0>

Baud

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

Rate

Generator

SSPM<3:0>

Note: I/O pins have diode protection to VDD and VSS.

Star t b it De te ct

Stop bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

End of XMIT/RCV

PIC16F882/883/884/886/887

13.4.4.1 I2C™ Master Mode Operation

The master device generates all of the serial clock

pulses and the S t a rt and Stop condition s. A transfer i s

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer , the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

recei vin g dev ice ( 7 bits) and the Rea d/Writ e (R/ W) bit.

In this case, the R/W bit wi ll be lo gic ‘0’ . S eri al d ata is

transmi tted eight bits a t a time. Af ter each byte is trans-

mitted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master Rec eive mode , the first byte transm itted con-

tains the slave address of the transmitting device

(7 bits) and th e R/W bit. In this case, the R/W bit w ill b e

logic ‘ 1’. Thus, the first byte transmitted is a 7-bit slave

addr ess f oll owed by a ‘1’ to indicate receive bit. Serial

data is rece ived via S DA, while SCL o utp uts the se ri al

clock. Serial data is received eight bits at a time. After

each byte is received, an Acknowledge bit is transmit-

ted. Start and Stop conditions indicate the beginning

and end of transmission.

The Baud R ate Generator us ed for the SPI mod e oper-

ation is now used to set the SCL clock frequency for

either 100 kHz, 400 kHz, or 1 MHz I2C operation. The

Baud Rate Generator reload value is contained in the

lower 7 bits of the SSPADD register. The Baud Rate

Generator will automatically begin counting on a write

to the SSPBUF. Once the given operation is complete

(i.e., transmission of the last data bit is followed by

ACK), the internal clock will automatically stop counting

and the SCL pin will remain in its last state.

A typical transmit sequence would go as follows:

a) The user generates a Start condition by setting

the Sta rt Enab le (SEN) bit (SSPCON2 regi ster).

b) SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

c) The user loa ds the SSPBUF with the addres s to

transmit.

d) Address is shifted out the SDA pin until all eight

bits are transmitted.

e) The MSSP module sh ift s in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit (SSPCON2 register).

f) Th e MSSP module g enerate s an interrup t at th e

end of th e ninth c lock cyc le by settin g the SSPIF

bit.

g) The user loads the SSPBUF with eight bits of

data.

h) Dat a is shi fte d out the SD A pin un til all e ight bit s

are transmitted.

i) The MSSP modu le shift s in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit (SSPCON2 register).

j) The MSSP modul e gene rates an int errupt a t the

end of th e ninth c lock cyc le by settin g the SSPIF

bit.

k) The user generates a Stop condition by setting

the Stop Enable bit PEN (SSPCON2 register).

l) Interru pt is genera ted once the Stop condition i s

complete.

PIC16F882/883/884/886/887

13.4.5 BAUD RATE GENERATOR

In I2C Master mode, the reload value for the BRG is

located in the lower 7 bits of the SSPADD register

(Figure 13-11). When the BRG is loaded with this

value, the BRG counts down to 0 and stops until

another reload has taken place. The BRG count is

decremented twice per instruction cycle (TCY) on the

Q2 and Q4 clocks. In I2C Master mode, the BRG is

reloaded automatically. If clock arbitration is taking

place, for instance, the BRG will be reloaded when the

SCL pin is sampled high (Figure 13-12).

FIGURE 13-11: BAUD RATE GENERATOR BLOCK DIAGRAM

FIGURE 13-12: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SSPM<3:0>

BRG Down Counter

CLKOUT FOSC/4

SSPADD<6:0>

SSPM<3:0>

SCL

Reload

Control Reload

SDA

SCL

SCL de-asserted but slave holds

DX-1DX

BRG

SCL is sampled high, reload takes

place and BRG starts it s count

03h 02h 01h 00h (hold off) 03h 02h

Reload

BRG

Value

SCL low (clock arbitration) SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

PIC16F882/883/884/886/887

13.4.6 I2C™ MASTER MODE START

CONDITION TIMING

To initiate a Start condit ion, the user sets the S tar t Con-

dition Enable bit SEN of the SSPCON2 register. If the

SDA and SCL pins are sampled high, the Baud Rate

Generator is reloaded with the contents of

SSPADD<6:0> and start s its count. If SCL and SDA a re

both sampled high when the Baud Rate Generator

times out (TBRG), the SDA pin is driven low. The action

of the SDA being driven low, while SCL is high, is the

Start condition, and causes the S bit of the SSPSTAT

ator is reloaded with the contents of SSPADD<6:0>

and res umes it s co unt. When the Baud Rate G enerator

times out (T BRG), the SEN bit of th e SSPCON2 regis ter

will be automatically cleared by hardware, the Baud

Rate Generator is suspended leaving the SDA line held

low and the Start condition is complete.

13.4.6.1 WCOL Status Flag

If the user writes the SSPBUF when a Start sequence

is in progress, the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

FIGURE 13-13: FIRST START BIT TIMING

Note: If, at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low, or if during the Start conditio n the

SCL line is sampled low before the SDA

line is driven low , a bus collision occurs, the

Bus Collision Interrupt Flag, BCLIF, is set,

the Start condition is aborted, and the I2C

module is reset into its Idle state.

Note: Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the Start

conditi on is complete.

SDA

SCL

TBRG

1st Bit 2nd Bit

TBRG

SDA = 1, At completion of Start bit,

SCL = 1

Write to SSPBUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here Set S bit (SSPSTAT)

and sets SSPIF bit

PIC16F882/883/884/886/887

13.4.7 I2C™ MASTER MODE REPEATED

START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit

(SSPCON2 register) is programmed high and the I2C

logic module is in the Idle state. When the RSEN bit is

set, the SCL pin is asserted low. When the SCL pin is

sampled low, the Baud Rate Generator is loaded with

the contents of SSPADD<5:0> and begins counting.

The SDA pin is released (brought high) for one Baud

Rate Generator count (TBRG). When the Baud Rate

Generator times out, if SDA is sampled high, the SCL

pin will be de-asserted (brought high). When SCL is

sampled high, the Baud Rate Generator is reloaded

with the contents of SSPADD<6:0> and begins count-

ing. SDA and SCL mu st be sampled high for one TBRG.

This ac tion is then followed by assertio n of the SDA pin

(SDA = 0) for one TBRG, while SCL is high. Following

this, the RSEN bit (SSPCON2 reg ister) will be aut omat-

ically cleared and the Baud Rate Generator will not be

reloaded, leaving the SDA pin held low. As soon as a

Start condition is detected on the SDA and SCL pins,

the S bit (SSPSTAT register) wil l be set. The SSPIF bit

will no t be set unt il the Baud Rate Gene rator has timed

out.

Immediately following the SSPIF bit getting set, the

user may write the SSPBUF with the 7-bit address in

7-bit mode, or the default first address in 10-bit mode.

After the first eight bits are transmitted and an ACK is

received, the user may then tra nsmit an additional eight

bits of add ress (1 0-bit mod e), or ei ght bi ts o f dat a (7-b it

mode).

13.4.7.1 WCOL Status Flag

If the user writes the SSPBUF when a Repeated Start

sequenc e is in pro gress , the WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 13-14: REPEAT START CONDITION WAVEFORM

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

conditi on occ urs if:

• SDA is sampled l ow wh en SCL goes

from low-to-high.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data “1”.

Note: Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPCON2 is disabled until the Repeated

Start condition is complete.

SDA

SCL

Sr = Repeated Start

Write to SSPCON 2

Write to SSPBUF occurs here

Falling edge of ninth clock

End of Xmit

At completion of Start bit,

hardware clear RSEN bit

1st bit

Set S (SSPSTAT<3>)

TBRG

SDA = 1,

SCL (no change) SCL = 1

occurs here,

TBRG TBRG TBRG

and set SSPIF

PIC16F882/883/884/886/887

13.4.8 I2C™ MAST E R MODE

TRANSMISSION

Transmission of a data byte, a 7-bit address, or the

other half of a 10-bit address, is accomplished by sim-

ply writing a value to the SSPBUF register. This action

will set the Buffer Full bit, BF, and allow the Baud Rate

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDA pin after the falling edge of SCL is

asserted (see data hold time specification, parameter

106). SC L is held low for o ne Baud Rate G enerator roll-

ove r co un t ( TBRG). Data should be valid before SCL is

released high (see data setup time specification,

parameter 107). When the SCL pin is released high, it

is held that way for TBRG. The data on the SDA pin

must remain stable for that duration and some hold

time after the next falling edge of SCL. After the eighth

bit is shifted out (the falling edge of the eighth clock),

the BF bit is cleared and the master releases SDA,

allowing the slave device being addressed to respond

with an ACK bit during the ninth bit time, if an address

match occurs, or if data was received properly. The

status of ACK is written into the ACKDT bit on the fall-

ing edge of the ninth clock. If the master receives an

Acknowledge, the Acknowledge Status bit, ACKSTAT,

is cle are d. I f no t, the bit is s et. Af te r th e n int h c lo ck , th e

SSPIF bit i s s et and th e m aster clo ck (Ba ud Rate Gen-

erator) is suspended until the next data byte is loaded

into the SSPBUF, leaving SCL low and SDA

unchanged (Figure 13-15).

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL, until all

seven addres s bit s an d the R/W bit, a re com pleted . On

the falling edge of the eighth clock, the master will de-

assert the SDA pin, allowing the slave to respond with

an Ackno wledge. On th e fallin g edge of the n inth clock ,

the master will sample the SDA pin to see if t he address

was rec ognized by a sla ve. The st atus of the ACK bit is

loaded into the ACKSTAT Status bit (SSPCON2 regis-

ter). Following the falling edge of the ninth clock trans-

mission of the address, the SSPIF is set, the BF bit is

cleared and the Baud Rate Generator is turned off, until

another write to the SSPBUF takes p lac e, ho ldi ng SCL

low and allowing SDA to float.

13.4.8.1 BF Status Flag

In Transm it mo de, the BF bit (SS PSTAT register) is s et

when the CPU writes to SSPBUF, and is cleared when

all eight bits are shifted out.

13.4.8.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the buf-

fer are unchanged (the write doesn’t occur). WCOL

must be cleared in software.

13.4.8.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit (SSPCON2

Acknowledge (ACK = 0), and is set when the slave

does not Acknowledge (ACK = 1). A slave sends an

Acknowledge when it has recognized its address

(including a general call), or when the slave has

properly received its data.

13.4.9 I2C™ MASTER MODE RECEPTION

Master mode recepti on is enabl ed by progra mmin g the

Receive Enable bit, RCEN (SSPCON2 register).

The Baud Rate Generator begins counting, and on

each rollover, the state of the SCL pin changes (high-

to-low/low-to-high) and data is shifted into the SSPSR.

After the falling edge of the eighth clock, the RCEN bit

is automatically cleared, the contents of the SSPSR are

loaded into the SSPBUF, the BF bit is set, the SSPIF

flag bit is set and the Baud Rate Generator is sus-

pended from counting, holding SCL low. The MSSP is

now in Idle state, awaiting the next command. When

the buffer is read by the CPU, the BF bit is automati-

cally c leared . The us er can then s end an A cknowl edg e

bit at the end of reception, by setting the Acknowledge

Sequence Enable bit ACKEN (SSPCON2 register).

13.4.9.1 BF Status Flag

In receiv e op eration, the B F bit is s et whe n an add r es s

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

13.4.9.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when eight

bits are received into the SSPSR and the BF bit is

already set from a previous reception.

13.4.9.3 WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), th e WCOL bi t is set an d the conte nts of th e buffer

are unchanged (the write doesn’t occur).

Note: The MSSP module must be in an Idle state

before the R CEN bit is set, or the R CEN bit

will be disregarded.

PIC16F882/883/884/886/887

FIGURE 13-15 : I2C™ MASTER MODE WAVEFORM (T RANSMISSION, 7 OR 10-BIT ADDRESS)

SDA

SCL

SSPIF

SEN

A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0

ACK

Transmitting Data or Second Half

R/W = 0Transmit Address to Slave

123456789 123456789 P

Cleared in software service routine

SSPBUF is written in software

From SSP inter rupt

After Start condition, SEN cleared by hardware.

SSPBUF written with 7-bit address and R/W

start transmit

SCL held low

while CPU

responds to SSPIF

SEN = 0

of 10-bit Address

Write SSPCON2<0> SEN = 1

Start condition begins From slave, clear ACKSTAT bit SSPCON2<6>

ACKSTAT in

SSPCON2 = 1

Cleared in software

SSPBUF written

PEN

Cleared in software

R/W

PIC16F882/883/884/886/887

FIGURE 13-16 : I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1

SDA

SCL 12345678912345678 9 1234

Bus Master

terminates

transfer

ACK Receiving Data from Slave

Receiving Data from Slave D0

D3D4

D6D7

ACK

R/W = 1

Transmit Address to Slave

SSPIF

ACK is not sent

Write to SSPCON2<0> (SEN = 1)

Write to SSPBUF occurs here

ACK from Slave

Master configured as a receiver

by programming SSPCON2<3>, (RCEN = 1)PEN bit = 1

written her e

Data shifted in on falling edge of CLK

Cleared in software

Start XMIT

SEN = 0

SSPOV

SDA = 0, SCL = 1

while CPU

ACK

Last bit is shifted into SSPSR and

contents ar e unloaded into SSPBUF

Cleared in software

Set SSPIF interrupt

at end of receive

Set P bit

(SSPSTAT<4>)

and SSPIF

Cleared in

software

ACK from Master

Set SSPIF at end

Set SSPIF interrupt

at end of Acknowledge

sequence

Set SSPIF interrupt

at end of Acknow-

ledge sequ en ce

of receive

Set ACKEN start Acknowledge sequence

SSPOV is set because

SSPBUF is still full

SDA = ACKDT = 1

RCEN cleared

automatically

RCEN = 1 start

next receive

Write to SSPCON2<4>

to start Acknowledge sequence

SDA = ACKDT (SSPCON2<5>) = 0

RCEN cleared

automatically

responds to SSPIF

ACKEN

Begin Start Condition

Cleared in software

SDA = ACKDT = 0

PIC16F882/883/884/886/887

13.4.10 ACKNOWLEDGE SEQUENCE TIMING

An Acknowledge sequence is enabled by setting the

Acknowle dge Sequ ence Enable b it, ACKEN (SSPCON2

and the co ntents of th e Acknow ledge Data bit (ACKD T)

is pres ented on th e SDA pin. If the us er wish es to gener-

ate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The Baud Rate

Generato r then count s for one ro llover pe riod (TBRG) and

the SCL pin is de-asserted (pulled high). When the SCL

pin is sampled high (clock arbitration), the Baud Rate

Generator counts for TBRG. The SCL pin is then pulled

low. Following this, the ACKEN bit is automatically

cleared, the Baud Rate Generator is turned off and the

MSSP mo du le t hen g oe s in to Idle m od e ( Fig ure 13-17).

13.4.10.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

13.4.11 STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN (SSPCON2 register). At the end of a receive/

transmit, the SCL line is held low after the falling edge

of the ninth clock. When the PEN bit is set, the master

will assert th e SDA line low. When the SDA li ne is sam-

pled low, the Baud Rate Generator is reloaded and

counts down to 0. When the Baud Rate Generator

times out, the SCL pin will be brought high, and one

TBRG (Baud Rate Generator rollover count) later, the

SDA pin wi ll be de-asserte d. When the SDA p in is sam-

pled high while SCL is high, the P bit (SSPSTAT regis-

ter) is set. A TBRG later, the PEN bit is cleared and the

SSPIF bit is set (Figure 13-18).

13.4.11.1 WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the bu f fer are un ch anged (th e write doesn’t

occur).

FIGURE 13-17: ACKNOWLEDGE SEQUENCE WAVEFORM

Note: TBRG = one Baud Rate Generator period.

SDA

SCL

Set SSPIF at the end

Acknowledge sequence starts here,

Write to SSPCON 2 ACKEN automatically cleared

Cleared in

TBRG TBRG

of receive

ACK

ACKEN = 1, AC K D T = 0

SSPIF

software Set SSPIF at the end

of Acknowledge sequence

Cleared in

software

PIC16F882/883/884/886/887

FIGURE 13-18: STOP CONDITION RECEIVE OR TRANSMIT MODE

13.4.12 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition, de-

asserts the SCL pin (SCL allowed to float high). When

the SCL pin is allowed to float high, the Baud Rate Gen-

erator (BRG) is suspended from counting until the SCL

pin is ac tually sam pled high. When the SCL pin is sam -

pled high, the Baud Rate Generator is reloaded with

the contents of SSPADD<6:0> and begins counting.

This ensures that the SCL high time will always be at

least one BRG rollover count, in the ev ent that the clock

is held low by an external device (Figure 13-19).

13.4.13 SL EE P OP ER AT ION

While in Sleep mode, the I2C module can receive

addresses or data, and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

13.4.14 EFFECT OF A RESET

A Reset disables the MSSP module and terminat es the

current transfer.

FIGURE 13-19: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2

Set PEN

Falling edge of

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

9th clock

SCL brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG TBRG

after SDA sampled high, P bit (SSPSTAT) is set

TBRG

to set up Stop cond iti on

ACK

TBRG

PEN bit (SSPCON2) is cleared by

hardware and the SSPIF bi t is set

SCL

SDA

BRG overflow,

Release SCL,

If SCL = 1, load BRG with

SSPADD<6:0>, and start count BRG overflow occurs,

Release SCL, Slave device holds SCL low SCL = 1, BRG starts counting

clock high interval

SCL line sampled once every machine cycle (TOSC*4),

Hold off BRG until SCL is sampled high

TBRG TBRG TBRG

to measure high time interval

PIC16F882/883/884/886/887

13.4.15 MULT I-MAS TER MO DE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

deter mination of when the bus i s free. The S top (P) and

Start (S) bits are cleared from a Reset, or when the

MSSP module is disabled. Control of the I 2C b us may

be taken when the P bit (SSPSTAT register) is set, or

the bus is idle with both the S and P bits clear. When

the bus is busy, enabling the SSP Interrupt will gener-

ate the interrupt when the Stop condition occurs.

In Multi-Master operation, the SDA line must be moni-

tored for arbitration, to see if the signal level is the

expect ed output level. This c heck is perfo rmed in hard-

ware, with the result placed in the BCLIF bit.

Arbitration can be lost in the following states:

• Address transfer

• Data transfer

• A Start condition

• A Repeated Start condition

• An Acknowledg e condition

13.4.16 MULTI -MASTER

COMMUNICATION, BUS

COLLISION, AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA, by letting SDA float high and

anothe r mast er asser ts a ‘ 0’. When the SCL pin float s

high, data should be stable. If the expected data on

SDA is a ‘1’ and the da t a s am ple d on th e SDA pin = 0,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag (BCLIF) and reset the

I2C port to its Idle state (Figure 13-20).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF bit is

cleared, the SDA and SCL lines are de-asserted, and

the SSPBUF c an be writte n to. W hen the user services

the bus c ollis ion inte rrupt ser vice ro utine, a nd if the I2C

bus is free, the user can resume communication by

asserting a Start condition.

If a Start, Repeated Start, Stop, or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are de- assert ed, and t he respe ctiv e contro l bit s in

the SSPCON2 register are cleared. When the user

services the bus collision interrupt service routine, and

if the I2C bus is free, the user can resume

communication by asserting a Start condition.

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPIF bit will be

set.

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the trans-

mitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the

determination of when the bus is free. Control of t he I2C

bus can be t aken when the P bit is set in the SSPSTAT

cleared.

FIGURE 13-20: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA

SCL

BCLIF

SDA released

SDA line pulled low

by an other source Sample SDA,

While SCL is high, data doesn’t

Bus collis ion has occ urred

Set bus collision

interrupt (BCLIF)

match what is driven by the master,

by master

Data changes

while SCL = 0

PIC16F882/883/884/886/887

13.4.16.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the begi nning of

the Start condition (Figure 13-21).

b) SCL is sam pl ed l ow before SDA is as se rted low

(Figure 13-22).

During a Start condition, both the SDA and the SCL

pins are monitored, if:

the SDA pin is already low,

or the SCL pin is already low,

then:

the Start condition is aborted,

and the BCLIF flag is set,

and the MSSP module is reset to its Idle state

(Figure 13-21).

The Start condition begins with the SDA and SCL pins

de-asserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded from SSPADD<6:0>

and counts down to 0. If the SCL pin is sampled low

whil e SD A is hi g h, a bus co l li si o n oc cur s, be ca use it is

assumed that another master is attempting to drive a

data ‘1’ during the S tart condit ion .

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 13-23). If, however , a ‘1’ is sampled on the SDA

pin, the SDA pin is as sert ed low at the end of the B RG

count. The Baud Rate Generator is then reloaded and

count s down to 0, and during thi s time, if the SCL pin is

sampled as ‘0’, a bus collision does not occur. At the

end of t he BRG co unt , the SCL pin is a ss erte d lo w.

FIGURE 13-21: BUS COLLISION DURING START CONDITION (SDA ONLY)

Note: The re ason that bus coll ision is not a fact or

during a Start condition, is that no two bus

masters can assert a Start condition at the

exact same time. Therefore, one master

will always assert SDA before the other.

This condition does not cause a bus colli-

sion, because the two masters must be

allow ed to arbitrate t he first addres s follow-

ing the Start co nditio n. If the addres s is the

same, arbitration must be allowed to con-

tinue into the data portion, Repeated Start

or Stop conditions.

SDA

SCL

SEN

SDA sampled low before

SDA goes low before the SEN bit is set.

S bit and SSPIF set because

SSP module reset into Idle state.

SEN cleared automatically because of bus collision.

S bit and SSPIF set because

Set SEN, enable Start

condition if SDA = 1, SCL = 1.

SDA = 0, SCL = 1.

BCLIF

SSPIF

SDA = 0, SCL = 1.

SSPIF and BCLIF are

cleared in software.

SSPIF and BCLIF are

cleared in software.

Set BCLIF,

Start condition. Set BCLIF.

PIC16F882/883/884/886/887

FIGURE 13-22: BUS COLLISION DURING ST ART CONDITION (SCL = 0)

FIGURE 13-23: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA

SCL

SEN Bus collision occurs, set BCLIF

SCL = 0 before SDA = 0,

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

TBRG TBRG

SDA = 0, SCL = 1

BCLIF

SSPIF

Interrupt cleared

in software

Bus collision occurs, set BCLIF

SCL =0 before BRG time-out,

‘0’‘0’

SDA

SCL

SEN

Set S

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

Less th an TBRG TBRG

SDA = 0, SCL = 1

BCLIF

SSPIF

Interrupts cleared

in software

Set SS PIF

SDA = 0, SCL = 1

SDA pulled low by other master

Reset BRG and assert SDA

SCL pulled low after BRG

time-out

Set SS PIF

‘0’

PIC16F882/883/884/886/887

13.4.16.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occu rs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level.

b) SCL goes low before SDA is asserted low, indi-

cating that another master is attempting to trans-

mit a data ’1’.

When the user de-asserts SDA and the pin is allowed

to float high, the BRG is loaded with SSPADD<6:0>

and counts down to 0. The SCL pin is then de-asserted,

and when sampled high, the SDA pin is sampled.

If SDA is low, a bus collis ion has oc curr ed (i.e, another

master is attempting to transmit a data ‘0’, see

Figure 13-24). If SDA is sampled high, the BRG is

reloaded and begins counting. If SDA goes from high-

to-low before the BRG times out, no bus collision

occurs because no two masters can assert SDA at

exactly the same time.

If SCL goes from high-to-low before the BRG times out

and SDA has not alread y been asserted, a bus collision

occurs. In this case, another master is attempting to

tran smit a data ‘1’ during the Repeated Start condition

(Figure 13-25).

If at the end of the BRG time-out, both SCL and SDA are

still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven l ow and the R epe ated S tart cond ition is c omp lete.

FIGURE 13-24: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

FIGURE 13-25: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

SDA

SCL

RSEN

BCLIF

SSPIF

Sample SDA when SCL goes high,

If SDA = 0, set BCLIF and release SDA and SCL

Cleared in software

‘0’

SDA

SCL

BCLIF

RSEN

SSPIF

Interrupt cleare d

in software

SCL goes low before SDA,

Set BCLIF, release SDA and SCL

TBRG TBRG

‘0’

PIC16F882/883/884/886/887

13.4.16.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been de-asserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is de-asserted, SCL is

sampled low before SDA goes high.

The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),

the Baud R ate Generator is load ed with SSP AD D<6:0>

and cou nt s d own to 0. After the BRG times o ut, SDA i s

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 13-26). If the SCL pin is sam-

pled low be fore SDA is all owed to flo at h igh , a bus co l-

lision occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 13-27).

FIGURE 13-26: BUS COLLISION DURING A STOP CONDITION (CASE 1)

FIGURE 13-27: BUS COLLISION DURING A STOP CONDITION (CASE 2)

SDA

SCL

BCLIF

PEN

SSPIF

TBRG TBRG TBRG

SDA asserted low

SDA sampled

low after TBRG,

set BCLIF

‘0’

SDA

SCL

BCLIF

PEN

SSPIF

TBRG TBRG TBRG

Assert SDA SCL goes low before SDA goes high,

set BCLIF

‘0’

PIC16F882/883/884/886/887

13.4.17 SSP MA SK REGIS T ER

An SSP Mask (SSPMSK) register is available in I2C

Slave mode as a mask for the value held in the

SSPSR register during an address comparison

operation. A zero (‘0’) bit in the SSPMSK register has

the effect of making the corresponding bit in the

SSPSR register a “don’t care”.

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSP operation until written with a mask value.

This register must be initiated prior to setting

SSPM<3:0> bits to select the I2C Slave mode (7-bit or

10-bit address).

This register can only be accessed when the appropriate

mode is selected by bits (SSPM<3:0> of SSPCON).

The SSP Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10- bit Address mode : address com pare of A<7:0 >

only. The SSP mask has no effect during the

reception of the first (high) byte of the address.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSPADD<n> to detect I2C address match

0 = The received address bit n is not used to detect I2C address match

bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(2)

I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111):

1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match

0 = The received address bit 0 is not used to detect I2C address match

Note 1: When SSPCON bits SSPM<3 :0> = 1001, any read s or writes to the SSPADD SFR addre ss are a ccessed

through the SSPMSK register.

2: In all other SSP modes, this bit has no effect.

PIC16F882/883/884/886/887

14.0 SPECIAL FEATURES OF THE

CPU

The PIC16F882/883/884/886/887 have a host of fea-

tures intended to maximize system reliability, minimize

cost through elimination of external components, pro-

vide power-saving features and offer code protection.

These features are:

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Ti mer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Oscillator selection

• Sleep

• Code protection

• ID Locations

• In-Circuit Serial Programming™

• Low-voltage In-Circuit Serial Programming™

The PIC16 F88 2/8 83/8 84 /886/887 have two time rs that

offer necessary delays on power-up. One is the

Oscillator Start-up Timer (OST), intended to keep the

chip in Reset until the crystal oscillator is stable. The

other is t he Power-up Timer (PWRT), wh ic h p rov ide s a

fixed delay of 64 ms (nominal) on power-up only,

designed to keep the part in Reset while the power

supply stabilizes. There is also circuitry to reset the

device if a brown-out occurs, which can use the

Power-up Timer to provide a t least a 64 ms Reset. With

these three functions-on-chip, most applications need

no external Reset circuitry.

The Sleep mode is de signe d to of fer a very low-c urrent

Power-Dow n mode. The us er ca n wa ke -up fro m Slee p

through:

• External Reset

• Watchdog Timer Wake-up

• An interrupt

Several oscillator options are also made available to

allow the part to fit the application. The INTOSC option

saves system cost while the LP crystal option saves

power. A set of Configuration bits are used to select

various options (see Register 14-3).

PIC16F882/883/884/886/887

14.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’), or lef t unprogrammed (read as ‘1’) to select various

device configurations as shown in Register 14-1.

These bits are mapped in program memory location

2007h and 2008h, respectively.

Note: Address 2007h and 2 008h are beyond t he

user program memor y space. It belon gs to

the special configuration memory space

(2000h-3FFFh), which can be accessed

only during programming. See “PIC16F88X

Memory Programming Specification”

(DS41287) for more information.

——DEBUGLVP FCMEN IESO BOREN1 BOREN0

bit 15 bit 8

CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0

bit 7 bit 0

bit 15-14 Unimplemented: Read as ‘1’

bit 13 DEBUG: In-Circuit Debugger Mode bit

1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins

0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger

bit 12 LVP: Low Voltage Programming Enable bit

1 = RB3/PGM pin has PGM fun ction , low voltage pro gr amm i ng enable d

0 = RB3 pin is digital I/O, HV on MCLR must be used for programming

bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit

1 = Fail-Safe Clock Monitor is enabled

0 = Fail-Safe Clock Monitor is disabled

bit 10 IESO: Internal External Switchover bit

1 = Internal/External Switchover mode is enabled

0 = Internal/External Switchover mode is disabled

bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1)

11 = BOR enabled

10 = BOR enabled dur ing ope ration and disa bled in Sleep

01 = BOR controlled by SBOREN bit of the PCON register

00 = BOR disabled

bit 7 CPD: Data Code Protection bit(2)

1 = Dat a memory code protection is disabled

0 = Data memory code protection is enabled

bit 6 CP: Code Protection bit(3)

1 = Program memory code pro tection is disabled

0 = Program memory code pro tection is enabled

bit 5 MCLRE: RE3/MCLR pin function select bit(4)

1 = RE3/MCLR pin function is MCLR

0 = RE3/MCLR pin function is digital input, MCLR internally tied to VDD

bit 4 PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 3 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled and can be enabled by SWDTEN bit of the WDTCON register

bit 2-0 FOSC<2:0>: Oscillator Selection bits

111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN

110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN

101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN

100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN

011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN

010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire data EEPROM will be erased when the code protection is turned off.

3: The entire program memory will be erased when the code protection is turned off.

4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

PIC16F882/883/884/886/887

— — — — — WRT1 WRT0 BOR4V

bit 15 bit 8

— — — — — — — —

bit 7 bit 0

bit 15-11 Unimplemented: Read as ‘ 1’

bit 10-9 WRT<1:0>: Flash Program Memory Self Write Enable bits

PIC16F883/PIC16F884

00 = 0000h to 07FFh write protected, 0800h to 0FFFh may be modified by EECON control

01 = 0000h to 03FFh write protected, 0400h to 0FFFh may be modified by EECON control

10 = 0000h to 00FFh write protected, 0100h to 0FFFh may be modified by EECON control

11 = Write protection off

PIC16F886/PIC16F887

00 = 0000h to 0FFFh write protected, 1000h to 1FFFh may be modified by EECON control

01 = 0000h to 07FFh write protected, 0800h to 1FFFh may be modified by EECON control

10 = 0000h to 00FFh write protected, 0100h to 1FFFh may be modified by EECON control

11 = Write protection off

PIC16F882

00 = 0000h to 03FFh write protected, 0400h to 07FFh may be modified by EECON control

01 = 0000h to 00FFh write protected, 0100h to 07FFh may be modified by EECON control

11 = Write protection off

bit 8 BOR4V: Brown-out Reset Selection bit

0 = Brown-out Reset set to 2.1V

1 = Brown-out Reset set to 4.0V

bit 7-0 Unimplemented: Read as ‘1’

PIC16F882/883/884/886/887

14.2 Reset

The PIC16F882/883/884/886/887 differentiates

between various kinds of Reset:

a) Power-on Reset (POR)

b) WDT Reset during normal operation

c) WDT Reset during Sleep

d) MCLR Reset during normal operation

e) MCLR Reset during Sleep

f) Brown-out Reset (BOR)

Some regi sters a re not af fected in a ny Rese t conditio n;

their st a tus is un kn ow n o n POR a nd un ch ang ed in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset

•MCLR

Reset

•MCLR

Reset du ring Sleep

•WDT Reset

• Brown-out Reset (BOR)

They are not affected by a WDT Wake-up since this is

viewe d as the resumptio n of no rm al op eration. TO an d

PD bits are set or cleared differently in different Reset

situations, as indicated in Table 14-2. These bits are

used in software to determine the nature of the Reset.

See Table 14-5 for a full description of Reset states of

all registers.

A simplif ied block diagra m of the On-Chip Rese t Circu it

is sh own i n Figure 14- 1.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 17.0 “Electrical

Specifications” for pulse-width specifications.

FIGURE 14-1: SIMPLIFI ED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/VPP pin

VDD

OSC1/

WDT

Module

VDD Rise

Detect

OST/PWRT

LFINTOSC

WDT

Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

11-bit Ripple Counter

Reset

Enable OST

Enable PWRT

Sleep

Brown-out(1)

Reset SBOREN

BOREN

CLKI pin

Note 1: Refer to the Conf iguration Word Register 1 (Register 14-1).

PIC16F882/883/884/886/887

14.2.1 POWER-ON RESET (POR)

The on-chip POR circuit holds the chip in Reset until VDD

has reached a high en ough level for proper operation. A

maximum rise time for VDD is required. See

Section 17.0 “Electrical Spe cification s” for details . If

the BOR is enabled, the maximum rise time specification

does not apply. The BOR circuitry will k eep the device in

Reset until VDD reaches VBOR (see Section 14.2.4

“Brown- ou t Re set (B OR )”).

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

14.2.2 MCLR

PIC16F882/883/884/886/887 has a noise filter in the

MCLR Reset path. The filter will detect and ignore

small pul ses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

The behavior of the ESD protection on the MCLR pin

has been altered from early devices of this family.

Vo lta ges app lied to the pin th at exce ed it s s pecif icatio n

can resu lt in both MCL R Rese t s a nd e xc es sive c urre nt

bey ond t h e de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt .

For this rea son, Microc hip recomme nds that the MC LR

pin no long er be tied direc tly to VDD. The use of an RC

network, as shown in Figure 14-2, is suggested.

An internal MCLR option is enabled by clearing the

MCLRE bi t in the Configura tion Word R egister 1. When

MCLRE = 0, the Reset signal to the chip is generated

internally. When the MCLRE = 1, the RA3/MCLR pin

becomes an external Reset input. In this mode, the

RA3/MCLR pin has a we ak pull -up to VDD.

FIGURE 14-2: RECOMMENDED MCLR

CIRCUIT

14.2.3 POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 64 ms (nominal)

time-out on power-up only, from POR or Brown-out

Reset. The Power-up Ti mer operates from the 31 kHz

LFINTOSC oscillator. For more information, see

Section 4.5 “Internal Clock Mo des”. Th e ch ip is ke pt

in Reset as long as PWRT is active. The PWRT delay

allows the VDD to rise to an acceptable level. A

Configuration bit, PWR TE, can disable (if set) or enable

(if cleared or programmed) the Power-up Timer. The

Power-up Timer should be enabled when Brown-out

Reset is enabled, although it is not required.

The Power-up Timer delay will vary from chip-to-chip

and vary due to:

•V

DD variation

• Temperature variation

• Process variation

See DC parameters for details (Section 17.0 “Electrical

Specifications”).

Note: The POR circuit does not produce an

internal Reset when VDD declines. To

re-enable the POR, VDD must reach Vss

for a minimum of 100 μs.

VDD PIC16F886

MCLR

1kΩ (or greater)

0.1 μF

(optional, not critical)

PIC16F882/883/884/886/887

14.2.4 BROWN-OUT RESET (BOR)

The BOREN0 and BOREN1 bits in the Configuration

Word Register 1 select one of four BOR modes. Two

modes h ave been a dded to all ow softwa re or hardwa re

control of the BOR enable. When BOREN<1:0> = 01,

the SBOREN bit (PCON<4>) enables/disables the

BOR allowing it to be controlled in software. By

selecting BOREN<1:0>, the BOR is automatically

disabled in Sleep to conserve power and enabled on

wake-up. In this mode, the SBOREN bit is disabled.

See Register 14-3 for the Configuration Word

definition.

The BOR4V bit in the Configuration Word Register 2

selects one of two Brown-out Reset voltages. When

BOR4B = 1, VBOR is s et to 4V. When BOR4V = 0, VBOR

is set to 2.1V.

If VDD falls below VBOR for greater than parameter

(TBOR) (see Section 17.0 “Electrical Specifications”),

the Brown-out situation will reset the device. This will

occur regardless of VDD slew rate. A Reset is not insured

to occur if VDD falls bel ow VBOR for less than p arameter

(TBOR).

On any Reset (Power-on, Brown-out Reset, Watchdog

T imer , et c.), the ch ip will remai n in Reset unt il VDD rises

above VBOR (see Figure 14-3). The Power-up Timer

will no w be invoked, if enabled and will keep the chip in

Reset an additional 64 ms.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-u p Timer will be re-initialized. Onc e VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

FIGURE 14-3: BROWN-OUT SITUATIONS

Note: The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word

64 ms(1)

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset 64 ms(1)

< 64 ms

64 ms(1)

VBOR

VDD

Internal

Reset

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

PIC16F882/883/884/886/887

14.2.5 TIME-OUT SEQUENCE

On power-u p, the tim e-out sequ ence is as fo llows: first,

PWR T time-out is invoked after PO R has exp ired, the n

OST is act iv ated af te r the PWRT time-ou t has exp ire d.

The total time-out will vary based on oscillator

configuration and PWRTE bit status. For example, in

EC mode with PWRTE bit erased (PWRT disabled),

there will be no time-out at all. Figures 14-4, 14-5

and 14-6 depict time-out sequences. The device can

execute code from the INTOSC while OST is active by

enablin g Two-Spee d Start-up or Fai l-Saf e M on itor (see

Section 4.7.2 “Two-speed Start-up Sequence” and

Section 4.8 “Fail-Safe Clock Monitor”).

Since the time-outs oc cur from the PO R pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 14-5). This is useful for testing purposes or

to synchronize more than one

PIC16F882/883/884/886/887 device operating in par-

allel.

Table 14-5 shows the Reset conditions for some

special registers, while Table 14-4 shows the Reset

conditions for all the registers.

14.2.6 POWER CONTROL (PCON)

The Power Control register PCON (address 8Eh) has

two Status bits to indicate what type of Reset that last

occurred.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a Brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled

(BOREN<1:0> = 00 in the Configuration Word

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaf fec ted oth erwise. T he user m ust write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

For more information, see Section 3.2.2 “Ultra

Low-Power Wake-up” and Section 14.2.4

“Brown-out Reset (BOR)”.

TABLE 14-1: TIME-OUT IN VARIOUS SITUATIONS

TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE

TABLE 14-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

Oscillator Configuration Power-up Brown-out Reset Wake-up from

Sleep

PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1

XT, HS, LP TPWRT +

1024 • TOSC 1024 • TOSC TPWRT +

1024 • TOSC 1024 • TOSC 1024 • TOSC

LP, T1OSCIN = 1TPWRT —TPWRT ——

RC, EC, INTOSC TPWRT —TPWRT ——

POR BOR TO PD Condition

0x11Power-on Reset

u011Brown-out Reset

uu0uWDT Reset

uu00WDT Wake-up

uuuuMCLR Reset during normal operation

uu10MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all ot her

Resets

PCON — — ULPWUE SBOREN ——PORBOR --01 --qq --0u --uu

STATUS IRP RP1 RPO TO PD ZDC C0001 1xxx 000q quuu

Legend: u = unchanged , x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR.

Note 1: Other (non Power-up) Resets include MCLR Rese t and Watchdog Timer Reset dur ing nor ma l operation.

PIC16F882/883/884/886/887

FIGURE 14-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

FIGURE 14-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT T ime-out

OST Time-out

Internal Reset

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

PIC16F882/883/884/886/887

TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER

Reset

MCLR Reset

WDT Reset

Brown-out Reset(1)

Wake-up from Sleep through

Interrupt

Wake-up from Sleep through

WDT Time-out

W—xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h/80h/10

0h/180h xxxx xxxx xxxx xxxx uuuu uuuu

TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h/82h/10

2h/182h 0000 0000 0000 0000 PC + 1(3)

STATUS 03h/83h/10

3h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4)

FSR 04h/84h/10

4h/184h xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 05h xxxx xxxx 0000 0000 uuuu uuuu

PORTB 06h/106h xxxx xxxx 0000 0000 uuuu uuuu

PORTC 07h xxxx xxxx 0000 0000 uuuu uuuu

PORTD 08h xxxx xxxx 0000 0000 uuuu uuuu

PORTE 09h ---- xxxx ---- 0000 ---- uuuu

PCLATH 0Ah/8Ah/10

Ah/18Ah ---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh/8Bh/10

Bh/18Bh 0000 000x 0000 000u uuuu uuuu(2)

PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2)

PIR2 0Dh 0000 0000 0000 0000 uuuu uuuu(2)

TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu

TMR2 11h 0000 0000 0000 0000 uuuu uuuu

T2CON 12h -000 0000 -000 0000 -uuu uuuu

SSPBUF 13h xxxx xxxx uuuu uuuu uuuu uuuu

SSPCON 14h 0000 0000 0000 0000 uuuu uuuu

CCPR1L 15h xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1H 16h xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON 17h 0000 0000 0000 0000 uuuu uuuu

RCSTA 18h 0000 000x 0000 0000 uuuu uuuu

TXREG 19h 0000 0000 0000 0000 uuuu uuuu

RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu

CCPR2L 1Bh xxxx xxxx uuuu uuuu uuuu uuuu

Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 14-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Rese ts will caus e bit 0 = u.

6: Accessible only when SSPCON register bits SSPM<3:0> = 1001.

PIC16F882/883/884/886/887

CCPR2H 1Ch xxxx xxxx uuuu uuuu uuuu uuuu

CCP2CON 1Dh --00 0000 --00 0000 --uu uuuu

ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 1Fh 00-0 0000 00-0 0000 uu-u uuuu

OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu

TRISA 85h 1111 1111 1111 1111 uuuu uuuu

TRISB 86h/186h 1111 1111 1111 1111 uuuu uuuu

TRISC 87h 1111 1111 1111 1111 uuuu uuuu

TRISD 88h 1111 1111 1111 1111 uuuu uuuu

TRISE 89h ---- 1111 ---- 1111 ---- uuuu

PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu

PIE2 8Dh 0000 0000 0000 0000 uuuu uuuu

PCON 8Eh --01 --0x --0u --uu(1, 5) --uu --uu

OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu

OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu

SSPCON2 91h 0000 0000 0000 0000 uuuu uuuu

PR2 92h 1111 1111 1111 1111 1111 1111

SSPADD(6) 93h 0000 0000 0000 0000 uuuu uuuu

SSPMSK(6) 93h 1111 1111 1111 1111 1111 1111

SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu

WPUB 95h 1111 1111 1111 1111 uuuu uuuu

IOCB 96h 0000 0000 0000 0000 uuuu uuuu

VRCON 97h 0000 0000 0000 0000 uuuu uuuu

TXSTA 98h 0000 -010 0000 -010 uuuu -uuu

SPBRG 99h 0000 0000 0000 0000 uuuu uuuu

SPBRGH 9Ah 0000 0000 0000 0000 uuuu uuuu

PWM1CON 9Bh 0000 0000 0000 0000 uuuu uuuu

ECCPAS 9Ch 0000 0000 0000 0000 uuuu uuuu

PSTRCON 9Dh ---0 0001 ---0 0001 ---u uuuu

ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu

ADCON1 9Fh 0-00 ---- 0-00 ---- u-uu ----

WDTCON 105h ---0 1000 ---0 1000 ---u uuuu

CM1CON0 107h 0000 0-00 0000 0-00 uuuu u-uu

CM2CON0 108h 0000 0-00 0000 0-00 uuuu u-uu

TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED)

Reset

MCLR Reset

WDT Reset (Continued)

Brown-out Reset(1)

Wake-up from Sleep through

Interrupt

Wake-up from Sleep through

WDT Time-o ut (Continue d)

Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 14-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Rese ts will caus e bit 0 = u.

6: Accessible only when SSPCON register bits SSPM<3:0> = 1001.

PIC16F882/883/884/886/887

TABLE 14-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

CM2CON1 109h 0000 0--0 0000 0--0 uuuu u--u

EEDAT 10Ch 0000 0000 0000 0000 uuuu uuuu

EEADR 10Dh 0000 0000 0000 0000 uuuu uuuu

EEDATH 10Eh --00 0000 --00 0000 --uu uuuu

EEADRH 10Fh ---0 0000 ---0 0000 ---u uuuu

SRCON 185h 0000 00-0 0000 00-0 uuuu uu-u

BAUDCTL 187h 01-0 0-00 01-0 0-00 uu-u u-uu

ANSEL 188h 1111 1111 1111 1111 uuuu uuuu

ANSELH 189h 1111 1111 1111 1111 uuuu uuuu

EECON1 18Ch ---- x000 ---- q000 ---- uuuu

EECON2 18Dh ---- ---- ---- ---- ---- ----

Condition Program

Counter Status

Power-on Reset 000h 0001 1xxx --01 --0x

MCLR Reset during normal operation 000h 000u uuuu --0u --uu

MCLR Reset during Sleep 000h 0001 0uuu --0u --uu

WDT Reset 000h 0000 uuuu --0u --uu

WDT Wake- up PC + 1 uuu0 0uuu --uu --uu

Brown-out Reset 000h 0001 1uuu --01 --u0

Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu --uu --uu

Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’.

Note 1: When the wak e-up is due to an interrupt and Gl obal Interrup t Enable bit, GIE, is set, the PC is loade d with

the inter rupt vector (0004h) after executio n of PC + 1.

TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED)

Reset

MCLR Reset

WDT Reset (Continued)

Brown-out Reset(1)

Wake-up from Sleep through

Interrupt

Wake-up from Sleep through

WDT Time-ou t (Continued )

Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 14-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Rese ts will caus e bit 0 = u.

6: Accessible only when SSPCON register bits SSPM<3:0> = 1001.

PIC16F882/883/884/886/887

14.3 Interrupts

The PIC16F882/883/884/886/887 has multiple

interrupt sources:

• Extern al Inte rrup t RB0/INT

• Tim er0 Overflow Interrupt

• PORTB Change Interrupts

• 2 Comparator Interrupts

• A/D Interrupt

• Tim er1 Overflow Interrupt

• Timer2 Match Interrupt

• EEPROM Data Write Interrupt

• Fail-Safe Clock Monitor Interrupt

• Enhanced CCP Interrupt

• EUSART Receive and Transmit Interrupts

• Ultra Low-Power Wake-up Interrupt

• MSSP Interrupt

The Interrup t Control register (INTCON) and Peripheral

Interrupt Request Register 1 (PIR1) record individual

interrupt requests in flag bits. The INTCON register

also has individual and global interrupt enable bits.

A Global Interrupt Enable bit, GIE (INTCON<7>),

enables (if set) all unmasked interrupts, or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in the

INTCON, PIE1 and PIE2 re gis ter s, respe ctive ly. GIE is

cleared on Reset.

The Return from Interrupt instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enabl es unm as ke d interrupts.

The following interrupt flags are contained in the INT-

CON register:

• INT Pin Interrupt

• PORTB Change Interrupts

• Tim er0 Overflow Interrupt

The perip heral interru pt flags ar e cont ained in the PIR1

and PIR2 registers. The co rresponding interrupt enable

bits are contained in PIE1 and PIE2 registers.

The following interrupt flags are contained in the PIR1

• A/D Interrupt

• EUSART Receive and Transmit Interrupts

• Tim er1 Overflow Interrupt

• Synchronous Serial Port (SSP) Interrupt

• Enhanced CCP1 Interrupt

• Tim er1 Overflow Interrupt

• Timer2 Match Interrupt

The following interrupt flags are contained in the PIR2

• Fail-Safe Clock Monito r Interru pt

• 2 Comp ara tor Inte rrupts

• EEPROM Data Write Interrupt

• Ultra Low-Power Wake-up Interrupt

• CCP2 Inte rrupt

When an interrupt is serviced:

• The G IE is c lea red t o di sa ble any fu rthe r int errupt.

• The return address is pushed onto the stack.

• The PC is loaded with 0004h.

For external interrupt events, such as the INT pin,

PORTB change interrupts, the interrupt latency will be

three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 14-8). The latency is the same for one or

two-cycle instructions. Once in the Interrupt Service

Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

For additional information on Timer1, Timer2,

comparators, A/D, data EEPROM, EUSART, MSSP or

Enhanced CCP modules, refer to the respective

peripheral section.

14.3.1 RB0/INT INTERRUPT

External interrupt on RB0/INT pin is edge-triggered;

either rising if the INTEDG bit (OPTION_REG<6>) is

set, or falling, if the INTEDG bit is clear. When a valid

edge appears on the RB0/INT pin, the INTF bit

(INTCO N<1>) is set. This interr upt can be disabled by

clearing the INTE control bit (INTCON<4>). The INTF

bit must be cl eared in software in the Inte rrupt Servi ce

Routine b efore re- enabling t his interr upt. The RB 0/INT

interrup t can wake-up t he processor fr om Sleep, if th e

INTE bit was set prior to going into Sleep. The status of

the GIE bit decides whether or not the processor

branches to the interrupt vector following wake-up

(0004h). See Section 14.6 “Power-Down Mode

(Sleep)” for details on Sleep and Figure 14-10 for

timing of wake-up from Sleep through RB0/INT

interrupt.

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts, which were

ignored, are still pending to be serviced

when the GIE bit is set again.

PIC16F882/883/884/886/887

14.3.2 TIMER0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

the T0IF (INTCON<2>) bit. The interrupt can be

enabled/disabled by setting/clearing T0IE (INTCON<5>)

bit. See Section 5.0 “Timer0 Module” for operation of

the Timer0 module.

14.3.3 PORTB INTERRUPT

An input change on PORTB change sets the RBIF

(INTCON<0>) bit. The interrupt can be

enabled/disabled by setting/clearing the RBIE

(INTCON<3>) bit. Plus, individual pins can be

configured through the IOCB register.

FIGURE 14-7: INTERRUPT LOGIC

Note: If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 c ycle), then the RBIF int er-

rupt flag may not get set. See

Section 3.4.3 “Interrupt-on-Cha nge” for

more information.

C1IF

C1IE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in Sleep mode)(1)

Inter rupt to CPU

EEIE

EEIF

ADIF

ADIE

IOC-RB0

IOCB0

IOC-RB1

IOCB1

IOC-RB2

IOCB2

IOC-RB3

IOCB3

CCP1IF

CCP1IE

OSFIF

OSFIE

C2IF

C2IE

IOC-RB4

IOCB4

IOC-RB5

IOCB5

IOC-RB6

IOCB6

IOC-RB7

IOCB7

RCIF

RCIE

TMR2IE

TMR2IF

SSPIE

SSPIF

TXIE

TXIF

TMR1IE

TMR1IF

Note 1: Some peripherals depend upon the

system clock for operation. Since the

system clock is suspended during

Sleep, these peripherals will not wake

the part from Sleep. See Section 14.6.1

“Wake-up from Sleep”.

BCLIE

BCLIF

ULPWUIF

ULPWUIE

CCP2IF

CCP2IE

PIC16F882/883/884/886/887

FIGURE 14-8: INT PIN INTERRUPT TIMING

TABLE 14-6: SUMMARY OF INTERRUPT REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all ot her

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 0000 00-0 0000 00-0

PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by the Interrupt module.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT p in

INTF flag

(INTCON<1>)

GIE bi t

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC PC + 1 PC + 1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycl e

Inst (PC) Inst (PC + 1)

Inst (PC – 1) Inst (0004h)

Dummy Cycl e

Inst ( PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 17.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1) (2)

(3) (4)

(5)

(1)

PIC16F882/883/884/886/887

14.4 Context Savi ng During Int errupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W and STATUS

registers). This must be implemented in software.

Since th e upper 16 bytes of all GPR banks are c om-

mon in the PIC16F882/883/884/886/887 (see

Figures 2-2 and 2-3), temporary holding registers,

W_TEMP and STATUS_TEMP, should be placed in

here. These 16 lo cations do not require banking and

theref ore, ma ke it e asi er to con tex t save and r estor e.

The same c ode show n in Exa mple 14-1 c an be used

to:

• Store the W register

• Store the STATUS register

• Execute the ISR code

• Restore the Status (and Bank Select Bit register)

• Restore the W register

EXAMPLE 14-1: SAVING STATUS AND W REGISTERS IN RAM

Note: The PIC16F882/883/884/886/887 nor-

mally does not require saving the

PCLATH. However, if computed GOTO’s

are used in the ISR and the main code, the

PCLATH must be saved and restored in

the ISR.

MOVWF W_TEMP ;Copy W to TEMP register

SWAPF STATUS,W ;Swap status to be saved into W

;Swaps are used because they do not affect the status bits

MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register

:(ISR) ;Insert user code here

SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF STATUS ;Move W into STATUS register

SWAPF W_TEMP,F ;Swap W_TEMP

SWAPF W_TEMP,W ;Swap W_TEMP into W

PIC16F882/883/884/886/887

14.5 Watchdog Timer (WDT)

The WDT has the following features:

• Operates from the LFINTOSC (31 kHz)

• Contains a 16-bit prescaler

• Shares an 8-bit prescaler with Timer0

• Time-out period is from 1 ms to 268 seconds

• Configuration bit and software controlled

WDT is cleared under certain conditions described in

Table 14-7.

14.5.1 WD T OS CIL LAT OR

The WDT derives its time base from the 31 kHz

LFINTOSC. The LTS bit of the OSCCON regi ste r doe s

not reflect that the LFINTOSC is enabled.

The value of WDTCON is ‘---0 1000’ on all R esets.

This gives a nominal time base of 17 ms.

14.5.2 WDT CONTROL

The WDTE bit is located in the Configuration Word

When the WDTE bit in the Configuration Word

SWDTEN bit can be used to enable and disable the

WDT. Setting the bit will enable it and clearing the bit

will disable it.

The PSA and PS<2:0> bits of the OPTION register

have the same function as in previous versions of the

PIC16F882/883/884/886/887 Family of microcon-

trollers. See Section 5.0 “Timer0 Module” for more

information.

FIGURE 14-9: WATCHDOG TIMER BLOCK DIAGRAM

Note: When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

bec ause the WD T Ri pple Cou nte r i s us ed

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

TABLE 14-7: WDT STATUS

Conditions WDT

WDTE = 0Cleared

CLRWDT Command

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST

31 kHz

PSA

16-bit WDT Prescaler

From TMR0 Clock Source

Prescaler(1)

PS<2:0>

PSA

WDT Time-out

WDTPS<3:0>

WDTE from the Configuration Word Register 1

SWDTEN from WDTCON

LFINTOSC Clock

Note 1: This is the shared Timer0/WDT prescaler . See Section 5.1.3 “Software Programmable Prescaler” for more information.

PIC16F882/883/884/886/887

TABLE 14-8: SUMMARY OF WATCHDOG TIMER REGISTER

U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

0000 = 1:32

0001 = 1:64

0010 = 1:128

0011 = 1:256

0100 = 1:512 (Reset v alue)

0101 = 1:1024

0110 = 1:2048

0111 = 1:4096

1000 = 1:8192

1001 = 1:16384

1010 = 1:32768

1011 = 1:65536

1100 = reserved

1101 = reserved

1110 = reserved

1111 = reserved

bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer(1)

1 = WDT is turned on

0 = WDT is turned off (Reset value)

Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE

Configu ration bi t = 0, then it is possible to turn WDT on/off with this control bit.

Name B it 7 B i t 6 Bit 5 Bit 4 Bit 3 B it 2 B it 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

CONFIG1(1) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 ——

OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Register 1 4-1 for operation of all Configuration Word Register 1 bits.

PIC16F882/883/884/886/887

14.6 Power-Down Mode (Sleep)

The Power-down mode is entered by executing a

SLEEP instruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running.

•PD

bit in the STATUS register is cleared.

•TO

bit is set.

• Oscillator driver is turned off.

• I/O ports maintain the status they had before

SLEEP was executed (driving high, low or

high-impedance).

For lowest current consumption in this mode, all I/O pins

should be either at VDD or VSS, with no external circuitry

drawing current from the I/O pin and the comparators

and CVREF should be disabled. I/O pins that are

high-impedance inputs should be pulled high or low

externally to avoid switching current s caused by floating

input s. The T0CKI input should also be at VDD or VSS for

lowest current consumption. The contribution from

on-chip pull-ups on PORTA should be considered.

The MCLR pin must be at a logic high level.

14.6.1 WAKE-UP FROM SLEEP

The devi ce can wa ke-up from Sleep through on e of the

following events:

1. External Reset input on MCLR pin.

2. W atchd og T imer W ake-up (if WDT was enabled).

3. Interrupt from RB0/INT pin, PORTB change or a

peripheral interrupt.

The firs t event wi ll ca use a de vice Res et. The two latter

events are considered a continuation of program exe-

cution. The T O an d PD bit s in the STATUS re gister can

be used to determine the c ause of device Reset. The

PD bit, which is set on power-up, is cleared when Sleep

is invoked. TO bit is cleare d if W DT Wake-u p occurre d.

The follo wing periph eral interrupt s can wake the device

from Sleep:

1. TMR1 inte rrupt. T imer1 must be operating as a n

asynchronous counter.

2. ECCP Capture mode interrupt.

3. A/D conversion (when A/D clo ck source is FRC).

4. EEPROM write operation completion.

5. Comparator output changes state.

6. Interrupt-on-change.

7. External Interrupt from INT pin.

8. EUSART Break detect, I2C slave.

Other peripherals cannot generate interrupts since

during Sleep, no on-chip clocks are present.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up thro ugh an interrupt eve nt, the co rres pon din g

interrupt enable bit must be set (enabled). Wake-up

occurs regardless of the state of the GIE bit. If the GIE

bit is clear (disabled), the device continues execution at

the inst ruction af ter the SLEEP ins truction. If the GIE b it

is set (enabled), the device executes the instruction

after the SLEEP instruction, then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

14.6.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and inte rrupt fla g bit s et, one of the fo llow ing wil l occu r:

• If the interrupt occurs before the execution of a

SLEEP instruction, the SLEEP instruction will

comple te as a NOP. Therefo re, the WDT an d WDT

prescaler and postscaler (if enabled) will not be

cleared, the TO bit will not be set and the PD bit

will not be cleared.

• If the interrupt occurs during or after the ex ecu-

tion of a SLEEP instruction, the device will imme-

diately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. The refore, the WDT and WDT pres caler

and pos tsc aler (if enable d) wi ll be c leared , the T O

bit will be set and the PD bit will be cl eare d.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruct ion completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT instru ction

should be executed before a SLEEP instruction.

Note: It should be noted that a Reset generated

by a WDT time-out does not drive MCLR

pin low.

Note: If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the corresponding

interrupt flag bits set, the device will

immediately wake-up from Sleep. The

SLEEP instruction is completely executed.

PIC16F882/883/884/886/887

FIGURE 14-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT

14.7 Code Protecti on

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out using ICSP™ for verifi cation purposes.

14.8 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal exe cution but are readable

and writable during Program/Verify mode. Only the

Least Significan t 7 bit s of the ID locations are used.

14.9 In-Ci rcuit Serial Programming™

The PIC1 6F8 82/ 883 /884 /886/887 mic roc on trol lers ca n

be seri ally pr ogrammed while in the en d app lication c ir-

cuit. This is simply done with two lines for clock and

data and three other lines for:

• power

• ground

• programming voltage

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

The device is placed into a Program/Verify mode by

holding the RB6/ICSPCLK and RB7/ICSPDA T pins low ,

while raising th e MCLR (VPP) pin from VIL to VIHH. See

the “PIC16F88X Memory Programming Specification”

(DS41287) for more information. RB7 becomes the

programming data and RB6 becomes the programming

clock. Bo th RB7 and RB 6 are Schmi tt Trigger inputs in

this mode.

After Reset, to place the device into Program/Verify

mode, the Program Counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14 bits of program data

are then supplied to or from the device, depending on

whether the command was a Load or a Read. For

complete details of serial programming, please refer to

the “PIC16F88X Memory Programming Specification”

(DS41287).

A typical In-Circuit Serial Programming connection is

shown in Figure 14-11.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC – 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency(3)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2 0004h 000 5h

Dummy Cycle

TOST(2)

PC + 2

Note 1: XT, HS or LP Osc illa tor mode assume d.

2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.

3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.

4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

Note: The entire data EEPROM and Flash

program memory will be erased when the

code protection is switched from on to off.

See the “PIC16F88X Memory Programming

Specification” (DS41287) for more

information.

PIC16F882/883/884/886/887

FIGURE 14-11: TYPICAL IN-CIRCUIT

SERIAL

PROGRAMMING™

CONNECTION

14.10 Low-Voltage (Single-Supply) ICSP

Programming

The LVP bit of the Configuration Word enables

low-voltage ICSP programming. This mode allows the

microcontroller to be programmed via ICSP using a

VDD source in the operating voltage range. This only

means that VPP does not h ave to be brough t to VIHH but

can instead be left at the normal operating voltage. In

this mode, the RB3/PGM pin is dedicated to the

programming function and ceases to be a general

purpose I/O pin. During programming, VDD is app lied to

the MC LR pin. To enter Programming mode, VDD must

be appli ed to the RB3/PG M provid ed the LVP bit is set.

The LVP bit defaults to on (‘1’) from the factory.

If Low-V olt age Programming mode is not us ed, the L VP

bit can be programmed t o a ‘0’ and RB3/PGM be comes

a digital I/O pin. However, the LVP bit may only be

programmed when programming is entered with VIHH

on MCL R. The L VP bi t can only be charged whe n using

high voltage on MCLR.

It should be noted, that once the LVP bit is programmed

to ‘0’, only the High-Voltage Programming mode is

available and only High-Voltage Programming mode

can be used to program the device.

When using low-voltage ICSP, the part must be

supplied at 4.5V to 5.5V if a bulk erase will be executed.

This includes reprogramming of the code-protect bits

from an on state to an off state. For all other cases of

low-voltage ICSP, the part may be programmed at the

normal operating voltage. This means calibration

values, unique user IDs or user code can be

reprogrammed or added.

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC16F882/883/

VDD

VSS

RE3/MCLR/VPP

RB6

RB7

+5V

VPP

CLK

Data I/O

* * *

* Isolation devices (as required)

884/886/887

Note 1: The High-Voltage Programming mode is

always available, regardless of the state

of the LVP bit, by applying VIHH to the

MCLR pin.

2: While in Low-Voltage ICSP mode, the

RB3 pin can no longer be used as a

general purpose I/O pin.

3: When using Low-Voltage ICSP Program-

ming (LVP) and the pull-ups on PORTB

are enabled, bit 3 in the TRISB register

must be cleared to disable the pull-up on

RB3 and ensure the proper operation of

the device.

4: RB3 should not be allowed to float if LVP

is enabled. An external pull-down device

should be used to default the device to

normal operating mode. If RB3 floats

high, the PIC16F882/883/884/886/887

device will enter Programming mode.

5: LVP mode is enabled by default on all

device s shi pped from Microchi p. It can b e

disabled by clearing the LVP bit in the

CONFIG register.

PIC16F882/883/884/886/887

14.11 In-Circuit Debugger

The PIC16F882/883/884/886/887-ICD can be used in

any of the package types. The device will be mounted

on the ta rget appl ication boa rd, which in turn ha s a 3 or

4 wire connection to the ICD tool.

When the debug bit in the Configuration Word

(CONFIG<13>) is programmed to a ‘0’, the In-Circuit

Debug ger fun ct ion ali t y is enabled. This fun ct ion allo w s

simple debugging functions when used with MPLAB®

ICD 2. When the microcontroller has this feature

enabled, some of the resources are not available for

general use. See Table 14-9 for more detail.

For more information, see “Using MPLAB® ICD 2”

(DS51265), available on Microchip’s web site

(www.microchip.com).

14.11.1 ICD PINOUT

The devices in the PIC16F88X family carry the

circuitry for the In-Circuit Debugger on-chip and on

existing device pins. This eliminates the need for a

sepa rate di e or p acka ge for th e ICD d evice . The pi nout

for the ICD device is the same as the devices (see

Section 1.0 “Device Overview” for complete pinout

and pin descriptions). Table 14-9 shows the location

and function of the ICD related pins on the 28 and 40

pin devices.

TABLE 14-9: PIC16F883/884/886/887-ICD PIN DESCRIPTIONS

Note: The user’s application must have the

circuitry required to support ICD

functionality. Once the ICD circuitry is

enabled, normal device pin functions on

RB6/ICSPCLK and RB7/ICSPDAT will not

be usab le. The IC D circuitry uses the se pins

for communication with the ICD2 external

debugger.

Pin (PDIP)

Name Type Pull-up Description

PIC16F884/887 PIC16F882/883/

886

40 28 ICDDATA TTL — In-Circuit Debugger Bidirectional data

39 27 ICDCLK ST — In-Circuit Debugger Bidirectional clock

11MCLR

/VPP HV — Programming voltage

11,32 20 VDD P—

12,31 8,19 VSS P—

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, P = Power, HV = High Voltage

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

15.0 INSTRUCTION SET SUMMARY

The PIC16F882/883/884/886/887 instruction set is

highly orthogo nal and is co mp rised o f three b asic cate-

gories:

•Byte-oriented operations

•Bit-oriented operations

•Literal and cont rol operations

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type and one or

more operands, which further specify the operation of

the instruction. The formats for each of the categories

is presented in Figure 15-1, while the various opcode

fields are sum m ariz ed in Table 15-1.

Table 15-2 lists the instructions recognized by the

MPASMTM assembler.

For byte-oriented instructions, ‘f’ represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The desti nation designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W regis ter . If ‘d’ is one, the res ult is place d

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

One instr uction cycle co nsists of four os cillator periods ;

for an oscillator frequency o f 4 MHz, t his gives a normal

instruction execution time of 1 μs. All instructions are

executed within a single instruction cycle, unless a

conditional test is true, or the program counter is

change d as a result of an instruction. When this occurs,

the execution takes two instruction cycles, with the

second cycle executed as a NOP.

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

15.1 Read-M odify-Write Operations

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (RMW)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

For example, a CLRF PORTA instruction will read

PORTA, clear all th e data bit s, then write the result b ack

to PORTA. This example would have the unintended

consequence of clearing the condition that set the RAIF

flag.

TABLE 15-1: OPCODE FIELD

DESCRIPTIONS

FIGURE 15-1: GENERAL FORMAT FOR

INSTRUCTIONS

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral fie ld, constant data or label

xDon’t care location (= 0 or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

dDestination select; d = 0: store result i n W,

d = 1: store result in file register f.

Default is d = 1.

PC Program Counter

TO Time-out bit

CCarry bit

DC Digit carry bit

ZZero bit

PD Power-down bit

Byte-oriented file registe r operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriente d file register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (li te r a l )

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC16F882/883/884/886/887

TABLE 15-2: PIC16F882/883/884/886/887 INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

–

f, d

–

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0xxx

dfff

lfff

0xx0

dfff

ffff

xxxx

ffff

0000

ffff

C, DC, Z

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1, 2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

–

Add literal and W

AND literal with W

Call Subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move litera l to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C, DC, Z

TO, PD

C, DC, Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

PIC16F882/883/884/886/887

15.2 Instruction Descriptions

ADDLW Add literal and W

Syntax: [ label ] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → (W)

Status Affected: C, DC, Z

Description: The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the

W register.

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) + (f) → (destination)

Status Affected: C, DC, Z

Desc ription: Add the contents o f the W regis ter

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W registe r . I f

‘d’ is ‘1’, the result is stored back

in register ‘f’.

ANDLW AND literal with W

Syntax: [ label ] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. (k) → (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .AND. (f) → (destination)

Status Affected: Z

Description: AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is sto r ed bac k in regi ste r ‘f’.

BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

St at us Af fe cte d: None

Description: Bit ‘b’ in register ‘f’ is cleared.

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

St at us Af fe cte d: None

Description: Bit ‘b’ in register ‘f’ is set.

BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

St at us Af fe cte d: None

Descr iption: If bit ‘b’ in reg ister ‘f’ is ‘1’, t he ne xt

instruction is executed.

If bit ‘b’ in reg ister ‘f’ is ‘0’, t he ne xt

instruction is discarded, and a NOP

is exec uted ins tea d, m ak ing thi s a

two-cycle instruction.

PIC16F882/883/884/886/887

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Desc ription: If bit ‘b’ in regi ster ‘f’ is ‘0’, the ne xt

instructi on is exec uted .

If bit ‘b’ is ‘1’, then the next

instructi on is dis ca rded an d a NOP

is exec ute d i nst ead, making thi s a

two -cycle instruc tion.

CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0 ≤ k ≤ 2047

Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Description: Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit

immediate address is loaded into

PC bits <10:0>. The upper bits of

the PC are loa ded from PCLATH.

CALL is a two-cycle instruction.

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0 ≤ f ≤ 127

Operation: 00h → (f)

1 → Z

Status Affected: Z

Desc ript ion : The conten t s of regi ste r ‘f’ are

cleared and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

Status Affected: Z

Description: W register is cleared. Zero bit (Z)

is set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

St at us Af fe cte d: T O, PD

Description: CLRWDT instruction resets the

W atchdog T imer . It also resets the

prescaler of the WDT.

Status bits TO and PD are set.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (destination)

St at us Af fe cte d: Z

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (destination)

St at us Af fe cte d: Z

Description: Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

stored back in register ‘f’.

PIC16F882/883/884/886/887

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (destination);

skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are

decrem ented. If ‘d’ is ‘0’, th e result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘1’, the next

instruction is executed. If the

resu lt is ‘0’, then a NOP is

executed instead, making it a

two-cycle instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Status Affected: None

Description: GOTO is an unconditional branch.

The e le ven -bi t im me dia t e v al ue i s

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTO is a

two-cycle instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (destination)

Status Affected: Z

Description: The contents of register ‘f’ are

incremen ted. If ‘ d’ is ‘0’, th e result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (destination),

skip if result = 0

St at us Af fe cte d: None

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, a NOP is executed

instead, making it a two-cycle

instruction.

IORLW Inclusive OR literal with W

Syntax: [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → (W)

St at us Af fe cte d: Z

Descr iption: T he content s of the W reg ister are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W registe r.

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (destination)

St at us Af fe cte d: Z

Description: Inclusive OR the W register with

placed in the W register. If ‘d’ is

‘1’, the result is pla ce d back in

PIC16F882/883/884/886/887

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Desc ript ion : The conten t s of regi ste r ‘f’ is

moved to a destination dependent

upon the status of ‘d’. If d = 0,

destination is W register. If d = 1,

the destination is file register ‘f’

itself. d = 1 is useful to test a file

affected.

Words: 1

Cycles: 1

Example:MOVF FSR, 0

After Instruction

W= value in FSR

Z= 1

MOVLW Move literal to W

Syntax: [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Desc ription: The e ight-bit literal ‘k’ is loa ded into

W register. The “don’t cares” will

assemble as ‘0’s.

Words: 1

Cycles: 1

Example:MOVLW 0x5A

After Instruction

W= 0x5A

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0 ≤ f ≤ 127

Operation: (W) → (f)

St at us Af fe cte d: None

Description: Move data from W register to

Words: 1

Cycles: 1

Example:MOVW

FOPTION

Before Instruction

OPTION= 0xFF

W = 0x4F

After Instruction

OPTION= 0x4F

W = 0x4F

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

St at us Af fe cte d: None

Description: No operation.

Words: 1

Cycles: 1

Example:NOP

PIC16F882/883/884/886/887

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

Status Affected: None

Description: Return from Interrupt. Stack is

POPed an d Top-of-S t ack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global

Interrupt Enable bit, GIE

(INTCON<7>). This is a two-cycle

instruction.

Words: 1

Cycles: 2

Example:RETFIE

After Interrupt

PC = TOS

GIE = 1

RETLW Return with literal in W

Syntax: [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

St at us Af fe cte d: None

Description: The W register is loaded with the

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

Words: 1

Cycles: 2

Example:

TABLE

CALL TABLE;W contains

table ;offset value

• ;W now has

• ;table value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ;End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS → PC

St at us Af fe cte d: None

Description: Return from subroutine. The stack

is POPed an d t he top of th e s tack

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

PIC16F882/883/884/886/887

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Words: 1

Cycles: 1

Example:RLF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W = 1100 1100

C=1

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Desc ript ion : The contents of register ‘f’ are

rotat ed one bit to the r ight throug h

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is place d

back in register ‘f’.

SLEEP Enter Sleep mode

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

St at us Af fe cte d: TO, PD

Descripti on: The power-down S tatus bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer an d its

prescaler are cleared.

The processor is put into Sleep

mode with th e oscillat or stopped.

SUBLW Subtract W from literal

Syntax: [ label ] SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k - (W) → (W)

Status Affected: C, DC, Z

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

C = 0W > k

C = 1W ≤ k

DC = 0W<3:0> > k<3:0>

DC = 1W<3:0> ≤ k<3:0>

PIC16F882/883/884/886/887

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (destination)

Status Affected: C, DC, Z

Description: Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

stored back in register ‘f’.

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (destination<7:4>),

(f<7:4>) → (destination<3:0>)

Status Affected: None

Description: The upper and lower nibbles of

‘0’, the result is placed in the W

placed in register ‘f’.

XORLW Exclusive OR literal with W

Syntax: [ label ] XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Description: The contents of the W register

are XOR’ed with the eight-b it

literal ‘k’. The result is placed in

the W register.

C = 0W > f

C = 1W ≤ f

DC = 0W<3:0> > f<3:0>

DC = 1W<3:0> ≤ f<3:0>

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (destination)

St at us Af fe cte d: Z

Description: Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

stored back in register ‘f’.

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

16.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Devic e Progra mm ers

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

16.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold sep ara tel y)

- I n-Ci rcuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Ex ten si ve on-l ine help

• Integrat ion of select thir d party tool s, such as

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your s ource file s (either assembl y or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Deb ug us ing :

- Source file s (asse mbly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC16F882/883/884/886/887

16.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assemb ler for all PIC MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly co de

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control over the

assembly process

16.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC18 and PIC24 families of microcon-

trollers and the dsPIC30 and dsPIC33 family of digital

signal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compil ers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

16.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manag es the cre ation an d

modification of library files of precompiled code. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and ex traction

16.5 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linke d with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Ric h dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

16.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most periph erals and inte rnal regi sters.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

PIC16F882/883/884/886/887

16.7 MPLAB ICE 2000

High-Performance

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing feat ures. Interc hangeabl e proces sor modul es allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows® 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

16.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash D SC® and MCU devic es. It debugs and

programs PIC® and dsPIC® Flash microcontrollers with

the easy-to-use, powerful graphical user interface of the

MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE pro be is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high speed, noise tolerant, low-

voltage differential signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB ID E, new devic es w ill be supported,

and new features will be added, suc h as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages ov er competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables .

16.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial ProgrammingTM (ICSPTM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug sou rce code by s etting bre akpoi nts , singl e step -

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

16.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for men us an d error m essages and a m odu-

lar, detachable socket assembly to support various

pack age types. The ICSP™ cable assembly is incl uded

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer ca n read, verif y and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 h as high-spe ed co mmunicat ions an d

optimized algorithms for quick programming of large

memory devices and in corporates an SD/MMC card for

file storage and secure data applications.

PIC16F882/883/884/886/887

16.11 PICSTART Plus Development

Programmer

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Inte grated D evelopm ent Envir onment software m akes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76 X, may be sup ported with an a dapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

16.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash m emory microcon trollers. The PICkit 2 S tarter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler , and is desig ned to hel p get up to s peed

quickly using PIC® microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

16.13 Demonstration, Development and

Evaluation Boards

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards includ e prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart® battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

PIC16F882/883/884/886/887

17.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings(†)

Ambient temperature under bias..........................................................................................................-40° to +125°C

Storage temperature........................................................................................................................ -65°C to +150°C

Vo lt a ge on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V

Vo lt a ge on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation(1) ...............................................................................................................................800 mW

Maximum curr ent out of VSS pin ...................................................................................................................... 95 mA

Maximum curr ent into VDD pin......................................................................................................................... 95 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA

Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin..............................................................................................25 mA

Maximum current sunk by all ports (combined)(2)............................................................................................ 90 mA

Maximum current sourced by all ports (combined)(2)....................................................................................... 90 mA

Note 1: Power diss ip ation is ca lcula ted as follo ws: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL).

2: PORTD and PORTE are implemented on PIC16F886/PIC16F887 only.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

PIC16F882/883/884/886/887

FIGURE 17-1: PIC16F883/884/886/887 VOLTAGE-FREQUENCY GRAPH,

-40°C

≤

+125°C

FIGURE 17-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Frequency (MHz)

VDD (V)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

82010

125

2.0

VDD (V)

4.0 5.04.5

Temperature (°C)

2.5 3.0 3.5 5.5

± 1%

± 2%

± 5%

PIC16F882/883/884/886/887

17.1 DC Characteristics: PIC16F883/884/886/887-I (Industrial)

PIC16F883/884/886/887-E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwis e stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

D001

D001C

D001D

VDD Supply Voltage 2.0

2.0

3.0

4.5

—

5.5

FOSC < = 8 MHz: HFINTOSC, EC

FOSC < = 4 MHz

FOSC < = 10 MHz

FOSC < = 20 MHz

D002* VDR RAM Data Retention

Voltage(1) 1.5 — — V Device in Sleep mode

D003 VPOR VDD Start Voltage to

ensure internal Power-on

Reset signal

—VSS —VSee Section 14.2.1 “Power-on Reset

(POR)” for details.

D004* SVDD VDD Rise Rate to ensure

internal Power-on Reset

signal

0.05 — — V/ms See Section 14.2.1 “Power-on Reset

(POR)” for details.

* These parameters are characterized but not tested.

† Data in “Typ” colum n i s at 5.0 V, 25°C unles s othe rwis e s t ate d. These p ara me ters are for d es ign gu ida nc e

only and are not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

PIC16F882/883/884/886/887

17.2 DC Characteristics: PIC16F883/884/886/887-I (Industrial)

PIC16F883/884/886/887-E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Device Char ac teri st ics Min. Typ† Max. Units Conditions

VDD Note

D010 Supply Current (IDD)(1, 2) —1319μA2.0FOSC = 32 kHz

LP Oscillator mode

—2230μA3.0

—3360μA5.0

D011* — 180 250 μA2.0F

OSC = 1 MHz

XT Oscillator mode

— 290 400 μA3.0

— 490 650 μA5.0

D012 — 280 380 μA2.0F

OSC = 4 MHz

XT Oscillator mode

— 480 670 μA3.0

—0.91.4mA5.0

D013* — 170 295 μA2.0F

OSC = 1 MHz

EC Osci llator mode

— 280 480 μA3.0

— 470 690 μA5.0

D014 — 290 450 μA2.0F

OSC = 4 MHz

EC Osci llator mode

— 490 720 μA3.0

—0.851.3 mA 5.0

D015 — 8 20 μA2.0F

OSC = 31 kHz

LFINTOSC mode

—1640μA3.0

—3165μA5.0

D016* — 416 520 μA2.0F

OSC = 4 MHz

HFINTOSC mode

— 640 840 μA3.0

—1.131.6 mA 5.0

D017 — 0.65 0.9 mA 2.0 FOSC = 8 MHz

HFINTOSC mode

— 1.01 1.3 mA 3.0

— 1.86 2.3 mA 5.0

D018 — 340 580 μA2.0F

OSC = 4 MHz

EXTRC mode(3)

— 550 900 μA3.0

—0.921.4 mA 5.0

D019 — 3.8 4.7 mA 4.5 FOSC = 20 MHz

HS Osci llator mode

—4.04.8mA5.0

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unl es s o the rw ise stated. Th ese parameters are for des ign gui da nce

only and are not tested.

Note 1: The test condit ions for all IDD meas uremen ts in a ctive opera tion m ode a re: O SC1 = exte rnal squ are w ave,

from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loadin g and swi tchin g rate, osci llator type, int erna l code exe cutio n patte rn and temp erature, al so have

an impact on the current consumption.

3: For RC oscil lator configurat ions, current throu gh REXT is not incl uded. The current t hrough the resisto r can

be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ.

PIC16F882/883/884/886/887

17.3 DC Characteristics: PIC16F883/884/88 6/887-I (Industrial)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Device Characteristics Min. Typ† Max. Units Conditions

VDD Note

D020 Power-down Base

Current(IPD)(2) — 0.05 1.2 μA 2.0 WDT, BOR, Comparators, VREF and

T1OSC dis ab led

— 0.15 1.5 μA3.0

— 0.35 1.8 μA5.0

— 150 500 nA 3.0 -40°C ≤ TA ≤ +25°C

D021 — 1.0 2.2 μA 2.0 WDT Current(1)

—2.04.0μA3.0

—3.07.0μA5.0

D022 — 42 60 μA 3.0 BOR Current(1)

— 85 122 μA5.0

D023 — 32 45 μA 2.0 Comparator Current(1), both

comparator s enabl ed

—6078μA3.0

— 120 160 μA5.0

D024 — 30 36 μA2.0CV

REF Current(1) (high range)

—4555μA3.0

—7595μA5.0

D025* — 39 47 μA2.0CV

REF Current(1) (low range)

—5972μA3.0

— 98 124 μA5.0

D026 — 2.0 5.0 μA 2.0 T1OSC Current(1), 32.768 kHz

—2.55.5μA3.0

—3.07.0μA5.0

D027 — 0.30 1.6 μA 3.0 A/D Current(1), no conversion in

progress

— 0.36 1.9 μA5.0

D028 — 90 125 μA 3.0 VP6 Reference Current

— 125 162 μA5.0

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unl es s o the rw ise stated. Th ese parameters are for des ign gui da nce

only and are not tested.

Note 1: The peripheral c urre nt is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. Th e periph eral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

PIC16F882/883/884/886/887

17.4 DC Characteristics: PIC16F883/884/886/887-E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C for extended

Param

No. Device Characteristics Min. Typ† Max. Units Conditions

VDD Note

D020E Power-down Base

Current (IPD)(2) —0.05 9μA 2.0 WDT, BOR, Comparators, VREF and

T1OSC disabled

—0.1511 μA3.0

—0.3515 μA5.0

D021E — 1 28 μA 2.0 WDT Current(1)

—230μA3.0

—335μA5.0

D022E — 42 65 μA 3.0 BOR Current(1)

—85127μA5.0

D023E — 32 45 μA 2.0 Comp ara tor Curren t(1), both

comparators enabled

—6078μA3.0

—120160μA5.0

D024E — 30 70 μA2.0CV

REF Current(1) (high range)

—4590μA3.0

—75120μA5.0

D025E* — 39 91 μA2.0CV

REF Current(1) (low range)

—59117μA3.0

—98156μA5.0

D026E — 3.5 18 μA 2.0 T1OSC Current(1), 32.768 kHz

—4.021 μA3.0

—5.024 μA5.0

D027E — 0.30 12 μA 3.0 A/D Current(1), no conversion in

progress

—0.3616 μA5.0

D028E — 90 130 μA 3.0 VP6 Reference Current

—125170μA5.0

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5 .0V, 25°C unle ss oth erwis e s t at ed. These p ara me ters are for design gui dan ce

only and are not tested.

Note 1: The peripheral c urre nt is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. Th e periph eral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

PIC16F882/883/884/886/887

17.5 DC Characteristics: PIC16F883/884/886/887-I (Industrial)

PIC16F883/884/886/887-E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industr ial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

VIL Input Low Voltage

I/O Port:

D030 with TTL buffer Vss — 0.8 V 4.5V ≤ VDD ≤ 5.5V

D030A Vss — 0.15 VDD V2.0V ≤ VDD ≤ 4.5V

D031 with Schmitt Trigger buffer Vss — 0.2 VDD V2.0V ≤ VDD ≤ 5.5V

D032 MCLR, OSC1 (RC mode)(1) VSS —0.2 VDD V

D033 OSC1 (XT and LP modes) VSS —0.3V

D033A OSC1 (HS mode) VSS —0.3 VDD V

VIH Input High Voltage

I/O ports: —

D040 with TTL buffer 2.0 — VDD V4.5V ≤ VDD ≤ 5.5V

D040A 0.25 VDD + 0.8 — VDD V2.0V ≤ VDD ≤ 4.5V

D041 with Schmitt Trigger buffer 0.8 VDD —VDD V2.0V ≤ VDD ≤ 5.5V

D042 MCLR 0.8 VDD —VDD V

D043 OSC1 (XT and LP modes) 1.6 — VDD V

D043A OSC1 (HS mode) 0. 7 VDD —VDD V

D043B OSC1 (RC mode) 0.9 VDD —VDD V(Note 1)

IIL Input Leakage Current(2)

D060 I/O ports — ± 0.1 ± 1μAVSS ≤ VPIN ≤ VDD,

Pin at high-impedance

D061 MCLR(3) —± 0.1 ± 5μAVSS ≤ VPIN ≤ VDD

D063 OSC1 — ± 0.1 ± 5μAVSS ≤ VPIN ≤ VDD, XT, HS and

LP oscillator configuration

D070* IPUR PORTB Weak Pull-up C urrent 50 250 4 00 μAVDD = 5.0V, VPIN = VSS

VOL Output Low Voltage(5)

D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.)

VOH Output High Voltage(5)

D090 I/O ports V DD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.)

* These paramet ers are charact erized but not tested.

† Data in “T yp” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

no t te sted.

Note 1: In RC oscillator configuration, the O SC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: See Section 10.3.1 “Using the Data EEPROM” for additional information.

5: Including OSC2 in CLKOUT mode.

PIC16F882/883/884/886/887

D100 IULP Ultra Low-Power Wake-Up

Current — 200 — nA See Application Note AN879,

“Using the Microchip Ultra

Low-Power Wake-up Module”

(DS00879)

Capacitive Loading S pecs on

Output Pins

D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when

external clock is used to drive

OSC1

D101A* CIO All I/O pins — — 50 pF

Data EEPROM Memory

D120 EDByte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C

D120A EDByte Endurance 10K 100K — E/ W +85°C ≤ TA ≤ +125°C

D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON1 to read/write

VMIN = Minimum operating

voltage

D122 TDEW Erase/Write Cycle Time — 5 6 ms

D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications

are violated

D124 TREF Number of Total Erase/Write

Cycles before Refresh(4) 1M 10M — E/W -40°C ≤ TA ≤ +85°C

Program Flash Memory

D130 EPCell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C

D130A EDCell Endurance 1K 10K — E/W +85°C ≤ TA ≤ +125°C

D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating

voltage

D132 VPEW VDD for Row Erase/Write VMIN —5.5V

VDD for Bulk Erase Operations 4.5 — 5.5 V

D133 TPEW Erase/Write cycle time — 2 2.5 ms

D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications

are violated

17.5 DC Characteristics: PIC16F883/884/886/887-I (Industrial)

PIC16F883/884/886/887-E (Extended) (Continued)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industr ial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

* These paramet ers are charact erized but not tested.

† Data in “T yp” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

no t te sted.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: See Section 10.3.1 “Using the Data EEPROM” for additional information.

5: Including OSC2 in CLKOUT mode.

PIC16F882/883/884/886/887

17.6 Thermal Considerations

Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristic Typ. Units Conditions

TH01 θJA Thermal Resistance

Junction to Ambient 47.2 C/W 40-pin PDIP package

24.4 C/W 44 -pin QFN package

45.8 C/W 44-pin TQFP package

60.2 C/W 28-pin PDIP package

80.2 C/W 28-pin SOIC package

89.4 C/W 28-pin SSOP package

29 C/W 28-pin QFN package

TH02 θJC Thermal Resistance

Junction to Case 24.7 C/ W 40-pin PDIP package

20.0 C/W 44 -pin QFN package

14.5 C/W 44-pin TQFP package

29 C/W 28-pin PDIP package

23.8 C/W 28-pin SOIC package

23.9 C/W 28-pin SSOP package

20.0 C/W 28-pin QFN package

TH03 TJJunction Temperature 150 C For derated power calculations

TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O

TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD

(NOTE 1)

TH06 PI/OI/O Power Dissipation — W PI/O = Σ (IOL * V OL) + Σ (IOH * (VDD - V OH))

TH07 PDER Derated Power — W PDER = (TJ - TA)/θJA

(NOTE 2, 3)

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature.

3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power

dissipation or derated power (PDER).

PIC16F882/883/884/886/887

17.7 Ti ming Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

FIGURE 17-3: LOAD CONDITIONS

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O PORT t1 T1CKI

mc MCLR wr WR

Uppe rcase lett ers and their meanings:

SFFall PPeriod

HHigh RRise

I Invalid (High-impedance) V Valid

L Low Z High-impedance

Legend: CL= 50 pF for all pins

15 pF for OSC2 output

Load Con dition

PIC16F882/883/884/886/887

17.8 AC Characteristics: PIC16F883/884/886/887 (Industrial, Extended)

FIGURE 17-4: CLOCK TIMING

TABLE 17-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Opera ting C ondition s (u nl ess o th erwise stated)

Oper ati ng t em peratur e -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

OS01 FOSC Externa l CLKIN Freq uency(1) DC — 37 k Hz LP Oscillat or m ode

DC — 4 MHz XT Oscillator mode

DC — 20 MHz HS Oscillator mode

DC — 20 MHz EC Oscillator mode

Oscillator Frequency (1) — 32.768 — kHz LP Oscillator mode

0.1 — 4 MHz XT Oscillator mode

1 — 2 0 MHz HS Oscillator mode

DC — 4 MHz RC Oscillator mode

OS02 TOSC External CLKIN Period(1) 27 — • μs LP Oscillator m ode

250 — • ns XT Oscillator mode

50 — • ns HS Osc illat or mo de

50 — • ns EC Oscillator mo de

Oscillator Period(1) —30.5— μs LP Osc i llator m ode

250 — 10,000 ns XT Oscillator m ode

50 — 1,000 ns HS O scillator mo de

250 — — ns RC Oscillator mode

OS03 TCY Instruction Cyc l e Time(1) 200 TCY DC ns TCY = 4/FOSC

OS04* TosH,

TosL External CLKIN High,

External CLKIN Low 2——μs LP oscillator

100 — — ns XT oscillator

20 — — ns H S osc i llator

OS05* TosR,

TosF External CLKIN Rise,

External CLKIN Fall 0 — • ns LP oscillator

0 — • ns XT oscillator

0 — • ns HS oscillator

* T hes e parameter s ar e characte rized but no t test ed.

† Data in “T yp” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and

are no t tested.

Note 1: Instruct io n cycle peri od (TCY) equals four tim es the input os ci lla to r time base per iod. Al l spec i fied val ues are

based on chara ct er izat i on data for that particular oscilla to r type under standard operating condit io ns w it h th e

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

highe r than expect ed current co nsumpti on. Al l devi ces are test ed to oper at e at “min” va lu es with an ext er nal

clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for

all devi ces.

OSC1/CLKIN

OSC2/CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

OS02

OS03OS04 OS04

OSC2/CLKOUT

(LP,XT,HS Modes)

(CLKOUT Mode)

PIC16F882/883/884/886/887

TABLE 17-2: OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristic Freq.

Tolerance Min. Typ† Max. Units Conditions

OS06 TWARM Internal Oscillator Switch

when running(3) ———2TOSC Slo w est clock

OS07 TSC Fail-Safe Sample Clock

Period(1) ——21—msLFINTOSC/64

OS08 HFOSC Internal Calibrated

HFINTOSC Frequency(2) ±1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C

±2% 7.84 8.0 8.16 MHz 2.5V ≤ VDD ≤ 5.5V,

0°C ≤ TA ≤ +85°C

±5% 7.60 8.0 8.40 MHz 2.0V ≤ VDD ≤ 5.5V,

-40°C ≤ TA ≤ +85°C (Ind.),

-40°C ≤ TA ≤ +125°C (Ext.)

OS09* LFOSC Internal Uncalibrat ed

LFINTOSC Frequency — 153145kHz

OS10* TIOSC

ST HFINTOSC Oscillator

W ake-up from Sleep

Start-up Time

— 5.5 12 24 μsVDD = 2.0V, -40°C to +85°C

—3.5714μsVDD = 3.0V, -40°C to +85°C

—3611μsV

DD = 5.0V, -40°C to +85°C

* These parameters are characterized but not tested.

† D ata in “Typ” column is at 5. 0V, 25°C unless oth er w i se s tated. T hes e parameter s ar e f or desi g n gui dance only

and are not test ed.

Note 1: Instruction cycle per iod (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device e xecuting co de. Exceedi ng these specified lim its may r esult in an unstab le oscillator operation and/or

higher tha n expected current co nsumption. All devic es are tested t o operate at “mi n” v al ues w ith an external

clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock)

for all devi ces .

2: To ensur e t hese oscilla tor frequenc y t olerances, VDD and VSS must be capaci tiv e ly decoupl ed as cl ose to the

device a s possible. 0. 1 μF and 0. 01 μF values in parallel are recommended.

3: By design .

PIC16F882/883/884/886/887

FIGURE 17-5: CLKOUT AND I/O TIMING

FOSC

CLKOUT

I/O pi n

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

OS11

OS19

OS13

OS15

OS18, OS19

OS20

OS21

OS17 OS16

OS14

OS12

OS18

Old Value New Value

Write Fetch Read ExecuteCycle

TABLE 17-3: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditi ons (unle ss otherw is e stated )

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

OS11 TOSH2CKLFOSC↑ to CLKOUT↓ (1) — — 70 ns VDD = 5.0V

OS12 TOSH2CKHFOSC↑ to CLKOUT↑ (1) — — 72 ns VDD = 5.0V

OS13 TCKL2IOVCLKOUT↓ to Port out valid(1) — — 20 ns

OS14 TIOV2CKH Port input valid before CLKOUT↑(1) TOSC + 200 ns — — ns

OS15* TOSH2IOVFOSC↑ (Q1 cycle) to Port out valid — 50 70 ns VDD = 5.0V

OS16 TOSH2IOIFOSC↑ (Q2 cycle) to Port input invalid

(I/O in hold time) 50 — — ns VDD = 5.0V

OS17 TIOV2OSH Port input valid to FOSC↑ (Q2 cycle)

(I/O in setup time) 20 — — ns

OS18 TIOR Port output rise time(2) —

—15

40 72

32 ns VDD = 2.0V

VDD = 5.0V

OS19 TIOF Port output fall time(2) —

—28

15 55

30 ns VDD = 2.0V

VDD = 5.0V

OS20* TINP INT pin input high or low time 25 — — ns

OS21* TRAP PORT A interrupt-on-change new input

level time TCY ——ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

2: Includes OSC2 in CLKOUT mode.

PIC16F882/883/884/886/887

FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

FIGURE 17-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Start-Up Time

Internal Reset(1)

Wat c hdog Timer

I/O pins

Note 1: Asserted low.

Reset(1)

VBOR

VDD

(Device in Brown-out Reset) (Device not in Brown-out Reset)

33*

* 64 ms delay only if PWRTE bit in the Configuration Word Register 1 is programmed to ‘0’.

Reset

(due to BOR)

VBOR + VHYST

PIC16F882/883/884/886/887

TABLE 17-4: RESET, WATCHDOG TI MER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditi ons (unle ss otherw is e stated )

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

30 TMCLMCLR Puls e Width (low) 2

5—

——

—μs

μsVDD = 5V, -40°C to +85°C

VDD = 5V

31 TWDT Watchdog Timer Time-out

Period (No Prescaler) 10

10 16

16 29

31 ms

ms VDD = 5V, -40°C to +85°C

VDD = 5V

32 TOST Oscillation Start-up Timer

Period(1, 2) —1024—TOSC (NOTE 3)

33* TPWRT Power-up Timer P eriod 40 65 140 ms

34* TIOZ I/O High-impedance from

MCLR Low or W atchdog Timer

Reset

——2.0μs

35 VBOR Brown-out Reset Vo ltage 2.0 — 2.2 V BOR4V bit = 0 (NOTE 4)

3.6 4.0 4.4 V BOR4V bit = 1, -40°C to +85°C

(NOTE 4)

3.6 4.0 4.5 V BOR4V bit = 1, -40°C to +125°C

(NOTE 4)

36* VHYST Brow n-out Reset Hysteresis — 50 — mV

37* TBOR Brown- out Reset Minimum

Detection Period 100 — — μsVDD ≤ VBOR

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: Instruction cy cle period (TCY) equals four times the input oscillator time base period. All specified values

are based on charac teri za tion data for that part ic ular oscillator typ e unde r st andard operating con di tions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-

ation and/or higher than expected current consumption. All devices are tested to operate at “min” values

with an e xte rna l c loc k app lie d to th e O SC 1 p in. When an exter nal clock inpu t is us ed , th e “m ax ” cy c le t im e

limit is “DC” (no clock) for all devices.

2: By design.

3: Period of the slow er clock.

4: To ensure these v oltag e tolerance s, VDD and VSS m ust be ca paciti vely dec oupled as close to the device a s

possible. 0.1 μF and 0.01 μF values in parallel are recommended.

PIC16F882/883/884/886/887

FIGURE 17-8: TIMER0 AND TIMER1 EX TERNAL CLOCK TIMINGS

TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

41* TT0L T0CK I Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

42* TT0P T 0CK I Period Greater of:

20 or TCY + 40

— — ns N = prescale value

(2, 4, ..., 256)

45* TT1H T1CKI High

Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Pr escaler 15 — — ns

Asynchronous 30 — — ns

46* TT1L T1CKI Low

Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Pr escaler 15 — — ns

Asynchronous 30 — — ns

47* TT1P T1CKI Input

Period S ync hronous Greater of:

30 or TCY + 40

— — ns N = prescale value

(1, 2, 4, 8)

Asynchronous 60 — — ns

48 FT1 Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN) — 32.768 — kHz

49* TCKEZTMR1 Delay from External Clock Edge to Timer

Increment 2 TOSC —7 TOSC — Timers in Sync

mode

* These parameters are characterized but not tested.

† Data in “T yp” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

T0CKI

T1CKI

40 41

45 46

47 49

TMR0 or

TMR1

PIC16F882/883/884/886/887

FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (ECCP)

TABLE 17-6: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP)

Standard Operating Conditi ons (unle ss otherw is e stated )

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns

With Prescaler 20 — — ns

CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns

With Prescaler 20 — — ns

CC03* TccP CCP1 I nput Period 3TCY + 40

N— — ns N = prescale

value (1, 4 or

16)

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note: Refer to Figure 17-3 for load conditions.

(Capture mode)

CC01 CC02

CC03

CCP1

PIC16F882/883/884/886/887

TABLE 17-7: COMPARATOR SPECIFICATIONS

TABLE 17-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS

TABLE 17-9: VOLTAGE (VR) REFERENCE SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operati ng Tem per ature -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristics Min. Typ† Max. Units Comments

CM01 VOS Input Offset Voltage — ± 5.0 ± 10 mV (VDD - 1.5)/2

CM02 VCM Input Co mmon Mode Voltage 0 — VDD - 1.5 V

CM03* CMRR Common Mode Rejection Ratio +55 — — dB

CM04* TRT Response Time Falling — 150 600 ns (NOTE 1)

Rising — 200 1000 ns

CM05* TMC2COV Comparator Mode Change to

Output Valid —— 10 μs

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Respons e time is me as ured with one com p ara tor in put at (VDD - 1.5)/2 - 100 mV to (VDD -1.5)/2+20mV.

S tandard Operating Conditi ons (unle ss othe rwis e stated)

Operati ng tem pera ture -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristics Min. Typ† Max. Units Comments

CV01* CLSB Step Size(2) —

—VDD/24

VDD/32 —

—V

VLow Range (VRR = 1)

High Range (VRR = 0)

CV02* CACC Absolute Accuracy —

——

—± 1/2

± 1/2 LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

CV03* CRUnit Resistor Value (R) — 2k — Ω

CV04* CST Settli ng Time(1) ——10μs

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.

2: See Section 8.10 “Comparator Voltage Reference” for more information.

VR Voltage Reference Specifications Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Param

No. Symbol Characteristics Min. Typ. Max. Units Comments

VR01 VROUT VR voltage output 0.5 0.6 0.7 V

VR02* TSTABLE Settling Time — 10 100* μs

* These parameters are characterized but not tested.

PIC16F882/883/884/886/887

TABLE 17-10: PIC16F883/884/886/887 A/D CONVERTER (ADC) CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

AD01 NRResolution — — 10 bits bit

AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V

AD03 EDL Different ial Error — — ±1 LSb No missi ng codes to 10 bits

VREF = 5.12V

AD04 EOFF Offset Error 0 +1.5 +3.0 LSb VREF = 5.12V

AD07 EGN Gain Error — — ±1 LSb VREF = 5.12V

AD06

AD06A VREF Reference Voltage(3) 2.2

2.7 ——

VDD VAbsolute minimum to ensure 1 LSb

accuracy

AD07 VAIN Full-Scale Range VSS —VREF V

AD08 ZAIN Recommended

Impedance of Analog

Voltage Source

—— 10kΩ

AD09* IREF VREF Input Current(3) 10 — 1000 μADuring VAIN acquisition.

Based on differential of VHOLD to VAIN.

—— 50μA During A/D conversion cycle.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing

codes.

3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input.

4: When ADC is off, it will not consume any current other than leakage current. The power-down current

specific ati on inc ludes any such lea ka ge from the AD C module.

PIC16F882/883/884/886/887

TABLE 17-11: PIC16F883/884/886/887 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C ≤ TA ≤ +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

AD130* TAD A/D C lock Period 1.6 — 9.0 μsTOSC-base d, VREF ≥ 3.0V

3.0 — 9.0 μsTOSC-based, VREF full range

A/D Internal RC

Oscillator Period 3.0 6.0 9.0 μsADCS<1:0> = 11 (ADRC mode)

At V DD = 2.5V

1.6 4.0 6.0 μsAt VDD = 5.0V

AD131 TCNV C onversion Time

(not includin g

Acquisiti on Time)(1)

—11—TAD Set GO/DONE bit to new data i n A/D

Result register

AD132* TACQ Acquis iti on Tim e 11.5 — μs

AD133* TAMP Amplifier Settling Time — — 5 μs

AD134 TGO Q4 to A/D Clock Start —

—

TOSC/2

TOSC/2 + TCY

—

— If the A/D clock source is selected as

RC, a time of TCY is added before the

A/D clock st art s. This allo ws the SLEEP

instruction to be executed.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.

2: See Section 9.3 “A/D Acquisition Requirements” for mini mum con ditions.

PIC16F882/883/884/886/887

FIGURE 17-10: PIC16F883/884/886/887 A/D CONVERSION TIMING (NORMAL MODE)

FIGURE 17-11: PIC16F883/884/886/887 A/D CONVERSION TIMING (SLEEP MODE)

AD131

AD130

BSF ADCON0, GO

A/D CLK

A/D Data

ADRES

ADIF

Sample

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

987 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 TCY

AD134 (TOSC/2(1))

1 TCY

AD132

AD131

AD130

BSF ADCON0, GO

A/D CLK

A/D Data

ADRES

ADIF

Sample

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

9 7 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be execut ed.

AD134

1 TCY

(TOSC/2 + TCY(1))

1 TCY

PIC16F882/883/884/886/887

FIGURE 17-12: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TABLE 17-12: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 17-13: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

TABLE 17-13: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param.

No. Symbol Characteristic Min. Max. Units Conditions

120 TCKH2DTV SYNC XMIT (Master & Slave)

Clock high to data-o ut valid —40ns

121 TCKRF Clock out rise time and fall time (Master mode) — 20 ns

122 TDTRF Data-out rise time and fall time — 20 ns

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param.

No. Symbol Characteristic Min. Max. Units Conditions

125 TDTV2CKL SYNC RCV (Master & Slave)

Data-hold before CK ↓ (DT hold time) 10 — ns

126 TCKL2DTL Data-hold after CK ↓ (DT hold time) 15 — ns

Note: Refer to Figure 17-3 for load conditio ns.

121 121

120 122

RC6/TX/CK

RC7/RX/DT

Note: Refer to Figure 17-3 for load conditions.

125

126

RC6/TX/CK

RC7/RX/DT

PIC16F882/883/884/886/887

FIGURE 17-14 : SP I MAST ER MODE TIMING (CKE = 0, SMP = 0)

FIGURE 17-15 : SP I MAST ER MODE TIMING (CKE = 1, SMP = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76

MSb LSb

bit 6 - - - - - -1

MSb In LSb In

bit 6 - - - -1

Note: Refer to Figure 17-3 for load conditions.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb

bit 6 - - - - - -1 LSb

Note: Refer to Figure 17-3 for load conditions.

73 74

MSb In LSb In

bit 6 - - - -1

PIC16F882/883/884/886/887

FIGURE 17-16 : SPI SLAVE MODE TIMING (CKE = 0)

FIGURE 17-17 : SPI SLAVE MODE TIMING (CKE = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76 77

MSb LSb

bit 6 - - - - - -1

MSb In bit 6 - - - -1 LSb In

Note: Refer to Figure 17-3 for load conditions.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb bit 6 - - - - - -1 LSb

MSb In bit 6 - - - -1 LSb In

Note: Refer to Figure 17-3 for load conditions.

PIC16F882/883/884/886/887

TABLE 17-14: SPI MODE REQUIREMENTS

FIGURE 17-18 : I2C™ BUS START/STOP BITS TIMING

Param

No. Symbol Characteristic Min. Typ† Max. Units Conditions

70* TSSL2SCH,

TSSL2SCLSS↓ to SCK↓ or SCK↑ input TCY ——ns

71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns

72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns

73* TDIV2SCH,

TDIV2SCLSetup time of SD I data input to SCK edge 100 — — ns

74* TSCH2DIL,

TSCL2DILHold time of SDI data input to SCK edge 100 — — ns

75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns

2.0-5.5V — 25 50 ns

76* TDOF SDO data output fall time — 10 2 5 ns

77* TSSH2DOZSS↑ to SDO output high-impedance 10 — 50 ns

78* TSCR SCK output rise time

(Master mode) 3.0-5.5V — 10 25 ns

2.0-5.5V — 25 50 ns

79* TSCF SCK output fall time (Master mode) — 10 25 ns

80* TSCH2DOV,

TSCL2DOVSDO data output valid after

SCK edge 3.0-5.5V — — 50 ns

2.0-5.5V — — 145 ns

81* TDOV2SCH,

TDOV2SCLSDO data output setup to SCK edge Tcy — — ns

82* TSSL2DOV SDO data output valid after SS↓ edge — — 50 ns

83* TSCH2SSH,

TSCL2SSHSS ↑ after SCK edge 1.5TCY + 40 — — ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note: Refer to Figure 17-3 for load conditions.

SCL

SDA

Start

Condition Stop

Condition

PIC16F882/883/884/886/887

TABLE 17-15: I2C™ BUS START/STOP BITS REQUIREMENTS

FIGURE 17-19 : I2C™ BUS DATA TIMING

Param

No. Symbol Characteristic Min. Typ. Max. Units Conditions

90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated

Start condition

Setup time 400 kHz mode 600 — —

91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first

clo ck pulse is generated

Hold time 400 kHz mode 600 — —

92* TSU:STO Stop conditio n 100 kHz mode 4700 — — ns

Setup time 400 kHz mode 600 — —

93 THD:STO Stop condition 100 kHz mode 4000 — — ns

Hold time 400 kHz mode 600 — —

* These parameters are characterized but not tested.

Note: Refer to Figure 17-3 for load conditions.

91 92

100 101

103

106 107

109 109 110

102

SCL

SDA

Out

PIC16F882/883/884/886/887

TABLE 17-16: I2C™ BUS DATA REQUIREMENTS

Param.

No. Symbol Characteristic Min. Max. Units Conditions

100* THIGH Clock high time 100 kHz mode 4.0 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — μs Device must operate at a

minimum of 10 MHz

SSP Module 1.5TCY —

101* TLOW Clock low tim e 100 kHz mode 4.7 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — μs Device must operate at a

minimum of 10 MHz

SSP Module 1.5TCY —

102* TRSDA and SCL rise

time 100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1CB300 ns CB is specified to be from

10-400 pF

103* TFSDA and SCL fall

time 100 kHz mode — 300 ns

400 kHz mode 20 + 0.1CB300 ns CB is specified to be from

10-400 pF

90* TSU:STA Start condition

setup time 100 kHz mode 4.7 — μs O nly releva nt for

Repeat ed Start condition

400 kHz mode 0.6 — μs

91* THD:STA Start condition hold

time 100 kHz mode 4.0 — μs Af te r this period the firs t

clock pulse is generated

400 kHz mode 0.6 — μs

106* THD:DAT Data input hold time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 μs

107* TSU:DAT Data input setup

time 100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

92* TSU:STO Stop condition

setup time 100 kHz mode 4.7 — μs

400 kHz mode 0.6 — μs

109* TAA Output valid from

clock 100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

110* TBUF Bus free time 100 kHz mode 4.7 — μs T ime th e bus m ust be fre e

before a new transmission

can start

400 kHz mode 1.3 — μs

CBBus capacitive loading — 400 pF

* These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I2C bus de vice ca n be us ed in a St andard mode (100 kHz) I2C bus syste m, but the

requiremen t TSU:DAT ≥ 250 ns mus t the n be m et. Th is wi ll auto mat ic all y be the c as e if the dev ic e do es not

stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it

must outpu t the nex t da ta bit to the SDA l ine TR max. + TSU:DAT = 1000 + 25 0 = 12 50 ns (a cc ord ing to th e

Standard mode I2C bu s specificati on), before the SCL line is released.

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents

(mean + 3σ) or (mean - 3σ) respectively , where σ is a standard deviation, over each temperature range.

FIGURE 18-1: TYP ICAL IDD vs. FOSC OVER VDD (EC MODE)

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only . The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

Typical 2V 3V 4V 5V 5.5V

1Mhz 0.086 0.153 0.220 0.277 0.310

2Mhz 0.150 0.2596 0.3718 0.4681 0.5236

4Mhz 0.279 0.472 0.675 0.850 0.951

6Mhz 0.382 0.635 0.903 1.135 1.269

8Mhz 0.486 0.798 1.132 1.420 1.587

10Mhz 0.589 0.961 1.360 1.706 1.905

12Mhz 0.696 1.126 1.596 2.005 2.241

14Mhz 0.802 1.291 1.832 2.304 2.577

16Mhz 0.908 1.457 2.068 2.603 2.913

18Mhz 1.017 1.602 2.268 2.848 3.185

20Mhz 1.126 1.748 2.469 3.093 3.458

Max 2V 3V 4V 5V 5.5V

1Mhz 0.168 0.236 0.315 0.412 0.452

2Mhz 0.261 0.394 0.537 0.704 0.780

4Mhz 0.449 0.710 0.981 1.287 1.435

6Mhz 0.577 0.972 1.331 1.739 1.950

8Mhz 0.705 1.233 1.682 2.191 2.465

10Mhz 0.833 1.495 2.032 2.642 2.979

12Mhz 0.956 1.711 2.372 3.101 3.506

14Mhz 1.078 1.926 2.713 3.560 4.032

16Mhz 1.201 2.142 3.054 4.018 4.558

18Mhz 1.305 2.326 3.295 4.324 4.887

20Mhz 1.409 2.510 3.536 4.630

EC Mode

5.5V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz

VDD (V)

IDD (mA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -cas e Tem p) + 3σ

(-40°C to 125°C)

PIC16F882/883/884/886/887

FIGURE 18-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)

FIGURE 18-3: TYP ICAL IDD vs. FOSC OVER VDD (HS MODE)

5.5V

0.0

1.0

2.0

3.0

4.0

5.0

6.0

1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz

VDD (V)

IDD (mA)

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-case Tem p) + 3σ

(-40°C to 125°C)

3V 3.5V 4V 4.5V 5V 5.5V

0.567660978 0.6909750.8211857610.9883470541.0462473761.119615457

1.1610564131.4069334781.6664380432.0030751092.1193190652.268818804

2.883088587 3.03554863 3.23775

3.741393.967407543

HS Mode

3.5V

4.5V

5.5V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

4 MHz 10 MHz 16 MHz 20 Mhz

FOSC

IDD (mA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F882/883/884/886/887

FIGURE 18-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)

FIGURE 18-5: TYP ICAL IDD vs. VDD OVER FOSC (XT MODE)

3V 3.5V 4V 4.5V 5V 5.5V

0.8868608641.0693043161.2645617521.4868166111.5076394231.520959608

1.6176371031.9623642592.3355493582.7630868222.8139211682.849632041

3.8375797553.9157601913.967889512

4.685048474 4.78069621

HS Mode

3.5V

4.5V

5.5V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

4 MHz 10 MHz 16 MHz 20 MHz

FOSC

IDD (mA)

Typical: Statistical Mean @25°C

Maximum: Mean (W ors t-case Tem p ) + 3σ

(-40°C to 125°C)

2 2.5 3 3.5 4 4.5 5 5.5

180.1774 235.0683 289.9592 337.753 385.547 436.866 488.184 554.8964

283.7333 382.484 481.2347 577.923 674.6106 783.831 893.052 1033.15

Vdd 2 2.5 3 3.5 4 4.5 5 5.5

244.8837 320.7132 396.5426 461.707 526.8719 587.642 648.412 724.0755

375.529 522.3721 669.2152 822.619 976.0232 1163.67 1351.32

XT Mode

1 MHz

4 MHz

200

400

600

800

1,000

1,200

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

(uA)

Typical: Statistical Mean @25×C

Maximum: Mean (Worst Case Temp) + 3

(-40×C to 125×C)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F882/883/884/886/887

FIGURE 18-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)

FIGURE 18-7: TYP ICAL IDD vs. VDD OVER FOSC (EXTRC MODE)

XT Mode

4 MHz

1 MHz

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD (uA)

Typical: Statistical Mean @25°C

Maximum: Me an (Wors t-c ase Temp ) + 3σ

(-40°C to 125°C)

(EXTR C Mo d e )

1 Mhz

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD (uA)

4 Mhz

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F882/883/884/886/887

FIGURE 18-8: MAXIMUM IDD vs. VDD (EXTRC MODE)

FIGURE 18-9: IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)

1 Mhz

4 Mhz

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2,000

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD (uA)

Typical: Statistical Mean @25×C

Maximum: Mean (Worst Case Temp) + 3

(-40×C to 125×C)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

LFINTOSC Mode, 31KHZ

Typical

Maximum

VDD (V)

IDD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

PIC16F882/883/884/886/887

FIGURE 18-10 : IDD vs. VDD (LP MODE)

FIGURE 18-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD (uA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-cas e Temp) + 3σ

(-40°C to 125°C)

32 kHz Maximum

32 kHz Typical

4V 5V 5.5V

197.9192604299.82617395.019 496.999 574.901

210.9124688 324.4079431.721 544.182 620.66

239.9707708369.77809491.538 623.314 717.723

298.6634479460.30461619.714 793.635 901.409

414.3997292639.99889 878.13 1127.53 1275.6

649.86985881014.40021421.21 1858.97 2097.71

2V 3V 4V 5V 5.5V

HFINTOSC

5.5V

500

1,000

1,500

2,000

2,500

125 kHz 25 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz

VDD (V)

IDD (uA)

Typical: Statistical Mean @25×C

Maximum: Mean (Worst Case Tem p) + 3

(-40×C to 125×C)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F882/883/884/886/887

FIGURE 18-12 : MAXIMU M IDD vs. FOSC OVER VDD (HFINTOSC MODE)

FIGURE 18-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

HFINTOSC

5.5V

500

1,000

1,500

2,000

2,500

3,000

125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz

VDD (V)

IDD (uA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -c ase Tem p) + 3σ

(-40°C to 125°C)

Typical

(Sleep M od e all Peripherals Disabled)

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

(uA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

0.00

PIC16F882/883/884/886/887

FIGURE 18-14 : MAXIMU M IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

FIGURE 18-15 : CO MPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED)

Maximum

(Sleep Mode all Peripherals Disabled)

Max. 125°C

Max. 85°C

2.02.5 3.03.5 4.04.5 5.05.5

VDD (V)

IPD (μA)

Maximum: Mean + 3σ

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Typical Max

31.9 43.9

45.6 60.8

59.3 77.7

73.0 95.8

86.7 113.8

100.4 131.8

114.1 149.9

127.7

Typical

Maximum

100

120

140

160

180

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F882/883/884/886/887

FIGURE 18-16 : BO R IPD vs. VDD OVER TEMPERATURE

FIGURE 18-17: TYPICAL WDT IPD vs. VDD (25°C)

100

120

140

160

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (μA)

Typical: Statistical Mean @25°C

Maximum: Me an (Wors t-case Te mp) + 3σ

(-40°C to 125°C)

Maximum

Typical

Typical Max 85×C Max 125×C

21.007 2.140 27.702

2.51.146 2.711 29.079

31.285 3.282 30.08

3.51.449 3.899 31.347

41.612 4.515 32.238

4.51.924 5.401 33.129

52.237 6.288 34.02

5.52.764 7.776

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typical: Statistical Mean @25°C

PIC16F882/883/884/886/887

FIGURE 18-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE

FIGURE 18-19 : WD T PERIO D vs. VDD OVER TEMPERATURE

Max. 125°C

Max. 85°C

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Maximum: Mean + 3

Maximum: Mean + 3σ

WDT Time-out Period

Typical

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Time (ms)

Maximum: Mean + 3σ (-40°C to 125°C)

Max. (125°C)

Max. (85°C)

Minimum

PIC16F882/883/884/886/887

FIGURE 18-20: WDT PERIOD vs. TEMPERATURE (VDD = 5.0V )

FIGURE 18-21 : CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE)

Vdd = 5V

Maximum

Typical

Minimum

-40°C 25°C 85°C 125°C

Temperature (°C)

Time (m s )

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-c ase Tem p) + 3σ

Max 85×C M ax 125×C

35.8 68.0

44.8 77.3

53.8 86.5

62.8 94.3

71.8 102.1

81.0 109.8

90.1 117.6

99.2 125.1

Max 85×C M ax 125×C

46.5 86.4

58.3 98.1

70.0 109.9

High Range

Typical

Max. 85°C

100

120

140

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

PIC16F882/883/884/886/887

FIGURE 18-22 : CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)

FIGURE 18-23: TYPICAL VP6 REFERENCE IPD vs. VDD (25°C)

low Range

Typical

Max. 85°C

Max. 125°C

100

120

140

160

180

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typical: Statistical Mean @25°C

Maximum: Me an (Wors t-c ase Te mp) + 3σ

(-40°C to 125°C)

VP6 Reference IPD vs. VDD (25×C)

100

120

140

160

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typical

PIC16F882/883/884/886/887

FIGURE 18-24: MAXIMUM VP6 REFERENCE IPD vs. VDD OVER TEMPERATURE

FIGURE 18-25 : T1O SC IPD vs. VDD OVER TEMPERATURE (32 kHz)

Max VP6 Reference IPD vs. VDD Over Temperature

100

120

140

160

180

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Max 125°C

Max 85°C

Typ 25×C Max 85×C Max 125×C

2 2.022 4.98 17.54

2.5 2.247 5.23 19.02

3 2.472 5.49 20.29

3.5 2.453 5.79 21.50

4 2.433 6.08 22.45

4.5 2.711 6.54 23.30

5 2.989 7.00 24.00

5.5 3.112 7.34 Typ. 25°C

Max. 85°C

Max. 125°C

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F882/883/884/886/887

FIGURE 18-26 : VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)

FIGURE 18-27 : VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)

(VDD = 3V, -40×C TO 125×C)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

IOL (m A)

VOL (V)

Max. 85°C

Max. 125°C

Typical 25°C

Min. -40°C

Typical: Statistical Mean @25°C

Maximum: Mean + 3σ

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

IOL (mA)

VOL (V)

Typical: Statistical Mean

Maximum: Means + 3

Typical: Statistical Mean @25°C

Maximum: Mean + 3σ

Max. 85°C

Typ. 25°C

Min. -40°C

Max. 125°C

PIC16F882/883/884/886/887

FIGURE 18-28 : VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)

FIGURE 18-29 : VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0 IOH (mA)

VOH (V)

Typ. 25°C

Max. -40°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -cas e Tem p) + 3σ

(-40°C to 125°C)

(, )

3.0

3.5

4.0

4.5

5.0

5.5

-5.0-4.5-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0 IOH (mA)

VOH (V)

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F882/883/884/886/887

FIGURE 18-30: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

FIGURE 18-31: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

(TTL Input, -40×C TO 125×C)

0.5

0.7

0.9

1.1

1.3

1.5

1.7

2.02.5 3.03.5 4.04.5 5.05.5

VDD (V)

VIN (V)

Typ. 25°C

Max. -40°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-c ase Tem p) + 3σ

(-40°C to 125°C)

(ST Input, -40×C TO 125×C)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN (V)

VIH Max. 125°C

VIH Min. -40°C

VIL Min. 125°C

VIL Max. -40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-case Tem p) + 3σ

(-40°C to 125°C)

PIC16F882/883/884/886/887

FIGURE 18-32: COMPARATOR RESPO NSE TIME (RISING EDGE)

FIGURE 18-33 : CO MPARATOR RESP ONSE TIME (FALLING EDGE)

V- input = Transition from VCM + 100MV to VCM - 20MV

V+ input = VCM

4 200 278 639 846

5.5 140 202 531

100

200

300

400

500

600

700

800

900

1,000

2.0 2.5 4.0 5.5

VDD (Volts)

Response Time (nS)

Max. (85°C)

Typ. (25°C)

Min. (-40°C)

Max. (125°C)

Note:

V- input = Transition from VCM + 100MV to VCM - 20MV

V+ input = VCM

VCM = VDD - 1.5V )/2

Vdd -40×C 25×C 85×C 125×C

2 279 327 547 557

2.5 226 267 425 440

4 172 204 304 319

5.5 119 142 182

100

200

300

400

500

600

2.0 2.5 4.0 5.5

VDD (Volts)

Response Time (nS)

Max. (85°C)

Typ. (25°C)

Min. (-40°C)

Note:

V- input = Transition from VCM - 100MV to V CM + 20MV

V+ input = VCM

VCM = VDD - 1.5V)/2

Max. (125°C)

PIC16F882/883/884/886/887

FIGURE 18-34: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)

FIGURE 18-35: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE

LFINTOSC 31Khz

5,000

10,000

15,000

20,000

25,000

30,000

35,000

40,000

45,000

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Frequency (Hz)

Max. -40°C

Typ. 25°C

Min. 85°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case) + 3σ

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Time (μs)

25°C

85°C

125°C

-40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F882/883/884/886/887

FIGURE 18-36: TYP ICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

FIGURE 18-37: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Time (μs)

85°C

25°C

-40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case) + 3σ

-40C to +85C

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Time (μs)

-40°C

85°C

25°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case) + 3σ

PIC16F882/883/884/886/887

FIGURE 18-38: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

FIGURE 18-39: TYP ICAL HFINTOSC FREQUENCY CHANGE vs. VDD ( 25°C)

-40C to +85C

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Time (μs)

-40°C

25°C

85°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

-5

-4

-3

-2

-1

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Cha n ge f r o m C a librat i on (%)

PIC16F882/883/884/886/887

FIGURE 18-40: TYP ICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C)

FIGURE 18-41: TYP ICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C)

-5

-4

-3

-2

-1

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Change from Calibration (%)

-5

-4

-3

-2

-1

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Change fr om Calibration (%)

PIC16F882/883/884/886/887

FIGURE 18-42: TYP ICAL HFINTOSC FREQUENCY CHANGE vs. VDD ( -40°C)

FIGURE 18-43: TYPICAL VP6 REFERENCE VOLTAGE vs. VDD (25°C)

-5

-4

-3

-2

-1

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Change fr om Calibration (%)

VP6 Reference Voltage vs. VDD (25×C)

0.55

0.56

0.57

0.58

0.59

0.60

0.61

0.62

0.63

0.64

0.65

23455.5

VDD (V)

VP6 (V)

Typical

PIC16F882/883/884/886/887

FIGURE 18-44 : VP6 DRIFT OV ER TE MP ERATURE NORMALIZED AT 25°C (VDD 5V)

FIGURE 18-45 : VP6 DR IFT OVER TEMP ERATURE NORMALIZED AT 25°C (VDD 3V)

-1

-40 025 85 125

Temperature in Degrees C

Change fro m Nomin al in %

-2

-1

-40 025 85 125

Temperature in Degrees C

Change from Nominal in %

-2

PIC16F882/883/884/886/887

FIGURE 18-46: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C)

FIGURE 18-47: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 85°C)

Typical VP6 Reference Voltage Distribution (VDD=3V, 25×C)

0.500

0.510

0.520

0.530

0.540

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

0.650

0.660

0.670

0.680

0.690

0.700

Voltage (V)

Number of Parts

Parts=118

Typical VP6 Reference Voltage Distribution (VDD=3V, 85×C)

0.500

0.510

0.520

0.530

0.540

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

0.650

0.660

0.670

0.680

0.690

0.700

Voltage (V)

Number of Parts

Parts=118

PIC16F882/883/884/886/887

FIGURE 18-48: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C)

FIGURE 18-49: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, -40°C)

Typical VP6 Reference Voltage Distribution (VDD=3V, 125×C)

0.500

0.510

0.520

0.530

0.540

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

0.650

0.660

0.670

0.680

0.690

0.700

Voltage (V)

Number of Parts

Parts=118

Typical VP6 Reference Voltage Distribution (VDD=3V, -40×C)

0.500

0.510

0.520

0.530

0.540

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

0.650

0.660

0.670

0.680

0.690

0.700

Voltage (V)

Number of Parts

Parts=118

PIC16F882/883/884/886/887

FIGURE 18-50: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C)

FIGURE 18-51: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 85°C)

Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C)

0.500

0.510

0.520

0.530

0.540

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

0.650

0.660

0.670

0.680

0.690

0.700

Voltage (V)

Number of Parts

Parts=118

Typical VP6 Reference Voltage Distribution (VDD=5V, 85×C)

0.500

0.510

0.520

0.530

0.540

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

0.650

0.660

0.670

0.680

0.690

0.700

Voltage (V)

Number of Parts

Parts=118

PIC16F882/883/884/886/887

FIGURE 18-52: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125°C)

FIGURE 18-53: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, -40°C)

Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C)

0.500

0.510

0.520

0.530

0.540

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

0.650

0.660

0.670

0.680

0.690

0.700

Voltage (V)

Number of Parts

Parts=118

Typical VP6 Reference Voltage Distribution (VDD=5V, -40×C)

0.500

0.510

0.520

0.530

0.540

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

0.630

0.640

0.650

0.660

0.670

0.680

0.690

0.700

Voltage (V)

Number of Parts

Parts=118

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

19.0 PACKAGING INFORMATION

19.1 Package Mark ing Information

28-Lead QF N

XXXXXXXX

YYWWNNN

Example

16F886

/ML

0710017

28-Lead SOIC (7.50 mm)

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC16F886/SO

0710017

28-Lead PDIP

XXXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXXXXX

Example

PIC16F883

0710017

28-Lead SSOP

XXXXXXXXXXXX

YYWWNNN

Example

PIC16F883

-I/SS 0710017

-I/P

Legend: XX...X Cust om er-s pec ifi c info rma tio n

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the eve nt the full Microc hip p art number c annot be marked on one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

PIC16F882/883/884/886/887

19.1 Package Mark ing Information (Continue d)

40-Lead PDIP

XXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC16F885

0710017

XXXXXXXXXX

44-Lead QFN

XXXXXXXXXX

YYWWNNN

PIC16F887

Example

-I/ML

0710017

44-Lead TQFP

XXXXXXXXXX

YYWWNNN

Example

PIC16F887

-I/PT0710017

-I/P

Legend: XX...X Cust om er-s pec ifi c info rma tio n

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the eve nt the full Microc hip p art number c annot be marked on one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

PIC16F882/883/884/886/887

19.2 Package Details

The following sections give the technical details of the packages.

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&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& .  - --

##4>#& .  < 

: 9&  - -? 

&& 9  - 

9#4!!  <  

69#>#& )   

9*9#>#& )  < 

: *+ 1 = = -

NOTE 1

  * ,1

PIC16F882/883/884/886/887

##$%&'(#)

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  = = ?

##44!!   = =

&#%%+   = -

: >#& . -1,

##4>#& . 1,

: 9&  1,

,'%@&A   = 

3&9& 9  = 

3&& 9 .3

3& IB = <B

9#4!!  < = --

9#>#& ) - = 

#%& DB = B

#%&1&&' EB = B

NOTE 1

123

  * ,1

PIC16F882/883/884/886/887

*+#('#

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  ?1,

: 8&  = = 

##44!!  ?  <

&#%%   = =

: >#& .  < <

##4>#& .  - ?

: 9&    

3&9& 9   

3&& 9 .3

9#4!!   = 

3& B B <B

9#>#& )  = -<

NOTE 1

  * ,-1

PIC16F882/883/884/886/887

,-%!./010,-!

2*'(().*

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 4!!*!"&#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  ?1,

: 8&  <  

&#%%    

,&&4!! - .3

: >#& . ?1,

.$!##>#& . -? - 

: 9&  ?1,

.$!##9&  -? - 

,&&>#& ) - - -

,&&9& 9   

,&&&.$!## C  = =

DEXPOSED D2

NOTE 1

TOP VIEW BOTTOM VIEW

PAD

  * ,1

PIC16F882/883/884/886/887

,-%!./010,-!

2*'(().*

&&255***''54

PIC16F882/883/884/886/887

30

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

 '!#&.0

1,2 1!'!&$& "!**&"&&!

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 

&  1,

&&  = = 

##44!!   = 

1!&&   = =

"#&"#>#& .  = ?

##4>#& . < = <

: 9&  < = 

&& 9  = 

9#4!!  < = 

69#>#& ) - = 

9*9#>#& )  = -

: *+ 1 = = 

NOTE 1

123

A1 b1

  * ,?1

PIC16F882/883/884/886/887

33,-%!./1,-!

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 4!!*!"&#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 

&  ?1,

: 8&  <  

&#%%    

,&&4!! - .3

: >#& . <1,

.$!##>#& . ?- ? ?<

: 9&  <1,

.$!##9&  ?- ? ?<

,&&>#& )  - -<

,&&9& 9 -  

,&&&.$!## C  = =

DEXPOSED

PAD

NOTE 1

BOTTOM VIEW

TOP VIEW

A3 A1

  * ,-1

PIC16F882/883/884/886/887

33,-%!./1,-!

&&255***''54

PIC16F882/883/884/886/887

334*,-5461616%'4,-

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 ,'%!&!&D!E' 

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%9#! 7 

9#&  <1,

: 8&  = = 

##44!!    

&#%%   = 

3&9& 9  ? 

3&& 9 .3

3& B -B B

: >#& . 1,

: 9&  1,

##4>#& . 1,

##49&  1,

9#4!!   = 

9#>#& ) - - 

#%& B B -B

#%&1&&' B B -B

NOTE 1 NOTE 2

123

  * ,?1

PIC16F882/883/884/886/887

334*,-5461616%'4,-

&&255***''54

PIC16F882/883/884/886/887

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A (5/2006)

Initial release of this data sheet.

Revision B (7/2006)

Pin Diagrams (44-Pin QFN drawing); Revised Table

2-1, Addr. 1DH (CCP2CON); Section 3.0, 3.1; Section

3.4.4.6; Table 3; Table 3-1 (ANSEL); Table 3-3

(CCP2CON); Register 3-1; Register 3.2; Register 3-3;

3-11; Register 3 -12; R egist er 3-14; Table 3-5 (ANS EL);

Figure 3-5; Figure 3-11; Figure 8-2; Figure 8-3; Figure

9-1; Register 9-1; Section 9.1.4; Example 10-4; Figure

11-5; Table 11-5 (P1M); Sectio n 11.5.2; Section 11.5.7,

Number 4; Table 11-7 (CCP2CON); Section 12.3.1

(Para. 3); Figure 12-6 (Title); Sections 14.2, 14.3 and

14.4 DC Chara cteristic s (Max); Table 14-4 (OSCC ON);

Section 14.3 (TMR0); Section 14.3.2 (TMR0).

Revision C

Section 19.0 Packaging Information: Replaced

package drawings and added note.

Added PIC16F882 part number.

Replaced PICmicro with PIC.

Revision D

Replaced Package Drawings (Rev. AM); Replaced

Development Support Section; Revised Product ID

Section.

Revision E (01/2008)

Added Char Data; Removed Preliminary status;

Revised Device Table (PIC16F882, I/O); Revised the

following: Pin Diagram 44 TQFP, pin 30; Table 5, I/O

RA7; Table 1-1, RA1 and RA4; Section 2.2.1; Register

2-3, INTCON; Example 3-1; Section 3.2.2; Example

3-2; Figure 6-1; Section 6.2.2; Section 6.6; Section

8.10.3; Table 9-1; Equation 11-1; Added Figure 11-14

and renumbered remaining Figures; Register 11-3;

14.9; Section 14.10; Section 17.0; Updated Package

Drawings.

Revision F (04/2009)

Revised Product ID: Removed ‘F’ (std. voltage range)

from part numbers; Revised Figure 6-1: Timer1 Block

Diagram; Revised Figure 8-3, Comparator C2 Block

Diagram; Added note to Section 8.10.3; Revised

Section 8.1 0.7.

APPENDIX B: MIGRATING FROM

OTHER PIC®

DEVICES

This discusses some of the issues in migrating from

other PIC de vices to the PIC16F8 8X Family of devices.

B.1 PIC16F87X to PIC16F88X

TABLE B-1: FEATURE COMPARISON

Feature PIC16F87X PIC16F88X

Max Operating Speed 20 MHz 20 MHz

Max Program

Memory (Words) 8192 8192

SRAM (bytes) 368 368

A/D Resolution 10-bit 10-bit

Data EEPROM (Bytes) 256 256

Timers (8/16-bit) 2/1 2/1

Oscillator Modes 4 8

Brown-out Reset Y Y (2.1V/4V)

Software Control Option

of WDT/BOR NY

Internal Pull-ups RB<7:4> RB<7:0>,

MCLR

Interrupt-on-change RB<7:4> RB<7:0>

Comparator 2 2

References CVREF CVREF and

VP6

ECCP/CCP 0/2 1/1

Ultra Low-Power

Wake-Up NY

Extended WDT N Y

INTOSC Frequencies N 32 kHz-8 MHz

Clock Sw itching N Y

MSSP Standard w/Slave

Address Mask

USART AUSART EUSART

ADC Channels 8 14

Note: This device has been designed to perform

to the parameters of its data sheet. It has

been tested to an electrical specification

designed to determine its conformance

with these parameters. Due to process

differences in the manufacture of this

device, this device may have different

performan ce c harac teristi cs than it s earli er

version. These differences may cause this

device to perform differently in your

application than the earlier version of this

device.

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

INDEX

A/D Specifications....................................................263, 264

Absolute Maximum Ratings..............................................245

AC Characteristics

Industrial and Extended............................................255

Load Conditions.............. .. .... .. ....... .. .. .. .... .. .. ....... .. .. ..254

ACKSTAT .........................................................................198

ACKSTAT Status Flag ......................................................198

ADC ....................................................................................99

Acquisition Requirements ....................................... ..107

Associ a te d Re g i sters............ ..................... ...............109

Block Diag ram................... ............... ..................... ......99

Calculating Acquisition Time.....................................107

Channel Selection........................................ ....... .... ..100

Configuration.............................................................100

Configuring Interrupt.................................................103

Conversi o n Clo ck............ ............... ..................... ......100

Conversion Procedure ............................. .... ......... .. ..103

Internal Sampling Switch (RSS) Impedance..............107

Interrupts...................................................................101

Operation..................................................................102

Operation During Sleep ............................................102

Port Configuration.....................................................100

Reference Voltage (VREF).........................................100

Result For matting............ ............... ..................... ......102

Source Impedance................................... .... ........... ..107

Special Event Trigger................................................102

Starting an A/D Conversion ......................................102

ADCON0 Register .............................................................104

ADCON1 Register .............................................................105

ADRESH Register (ADFM = 0).........................................106

ADRESH Register (ADFM = 1).........................................106

ADRESL Register (ADFM = 0)..........................................106

ADRESL Register (ADFM = 1)..........................................106

Analog Input Connection Considerations............................90

Analog-to-Digital Converter. See AD C

ANSEL Register..................................................................40

ANSELH Register...............................................................48

Assembler

MPASM Assembler...................................................242

Baud Rate Generator........................................................195

BAUDCTL Register.... ......... ............... ........ .......................162

BF .....................................................................................198

BF Status Flag..................................... ........................... ..198

Block Diagrams

(CCP) Capture Mode Operation ...............................126

ADC ............................................................................99

ADC Transfer Function.............................................108

Analog Input Model.............................................90, 108

Auto-Shutdown .........................................................141

Baud Rate Generator................................................195

CCP PWM.................................................................128

Clock Source...............................................................61

Comparator C1 ................. ..................... ............... ......84

Comparator C1 and ADC Voltage Reference.............95

Comparator C2 ................. ..................... ............... ......84

Compare...................................................................127

Crystal Operation........................................................64

EUSART Receive .....................................................152

EUSART Transmit ....................................................151

External RC Mode...................................................... 65

Fail -Safe C l o ck Mon it o r (FSCM)... ...... ..... ...... ...... ...... . 71

In-Circuit Serial Programming Connections ............. 228

Interrupt Logic ........................................................... 221

MSSP (I2C Master Mode)......................................... 193

MSSP (I2C Mode)......... .. ....... .. .. .. .... .. .. ..... .... .. .. .. .. .... 189

MSSP (SPI Mode) .................................................... 183

On-Chip Res e t Circuit................ ............... ........ ........ 21 2

PIC16F883/886 .......................................................... 14

PIC16F884/887 .......................................................... 15

PWM (Enhanced)..................................................... 132

RA0 Pins..................................................................... 42

RA1 Pin ...................................................................... 43

RA2 Pin ...................................................................... 43

RA3 Pin ...................................................................... 44

RA4 Pin ...................................................................... 44

RA5 Pin ...................................................................... 45

RA6 Pin ...................................................................... 45

RA7 Pin ...................................................................... 46

RB0, R B 1, RB2 , R B3 Pi n s.... ...... ...... ..... .. ...... ...... .. ..... 50

RB4, R B 5, RB6 , R B7 Pi n s.... ...... ...... ..... .. ...... ...... .. ..... 51

RC0 Pin...................................................................... 54

RC1 Pin...................................................................... 54

RC2 Pin...................................................................... 54

RC3 Pin...................................................................... 55

RC4 Pin...................................................................... 55

RC5 Pin...................................................................... 55

RC6 Pin...................................................................... 56

RC7 Pin...................................................................... 56

RD0, RD1, RD2, RD3, RD4 Pins........................ ........ 58

RD5, RD6, RD7 Pins...... .............................. .............. 58

RE3 Pin ...................................................................... 60

Resonator Operation. ................................................. 64

Timer1 ........................................................................ 76

Timer2 ........................................................................ 81

TMR0/WDT Prescaler ................................................ 73

Watchdog Timer (WDT)............................................ 224

Break Character (12-bit) Transmit and Receive............... 169

BRG.................................................................................. 195

Brown-out Reset (BOR).................................................... 214

Associated................................................................ 215

Specifications ........................................................... 259

Timing and Characteristics......................... .... .... .. .... 258

Bus Collision During a Repeated Start Condition............. 206

Bus Collision During a Start Condition.............................. 204

Bus Collision During a Stop Condition....... ....................... 207

C Compilers

MPLAB C18.............................................................. 242

MPLAB C30.............................................................. 242

Capture Module. See Enhanced Capture/Compare/

PWM(ECCP)

Capture/Compare/PWM (CCP)

Associated Registers w/ Capture, Compare

and Timer1 ....................................................... 149

Associated Registers w/ PWM and Timer2 .............. 149

Capture Mode........................................................... 126

CCP Pin Configuration ............................................. 126

Compare Mode......................................................... 127

CCP Pin Configuration ..................................... 127

Software Interrupt Mode........................... 126, 127

Special Event Trigger....................................... 127

Timer1 Mode Selection............................. 126, 127

PIC16F882/883/884/886/887

Prescaler...................................................................126

PWM Mode.............. ..................... ............................128

Duty Cycle.......... ..................... ............... ...........129

Effects of Reset.................................................131

Example PWM Frequencies and

Resolutions, 20 MHZ ................................130

Example PWM Frequencies and

Resolutions, 8 MHz...................................130

Operation in Sleep Mode........................... .......131

Setup for Operation................. ..................... .....131

System Clock Frequency Changes...................131

PWM Period.............................. ................................129

Setup for PWM Operation............. ..................... .......131

Timer Resources.......................................................125

CCP1CON (Enhanced) Register.......................................124

CCP2CON Regis te r.............. .............. ............... ...............125

Clock Accuracy with Asynchronous Operation .... .............160

Clock Sources

External Modes. ..........................................................63

EC.......................................................................63

HS.......................................................................64

LP........................................................................64

OST.....................................................................63

RC.......................................................................65

XT .......................................................................64

Internal Modes ............................................................65

Frequency Selection............... ....... .... .. .... .. .........67

HFINTOSC..........................................................65

HFINTOSC/LFINTOSC Switch Timing ...............67

INTOSC ..............................................................65

INTOSCIO...........................................................65

LFINTOSC..........................................................67

Clock Switching. ..................................................................69

CM1CON0 Register.............. ..................... .............. ...........88

CM2CON0 Register.............. ..................... .............. ...........89

CM2CON1 Register.............. ..................... .............. ...........91

Code Examples

A/D Conversion.......... ............... ..................... ...........103

Assign ing Prescaler to Timer0....................................74

Assign ing Prescaler to WDT....... ..................... ...........74

Changing Between Capture Prescalers....................126

Indirect Addressing.....................................................37

Initializing PORTA.......................................................39

Initializing PORTB.......................................................47

Initializing PORTC.......................................................53

Initializing PORTD.......................................................57

Initializing PORTE.......................................................59

Loading the SSPBUF Register .................................184

Saving STATUS and W Registers in RAM ...............223

Ultra L o w - Powe r Wake -u p In i tia li zatio n ...... ...... ......... .41

Write Verify ...............................................................120

Writing to Flash Program Memory............................119

Code Protection ................................................................227

Comparator

C2OUT as T1 Gate................... ............... .............77, 91

Effects of a Reset........................................................87

Operation ....................................................................83

Operation During Sleep ..............................................87

Response Time...........................................................85

Specifications............................................................262

Synchronizing COUT w/Timer1 ..................................91

Comparator Module ........... ....... .. .... .. .... .. ....... .... .. .... .. ....... ..83

Associ a te d Re g i sters............................... ...................97

C1 Output State Versus Input Conditions...................85

Comparator Voltage Reference (CVREF)

Response Time....................................................... ....85

Comparator Voltage Reference (CVREF)............................ 94

Effects of a Reset ................... ............... ..................... 87

Specifications ........................................................... 262

Compare Module. See Enhanced Capture/

Compare/PWM (ECCP)

CONFIG1 Register ........................................................... 210

CONFIG2 Register ........................................................... 211

Configuration Bits ............................................................. 210

CPU Features............................. ............... ..................... .. 209

Customer Change Notification Service............................. 323

Customer Notification Ser vice .. ......... .............. ................. 323

Custome r Support............. ........................... ..................... 323

Data EEPRO M Mem ory.......... ..................... ..................... 111

Associated Registers................................................ 121

Code Protection........................................................ 120

Reading .................................................................... 114

Writing ...................................................................... 114

Data Memory ...................................................................... 22

DC Characteristics

Extended .................................................................. 250

Industrial................................................................... 249

Industrial and Extended............................ 247, 248, 251

Development Support.......................................................241

Device Overview................................................................. 13

ECCP. See Enhanced Capture/Compare/PWM

ECCPAS Regi ster......... ..................... .............. ................. 14 2

EEADR Register............................................................... 112

EEADR Registers............................................................. 111

EEADRH Registe r s............. ............... ............................. ..111

EECON1 Regist e r.... ............... ............... ........ ........... 11 1 , 113

EECON2 Regist e r.... ............... ............... .............. ............. 111

EEDAT Register ............................................................... 112

EEDATH Register............................................................. 112

EEPROM Data Memory

Avoiding Sp u rious Write ............. ...... ...... ...... ..... ...... . 120

Write Verify............................................................... 120

Effects o f Reset

PWM mode............... ..................... ..................... ...... 131

Electrical Specifications.................................................... 245

Enhanced Capture/Compare/PWM ..................................123

Enhanced Capture/Compare/PWM (ECCP)

Enhanced PWM Mode.............................................. 132

Auto-Restart ..................................................... 143

Auto-shutdown.................................................. 141

Direction Change in Full-Bridge Output Mode.. 138

Full-Bridge Application...................................... 136

Full-Bridge Mode .............................................. 136

Half-Bridge Application..................................... 135

Half-Bridge Application Examples .................... 144

Half-Bridge Mode. ............................................. 135

Output Relationships (Active-High and

Active-Low).............................................. 133

Output Relationships Diagram.......................... 134

Programmable Dead Band Delay..................... 144

Shoot-through Current...................................... 144

Start-up Considerations.................................... 140

Specifications ........................................................... 261

Time r R e so u r ces ....... ...... ...... ..... ...... ...... ...... ..... ...... . 124

Enhanced Universal Synchronous

Asynchronous Receiver T ransm itter (EUSART ) ....... 151

Errata.................................................................................. 12

PIC16F882/883/884/886/887

EUSART ...........................................................................151

Associated Registers

Baud Rate Generator........................................163

Asynchronous Mode.................................................153

12-bit Break Transmit and Receive ..................169

Associated Registers

Receive.....................................................159

Transmit....................................................155

Auto-Wa ke-up on Break .................... ...............168

Baud Rate Generator (BRG) ............................163

Clock Accuracy.................................................160

Receiver............................................................156

Setting up 9-bit Mode with Address Detect .......158

Transmitter........................................................153

Baud Rate Generator (BRG)

Auto Baud Rate Detect.....................................167

Baud Rate Error, Calculating.......................... ..163

Baud Rates, Asynchronous Modes ..................164

Formulas...........................................................163

High Baud Rate Select (BRGH Bit) ..................163

Synchronous Master Mode...............................171, 175

Associated Registers

Receive.....................................................174

Transmit....................................................172

Reception..........................................................173

Requirements, Synchronous Receive ..............266

Requirements, Synchronous Transm ission......266

Timing Diagram, Synchronous Receive ...........266

Timing Diagram, Synchronous Transmission...266

Transmission ....................................................171

Synchronous Slave Mode

Associated Registers

Receive.....................................................176

Transmit....................................................175

Reception..........................................................176

Transmission ....................................................175

Fail-Safe Clock Monitor .......................................................71

Fail-Safe Condition Clearing.......................................71

Fail-Safe Detection .....................................................71

Fail-Safe Operation.....................................................71

Reset or Wak e -up from Sleep...... ..................... ..........71

Firmware Instructions ........................................................231

Flash Pr ogram Memory ........................... .........................111

Writing.......................................................................117

Fuses. See Configuration Bits

General Call Address Support ..........................................192

General Purpose Register File............................................22

I2C (MSSP Module)

ACK Pulse.................................... .... .. .... .... .. .....189, 190

Addressing................................................................190

Read/Write Bit Information (R/W Bit)........................190

Reception..................................................................190

Serial Clock (RC3/SCK/SCL)....................................190

Slave Mode...............................................................189

Transmission.............................................................190

I2C Master Mode Reception..............................................198

I2C Master Mode Repeated Start Condition Timing . .........197

I2C Module

Acknowledge Sequence Timing................................201

Baud Rate Generator................................................195

BRG Bl o ck Diag ra m ...... ..... .. ...... .. ...... .. ..... ...... ...... .. . 195

BRG Reset Due to SDA Arbitration During

Start Condition.................................................. 205

BRG Timing.............................................................. 195

Bus Collision

Acknowledge.................................................... 203

Repeated Start Condition..................... .... .. .. .. .. 206

Repeated Start Condition Timing (Case1)........ 206

Repeated Start Condition Timing (Case2)........ 206

Start Condition.................................................. 204

Start Condition Timing.............................. 204, 205

Stop Condition.............................................. .... 207

Stop Condition Timing (Case 1) ............. .. .... .... 207

Stop Condition Timing (Case 2) ............. .. .... .... 207

Bus Collision timing...... ............................ ........ ........ 203

Clock Arbitration....................................................... 202

Clock Arbitration Timing (Master Transmit). ............. 202

Effect of a Reset....................................................... 202

General Call Address Support.................................. 192

Mas te r Mod e...... ...... ...... ..... ...... .......... ..... ...... ...... ..... 193

Master Mode 7-bit Reception Timing........................ 200

Master Mode Operation............................................ 194

Master Mode Start Condition Timing........................ 196

Master Mode Support............................................... 193

Master Mode Transmission ...................................... 198

Master Mode Transmit Sequence ............................ 194

Multi-Master Mode.................................................... 203

Repeat Start Condition Timing Waveform................ 197

Sleep Operation. ....................................................... 202

Stop Condition Receive or Transmit Timing............. 202

Stop Condition Timing .............................................. 201

Waveforms for 7-bit Reception................................. 191

Wave forms for 7 - b i t Trans miss i on.. ...... ..... ...... ...... ... 1 9 1

ID Locations...................................................................... 227

In-Circuit Debugger........................................................... 229

In-C i r cu i t Se rial Pro g ramm i n g (IC S P)... .. .. ..... .. ...... ...... ..... 227

Indirect Addressing, INDF and FSR registers..................... 37

Instruction Format............................................................. 231

Instruction Set................................................................... 231

ADDLW..................................................................... 233

ADDWF .................................................................... 233

ANDLW..................................................................... 233

ANDWF .................................................................... 233

BCF .......................................................................... 233

BSF........................................................................... 233

BTFSC...................................................................... 233

BTFSS...................................................................... 234

CALL......................................................................... 234

CLRF........................................................................ 234

CLRW....................................................................... 234

CLRWDT.................................................................. 234

COMF....................................................................... 234

DECF........................................................................ 234

DECFSZ................................................................... 235

GOTO....................................................................... 235

INCF......................................................................... 235

INCFSZ..................................................................... 235

IORLW...................................................................... 235

IORWF...................................................................... 235

MOVF....................................................................... 236

MOVLW.................................................................... 236

MOVWF.................................................................... 236

NOP.......................................................................... 236

RETFIE..................................................................... 237

RETLW..................................................................... 237

PIC16F882/883/884/886/887

RETURN...................................................................237

RLF ...........................................................................238

RRF...........................................................................238

SLEEP ......................................................................238

SUBLW .....................................................................238

SUBWF.....................................................................239

SWAPF .....................................................................239

XORLW.....................................................................239

XORWF.....................................................................239

Summary Ta b l e...... ............................ ..................... ..232

INTCON Register................................................................31

Inter-Integrated Circuit. See I2C

Internal Oscillator Block ....................................................256

INTOSC

Specifications....................................................257

Internal Sampling Switch (RSS) Impedance......................107

Inter net Address................................ ........................... .....323

Interrupts...........................................................................220

ADC ..........................................................................103

Associ a te d Re g i sters............................... .................222

Context Saving..........................................................223

Interrupt-on-Change....................................................47

PORTB Interrupt-on-C hange ....................................221

RB0/INT ....................................................................220

Timer0.......................................................................221

TMR1 ..........................................................................78

INTOSC

Specifications............................................................256

INTOSC Specifications .............................................256, 257

IOCB Register.............. ..................... ..................... .............49

Load Conditions............................ .... .. .. .. ....... .. .. .... .. .. .. .....254

Master Mode.....................................................................193

Master Mode Support ........................................................193

Master Synchronous Serial Port. See MSSP

MCLR................................................................................213

Internal......................................................................213

Memory Organization..........................................................21

Data ............................................................................22

Program ......................................................................21

Microc h i p In ternet Web Sit e.... ........................... ...............323

Migra tin g from other PICmic ro Devices ............... .............313

MPLAB ASM30 Assembler, Linker, Librarian ...................242

MPLAB ICD 2 In-Circuit Debugger....................................243

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator....................................................243

MPLAB Integrated Development Environment Software ..241

MPLAB PM3 Device Programmer.....................................243

MPLAB REA L IC E In -Circuit Em u l a to r System........ .........243

MPLINK Object Linker/MPL IB Objec t Librarian ....... .........242

MSSP................................................................................179

Block Diagram (SPI Mode) .......................................183

I2C Mode. See I2C

SPI Mode ..................................................................183

SPI Mode. See SPI

MSSP Module

Control Reg i sters .................. ..................... ...............179

I2C Operation............................................................189

SPI Master Mode ......................................................185

SPI Slave Mode........................................................186

Multi-Master Communicati on, Bus Collision and

Bus Arbitration .............. ........................... .................203

Multi-Master Mode ............................................................203

OPCODE Field Descriptions............................................. 231

OPTION Register................................................................ 30

OPTION_R EG Re g i ster........................... ............... ............ 75

OSCCON Register.............................................................. 62

Oscillator

Associ a te d Re g i sters......................... ................... 72, 80

Oscillat o r Module.............. ........ ....................... ................... 61

EC............................................................................... 61

HFINTOSC ................................................................. 61

HS............................................................................... 61

INTOSC...................................................................... 61

INTOSCIO .................................................................. 61

LFINTOSC.................................................................. 61

LP ............................................................................... 61

RC .............................................................................. 61

RCIO........................................................................... 61

XT............................................................................... 61

Oscillato r Parameters............... ......... ............................... 256

Oscillato r Specifications........ ........ .................................. .. 255

Oscillator Start-up Timer (OST)

Specifications ........................................................... 259

Oscillator Switching

Fail - Safe C l o c k Mon it o r .............. .......... ...... . . ..... ...... ... 71

Two-Spe ed Clock Start-up ............... ..................... ...... 69

OSCTUNE Regis te r.................... ............... ............... .......... 66

P1A/P1B/P1C/P1D.See Enhanced Capture/

Com p a r e /P WM (EC CP)....... .. ..... ...... ...... ...... . ...... ..... 132

Packaging......................................................................... 301

Mar ki n g... .. ...... ..... ...... ...... ...... ......... ...... ...... ..... . 301 , 3 0 2

PDIP Details. ............................................................ 303

PCL and PCLATH ............................................................... 37

Stack........................................................................... 37

PCON Register........................................................... 36, 215

PICSTART Plus Deve lopment Program mer..................... 244

PIE1 R e g is t e r...... ...... ..... .. ...... .. ...... ..... .. ...... ...... ..... ...... .. ..... 32

PIE2 R e g is t e r...... ...... ..... .. ...... .. ...... ..... .. ...... ...... ..... ...... .. ..... 33

Pin Diagram

PIC16F883/886, 28-pin (PDIP, SOIC, SSOP).............. 3

PIC16F883/886, 28-pin (QFN).. .................................... 4

PIC16F884/887, 40-Pin (PDIP) .................................... 6

PIC16F884/887, 44-pin (QFN).. .................................... 8

PIC16F884/887, 44-pin (TQFP).................................. 10

Pinout Descriptions

PIC16F883/886 .......................................................... 16

PIC16F884/887 .......................................................... 18

PIR1 Register ..................................................................... 34

PIR2 Register ..................................................................... 35

PORTA ............................................................................... 39

Additional Pin Functions............................................. 40

ANSE L R e g i st e r .. .. ...... .. ..... ...... ...... ...... . ...... ...... . 40

Ultra Low-Power Wake-up................... ......... 40, 41

Associated Registers.................................................. 46

Pin Descriptions and Diagrams .................................. 42

RA0............................................................................. 42

RA1............................................................................. 43

RA2............................................................................. 43

RA3............................................................................. 44

RA4............................................................................. 44

RA5............................................................................. 45

RA6............................................................................. 45

RA7............................................................................. 46

Specifications ........................................................... 257

PIC16F882/883/884/886/887

PORTA Register.................................................................39

PORTB................................................................................47

Additional Pin Functions .............................................47

ANSELH Register...............................................47

Weak Pull-up ......................................................47

Associ a te d Re g i sters............ ..................... .................52

Interrupt-on-Change....................................................47

P1B/P1C/P1D.See Enhanced Capture/

Comp are/PWM + ( EC C P+).. ...... ...... ...... ..... ...... ...47

Pin Descriptions and Diagrams. ..................................50

RB0.............................................................................50

RB1.............................................................................50

RB2.............................................................................50

RB3.............................................................................50

RB4.............................................................................51

RB5.............................................................................51

RB6.............................................................................51

RB7.............................................................................51

PORTB Register.................................................................48

PORTC ...............................................................................53

Associ a te d Re g i sters............ ..................... .................56

P1A.See Enhanced Capture/Compare/

PWM+ (ECCP+) ................ .............. ............... ....53

RC0.............................................................................54

RC1.............................................................................54

RC2.............................................................................54

RC3.............................................................................55

RC3 Pin.....................................................................190

RC4.............................................................................55

RC5.............................................................................55

RC6.............................................................................56

RC7.............................................................................56

Specifications............................................................257

PORTC Register.................................................................53

PORTD ...............................................................................57

Associ a te d Re g i sters............ ..................... .................58

P1B/P1C/P1D.See Enhanced Capture/

Comp are/PWM + ( EC C P+).. ...... ...... ...... ..... ...... ...57

RD0, RD1, RD2, RD3, RD4................. ............... ........58

RD5.............................................................................58

RD6.............................................................................58

RD7.............................................................................58

PORTD Register.................................................................57

PORTE................................................................................59

Associ a te d Re g i sters............ ..................... .................60

RE0.............................................................................60

RE1.............................................................................60

RE2.............................................................................60

RE3.............................................................................60

PORTE Register.................................................................59

Power-Down Mode (Sleep)...............................................226

Power-on Res e t (POR)....... ..................... ............... ..........213

Power-up Timer (PWRT) .... ..................... ............... ..........213

Specifications............................................................259

Precisio n In ternal Oscilla tor Paramete rs........ ............... ....257

Prescaler

Shared WDT/Timer0............. ............... ..................... ..74

Switching Prescaler As s i g n men t....................... ..........74

Program Memory................................................................21

Map and Stack............................................................21

Map and Stack (PIC16F883/884) ...............................21

Map and Stack (PIC16F886/887) ...............................21

Programming, Device Instructions....................................231

PSTRCON Regi ster.................... ..................... .................146

Pulse Steering...................................................................146

PWM (ECCP Module)

Pulse Steering.......................................................... 146

Stee ri n g Syn chro n iz a t ion...... ...... .. ...... ..... .. ...... .. ...... . 14 8

PWM Mode. See Enh anced Captur e/Compare/ PWM...... 132

PWM1CON Register......................................................... 145

RCREG............................................................................. 158

RCSTA Regist e r................... ..................... ............... ........ 161

Reader Response............................................................. 324

Read-Modify-Write Operations......................................... 231

RCREG Register...................................................... 167

Registers

ADCON0 (ADC Control 0)........................................ 104

ADCON1 (ADC Control 1)........................................ 105

ADRESH (ADC Result High) wi th ADFM = 0).......... 106

ADRESH (ADC Result High) wi th ADFM = 1).......... 106

ADRESL (ADC Result Low) with ADFM = 0)............ 106

ADRESL (ADC Result Low) with ADFM = 1)............ 106

ANSEL (Analog Select).............................................. 40

ANSE L H (Ana l o g Se le ct Hi g h ) ....... ...... ..... ...... ...... ..... 48

BAUDCTL (Baud Rate Control)................................ 162

CCP1CON (Enhanced CCP1 Control) ................. .... 124

CCP2CON (CCP2 Control) ...................................... 125

CM1CON0 (C1 Control) ............................................. 88

CM2CON0 (C2 Control) ............................................. 89

CM2CON1 (C2 Control) ............................................. 91

CONFIG1 (Configuration Word Register 1).............. 210

CONFIG2 (Configuration Word Register 2).............. 211

ECCPAS (Enhanced CCP Auto-shutdown Control). 142

EEADR (EEPR OM Add re ss)...... .. ...... .. ..... .. .. ...... .. .. . 112

EECON1 (EEPROM Control 1)......... ......... ........ ...... 113

EEDAT (EEPROM Data).......................................... 112

EEDA T H ( EEPRO M Dat a ) ... ...... ...... .. ..... ...... .. ...... ... 11 2

INTC ON (I n te r rupt Control) ...... ...... ...... ......... .......... ... 3 1

IOCB (Interrupt-on-Change PORTB).......................... 49

OPTION_REG (OPTION)..................................... 30, 75

OSCC ON (Osc il l a tor Con t r o l )....... ......... ...... ...... ......... 62

OSCTUNE (Oscillator Tuning ).................................. .. 66

PCON (Power Control Register)................................. 36

PCON (Power Control)............................................. 215

PIE1 (Peripheral Interrupt Enable 1) .......................... 32

PIE2 (Peripheral Interrupt Enable 2) .......................... 33

PIR1 (Peripheral Interrupt Register 1)........................ 34

PIR2 (Peripheral Interrupt Request 2)........................ 35

PORTA....................................................................... 39

PORTB....................................................................... 48

PORTC....................................................................... 53

PORTD....................................................................... 57

PORTE....................................................................... 59

PSTRCON (Pulse St eer i ng Co n trol)....... .............. .... 146

PWM1CON (Enhanced PWM Control)..................... 145

RCSTA (Receive Status and Control)...................... 161

Reset Values........ ..................... ..................... .......... 217

Rese t Val u e s ( sp e cial r e g i sters )....... ......... ...... ......... 219

Special Function Register Map

PIC16F883/884 ............................................ 23, 24

PIC16F886/887 .................................................. 25

Spec i a l Func t io n R e g i s t e r s....... ...... ...... ..... .......... ...... . 22

Special Register Summary

Bank 0 ................................................................ 26

Bank 1 ................................................................ 27

Bank 2 ................................................................ 28

Bank 3 ................................................................ 28

SRC ON (SR Lat c h C o n t r ol ).. .. ...... .. ...... ..... ...... .. ...... .. . 93

PIC16F882/883/884/886/887

SSPCON (MSSP Control 1)......................................181

SSPCON2 (SSP Control 2).......................................182

SSPMSK (SSP Mas k)....... ..................... ...................208

SSPSTAT (SSP Status)............................................180

STATUS......................................................................29

T1CON........................................................................79

T2CON........................................................................82

TRISA (Tri-State PORTA)...........................................39

TRISB (Tri-State PORTB)...........................................48

TRISC (Tr i-State PORTC) ................... .............. .........53

TRISD (Tr i-State PORTD) ................... .............. .........57

TRISE (Tri-State PORTE)...........................................59

TXSTA (Transmit Status and Control) ......................160

VRCON (Voltage Reference Control) .........................97

WDTCON (Watchdog Tim er Contro l)........................225

WPUB (Wea k Pull-up PORTB)...................................49

Reset.................................................................................212

Revision History................................................................313

SCK...................................................................................183

SDI....................................................................................183

SDO ..................................................................................183

Serial Clock, SCK..............................................................183

Serial Data In, SDI ............................................................183

Serial Data Out, SDO........................................................183

Serial Peripheral Interface. See SP I

Shoot-through Current ......................................................144

Slave Mode General Call Address Sequence...................192

Slave Select Synchronization............................................186

Slave Select, SS ...............................................................183

Sleep.................................................................................226

Wake-up....................................................................226

Wake-up Using Interrupts.........................................226

Softwa re Simulator ( MP L AB SIM).................... .................242

SPBRG..............................................................................163

SPBRGH...........................................................................163

Special Event Trigger........................................................102

Special Function Registers .................................................22

SPI Master Mode.............................................................185

Serial Clock...............................................................183

Serial Data In ............................................................183

Serial Data Out .........................................................183

Slave Select..............................................................183

SPI clock...................................................................185

SPI Mode ..................................................................183

SPI Bus Modes .................................................................188

SPI Mode

Associated Registers with SPI Operation .................188

Bus Mode Compatibility........................... .. .... .. .. .. .....188

Effects of a Reset......................................................188

Enabling SPI I/O .......................................................184

Operation ..................................................................183

Sleep Operation........................................................188

SPI Module

Slave Mode...............................................................186

Slave Select Synchronization ...................................186

Slave Synchronization Timing...................................186

Slave Ti min g with CKE = 0 .................. .....................187

Slave Ti min g with CKE = 1 .................. .....................187

SRCON Register.................................................................93

SS .....................................................................................183

SSP SSPBUF....................................................................185

SSPSR......................................................................185

SSPCON Register............................................................ 181

SSPCON2 Register.......................................................... 182

SSPMSK Register ............ ..................... ..................... ...... 208

SSPOV ............................................................................. 198

SSPOV Status Flag.......................................................... 198

SSPSTAT Regi ster................... ..................... ................... 180

R/W Bit ... ...... ...... ..... .. ...... ...... ..... ...... ...... .. ..... ...... ..... 190

STATUS Regi ster........................... ..................... ............... 29

T1CON Registe r..................... ............... .............. ............... 79

T2CON Registe r..................... ............... .............. ............... 82

Thermal Considerations .................................................... 253

Time-out Sequence ................................. .... .... .... ......... .... 215

Timer0................................................................................. 73

Associated Registers.................................................. 75

External Clock............................................................. 74

Interrupt ...................................................................... 75

Operation.............................................................. 73, 76

Specifications ........................................................... 260

T0CKI ......................................................................... 74

Timer1................................................................................. 76

Associated Registers.................................................. 80

Asynchronous Counter Mode..................................... 77

Reading and Writing........................................... 77

Interrupt ...................................................................... 78

Modes of Operation.................................................... 76

Operation During Sleep.............................................. 78

Oscillator..................................................................... 77

Prescaler .................................................................... 77

Specifications ........................................................... 260

Timer1 Gate

Inve r t in g Gate.... ...... ...... ..... ...... ...... ......... ...... ..... 77

Selecting Source .......................................... 77, 91

SR Latch............................................................. 92

Sync h ro n i zi n g C O U T w/Timer1........ .. ..... ...... .. ... 91

TMR1H Register.........................................................76

TMR1L Register.......................................................... 76

Timer2

Associated Registers.................................................. 82

Timers

Timer1

T1CON ............................................................... 79

Timer2

T2CON ............................................................... 82

Timing Diagrams

A/D Conver sion....... ..................... .............. ...............265

A/D Conversion (Sleep Mode).................................. 265

Acknowledge Sequence Timing ............................... 201

Asynchronous Receptio n.......................................... 158

Asynchronous Tra nsmiss ion..... ................................ 154

Asynchronous Transmission (Back to Back)............ 154

Auto Wake-up Bit (WUE) During Normal Operation. 168

Auto Wa ke-up Bi t (WUE) During Sl ee p .... .. .. ........... . 169

Automatic Baud Rate Calibration.............................. 167

Baud Rate Generator with Clock Arbitration............. 195

BRG Reset Due to SDA Arbi tration....... ................... 205

Brown-out Reset (BOR)............................................ 258

Brown-out Reset Situations...................................... 214

Bus Collision

Start Condition Timing...................................... 204

Bus Collision During a Repeated Start

Condition (Case 1)............................................ 206

Bus Collision During a Repeated Start

Condition (Case2)............................................. 206

Bus Collision During a Start Condition (SCL = 0)..... 205

PIC16F882/883/884/886/887

Bus Collision During a Stop Condition......................207

Bus Collision for Transmit and Acknowledge............203

CLKOUT and I/O. . .....................................................257

Clock Timing.............................................................255

Comparator Output................. ..................... ...............83

Enhanced Capture/Compare/PWM (ECCP).............261

EUSART Synchronous Receiv e (Mast er/ Slave).......266

EUSART Synchronous T ransm ission

(Master/Slave) ..................................................266

Fail-Safe Clock Monitor (FSCM).................................72

Full-Bridge PWM Output...........................................137

Half-Bridge PWM Output ..................................135, 144

I2C Bus Data.............................................................270

I2C Bus Start/Stop Bits ..............................................269

I2C Master Mode First Start Bit Timing.......... ...........196

I2C Master Mode Reception Timing..........................200

I2C Master Mode Transmission Timing.....................199

I2C Module

Bus Collision

Transmit Timing............. ..................... ......203

INT Pin Interrupt........................................................222

Internal Oscillator Switch Timing.................................68

Master Mode Transmit Clock Arbitration...................202

PWM Auto-shutdown

Auto-restart Enabled.........................................143

Firmware Restart..............................................143

PWM Direction Change ............................. ......... .... ..138

PWM Direction Change at Near 100% Duty Cycle...139

PWM Output (Active-High)........... .............. ...............133

PWM Output (A ctive-Low) ............. .............. .............134

Repeat Start Condition..................... .. .. .... .. .. ....... .. ....197

Reset, WDT, OST and Power-up Timer ...................258

Send Break Character Sequenc e.............................170

Slave Synchronization ..............................................186

SPI Mast e r Mode (CKE = 1, SMP = 1) ...... ...............267

SPI Mode Timing (Master Mode) SP I Mo de

Master Mode Timing Diagram ..........................185

SPI Mode Timing (Slave Mode with CKE = 0)..........187

SPI Mode Timing (Slave Mode with CKE = 1)..........187

SPI Slave Mode (CKE = 0) .......................................268

SPI Slave Mode (CKE = 1) .......................................268

Stop Condition Receive or Transmit .........................202

Synchronous Reception (Master Mode, SREN) .......174

Synchronous Transmission.......................................172

Synchronous Transmission (T hrough TXEN) ...........172

Time-out Sequence

Case 1 ..............................................................216

Case 2 ..............................................................216

Case 3 ..............................................................216

Timer0 and Timer1 External Clock ...........................260

Timer1 Incrementing Edge..........................................78

Two Speed Start-up......................... .. .. .... .. .. ....... .. .. .. ..70

Wake-up from Interrupt.............................................227

Timing Pa rameter Symb o l o g y................................. ..........254

Timing Requirements

I2C Bus Data.............................................................271

I2C Bus Start /Stop Bits........... ..................................270

SPI Mode..................................................................269

TRISA .................................................................................39

TRISA Register...................................................................39

TRISB .................................................................................47

TRISB Register...................................................................48

TRISC.................................................................................53

TRISC Register.......... ............... ..................... .....................53

TRISD.................................................................................57

TRISD Regist e r......... .............. ............... ..................... ........ 57

TRISE................................................................................. 59

TRISE Register................................................................... 59

Two-Speed Clock Start-up Mode........................................ 69

TXREG ............................................................................. 153

TXSTA Reg ister........................... ................................. .... 160

BRGH Bit.................................................................. 163

Ultra Low-Power Wake-up....................... ......... 16, 18, 40, 41

Voltage Reference (VR)

Specifications ........................................................... 262

Voltage Reference. See Comparator

Voltage Reference (CVREF)

Voltage References

Associated Registers.................................................. 97

VP6 Stabilization ................. ........ ........ ......... .............. 94

VREF. SEE ADC Reference Voltage

Wake-up on Break............................................................ 168

Wake-up Using Interrupts................................................. 226

Watchdog Timer (WDT).................................................... 224

Associated Registers................................................ 225

Clock Source............................................................ 224

Modes....................................................................... 224

Period....................................................................... 224

Specifications ........................................................... 259

Waveform for Slave Mode General Call

Address Sequence ................................................... 192

WCOL.......... ..................... ..................... ........... 196, 198, 201

WCOL Statu s Flag........................... ................. 196, 198 , 201

WDTCON Register........................................................... 225

WPUB Regist e r............... ..................... ........................... .... 49

WWW Address ...................................... ........................... 323

WWW, On-Line Support..................................................... 12

PIC16F882/883/884/886/887

NOTES:

PIC16F882/883/884/886/887

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PIC16F882/883/884/886/887

READER RESP ONSE

It is ou r intention to provide you w it h th e b es t documentation possible to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

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DS41291FPIC16F882/883/884/886/887

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PIC16F882/883/884/886/887

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: PIC16F883(1), PIC16F883T (1 , 2), PIC16F 88 4(1),

PIC16F884T(1, 2 ), PIC 16F886(1), PIC 1 6F 88 6T (1, 2),

PIC16F887(1), PIC16F887T (1 , 2)

VDD range 2.0V to 5.5V

Temperature

Range: I= -40°C to +85°C (Industrial)

E= -40°C to +125°C (Extended)

Package: ML = Quad Flat No Leads (QFN)

P = Plastic DIP

PT = Plastic Thin-Quad Flatpack (TQFP)

SO = Plastic Small Outline (SOIC) (7.50 mm)

SP = Skinny Plastic DIP

SS = Plastic Shrink Small Outline

Pattern: QTP, SQTP, Code or Special Requirements

(blank oth erwis e )

Examples:

a) PIC16F883-E/P 301 = Extend ed Temp., PDIP

package, 20 MHz, QTP patter n #301

b) PIC16F883-I/SO = Industrial Temp., SOIC

package, 20 MHz

Note 1: T = In tape and reel SSOP, SOIC and

QFN packages only.

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WORLDWIDE SALES AND SERVICE

03/26/09