SiC533
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S20-0485-Rev. C, 29-Jun-2020 1Document Number: 75010
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35 A VRPower® Integrated Power Stage
DESCRIPTION
The SiC533 is an integrated power stage solution optimized
for synchronous buck applications to offer high current, high
efficiency, and high power density performance. Packaged
in Vishay’s proprietary 4.5 mm x 3.5 mm MLP package,
SiC533 enables voltage regulator designs to deliver up to
35 A continuous current per phase.
The internal power MOSFETs utilize Vishay’s
state-of-the-art Gen IV TrenchFET® technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC533 incorporates an advanced MOSFET gate driver
IC that features high current driving capability, adaptive
dead-time control, an integrated bootstrap Schottky diode,
and zero current detection to improve light load efficiency.
The driver is also compatible with a wide range of PWM
controllers, supports tri-state PWM, and 5 V PWM logic.
A user selectable diode emulation mode (ZCD_EN#) is
included to improve the light load performance. The device
also supports PS4 mode to reduce power consumption
when system operates in standby state.
FEATURES
• Thermally enhanced PowerPAK® MLP4535-22L
package
• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode
• Delivers up to 35 A continuous current, 40 A at 10 ms peak
current
• High efficiency performance
• High frequency operation up to 2 MHz
• Power on reset
• 5 V PWM logic with tri-state and hold-off
• Supports PS4 mode light load requirement for IMVP8 with
low shutdown supply current (5 V, 3 μA)
• Under voltage lockout for VCIN
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for computing, graphics card and
memory
• Intel IMVP-8 VRPower delivery
- VCORE, VGRAPHICS, VSYSTEM AGENT Skylake, Kabylake
platforms
- VCCGI for Apollo Lake platforms
• Up to 24 V rail input DC/DC VR modules
TYPICAL APPLICATION DIAGRAM
Fig. 1 - SiC533 Typical Application Diagram
PWM
controller
Gate
driver
5V VIN
VOUT
VCIN
PWM
VDRV
VIN
BOOT
VSWH
PGND
GL
CGND
PHASE
ZCD_EN#
SiC533
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PINOUT CONFIGURATION
Fig. 2 - SiC533 Pin Configuration
PIN DESCRIPTION
PIN NUMBER NAME FUNCTION
1 ZCD_EN#
The ZCD_EN# pin enables or disables Diode Emulation. When ZCD_EN# is LOW, diode
emulation is allowed. When ZCD_EN# is HIGH, continuous conduction mode is forced.
ZCD_EN# can also be put in a high impedance mode by floating the pin. If both ZCD_EN#
and PWM are floating, the device shuts down and consumes typically 3 μA (9 μA max.)
current
2V
CIN Supply voltage for internal logic circuitry
23 CGND Analog ground for the driver IC
3N.C.
This pin can be either left floating or connected to CGND.
Internally it is either connected to GND or not internally
connected depending on manufacturing location.
Factory code “G” on line 3, pin 3 = CGND
Factory code “T” on line 3, pin 3 = not internally connected
4 BOOT High-side driver bootstrap voltage
5 PHASE Return path of high-side gate driver
6 to 8, 25 VIN Power stage input voltage. Drain of high-side MOSFET
9 to 11, 17, 18, 20, 26 PGND Power ground
12 to 16 VSWH Switch node of the power stage
19, 24 GL Low-side gate signal
21 VDRV Supply voltage for internal gate driver
22 PWM PWM control input
ORDERING INFORMATION
PART NUMBER PACKAGE MARKING CODE
SiC533CD-T1-GE3 PowerPAK® MLP4535-22L SiC533 5 V PWM optimized
SiC533DB Reference board
1
2
3
4
5
ZCD_EN#
VCIN
N.C.
BOOT
PHASE
16
15
14
13
12
V
SWH
V
SWH
V
SWH
V
SWH
V
SWH
11 10 9 8 7 6
17 18 19 20 21 22
PGND
PGND
PGND
PGND
PGND
GL
VDRV
PWM
PGND
VIN
VIN
VIN
PGND
26
VIN
25
CGND
23
GL
24
G Y W W
P/N
LL
T Y W W
P/N
LL
SiC533
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PART MARKING INFORMATION
Note
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
(1) The specification values indicated “AC” is VSWH to PGND, -8 V (< 20 ns, 10 μJ), min. and 35 V (< 50 ns), max.
(2) The specification value indicates “AC voltage” is VBOOT to PGND, 40 V (< 50 ns) max.
(3) The specification value indicates “AC voltage” is VBOOT to VPHASE, 8 V (< 50 ns) max.
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER CONDITIONS LIMIT UNIT
Input voltage VIN -0.3 to +28
V
Control logic supply voltage VCIN -0.3 to +7
Drive supply voltage VDRV -0.3 to +7
Switch node (DC voltage) VSWH
-0.3 to +28
Switch node (AC voltage) (1) -8 to +35
BOOT voltage (DC voltage) VBOOT
33
BOOT voltage (AC voltage) (2) 40
BOOT to PHASE (DC voltage) VBOOT- PHASE
-0.3 to +7
BOOT to PHASE (AC voltage) (3) -0.3 to +8
All logic inputs and outputs
(PWM and ZCD_EN#) -0.3 to VCIN + 0.3
Max. operating junction temperature TJ150
°CAmbient temperature TA-40 to +125
Storage temperature Tstg -65 to +150
Electrostatic discharge protection Human body model, JESD22-A114 2000 V
Charged device model, JESD22-C101 1000
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM UNIT
Input voltage (VIN)4.5-24
V
Drive supply voltage (VDRV) 4.555.5
Control logic supply voltage (VCIN) 4.555.5
BOOT to PHASE (VBOOT-PHASE, DC voltage) 4 4.5 5.5
Thermal resistance from junction to PCB - 5 - °C/W
Thermal resistance from junction to case - 2.5 -
= pin 1 indicator
P/N = part number code
=Siliconix logo
=ESD symbol
F = assembly factory code
Y = year code
WW = week code
LL = lot code
F Y W W
P/N
LL
SiC533
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Notes
(1) Typical limits are established by characterization and are not production tested
(2) Guaranteed by design
ELECTRICAL SPECIFICATIONS
(ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C, unless otherwise stated)
PARAMETER SYMBOL TEST CONDITION
LIMITS UNIT
MIN. TYP. MAX.
POWER SUPPLY
Control logic supply current IVCIN
VPWM = FLOAT - 80 -
μAVPWM = FLOAT, VZCD_EN# = 0 V - 120 -
fS = 300 kHz, D = 0.1 - 300 -
Drive supply current IVDRV
fS = 300 kHz, D = 0.1 - 7.5 12 mA
fS = 1 MHz, D = 0.1 - 25 -
PS4 mode supply current IVCIN + IVDRV VPWM = VZCD_EN# = FLOAT,
TA = -10 °C to +100 °C -39μA
BOOTSTRAP SUPPLY
Bootstrap diode forward voltage VFIF = 2 mA - - 0.65 V
PWM CONTROL INPUT
Rising threshold VTH_PWM_R 3.6 3.9 4.2
V
Falling threshold VTH_PWM_F 0.72 1 1.3
Tri-state voltage VTRI VPWM = FLOAT - 2.5 -
Tri-state rising threshold VTRI_TH_R 1.11.351.6
Tri-state falling threshold VTRI_TH_F 3.4 3.7 4
Tri-state rising threshold hysteresis VHYS_TRI_R - 325 - mV
Tri-state falling threshold hysteresis VHYS_TRI_F - 250 -
PWM input current IPWM
VPWM = 5 V - - 350 μA
VPWM = 0 V - - -350
ZCD_EN# CONTROL INPUT
Rising threshold VTH_ZCD_EN#_R 3.3 3.6 3.9
V
Falling threshold VTH_ZCD_EN#_F 1.1 1.4 1.7
Tri-state voltage VTRI_ZCD_EN# VZCD_EN# = FLOAT - 2.5 -
Tri-state rising threshold VTRI_ZCD_EN#_R 1.5 1.8 2.1
Tri-state falling threshold VTRI_ZCD_EN#_F 2.93.153.4
Tri-state rising threshold hysteresis VHYS_TRI_ZCD#_R - 375 - mV
Tri-state falling threshold hysteresis VHYS_TRI_ZCD#_F - 450 -
ZCD_EN# input current IZCD_EN#
VZCD_EN# = 5 V - - 100 μA
VZCD_EN# = 0 V - - -100
PS4 exit latency tPS4EXIT --5μs
TIMING SPECIFICATIONS
Tri-state to GH/GL rising
propagation delay tPD_TRI_R
No load, see Fig. 4
-20-
ns
Tri-state hold-off time tTSHO - 150 -
GH - turn off propagation delay tPD_OFF_GH -20-
GH - turn on propagation delay
(dead time rising) tPD_ON_GH -20-
GL - turn off propagation delay tPD_OFF_GL -20-
GL - turn on propagation delay
(dead time falling) tPD_ON_GL -20-
PWM minimum on-time TPWM_ON_MIN 30 - -
PROTECTION
Under voltage lockout VUVLO
VCIN rising, on threshold - 3.4 3.9 V
VCIN falling, off threshold 2.4 2.9 -
Under voltage lockout hysteresis VUVLO_HYST - 500 - mV
SiC533
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DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-State Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
VPWM_TH_R the low-side is turned off and the high-side is
turned on. When PWM input is driven below VPWM_TH_F the
high-side is turned off and the low-side is turned on. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC533 to
pull the PWM input into the tri-state region (see definition of
PWM logic and tri-state, Fig. 4). If the PWM input stays in
this region for the tri-state hold-off period, tTSHO, both
high-side and low-side MOSFETs are turned off. The
function allows the VR phase to be disabled without
negative output voltage swing caused by inductor ringing
and saves a Schottky diode clamp. The PWM and tri-state
regions are separated by hysteresis to prevent false
triggering. The SiC533 incorporates PWM voltage
thresholds that are compatible with 5 V logic.
Diode Emulation Mode and PS4 Mode (ZCD_EN#)
The ZCD_EN# pin enables or disables diode emulation
mode. When ZCD_EN# is driven below VTH_ZCD_EN#_F, diode
emulation is allowed. When ZCD_EN# is driven above
VTH_ZCD_EN#_R, continuous conduction mode is forced.
Diode emulation mode allows for higher converter efficiency
under light load situations. With diode emulation active, the
SiC533 will detect the zero current crossing of the output
inductor and turn off the low-side MOSFET. This ensures
that discontinuous conduction mode (DCM) is achieved.
Diode emulation is asynchronous to the PWM signal,
therefore, the SiC533 will respond to the ZCD_EN# input
immediately after it changes state.
The ZCD_EN# pin can be floated resulting in a high
impedance state. High impedance on the input of ZCD_EN#
combined with a tri-stated PWM output will shut down the
SiC533, reducing current consumption to typically 5 μA.
This is an important feature in achieving the low standby
current requirements required in the PS4 state in ultrabooks
and notebooks.
Voltage Input (VIN)
This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Switch Node (VSWH and PHASE)
The switch node, VSWH, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node, VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor.
Ground Connections (CGND and PGND)
PGND (power ground) should be externally connected to
CGND (control signal ground). The layout of the printed circuit
board should be such that the inductance separating CGND
and PGND is minimized. Transient differences due to
inductance effects between these two pins should not
exceed 0.5 V.
Control and Drive Supply Voltage Input (VDRV, VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
The SiC533 has an internal adaptive logic to avoid shoot
through and optimize dead time. The shoot through
protection ensures that both high-side and low-side
MOSFETs are not turned on at the same time. The adaptive
dead time control operates as follows. The high-side and
low-side gate voltages are monitored to prevent the
MOSFET turning on from tuning on until the other
MOSFET’s gate voltage is sufficiently low (< 1 V). Built in
delays also ensure that one power MOSFET is completely
off, before the other can be turned on. This feature helps to
adjust dead time as gate transitions change with respect to
output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate
drive, holding high-side and low-side MOSFET gates low,
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC533 also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of the
device.
SiC533
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FUNCTIONAL BLOCK DIAGRAM
Fig. 3 - SiC533 Functional Block Diagram
DEVICE TRUTH TABLE
ZCD_EN# PWM GH GL
Hi-Z (PS4 mode) X L L
LLL
H, IL > 0 A
L, IL < 0 A
LHHL
LHi-ZL L
HLLH
HHHL
HHi-ZL L
ZCD_EN#
VSWH
GL
+
-
GL
+
-
UVLO
VCIN
PWM logic
control &
state
machine
Anti-cross
conduction
control
logic
BOOT VIN
PWM
C
GND
V
CIN
P
GND
PHASE
V
DRV
V
DRV
SiC533
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PWM TIMING DIAGRAM
Fig. 4 - Definition of PWM Logic and Tri-State
ZCD_EN# - PS4 EXIT TIMING
Fig. 5 - ZCD_EN# - PS4 Exit Timing
VTH_PWM_R
VTH_PWM_F
VTH_TRI_R
VTH_TRI_F
PWM
GH
GL
tPD_OFF_GLtTSHO
tPD_ON_GHtPD_OFF_GH
tPD_ON_GL
tTSHO
tPD_TRI_R
tPD_TRI_R
PWM
V
SWH
ZCD_EN#
t
PS4EXIT
5
V
5
V
2.5 V
SiC533
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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 12 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH, (DCR = 0.32 m), TA = 25 °C
(All power loss and normalized power loss curves show SiC533 losses only unless otherwise stated)
Fig. 6 - Efficiency vs. Output Current (VIN = 12 V)
Fig. 7 - Power Loss vs. Switching Frequency (VIN = 12 V)
Fig. 8 - Efficiency vs. Output Current (VIN = 9 V)
Fig. 9 - Safe Operating Area (VIN = 12 V)
Fig. 10 - Power Loss vs. Output Current (VIN = 12 V)
Fig. 11 - Efficiency vs. Output Current (VIN = 19 V)
62
66
70
74
78
82
86
90
94
0 5 10 15 20 25 30 35
Efciency (%)
Output Current, IOUT (A)
1 MHz
750 kHz
500 kHz
Complete converter efciency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
200 300 400 500 600 700 800 900 1000 1100
Power Loss, PL(W)
Switching Frequency, fs (KHz)
IOUT = 25 A
62
66
70
74
78
82
86
90
94
0 5 10 15 20 25 30 35
Efciency (%)
Output Current, I
OUT
(A)
Complete converter efciency
P
IN
= [(V
IN
x I
IN
) + 5 V x (I
VDRV
+ I
VCIN
)]
P
OUT
= V
OUT
x I
OUT
, measured at output capacitor
1 MHz
750 kHz
500 kHz
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
0 5 10 15 20 25 30 35
Power Loss, PL(W)
Output Current, IOUT (A)
750 kHz
1 MHz
500 kHz
62
66
70
74
78
82
86
90
94
0 5 10 15 20 25 30 35
Efciency (%)
Output Current, IOUT (A)
1 MHz
500 kHz
750 kHz
Complete converter efciency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor
SiC533
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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 12 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH, (DCR = 0.32 m), TA = 25 °C
(All power loss and normalized power loss curves show SiC533 losses only unless otherwise stated)
Fig. 12 - UVLO Threshold vs. Temperature
Fig. 13 - BOOT Diode Forward Voltage vs. Temperature
Fig. 14 - PWM Threshold vs. Temperature
Fig. 15 - PS4 Exit Latency vs. Temperature
Fig. 16 - Driver Supply Current vs. Temperature
Fig. 17 - ZCD_EN# Threshold vs. Temperature
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
-60 -40 -20 0 20 40 60 80 100 120 140
Control Logic Supply Voltage, VCIN (V)
Temperature (°C)
VUVLO_FALLING
VUVLO_RISING
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
-60 -40 -20 0 20 40 60 80 100 120 140
BOOT Diode Forward Voltage, VF(V)
Temperature (°C)
IF= 2 mA
0.0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8
-60 -40 -20 0 20 40 60 80 100 120 140
PWM Threshold Voltage, VPWM (V)
Temperature (°C)
VTRI_TH_R
VTRI_TH_F
VTRI
VTH_PWM_R
VTH_PWM_F
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-60 -40 -20 0 20 40 60 80 100 120 140
Normalized PS4 Exit Latency, tPS4EXIT
Temperature (°C)
3
4
5
6
7
8
9
10
11
-60 -40 -20 0 20 40 60 80 100 120 140
Driver Supply Current, IVDRV (mA)
Temperature (°C)
fPWM = 300 kHz
0.0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8
-60 -40 -20 0 20 40 60 80 100 120 140
ZCD_EN# Threshold Voltage, VZCD_EN# (V)
Temperature (°C)
VTRI_ZCD_EN#_R
VTRI_ZCD_EN#_F
VTH_ZCD_EN#_R
VTH_ZCD_EN#_F
SiC533
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PCB LAYOUT RECOMMENDATIONS
Step 1: VIN / PGND Planes and Decoupling
1. Layout VIN and PGND planes as shown above.
2. Ceramic capacitors should be placed directly between
VIN and PGND, and close to the device for best
decoupling effect.
3. Different values / packages of ceramic capacitors should
be used to cover entire decoupling spectrum e.g. 1210,
0805, 0603, 0402.
4. Smaller capacitance values, placed closer to the
device’s VIN pin(s), results in better high frequency noise
absorbing.
Step 2: VSWH Plane
1. Connect output inductor to IC with large plane to lower
resistance.
2. VSWH plane also serves as a heat-sink for low-side
MOSFET. Make the plane wide and short to achieve the
best thermal path.
3. If a snubber network is required, place the components
as shown above, the network can be placed at bottom.
Step 3: VCIN / VDRV Input Filter
1. The VCIN / VDRV input filter ceramic cap should be placed
as close as possible to the IC. It is recommended to
connect two capacitors separately.
2. VCIN capacitor should be placed between pin 2 (VCIN)
and pin 3 (AGND of driver IC) to achieve best noise
filtering.
3. VDRV capacitor should be placed between pin 20
(PGND of driver IC) and pin 21 (VDRV) to provide maximum
instantaneous driver current for low side MOSFET during
switching cycle.
4. For connecting VCIN to AGND, it is recommended to use
a large plane to reduce parasitic inductance.
Step 4: BOOT Resistor and Capacitor Placement
1. The components need to be placed as close as possible
to IC, directly between PHASE (pin 5) and BOOT (pin 4).
2. To reduce parasitic inductance, chip size 0402 can be
used.
V
IN
V
SWH
P
GND
V
IN
Plane
P
GND
Plane
P
GND
Plane
V
SWH
Snubber
PGND
Cvcin
Cvdrv
AGND
Cboot
Rboot
SiC533
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Step 5: Signal Routing
1. Route the PWM and ZCD_EN# signal traces out of the
top left corner next to pin 1.
2. The PWM signal is an important signal, both signal and
return traces should not cross any power nodes on any
layer.
3. It is best to “shield” these traces from power switching
nodes, e.g. VSWH, with a GND island to improve signal
integrity.
4. GL (pin 19) has been connected with GL pad (pin 24)
internally.
Step 6: Adding Thermal Relief Vias
1. Thermal relief vias can be added on the VIN and AGND
pads to utilize inner layers for high-current and thermal
dissipation.
2. To achieve better thermal performance, additional vias
can be placed on VIN plane and PGND plane.
3. VSWH pad is a noise source, it is not recommended to
place vias on this pad.
4. 8 mil vias for pads and 10 mils vias for planes are the
optimal via sizes. Vias on pad may drain solder during
assembly and cause assembly issues. Consult with the
assembly house for guidelines.
Step 7: Ground Connection
1. It is recommended to make a single connection between
AGND and PGND which can be made on the top layer.
2. It is recommended to make the entire first inner layer
(below top layer) the ground plane and separate them
into AGND and PGND planes.
3. These ground planes provide shielding between noise
sources on top layer and signal traces on bottom layer.
P
GND
A
GND
A
GND
V
IN
Plane
P
GND
Plane
V
SWH
P
GND
V
IN
A
GND
VSWH
P
GND
A
GND
SiC533
www.vishay.com Vishay Siliconix
S20-0485-Rev. C, 29-Jun-2020 12 Document Number: 75010
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?75010.
PRODUCT SUMMARY
Part number SiC533
Description 35 A power stage, 4.5 VIN to 24 VIN, 5 V PWM with ZCD, PS4 mode
Input voltage min. (V) 4.5
Input voltage max. (V) 24
Continuous current rating max. (A) 35
Switch frequency max. (kHz) 2000
Enable (yes / no) No
Monitoring features -
Protection UVLO, THDN
Light load mode ZCD, PS4
Pulse-width modulation (V) 5
Package type PowerPAK MLP4535-22L
Package size (W, L, H) (mm) 4.5 x 3.5 x 0.75
Status code 2
Product type VRPower (DrMOS)
Applications Computer, industrial, networking
Package Information
www.vishay.com Vishay Siliconix
Revision: 20-Oct-14 1Document Number: 67234
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
MLP 4.5 x 3.5-22L BWL Case Outline
DIM. MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A (8) 0.70 0.75 0.80 0.027 0.0029 0.031
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.0078 0.0098 0.0110
D 4.50 BSC 0.177 BSC
e 0.50 BSC 0.019 BSC
E 3.50 BSC 0.137 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017
N (3) 22 22
Nd (3) 66
Ne (3) 55
D1-1 0.35 0.40 0.45 0.013 0.015 0.017
D1-2 0.15 0.20 0.25 0.005 0.007 0.009
D2-1 1.02 1.07 1.12 0.040 0.042 0.044
D2-2 1.02 1.07 1.12 0.040 0.042 0.044
D2-3 1.47 1.52 1.57 0.057 0.059 0.061
D2-4 0.25 0.30 0.35 0.009 0.011 0.013
E1-1 1.095 1.145 1.195 0.043 0.045 0.047
E1-2 2.67 2.72 2.77 0.105 0.107 0.109
E1-3 0.35 0.40 0.45 0.013 0.015 0.017
E1-4 1.85 1.90 1.95 0.072 0.074 0.076
E1-5 0.095 0.145 0.195 0.0037 0.0057 0.0076
E2-1 3.05 3.10 3.15 0.120 0.122 0.124
E2-2 1.065 1.115 1.165 0.0419 0.0438 0.0458
E2-3 0.695 0.745 0.795 0.027 0.029 0.031
E2-4 0.40 0.45 0.50 0.015 0.017 0.019
K1 0.40 BSC 0.015 BSC
K2 0.07 BSC 0.002 BSC
K3 0.05 BSC 0.001 BSC
K4 0.40 BSC 0.015 BSC
9
14
1
1110
5
4
3
2
16
1719
8
22
7
15
2021
6
13
18
12
9
14
1
11 10
5
4
3
2
16
17 19
8
22
7
15
20 21
6
13
18
12
D
E
A
A1
A2
b
e
L
D2-1
D2-2D2-3
D2-4
E2-1
E2-2E2-3
E2-4
K1
K2
A
Pin 1 dot
by marking
C
56
B
K3
D1-1
E1-1
E1-2
D1-2 K4
E1-4
E1-3
E1-5
0.1 CB
2x
0.1 CA
2x 0.08 C
Package Information
www.vishay.com Vishay Siliconix
Revision: 20-Oct-14 2Document Number: 67234
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals,
Nd is the number of terminals in X-direction and
Ne is the number of terminals in Y-direction.
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
T14-0626-Rev. A, 20-Oct-14
DWG: 6028
PAD Patter n
www.vishay.com Vishay Siliconix
Revision: 05-Nov-14 1Document Number: 66914
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Recommended Land Pattern PowerPAK® MLP4535-22L
Land pattern
Package outline top view, transparent
(not bottom view)
All dimensions in millimeters
22 21 20 19 18 17
22 21 20 19 18 17
678 91011
678 91011
1
2
3
4
5
16
15
14
13
12
16
15
14
13
12
4.5
(D2-4)
0.3 (D1-2)
0.2
(K4)
0.4
(D2-1)
1.07
(K1)
0.4
(D1-1)
0.4
(D2-2)
1.07
(D2-3)
1.52
(L)
0.4
(K2)
0.07
(K3)
0.05
(E1-2)
2.72
(E2-2)
1.11
(E1-1)
1.15
(E2-3)
0.75
(e)
0.5
1
2
3
4
5
(D1-5)
0.14
(E1-4)
1.9
(E1-3)
0.4
(E2-4)
0.45
3.5
3.5
(E2-1)
3.1
(b)
0.25
3.05
0.75 0.3
0.75 0.5 x 4 = 2
0.29
0.21
0.37
0.3
0.3
0.5 x 4 = 2
0.75 0.75
0.59
0.14
4.5
0.75 10.5 0.75 0.3
0.5 x 3 = 1.5
0.3
0.45 0.45
0.31
0.75 0.75
1
0.5 x 2
= 1
0.5 x 2
= 1
0.3
0.1
0.9 0.37 1.2
0.29
0.74
0.3
0.55 0.5
0.29
1.16 1.61
0.25
0.8 0.3
0.30.4
0.36
2.05
22 21 20 19 18 17
678 91011
1
2
3
4
5
16
15
14
13
12
Legal Disclaimer Notice
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Revision: 01-Jan-2021 1Document Number: 91000
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