SiC533 www.vishay.com Vishay Siliconix 35 A VRPower(R) Integrated Power Stage DESCRIPTION FEATURES The SiC533 is an integrated power stage solution optimized for synchronous buck applications to offer high current, high efficiency, and high power density performance. Packaged in Vishay's proprietary 4.5 mm x 3.5 mm MLP package, SiC533 enables voltage regulator designs to deliver up to 35 A continuous current per phase. * Thermally enhanced PowerPAK(R) MLP4535-22L package The internal power MOSFETs utilize Vishay's state-of-the-art Gen IV TrenchFET(R) technology that delivers industry benchmark performance to significantly reduce switching and conduction losses. The SiC533 incorporates an advanced MOSFET gate driver IC that features high current driving capability, adaptive dead-time control, an integrated bootstrap Schottky diode, and zero current detection to improve light load efficiency. The driver is also compatible with a wide range of PWM controllers, supports tri-state PWM, and 5 V PWM logic. A user selectable diode emulation mode (ZCD_EN#) is included to improve the light load performance. The device also supports PS4 mode to reduce power consumption when system operates in standby state. * Vishay's Gen IV MOSFET technology and a low-side MOSFET with integrated Schottky diode * Delivers up to 35 A continuous current, 40 A at 10 ms peak current * High efficiency performance * High frequency operation up to 2 MHz * Power on reset * 5 V PWM logic with tri-state and hold-off * Supports PS4 mode light load requirement for IMVP8 with low shutdown supply current (5 V, 3 A) * Under voltage lockout for VCIN * Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS * Multi-phase VRDs for computing, graphics card and memory * Intel IMVP-8 VRPower delivery - VCORE, VGRAPHICS, VSYSTEM platforms AGENT Skylake, Kabylake - VCCGI for Apollo Lake platforms * Up to 24 V rail input DC/DC VR modules TYPICAL APPLICATION DIAGRAM 5V VIN VIN VDRV BOOT PHASE VCIN ZCD_EN# PWM controller PWM VSWH VOUT Gate driver PGND GL CGND Fig. 1 - SiC533 Typical Application Diagram S20-0485-Rev. C, 29-Jun-2020 Document Number: 75010 1 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix PGND PGND PGND VIN VIN VIN PINOUT CONFIGURATION 11 10 9 8 7 6 25 VIN VSWH 12 26 PGND VSWH 13 VSWH 14 23 CGND VSWH 15 24 GL 18 19 20 21 22 GL PGND VDRV PWM PGND 17 PGND VSWH 16 5 PHASE 4 BOOT 3 N.C. 2 VCIN 1 ZCD_EN# Fig. 2 - SiC533 Pin Configuration PIN DESCRIPTION PIN NUMBER 1 NAME FUNCTION ZCD_EN# The ZCD_EN# pin enables or disables Diode Emulation. When ZCD_EN# is LOW, diode emulation is allowed. When ZCD_EN# is HIGH, continuous conduction mode is forced. ZCD_EN# can also be put in a high impedance mode by floating the pin. If both ZCD_EN# and PWM are floating, the device shuts down and consumes typically 3 A (9 A max.) current 2 VCIN Supply voltage for internal logic circuitry 23 CGND Analog ground for the driver IC N.C. This pin can be either left floating or connected to CGND. Internally it is either connected to GND or not internally connected depending on manufacturing location. Factory code "G" on line 3, pin 3 = CGND Factory code "T" on line 3, pin 3 = not internally connected 3 4 BOOT High-side driver bootstrap voltage 5 PHASE Return path of high-side gate driver 6 to 8, 25 VIN 9 to 11, 17, 18, 20, 26 PGND Power ground 12 to 16 VSWH Switch node of the power stage 19, 24 GL P/N P/N LL LL GYWW TYWW Power stage input voltage. Drain of high-side MOSFET Low-side gate signal 21 VDRV Supply voltage for internal gate driver 22 PWM PWM control input ORDERING INFORMATION PART NUMBER SiC533CD-T1-GE3 SiC533DB S20-0485-Rev. C, 29-Jun-2020 PACKAGE PowerPAK(R) MLP4535-22L MARKING CODE SiC533 5 V PWM optimized Reference board Document Number: 75010 2 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix PART MARKING INFORMATION = pin 1 indicator P/N = P/N = Siliconix logo = ESD symbol F = assembly factory code Y = year code WW = week code LL = lot code LL FYWW part number code ABSOLUTE MAXIMUM RATINGS ELECTRICAL PARAMETER CONDITIONS LIMIT VIN -0.3 to +28 Control logic supply voltage VCIN -0.3 to +7 Drive supply voltage VDRV Input voltage Switch node (DC voltage) -0.3 to +7 -0.3 to +28 VSWH Switch node (AC voltage) (1) BOOT voltage (DC voltage) -8 to +35 BOOT to PHASE (DC voltage) 40 -0.3 to +7 VBOOT- PHASE BOOT to PHASE (AC voltage) (3) -0.3 to +8 All logic inputs and outputs (PWM and ZCD_EN#) -0.3 to VCIN + 0.3 Max. operating junction temperature TJ 150 Ambient temperature TA -40 to +125 Storage temperature Tstg -65 to +150 Human body model, JESD22-A114 2000 Charged device model, JESD22-C101 1000 Electrostatic discharge protection V 33 VBOOT BOOT voltage (AC voltage) (2) UNIT C V Note * Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability (1) The specification values indicated "AC" is V SWH to PGND, -8 V (< 20 ns, 10 J), min. and 35 V (< 50 ns), max. (2) The specification value indicates "AC voltage" is V BOOT to PGND, 40 V (< 50 ns) max. (3) The specification value indicates "AC voltage" is V BOOT to VPHASE, 8 V (< 50 ns) max. RECOMMENDED OPERATING RANGE ELECTRICAL PARAMETER Input voltage (VIN) MINIMUM TYPICAL MAXIMUM 4.5 - 24 Drive supply voltage (VDRV) 4.5 5 5.5 Control logic supply voltage (VCIN) 4.5 5 5.5 4 4.5 5.5 BOOT to PHASE (VBOOT-PHASE, DC voltage) Thermal resistance from junction to PCB - 5 - Thermal resistance from junction to case - 2.5 - S20-0485-Rev. C, 29-Jun-2020 UNIT V C/W Document Number: 75010 3 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 C, unless otherwise stated) PARAMETER SYMBOL TEST CONDITION VPWM = FLOAT IVCIN VPWM = FLOAT, VZCD_EN# = 0 V fS = 300 kHz, D = 0.1 LIMITS MIN. UNIT TYP. MAX. - 80 - - 120 - - 300 - fS = 300 kHz, D = 0.1 - 7.5 12 fS = 1 MHz, D = 0.1 - 25 - IVCIN + IVDRV VPWM = VZCD_EN# = FLOAT, TA = -10 C to +100 C - 3 9 A VF IF = 2 mA - - 0.65 V POWER SUPPLY Control logic supply current Drive supply current PS4 mode supply current IVDRV A mA BOOTSTRAP SUPPLY Bootstrap diode forward voltage PWM CONTROL INPUT Rising threshold VTH_PWM_R 3.6 3.9 4.2 Falling threshold VTH_PWM_F 0.72 1 1.3 Tri-state voltage VTRI - 2.5 - VTRI_TH_R 1.1 1.35 1.6 4 Tri-state rising threshold Tri-state falling threshold VPWM = FLOAT VTRI_TH_F 3.4 3.7 Tri-state rising threshold hysteresis VHYS_TRI_R - 325 - Tri-state falling threshold hysteresis VHYS_TRI_F - 250 - VPWM = 5 V - - 350 VPWM = 0 V - - -350 PWM input current IPWM V mV A ZCD_EN# CONTROL INPUT Rising threshold VTH_ZCD_EN#_R 3.3 3.6 3.9 Falling threshold VTH_ZCD_EN#_F 1.1 1.4 1.7 Tri-state voltage VTRI_ZCD_EN# - 2.5 - VTRI_ZCD_EN#_R 1.5 1.8 2.1 Tri-state rising threshold Tri-state falling threshold VZCD_EN# = FLOAT VTRI_ZCD_EN#_F 2.9 3.15 3.4 Tri-state rising threshold hysteresis VHYS_TRI_ZCD#_R - 375 - Tri-state falling threshold hysteresis VHYS_TRI_ZCD#_F - 450 - VZCD_EN# = 5 V - - 100 VZCD_EN# = 0 V - - -100 ZCD_EN# input current IZCD_EN# PS4 exit latency tPS4EXIT - - 5 tPD_TRI_R - 20 - tTSHO - 150 - GH - turn off propagation delay tPD_OFF_GH - 20 - GH - turn on propagation delay (dead time rising) tPD_ON_GH - 20 - GL - turn off propagation delay tPD_OFF_GL - 20 - GL - turn on propagation delay (dead time falling) tPD_ON_GL - 20 - TPWM_ON_MIN 30 - - VCIN rising, on threshold - 3.4 3.9 VCIN falling, off threshold 2.4 2.9 - - 500 - V mV A s TIMING SPECIFICATIONS Tri-state to GH/GL rising propagation delay Tri-state hold-off time PWM minimum on-time No load, see Fig. 4 ns PROTECTION Under voltage lockout Under voltage lockout hysteresis VUVLO VUVLO_HYST V mV Notes (1) Typical limits are established by characterization and are not production tested (2) Guaranteed by design S20-0485-Rev. C, 29-Jun-2020 Document Number: 75010 4 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix DETAILED OPERATIONAL DESCRIPTION PWM Input with Tri-State Function Switch Node (VSWH and PHASE) The PWM input receives the PWM control signal from the VR controller IC. The PWM input is designed to be compatible with standard controllers using two state logic (H and L) and advanced controllers that incorporate tri-state logic (H, L and tri-state) on the PWM output. For two state logic, the PWM input operates as follows. When PWM is driven above VPWM_TH_R the low-side is turned off and the high-side is turned on. When PWM input is driven below VPWM_TH_F the high-side is turned off and the low-side is turned on. For tri-state logic, the PWM input operates as previously stated for driving the MOSFETs when PWM is logic high and logic low. However, there is a third state that is entered as the PWM output of tri-state compatible controller enters its high impedance state during shut-down. The high impedance state of the controller's PWM output allows the SiC533 to pull the PWM input into the tri-state region (see definition of PWM logic and tri-state, Fig. 4). If the PWM input stays in this region for the tri-state hold-off period, tTSHO, both high-side and low-side MOSFETs are turned off. The function allows the VR phase to be disabled without negative output voltage swing caused by inductor ringing and saves a Schottky diode clamp. The PWM and tri-state regions are separated by hysteresis to prevent false triggering. The SiC533 incorporates PWM voltage thresholds that are compatible with 5 V logic. The switch node, VSWH, is the circuit power stage output. This is the output applied to the power inductor and output filter to deliver the output for the buck converter. The PHASE pin is internally connected to the switch node, VSWH. This pin is to be used exclusively as the return pin for the BOOT capacitor. Diode Emulation Mode and PS4 Mode (ZCD_EN#) The ZCD_EN# pin enables or disables diode emulation mode. When ZCD_EN# is driven below VTH_ZCD_EN#_F, diode emulation is allowed. When ZCD_EN# is driven above VTH_ZCD_EN#_R, continuous conduction mode is forced. Diode emulation mode allows for higher converter efficiency under light load situations. With diode emulation active, the SiC533 will detect the zero current crossing of the output inductor and turn off the low-side MOSFET. This ensures that discontinuous conduction mode (DCM) is achieved. Diode emulation is asynchronous to the PWM signal, therefore, the SiC533 will respond to the ZCD_EN# input immediately after it changes state. The ZCD_EN# pin can be floated resulting in a high impedance state. High impedance on the input of ZCD_EN# combined with a tri-stated PWM output will shut down the SiC533, reducing current consumption to typically 5 A. This is an important feature in achieving the low standby current requirements required in the PS4 state in ultrabooks and notebooks. Voltage Input (VIN) This is the power input to the drain of the high-side power MOSFET. This pin is connected to the high power intermediate BUS rail. S20-0485-Rev. C, 29-Jun-2020 Ground Connections (CGND and PGND) PGND (power ground) should be externally connected to CGND (control signal ground). The layout of the printed circuit board should be such that the inductance separating CGND and PGND is minimized. Transient differences due to inductance effects between these two pins should not exceed 0.5 V. Control and Drive Supply Voltage Input (VDRV, VCIN) VCIN is the bias supply for the gate drive control IC. VDRV is the bias supply for the gate drivers. It is recommended to separate these pins through a resistor. This creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the IC. Bootstrap Circuit (BOOT) The internal bootstrap diode and an external bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. Connect a boot strap capacitor with one leg tied to BOOT pin and the other tied to PHASE pin. Shoot-Through Protection and Adaptive Dead Time The SiC533 has an internal adaptive logic to avoid shoot through and optimize dead time. The shoot through protection ensures that both high-side and low-side MOSFETs are not turned on at the same time. The adaptive dead time control operates as follows. The high-side and low-side gate voltages are monitored to prevent the MOSFET turning on from tuning on until the other MOSFET's gate voltage is sufficiently low (< 1 V). Built in delays also ensure that one power MOSFET is completely off, before the other can be turned on. This feature helps to adjust dead time as gate transitions change with respect to output current and temperature. Under Voltage Lockout (UVLO) During the start up cycle, the UVLO disables the gate drive, holding high-side and low-side MOSFET gates low, until the supply voltage rail has reached a point at which the logic circuitry can be safely activated. The SiC533 also incorporates logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. Document Number: 75010 5 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM BOOT V IN VDRV VCIN UVLO ZCD_EN# VCIN PWM PWM logic control & state machine Anti-cross conduction control logic + GL PHASE VSWH + VDRV CGND GL PGND Fig. 3 - SiC533 Functional Block Diagram DEVICE TRUTH TABLE ZCD_EN# PWM GH Hi-Z (PS4 mode) X L L L L H, IL > 0 A L, IL < 0 A L H H L L Hi-Z L L H L GL H L L H H H L H Hi-Z L L S20-0485-Rev. C, 29-Jun-2020 Document Number: 75010 6 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix PWM TIMING DIAGRAM VTH_PWM_R VTH_PWM_F PWM VTH_TRI_F VTH_TRI_R tPD_OFF_GL tTSHO GL tPD_ON_GL tPD_TRI_R tPD_ON_GH tTSHO tPD_OFF_GH tPD_TRI_R GH Fig. 4 - Definition of PWM Logic and Tri-State ZCD_EN# - PS4 EXIT TIMING 5V PWM tPS4EXIT VSWH 5V ZCD_EN# 2.5 V Fig. 5 - ZCD_EN# - PS4 Exit Timing S20-0485-Rev. C, 29-Jun-2020 Document Number: 75010 7 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS 94 40 90 35 86 30 500 kHz 82 Output Current, IOUT (A) Efficiency (%) Test condition: VIN = 12 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH, (DCR = 0.32 m), TA = 25 C (All power loss and normalized power loss curves show SiC533 losses only unless otherwise stated) 750 kHz 1 MHz 78 74 70 Complete converter efficiency PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] POUT = VOUT x IOUT, measured at output capacitor 66 1 MHz 1 MHz 20 500 kHz 15 10 5 62 0 0 5 10 15 20 25 30 35 0 15 30 45 60 75 90 105 120 135 150 Output Current, IOUT (A) PCB Temperature, TPCB (C) Fig. 6 - Efficiency vs. Output Current (VIN = 12 V) Fig. 9 - Safe Operating Area (VIN = 12 V) 5.0 16.0 IOUT = 25 A 14.0 Power Loss, PL (W) 4.5 Power Loss, PL (W) 25 4.0 3.5 3.0 2.5 12.0 10.0 8.0 6.0 2.0 4.0 1.5 2.0 1.0 0.0 200 300 400 500 600 700 800 1 MHz 750 kHz 500 kHz 0 900 1000 1100 5 10 15 20 25 30 35 Output Current, IOUT (A) Switching Frequency, fs (KHz) Fig. 7 - Power Loss vs. Switching Frequency (VIN = 12 V) Fig. 10 - Power Loss vs. Output Current (VIN = 12 V) 94 94 90 90 500 kHz 86 500 kHz 82 Efficiency (%) Efficiency (%) 86 1 MHz 750 kHz 78 74 70 82 750 kHz 78 1 MHz 74 70 Complete converter efficiency PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] POUT = VOUT x IOUT, measured at output capacitor 66 Complete converter efficiency PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] POUT = VOUT x IOUT, measured at output capacitor 66 62 62 0 5 10 15 20 25 30 35 Output Current, IOUT (A) Fig. 8 - Efficiency vs. Output Current (VIN = 9 V) S20-0485-Rev. C, 29-Jun-2020 0 5 10 15 20 25 30 35 Output Current, IOUT (A) Fig. 11 - Efficiency vs. Output Current (VIN = 19 V) Document Number: 75010 8 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS 4.2 1.8 4.0 1.6 Normalized PS4 Exit Latency, tPS4EXIT Control Logic Supply Voltage, VCIN (V) Test condition: VIN = 12 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH, (DCR = 0.32 m), TA = 25 C (All power loss and normalized power loss curves show SiC533 losses only unless otherwise stated) 3.8 3.6 VUVLO_RISING 3.4 3.2 VUVLO_FALLING 3.0 2.8 2.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 -60 -40 -20 0 20 40 60 80 -60 -40 -20 100 120 140 0 Temperature (C) 60 80 100 120 140 11 0.80 10 0.75 IF = 2 mA 0.70 0.65 0.60 0.55 0.50 Driver Supply Current, IVDRV (mA) BOOT Diode Forward Voltage, VF (V) 40 Fig. 15 - PS4 Exit Latency vs. Temperature Fig. 12 - UVLO Threshold vs. Temperature fPWM = 300 kHz 9 8 7 6 5 4 0.45 3 0.40 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) Temperature (C) Fig. 13 - BOOT Diode Forward Voltage vs. Temperature Fig. 16 - Driver Supply Current vs. Temperature 4.8 4.2 VTH_PWM_R 3.6 VTRI_TH_F 3.0 2.4 VTRI 1.8 VTRI_TH_R 1.2 VTH_PWM_F 0.6 ZCD_EN# Threshold Voltage, VZCD_EN# (V) 4.8 PWM Threshold Voltage, VPWM (V) 20 Temperature (C) 4.2 VTH_ZCD_EN#_R 3.6 3.0 VTRI_ZCD_EN#_F 2.4 VTRI_ZCD_EN#_R 1.8 1.2 VTH_ZCD_EN#_F 0.6 0.0 0.0 -60 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 Fig. 14 - PWM Threshold vs. Temperature S20-0485-Rev. C, 29-Jun-2020 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) Fig. 17 - ZCD_EN# Threshold vs. Temperature Document Number: 75010 9 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix PCB LAYOUT RECOMMENDATIONS Step 1: VIN / PGND Planes and Decoupling Step 3: VCIN / VDRV Input Filter Cvdrv VIN Plane VIN PGND VSWH Cvcin AGND PGND PGND Plane 1. Layout VIN and PGND planes as shown above. 2. Ceramic capacitors should be placed directly between VIN and PGND, and close to the device for best decoupling effect. 3. Different values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210, 0805, 0603, 0402. 4. Smaller capacitance values, placed closer to the device's VIN pin(s), results in better high frequency noise absorbing. 1. The VCIN / VDRV input filter ceramic cap should be placed as close as possible to the IC. It is recommended to connect two capacitors separately. 2. VCIN capacitor should be placed between pin 2 (VCIN) and pin 3 (AGND of driver IC) to achieve best noise filtering. 3. VDRV capacitor should be placed between pin 20 (PGND of driver IC) and pin 21 (VDRV) to provide maximum instantaneous driver current for low side MOSFET during switching cycle. 4. For connecting VCIN to AGND, it is recommended to use a large plane to reduce parasitic inductance. Step 2: VSWH Plane Step 4: BOOT Resistor and Capacitor Placement VSWH Cboot Snubber PGND Plane 1. Connect output inductor to IC with large plane to lower resistance. 2. VSWH plane also serves as a heat-sink for low-side MOSFET. Make the plane wide and short to achieve the best thermal path. Rboot 1. The components need to be placed as close as possible to IC, directly between PHASE (pin 5) and BOOT (pin 4). 2. To reduce parasitic inductance, chip size 0402 can be used. 3. If a snubber network is required, place the components as shown above, the network can be placed at bottom. S20-0485-Rev. C, 29-Jun-2020 Document Number: 75010 10 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix Step 5: Signal Routing Step 7: Ground Connection AGND AGND AGND VSWH PGND PGND 1. Route the PWM and ZCD_EN# signal traces out of the top left corner next to pin 1. 1. It is recommended to make a single connection between AGND and PGND which can be made on the top layer. 2. The PWM signal is an important signal, both signal and return traces should not cross any power nodes on any layer. 2. It is recommended to make the entire first inner layer (below top layer) the ground plane and separate them into AGND and PGND planes. 3. It is best to "shield" these traces from power switching nodes, e.g. VSWH, with a GND island to improve signal integrity. 3. These ground planes provide shielding between noise sources on top layer and signal traces on bottom layer. 4. GL (pin 19) has been connected with GL pad (pin 24) internally. Step 6: Adding Thermal Relief Vias VSWH AGND PGND VIN PGND Plane VIN Plane 1. Thermal relief vias can be added on the VIN and AGND pads to utilize inner layers for high-current and thermal dissipation. 2. To achieve better thermal performance, additional vias can be placed on VIN plane and PGND plane. 3. VSWH pad is a noise source, it is not recommended to place vias on this pad. 4. 8 mil vias for pads and 10 mils vias for planes are the optimal via sizes. Vias on pad may drain solder during assembly and cause assembly issues. Consult with the assembly house for guidelines. S20-0485-Rev. C, 29-Jun-2020 Document Number: 75010 11 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC533 www.vishay.com Vishay Siliconix PRODUCT SUMMARY Part number SiC533 Description 35 A power stage, 4.5 VIN to 24 VIN, 5 V PWM with ZCD, PS4 mode Input voltage min. (V) 4.5 Input voltage max. (V) 24 Continuous current rating max. (A) 35 Switch frequency max. (kHz) Enable (yes / no) Monitoring features Protection Light load mode Pulse-width modulation (V) Package type Package size (W, L, H) (mm) 2000 No UVLO, THDN ZCD, PS4 5 PowerPAK MLP4535-22L 4.5 x 3.5 x 0.75 Status code 2 Product type VRPower (DrMOS) Applications Computer, industrial, networking Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?75010. S20-0485-Rev. C, 29-Jun-2020 Document Number: 75010 12 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix MLP 4.5 x 3.5-22L BWL Case Outline 2x D A 5 6 Pin 1 dot by marking A 0.08 C K1 0.1 C A D1-2 D1-1 A1 22 21 20 19 A2 18 17 D2-1 K4 D2-4 17 18 19 20 21 22 2x 12 E2-2 2 3 e K2 4 5 B 6 7 8 9 11 10 9 10 11 C DIM. 8 D2-3 MILLIMETERS E1-2 13 12 K3 E2-3 E1-1 13 5 b 4 E1-5 15 14 E1-3 E2-4 14 E2-1 15 3 E 2 1 16 16 E1-4 0.1 C B 1 7 D2-2 6 L INCHES MIN. NOM. MAX. MIN. NOM. A (8) 0.70 0.75 0.80 0.027 0.0029 0.031 A1 0.00 - 0.05 0.000 - 0.002 0.30 0.0078 A2 b (4) 0.20 ref. 0.20 0.25 0.008 ref. 0.0098 D 4.50 BSC 0.177 BSC e 0.50 BSC 0.019 BSC E L 3.50 BSC 0.35 0.40 MAX. 0.0110 0.137 BSC 0.45 0.013 0.015 N (3) 22 22 Nd (3) 6 6 Ne (3) 5 5 0.017 D1-1 0.35 0.40 0.45 0.013 0.015 0.017 D1-2 0.15 0.20 0.25 0.005 0.007 0.009 D2-1 1.02 1.07 1.12 0.040 0.042 0.044 D2-2 1.02 1.07 1.12 0.040 0.042 0.044 D2-3 1.47 1.52 1.57 0.057 0.059 0.061 D2-4 0.25 0.30 0.35 0.009 0.011 0.013 E1-1 1.095 1.145 1.195 0.043 0.045 0.047 E1-2 2.67 2.72 2.77 0.105 0.107 0.109 E1-3 0.35 0.40 0.45 0.013 0.015 0.017 E1-4 1.85 1.90 1.95 0.072 0.074 0.076 E1-5 0.095 0.145 0.195 0.0037 0.0057 0.0076 E2-1 3.05 3.10 3.15 0.120 0.122 0.124 E2-2 1.065 1.115 1.165 0.0419 0.0438 0.0458 E2-3 0.695 0.745 0.795 0.027 0.029 0.031 E2-4 0.40 0.45 0.50 0.015 0.017 0.019 K1 0.40 BSC 0.015 BSC K2 0.07 BSC 0.002 BSC K3 0.05 BSC 0.001 BSC K4 0.40 BSC 0.015 BSC Document Number: 67234 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 20-Oct-14 Package Information www.vishay.com Vishay Siliconix Notes 1. Use millimeters as the primary measurement 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994 3. N is the number of terminals, Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body 6. Exact shape and size of this feature is optional 7. Package warpage max. 0.08 mm 8. Applied only for terminals T14-0626-Rev. A, 20-Oct-14 DWG: 6028 Document Number: 67234 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 20-Oct-14 PAD Pattern www.vishay.com Vishay Siliconix Recommended Land Pattern PowerPAK(R) MLP4535-22L Land pattern 0.74 0.3 0.75 1.2 2 0.29 0.25 1.16 4 0.31 0.8 0.3 16 0.14 15 14 1.61 13 2.05 0.37 3 5 12 22 10 11 21 20 19 18 16 2 15 3 14 4 13 5 12 Revision: 05-Nov-14 7 8 9 10 0.75 7 8 0.5 x 2 =1 9 1 10 0.5 x 2 =1 11 0.75 17 1 6 6 3 9 (D2-3) 1.52 0. 8 0.1 7 (D2-2) 1.07 0.37 0.3 0.3 6 (L) 0.4 0.59 0.75 12 0.4 0.3 0.3 17 0.45 0.9 13 3.5 14 0.36 18 0.75 0.75 0.3 (E2-3) 0.75 (e) 0.5 5 15 0.5 21 20 19 1 0.5 x 4 = 2 3.05 0.29 0.21 (K2) 0.07 16 (b) 0.25 (E2-1) 3.1 3.5 (D1-5) 0.14 3 4 (E1-1) 1.15 (K3) 0.05 (E1-4) 1.9 (E1-2) 2.72 (E2-2) 1.11 1 2 0.45 22 18 17 (E2-4) 0.45 21 20 19 (E1-3) 0.4 22 1 0.5 x 4 = 2 4.5 0.75 0.5 x 3 = 1.5 0.3 0.55 0.5 (D1-2) 0.2 (D1-1) 0.4 0.29 4.5 (K4) (D2-4) 0.3 0.4 (D2-1) (K1) 1.07 0.4 0.75 Package outline top view, transparent (not bottom view) All dimensions in millimeters 11 Document Number: 66914 1 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer's technical experts. Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. (c) 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 01-Jan-2021 1 Document Number: 91000