CY62187EV30, MoBL
®
64 Mbit (4M x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 001-48998 Rev. *C Revised July 10, 20 0 9
Features
■
Very High Speed
❐
55 ns
■
Wide Voltage Range
❐
2.2V to 3.7V
■
Ultra Low Standby Power
❐
Typical Standby Current: 8 μA
❐
Maximum Standby Current: 48 μA
■
Ultra Low Acti ve Power
❐
Typical Active Current : 4. 0 mA at f = 1 MHz
■
Easy Memory Expansion with CE
1
, CE
2,
and OE Features
■
Automatic Power Down when Deselected
■
CMOS for Optimum Speed and Power
■
Available in Pb-Free 48-Ball FBG A Package
Functional Description
The CY62187EV30 is a high performance CMOS static RAM
organized as 4M words by 16 bits
[1]
. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life™ (MoBL
®
) in portable appli-
cations such as cellular telephones. The device also has an
automatic power down feature that si gnificantly reduces power
consumption by 99 percent when addresses are not toggling.
The device can also be put into standby mode when deselected
(CE
1
HIGH or CE
2
LOW or both BHE and BLE are HIGH). The
input and output pins (IO
0
through IO
15
) are placed in a high
impedance state when: deselected (CE
1
HIGH or CE
2
LOW),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH), or during a
write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (IO
0
through IO
7
), is
written into the location specified on the address pins (A
0
through
A
21
). If Byte High Enable (BHE) is LOW, then dat a from I/O pins
(IO
8
through IO
15
) is written into the location specified on the
address pins (A
0
through A
21
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW , then data
from the memory location specifie d by the address pins appea r
on IO
0
to IO
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO
8
to IO
15
. See the Truth Table on page 9
for a complete description of read and write modes.
4096K × 16
RAM Array I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA-IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
Power-down
Circuit
CE
2
CE
1
A
20
A
19
A
21
Logic Block Diagram
Note
1. For best practice recommendations, refe r to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
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CY62187EV30
Document #: 001-48998 Rev. *C Page 2 of 12
Pin Configuration
Figure 1. 48-Ball VFBGA
Product Portfolio
Product V
CC
Range (V) Speed
(ns)
Power Dissipation
Operating I
CC
(mA) Standby I
SB2
(μA)
f = 1 MHz f = f
Max
Min Typ
[2]
Max Typ
[2]
Max Typ
[2]
Max Typ
[2]
Max
CY62187EV30LL 2.2 3.0 3.7 55 4.0 6 45 55 8 48
70 4.0 6 35 45 8 48
WE
A
11
A
10
A
6
A
0
A
3
CE
1
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
Vss
A
7
IO
0
BHE
CE
2
A
17
A
2
A
1
BLE
V
CC
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
A
19
A
18
A
20
3
26
5
4
1
D
E
B
A
C
F
G
H
A
16
Vcc
A
21
Note
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
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CY62187EV30
Document #: 001-48998 Rev. *C Page 3 of 12
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... – 55°C to + 125°C
Supply Voltage to Ground
Potential............................... ...........–0.3V to V
CC(max)
+ 0.3V
DC Voltage Applied to Outputs
in High Z State
[3, 4]
........................–0.3V to V
CC (max)
+ 0.3V
DC Input Voltage
[3, 4]
.............. ......–0.3V to V
CC (max)
+ 0.3V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch Up Current.....................................................>200 mA
Operating Range
Device Range Ambient
Temperature V
CC[5]
CY62187EV30LL Industrial –40°C to +85°C 2.2V to 3.7V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 55 ns 70 ns Unit
Min Typ
[2]
Max Min Typ
[2]
Max
V
OH
Output HIGH Voltage 2.2V < V
CC
< 2.7V I
OH
= –0.1 mA 2.0 2.0 V
2.7V < V
CC
< 3.7V I
OH
= –1.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage 2.2V < V
CC
< 2.7V I
OL
= 0.1 mA 0.4 0.4 V
2.7V < V
CC
< 3.7V I
OL
= 2.1 mA 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2V < V
CC
< 2.7V 1.8 V
CC
+ 0.3V 1.8 V
CC
+ 0.3V V
2.7V < V
CC
< 3.7V 2.2 V
CC
+ 0.3V 2.2 V
CC
+ 0.3V V
V
IL
Input LOW Voltage 2.2V< V
CC
< 2.7V –0.3 0.6 –0.3 0.6 V
2.7V < V
CC
< 3.7V –0.3 0.7 –0.3 0.7 V
I
IX
Input Leakage Current GND < V
I
< V
CC
–1 +1 –1 +1 μA
I
OZ
Output Leakage Current GND < V
O
< V
CC
, Output Disabled –1 +1 –1 +1 μA
I
CC
V
CC
Operating Supply
Current f = f
Max
= 1/t
RC
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
45 55 35 45 mA
f = 1 MHz 4.0 6 4.0 6 mA
I
SB2 [6]
Automatic CE
Power-Down
Current—CMOS Inputs
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.7V
848 848μA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz, V
CC
= V
CC(typ)
25 pF
C
OUT
Output Capacitance 35 pF
Notes
3. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
4. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
5. Full Device AC operation assumes a 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after V
CC
stabilization.
6. Only chip enables (CE
1
and CE
2
) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
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CY62187EV30
Document #: 001-48998 Rev. *C Page 4 of 12
Thermal Resistance
Tested initially and after any design or process changes that may affect these pa rameters.
Parameter Description Test Conditions FBGA Unit
Θ
JA
Thermal Resistance
(Junction to Ambient) S ti l l Air, soldered on a 3 × 4. 5 in ch,
2-layer printed circuit board 59.06 °C/W
Θ
JC
Thermal Resistance
(Junction to Case) 14.08 °C/W
Figure 2. AC Test Loads and Waveforms
Table 1. AC Test Loads
Parameter 2.2V to 3.7V Unit
R1 1103 Ω
R2 1554 Ω
R
TH
645 Ω
V
TH
2.2V < V
CC
< 3V V
CC
/2 V
3V < V
CC
< 3.7V 1.5 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
[2]
Max Unit
V
DR
V
CC
for Data Retention 1.5 V
I
CCDR [6]
Data Retention Current V
CC
= 1.5V, CE
1
> V
CC
– 0.2V, CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V 48 μA
t
CDR[7]
Chip Deselect to Data
Retention Time 0ns
t
R[8]
Operation Recovery Time t
RC
ns
Figure 3. Data Retention Waveform
[9]
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
t
CDR
V
DR
>1.5 V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE
.
BLE
or
V
CC(min)
V
CC(min)
CE
2
Notes
7. Tested initially and after an y design or process changes that may affect these parameters.
8. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
9. BHE.BLE is the AND of both BHE and BLE. Chip is desele cted by either di sabling the chip enable signals or by disabling both BHE and BLE.
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CY62187EV30
Document #: 001-48998 Rev. *C Page 5 of 12
Switching Characteristics
Over the Operating R ange
[10]
Parameter Description 55 ns 70 ns Unit
Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 55 70 ns
t
AA
Address to Data Valid 55 70 ns
t
OHA
Data Hold from Address Change 6 6 ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid 55 70 ns
t
DOE
OE LOW to Data Valid 25 35 ns
t
LZOE
OE LOW to LOW Z
[11]
55ns
t
HZOE
OE HIGH to High Z
[11, 12]
20 25 ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low Z
[11]
10 10 ns
t
HZCE
CE
1
HIGH and CE
2
LOW to High Z
[11, 12]
20 25 ns
t
PU
CE
1
LOW and CE
2
HIGH to Power Up 0 0 ns
t
PD
CE
1
HIGH and CE
2
LOW to Power Down 55 70 ns
t
DBE
BLE/BHE LOW to Data Valid 55 70 ns
t
LZBE
BLE/BHE LOW to Low Z
[11]
10 10 ns
t
HZBE
BLE/BHE HIGH to HIGH Z
[11, 12]
20 25 ns
Write Cycle
[13]
t
WC
Write Cycle Time 55 70 ns
t
SCE
CE
1
LOW and CE
2
HIGH
to Write End 45 60 ns
t
AW
Address Setup to Write End 45 60 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Setup to Write Start 0 0 ns
t
PWE
WE Pulse Width 40 50 ns
t
BW
BLE/BHE LOW to Write End 45 60 ns
t
SD
Data Setup to Write End 25 35 ns
t
HD
Data Hold from Wr ite End 0 0 ns
t
HZWE
WE LOW to High-Z
[11, 12]
20 25 ns
t
LZWE
WE HIGH to Low-Z
[11]
10 10 ns
Notes
10.Test condit ions for all parameters other than tri-state parameters assume signal transition time of 1V/ns, timing reference levels of V
TH
, input pulse level s of 0 to V
CC(typ)
,
and outpu t lo ad ing of the specified I
OL
/I
OH
as shown in AC Test Loads on page 4.
11. At any given temperature an d voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given
device.
12.t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedence state.
13.The inte rnal W rite t ime of the memory is defin ed by the overlap of WE , CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a write
and any of these signals can t erminate a write by going INA CTIVE. The data in put setup and h old timing should be referen ced to the edge of the signal that terminates
the write.
[+] Feedback
CY62187EV30
Document #: 001-48998 Rev. *C Page 6 of 12
Switching Waveforms
Figure 4. Read Cycle 1 (Address Transition Controlled)
[14, 15]
Figure 5. Read Cycle 2 (OE Controlled)
[15, 16]
ADDRESS
DATA OUT
PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
PD
t
HZBE
t
LZBE
t
HZCE
t
DBE
HIGH
I
CC
I
SB
IMPEDANCE
OE
CE
1
ADDRESS
V
CC
SUPPLY
CURRENT
BHE
/
BLE
DATA OUT
CE
2
Notes
14.The device is continuously selected. OE, CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
.
15.WE is HIGH for read cycle.
16.Address valid prior to or coincident with CE
1
, BHE, BLE transition LOW and CE
2
transition HIGH.
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CY62187EV30
Document #: 001-48998 Rev. *C Page 7 of 12
Figure 6. Write Cycle 1 (WE Controlled)
[13, 17, 18, 19]
Figure 7. Write Cycle 2 (CE
1
or CE
2
Controlled)
[13, 17, 18, 19]
Switching Waveforms
(continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
VALID DATA
t
BW
NOTE 19
ADDRESS
WE
DATA IO
OE
BHE
/
BLE
CE
1
CE
2
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
VALID DATA
NOTE 19
t
BW
t
SA
ADDRESS
WE
DATA IO
OE
BHE
/
BLE
CE
1
CE
2
Notes
17.Data I/O is high impedance if OE = V
IH
.
18.If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high impedance state.
19.During this period the I/Os are in output state and input signals should not be applied.
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CY62187EV30
Document #: 001-48998 Rev. *C Page 8 of 12
Figure 8. Write Cycle 3 (WE Controlled, OE LOW)
[18, 19]
Figure 9. Write Cycle 4 (BHE/BLE Controlled, OE LOW)
[18,19]
Switching Waveforms
(continued)
VAL ID DATA
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
t
BW
NOTE 19
ADDRESS
CE
1
CE
2
BHE
/
BLE
WE
DATA IO
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
VALID DATA
t
BW
t
SCE
t
PWE
NOTE 19
ADDRESS
CE
1
CE
2
BHE
/
BLE
WE
DATA IO
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CY62187EV30
Document #: 001-48998 Rev. *C Page 9 of 12
Truth Table
CE
1
CE
2
WE OE BHE BLE Inputs Outputs Mode Power
HX
[20]
X X X X High Z Deselect/Power Down Standby (I
SB
)
X
[20]
L X X X X High Z Deselect/Power Down Standby (I
SB
)
X
[20]
X
[20]
X X H H High Z Deselect/Power Down Standby (I
SB
)
LHHLLLData Out (IO
0
–IO
15
) Read Active (I
CC
)
L H H L H L High Z (IO
8
–IO
15
):
Data Out (IO
0
–IO
7
)Read Active (I
CC
)
LHHLLHData Out (IO
8
–IO
15
);
High Z (IO
0
–IO
7
)Read Active (I
CC
)
LHLXLLData In (IO
0
–IO
15
) W rite Active (I
CC
)
LHLXHLHigh Z (IO
8
–IO
15
);
Data In (IO
0
–IO
7
)Write Active (I
CC
)
LHLXLHData In (IO
8
–IO
15
);
High Z (IO
0
–IO
7
)Write Active (I
CC
)
L H H H L H High Z Output Disabled Active (I
CC
)
L H H H H L High Z Output Disabled Active (I
CC
)
L H H H L L High Z Output Disabled Active (I
CC
)
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
55 CY62187EV30LL-55BAXI 001-50044 48-Ball Fine Pitch Ball Grid Array (8 x 9.5 x 1.4 mm) Pb-Free In dustrial
70 CY62187EV30LL-70BAXI 001-50044 48-Ball Fine Pitch Ball Grid Array (8 x 9.5 x 1.4 mm) Pb-Free In dustrial
Note
20.The ‘X’ ( Don’t care) st at e for th e chip ena bles in the t ruth t able refer to the l ogic stat e (eit her HIGH or LOW). I ntermediate v olt age levels on these pins is not permi tted.
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CY62187EV30
Document #: 001-48998 Rev. *C Page 11 of 12
Document History Page
Document Title: CY62187EV30 MoBL
®
64 Mbit (4M x 16) Static RAM
Document Number: 001-48998
Rev. ECN No. Orig. of
Change Submission
Date Descriptio n o f Chan ge
** 2595932 VKN/PYRS 10/24/08 New Data Sheet
*A 2644442 VKN/PYRS 01/23/09 Updated the Package diagram on page 10
*B 2672650 VKN/PYRS 03/12/09 Extended the V
CC
range to 3.7V
Added 55 ns speed bin and it’s related information
Changed I
CC (typ)
from 2.5 mA to 3.5 mA at f = 1 MHz
Changed I
CC (max)
from 4 mA to 6 mA at f = 1 MHz
For 70 ns speed, changed I
CC (typ)
form 33 mA to 28 mA at f = f
MAX
For 70 ns speed, changed I
CC (max)
from 40 mA to 4 5 mA at f = f
MAX
For 70 ns speed, changed t
PWE
from 45 to 50 ns, t
SD
from 30 to 35 ns
Modified fo otnote #6
Changed 48-Ball FBGA package dimensions from 8 x 9.5 x 1.6 mm to
8 x 9.5 x 1.4 mm and updated package diagram on page 10
*C 2737164 VKN/AESA 07/13/09 Converted from preliminary to final
Changed I
CC(typ)
from 3.5 mA to 4 mA at f = 1 MHz
Changed I
CC(typ)
from 35 mA to 45 mA and from 28 mA to 35 mA for the speeds
50 ns and 70 ns respectively at f = f
max
Included V
CC
range in the test condition of the “Electrical Characteristics” table
for the specs V
OH
, V
OL
, V
IH
, V
IL
Changed V
IL(max)
from 0.8V to 0.7V for V
CC
= 2.7V to 3.7V
Changed C
IN
spec from 20 pF to 25 pF and C
OUT
spec from 20 pF to 35 pF
Included thermal specs for 48-FBGA
Included V
CC
range for V
TH
spec in the AC test load table
Changed t
LZBE
spec from 5 ns to 10 ns
Added footnote #20 related to chi p enable
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Document #: 001-48998 Rev. *C Revised July 10, 2009 Page 12 of 12
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their
respective holders.
CY62187EV30
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try oth er than circuit ry e mbod ied in a Cyp ress produc t. Nor do es it conve y or im ply any lic ense under paten t or ot her r ights. Cypr ess pr oducts are not wa rrante d nor in tende d to be us ed
for medical, life support, life saving, critical contr ol or safety applications, unless pu rsu an t to an exp re ss writ t en agr e em en t with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to t he user. The inclusion of Cypr ess products in life -support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and in ternati onal tr eaty provi sions . Cypr ess here by grants to licensee a personal, non- exclu sive, no n-tran sferab le lic ense to cop y, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of lice nsee product to be used on ly in conjunction wit h a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this S ource Code exce pt as specified above is prohib ited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOS E. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liabil ity ar ising ou t of t he app licati on or us e of an y product or circ uit de scrib ed herei n. Cypr ess does n ot auth orize it s product s for use a s critical componen ts in life-suppo rt systems where
a malfunction or failure may reasonably be expecte d to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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