74VHC139MTCX - Fairchild Semiconductor

November 1992

Revised April 1999

74VHC139 Dual 2-to-4 Decoder/Demultiplexer

74VHC139

Dual 2-to-4 Decoder/Demultiplexer

General Descript ion

The VHC13 9 i s a n a dva nced hig h sp eed C MO S D ua l 2-t o-

4 Decoder/Demultiplexer fabricated with silicon gate

CMOS technology. It achieves the high speed operation

similar to equivalent Bipolar Schottky TTL while maintain-

ing the CMOS low power dissipation.

The active LOW enable input can be used for gating or it

can be used as a data input for demultiplexing applications.

When the enable input is held HIGH, all four outputs are

fixed at a HIGH lo gic le vel independe nt of t he other i npu ts.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply volt-

age. This device can be used to interface 5V to 3V systems

and two sup ply systems such as battery ba ck up. This cir-

cuit pr eve nts dev ic e d estr uct ion due to m i sma tche d s upp l y

and input voltages.

Features

■High Speed: tPD = 5.0 ns (typ) at TA = 25°C

■Low power dissipation: ICC = 4 µA (Max.) at TA = 25°C

■High noise immunity: VNIH = VNIL = 28% VCC (Min.)

■Power down protection is provided on all inputs

■Pin and function compatible with 74HC139

Ordering Code:

Surface m ount pa c k ages are als o availa ble on Tape and Reel. Specify by appendi ng the suffix let te r “X” to the or dering co de.

Connection Diagram Pin Description

Truth Table

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Order Number Package Number Package Description

74VHC139M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

74VHC139SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC139MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC139N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

A0, A1Address Inpu ts

EEnable Inputs

O0–O3Outputs

Inputs Outputs

EA0A1O0O1O2O3

HXXHHHH

LLLLHHH

LHLHLHH

LLHHHLH

LHHHHHL

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74VHC139

Logic Symbols

IEEE/IEC

Functional Description

The VHC 139 is a high-spe ed dual 2-to-4 de coder/demulti -

plexer. The device has two inde pende nt decode rs, each of

which accepts two binary weighted inputs (A0–A1) and pro-

vides four mutually exclusive active-LOW outputs (O0–O3).

Each decoder has an active-LOW enable (E). When E is

HIGH all outputs are forced HIGH. The enable can be used

as the data input for a 4-output demultiplexer application.

Each half of the VHC139 generates all four minterms of

two variables. These four minterms are useful in some

applicat ions, repl acing multi ple gate functions as shown in

Figure 1

, and thereby reducing the number of packages

required in a logic network.

FIGURE 1. Gate Func tions (Each Half)

Logic Diagram

Pleas e note that this diagram is provide d only for the unders t anding o f lo gic operat ions and sh ould not be us ed to estim ate propa gation d elays.

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74VHC139

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: Absolute Maximum Ratings are values beyond which the device

may be da maged or ha ve its useful life impaire d. The datab ook specific a-

tions should be met, without exception, to ensure that the system design is

reliable over its pow er supply, temperatu re, and out put/input loa ding vari-

ables. Fairchild does not recommend operation outside databook specifica-

tions.

Note 2: Unused inputs must be he ld HIGH or LOW. They may not floa t.

DC Electrical Characteristics

AC Electrical Characteristics

Note 3: CPD is defined as th e v alue of th e intern al equivalent capacitan ce w hic h is calc ulated fr om t he operating cu rrent cons umption without load. Avera ge

operati ng c urrent ca n be obtained by the equation: ICC (op r.) = CPD * V CC * fIN + ICC/2 (pe r dec oder).

Supply Voltage (VCC)−0.5 V to +7.0V

DC Input Voltage (VIN)−0.5V to +7.0V

DC Output Voltage (VOUT)−0.5V to VCC + 0.5V

Input Diode Current (IIK)−20 mA

Output Diode Current (IOK)±20 mA

DC Output Current (IOUT)±25 mA

DC VCC/GND Current (ICC)±75 mA

Storage Temperature (TSTG)−65°C to +150°C

Lead Temperature (TL)

(Soldering, 10 seconds) 260°C

Supply Voltage (VCC)2.0V to +5.5V

Input Voltage (VIN)0V to +5.5V

Output Voltage (VOUT)0V to V

Operating Temperature (TOPR)−40°C to +85°C

Input Rise and Fall Time (tr, tf)

VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V

VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V

Symbol Parameter VCC

(V)

TA = 25°CT

A = −40°C to +85°CUnits Conditions

Min Typ Max Min Max

VIH HIGH Level 2.0 1.50 1.50 V

Input Voltage 3.0 − 5.5 0.7 VCC 0.7 VCC

VIL LOW Level 2.0 0.50 0.50 V

Input Voltage 3.0 − 5.5 0.3 VCC 0.3 VCC

VOH HIGH Level 2.0 1.9 2.0 1.9 VIN = VIH IOH = −50 µA

Output Voltage 3.0 2.9 3.0 2.9 V or VIL

4.5 4.4 4.5 4.4

3.0 2.58 2.48 VIOH = −4 mA

4.5 3.94 3.80 IOH = −8 mA

VOL LOW Level 2.0 0.0 0.1 0.1 VIN = VIH IOL = 50 µA

Output Voltage 3.0 0.0 0.1 0.1 V or VIL

4.5 0.0 0.1 0.1

3.0 0.36 0.44 VIOL = 4 mA

4.5 0.36 0.44 IOL = 8 mA

IIN Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAV

IN = 5.5V or GND

ICC Quiescent Supply Current 5.5 4.0 40.0 µAV

IN = VCC or GND

Symbol Parameter VCC

(V)

TA = 25°CT

A = −40°C to +85°CUnits Conditions

Min Typ Max Min Max

tPLH Propagation Delay 3.3 ± 0.3 7.2 11.0 1.0 13.0 ns CL = 15 pF

tPHL Anto On9.7 14.5 1.0 16.5 CL = 50 pF

5.0 ± 0.5 5.0 7.2 1.0 8.5 ns CL = 15 pF

6.5 9.2 1.0 10.5 CL = 50 pF

tPLH Propagation Delay 3.3 ± 0.3 6.4 9.2 1.0 11.0 ns CL = 15 pF

tPHL Ento On8.9 12.7 1.0 14.5 CL = 50 pF

5.0 ± 0.5 4.4 6.3 1.0 7.5 ns CL = 15 pF

5.98.31.09.5 C

L = 50 pF

CIN Input Capacitance 4 10 10 pF VCC = Open

CPD Power Dissipation Capacitance 26 pF (Note 3)

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74VHC139

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

Package Number M16A

16-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74VHC139

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Packag e Num be r MTC 16

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

74VHC139 Dual 2-to-4 Decoder/Demultiplexer

LIFE SUPPORT POLIC Y

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a life su pport

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa i lure of the life su pp ort

device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E