LTC6240/LTC6241/LTC6242 Single/Dual/Quad 18MHz, Low Noise, Rail-to-Rail Output, CMOS Op Amps DESCRIPTION FEATURES n n n n n n n n n n n n 0.1Hz to 10Hz Noise: 550nVP-P Input Bias Current: 0.2pA (Typ at 25C) 1pA Max (LTC6240) Low Offset Voltage: 125V Max Low Offset Drift: 2.5V/C Max Gain Bandwidth Product: 18MHz Output Swings Rail-to-Rail Supply Operation: 2.8V to 6V LTC6240/LTC6241/LTC6242 2.8V to 5.5V LTC6240HV/LTC6241HV/LTC6242HV Low Input Capacitance H-Grade Temperature Range: -40C to 125C Single LTC6240 in 5-Pin Low Profile (1mm) ThinSOTTM Package and 8-Pin SO for PCB Guard Ring Dual LTC6241 in 8-Pin SO and Tiny DFN Packages Quad LTC6242 in 16-Pin SSOP and 5mm x 3mm DFN Packages n n n n These op amps have an output stage that swings within 30mV of either supply rail to maximize the signal dynamic range in low supply applications. The input common mode range extends to the negative supply. They are fully specified on 3V and 5V, and an HV version guarantees operation on supplies up to 5V. The LTC6240 is available in the 8-pin SO and the 5-pin SOT23 packages. The LTC6241 is available in the 8-pin SO, and for compact designs it is packaged in a tiny dual fine pitch leadless (DFN) package. The LTC6242 is available in the 16-pin SSOP as well as the 5mm x 3mm DFN package. APPLICATIONS n The LTC(R)6240/6241/LTC6242 are single, dual and quad low noise, low offset, rail-to-rail output, unity gain stable CMOS op amps that feature 1pA of input bias current. Input bias current is guaranteed to be 1pA max on the single LTC6240. The 0.1Hz to 10Hz noise of only 550nVP-P, along with an offset of just 125V are significant improvements over traditional CMOS op amps. Additionally, noise is guaranteed to be less than 10nV/Hz at 1kHz. An 18MHz gain bandwidth, and 10V/s slew rate, along with the wide supply range and low input capacitance, make them perfect for use as fast signal processing amplifiers. Photo Diode Amplifiers Charge Coupled Amplifiers Low Noise Signal Processing Medical Instrumentation High Impedance Transducer Amplifier L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Low Noise Single-Ended Input to Differential Output Amplifier Noise Voltage vs Frequency C3 10pF C1 10pF R1 200k R3 4.99k VIN +2.5V - 1/2 LTC6241 -2.5V 1/2 LTC6241 + C2 10pF VOUT+ + - TA = 25C VS = 2.5V VCM = 0V 50 R4 4.99k VOUT- NOISE VOLTAGE (nV/Hz) C4 10pF 60 40 30 20 10 0 R2 200k 1 6241 TA01a 10 100 1k FREQUENCY (Hz) 10k 100k 6241 TA01b 624012fe 1 LTC6240/LTC6241/LTC6242 ABSOLUTE MAXIMUM RATINGS (Note 1) Total Supply Voltage (V+ to V-) LTC6240/LTC6241/LTC6242 ...................................7V LTC6240HV/LTC6241HV/LTC6242HV....................12V Input Voltage.......................... (V+ + 0.3V) to (V- - 0.3V) Input Current........................................................ 10mA Output Short-Circuit Duration (Note 2) ............ Indefinite Operating Temperature Range LTC6240C/LTC6241C/LTC6242C ..........-40C to 85C LTC6240I/LTC6241I/LTC6242I .............-40C to 85C LTC6240H/LTC6241H/LTC6242H ....... -40C to 125C Specified Temperature Range (Note 3) LTC6240C/LTC6241C/LTC6242C .............. 0C to 70C LTC6240I/LTC6241I/LTC6242I .............-40C to 85C LTC6240H/LTC6241H/LTC6242H ....... -40C to 125C Junction Temperature ........................................... 150C DHC, DD Package ............................................. 125C Storage Temperature Range .................. -65C to 150C DHC, DD Package .............................. -65C to 125C Lead Temperature (Soldering, 10 sec)................... 300C PIN CONFIGURATION LTC6240 LTC6240 TOP VIEW TOP VIEW NC 1 + +IN 3 - V- 2 +IN 3 4 -IN V- S5 PACKAGE 5-LEAD PLASTIC TSOT-23 4 8 NC 7 V+ 6 OUT 5 NC S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 250C/W LTC6241 - -IN 2 + 5 V+ OUT 1 TJMAX = 150C, JA = 190C/W LTC6241 TOP VIEW TOP VIEW 8 V+ OUT A 1 -IN A 2 +IN A 3 V - OUT A 1 7 OUT B A B -IN A 2 6 -IN B 5 +IN B 4 A +IN A 3 B V- 4 DD PACKAGE 8-LEAD (3mm s 3mm) PLASTIC DFN V+ 7 OUT B 6 -IN B 5 +IN B S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125C, JA = 43C/W UNDERSIDE METAL CONNECTED TO V- (PCB CONNECTION OPTIONAL) LTC6242 8 TJMAX = 150C, JA = 190C/W LTC6242 TOP VIEW TOP VIEW OUT A 1 16 OUT D -IN A 2 +IN A 3 14 +IN D V+ 4 13 V- +IN B 5 -IN B 6 11 -IN C OUT B 7 10 OUT C NC 8 9 A D 17 B C 15 -IN D 12 +IN C NC DHC PACKAGE 16-LEAD (5mm s 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W UNDERSIDE METAL CONNECTED TO V- (PCB CONNECTION OPTIONAL) OUT A 1 -IN A 2 +IN A 3 14 +IN D V+ 4 13 V- +IN B 5 -IN B 6 11 -IN C OUT B 7 10 OUT C NC 8 9 16 OUT D A B D C 15 -IN D 12 +IN C NC GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150C, JA = 135C/W 624012fe 2 LTC6240/LTC6241/LTC6242 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6240CS5#PBF LTC6240CS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 0C to 70C LTC6240HVCS5#PBF LTC6240HVCS5#TRPBF LTCRS 5-Lead Plastic TSOT-23 0C to 70C LTC6240IS5#PBF LTC6240IS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 -40C to 85C LTC6240HVIS5#PBF LTC6240HVIS5 #TRPBF LTCRS 5-Lead Plastic TSOT-23 -40C to 85C LTC6240HS5#PBF LTC6240HS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 -40C to 125C LTC6240HVHS5#PBF LTC6240HVHS5#TRPBF LTCRS 5-Lead Plastic TSOT-23 -40C to 125C LTC6240CS8#PBF LTC6240CS8#TRPBF 6240 8-Lead Plastic SO 0C to 70C LTC6240HVCS8#PBF LTC6240HVCS8#TRPBF 6240HV 8-Lead Plastic SO 0C to 70C LTC6240IS8#PBF LTC6240IS8#TRPBF 6240I 8-Lead Plastic SO -40C to 85C LTC6240HVIS8#PBF LTC6240HVIS8#TRPBF 240HVI 8-Lead Plastic SO -40C to 85C LTC6240HS8#PBF LTC6240HS8#TRPBF 6240H 8-Lead Plastic SO -40C to 125C LTC6240HVHS8#PBF LTC6240HVHS8#TRPBF 240HVH 8-Lead Plastic SO -40C to 125C LTC6241CDD#PBF LTC6241CDD#TRPBF LBPD 8-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC6241HVCDD#PBF LTC6241HVCDD#TRPBF LBRR 8-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC6241IDD#PBF LTC6241IDD#TRPBF LBPD 8-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC6241HVIDD#PBF LTC6241HVIDD#TRPBF LBRR 8-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC6241CS8#PBF LTC6241CS8#TRPBF 6241 8-Lead Plastic SO 0C to 70C LTC6241HVCS8#PBF LTC6241HVCS8#TRPBF 6241HV 8-Lead Plastic SO 0C to 70C LTC6241IS8#PBF LTC6241IS8#TRPBF 6241I 8-Lead Plastic SO -40C to 85C LTC6241HVIS8#PBF LTC6241HVIS8#TRPBF 241HVI 8-Lead Plastic SO -40C to 85C LTC6241HS8#PBF LTC6241HS8#TRPBF 6241H 8-Lead Plastic SO -40C to 125C LTC6241HVHS8#PBF LTC6241HVHS8#TRPBF 241HVH 8-Lead Plastic SO -40C to 125C LTC6242CDHC#PBF LTC6242CDHC#TRPBF 6242 16-Lead (5mm x 3mm) Plastic DFN 0C to 70C LTC6242HVCDHC#PBF LTC6242HVCDHC#TRPBF 6242HV 16-Lead (5mm x 3mm) Plastic DFN 0C to 70C LTC6242IDHC#PBF LTC6242IDHC#TRPBF 6242 16-Lead (5mm x 3mm) Plastic DFN -40C to 85C LTC6242HVIDHC#PBF LTC6242HVIDHC#TRPBF 6242HV 16-Lead (5mm x 3mm) Plastic DFN -40C to 85C LTC6242CGN#PBF LTC6242CGN#TRPBF 6242 16-Lead Plastic SSOP 0C to 70C LTC6242HVCGN#PBF LTC6242HVCGN#TRPBF 6242HV 16-Lead Plastic SSOP 0C to 70C LTC6242IGN#PBF LTC6242IGN#TRPBF 6242I 16-Lead Plastic SSOP -40C to 85C LTC6242HVIGN#PBF LTC6242HVIGN#TRPBF 242HVI 16-Lead Plastic SSOP -40C to 85C LTC6242HGN#PBF LTC6242HGN#TRPBF 6242H 16-Lead Plastic SSOP -40C to 125C LTC6242HVHGN#PBF LTC6242HVHGN#TRPBF 242HVH 16-Lead Plastic SSOP -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 624012fe 3 LTC6240/LTC6241/LTC6242 AVAILABLE OPTIONS PART NUMBER LTC6240CS5 LTC6240CS8 LTC6240HVCS5 LTC6240HVCS8 LTC6240IS5 LTC6240IS8 LTC6240HVIS5 LTC6240HVIS8 LTC6240HS5 LTC6240HS8 LTC6240HVHS5 LTC6240HVHS8 LTC6241CS8 LTC6241CDD LTC6241HVCS8 LTC6241HVCDD LTC6241IS8 LTC6241IDD LTC6241HVIS8 LTC6241HVIDD LTC6241HS8 LTC6241HVHS8 LTC6242CGN LTC6242CDHC LTC6242HVCGN LTC6242HVCDHC LTC6242IGN LTC6242IDHC LTC6242HVIGN LTC6242HVIDHC LTC6242HGN LTC6242HVHGN AMPS/PACKAGE 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 SPECIFIED TEMP RANGE 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 125C -40C to 125C -40C to 125C -40C to 125C 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 125C -40C to 125C 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 125C -40C to 125C SPECIFIED SUPPLY VOLTAGE 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V 3V, 5V, 5V 3V, 5V, 5V 3V, 5V 3V, 5V, 5V PACKAGE SOT-23 SO-8 SOT-23 SO-8 SOT-23 SO-8 SOT-23 SO-8 SOT-23 SO-8 SOT-23 SO-8 SO-8 DD SO-8 DD SO-8 DD SO-8 DD SO-8 SO-8 GN DHC GN DHC GN DHC GN DHC GN GN PART MARKING LTCRR 6240 LTCRS 6240HV LTCRR 6240I LTCRS 240HVI LTCRR 6240H LTCRS 240HVH 6241 LBPD 6241HV LBRR 6241I LBPD 241HVI LBRR 6241H 241HVH 6242 6242 6242HV 6242HV 6242I 6242 242HVI 6242HV 6242H 242HVH 624012fe 4 LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 4) LTC6241 S8 0C to 70C -40C to 85C l l LTC6242 GN 0C to 70C -40C to 85C l l LTC6240 0C to 70C -40C to 85C l l LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C l l VOS Match Channel-to-Channel (Note 5) LTC6241 S8 0C to 70C -40C to 85C l l LTC6242 GN 0C to 70C -40C to 85C l l LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C l l TC VOS Input Offset Voltage Drift (Note 6) IB Input Bias Current (Notes 4, 7) l LTC6241, LTC6242 LTC6240 IOS MIN Input Offset Current (Notes 4, 7) LTC6241, LTC6242 LTC6240 TYP MAX UNITS 40 125 250 300 V V V 50 150 275 300 V V V 50 175 300 350 V V V 100 550 650 725 V V V 40 160 300 375 V V V 50 185 325 400 V V V 150 650 700 750 V V V 0.7 2.5 V/C 75 pA pA 1 75 pA pA 75 pA pA 1 75 pA pA 0.2 l 0.2 l 0.2 l 0.2 l Input Noise Voltage 0.1Hz to 10Hz en Input Noise Voltage Density f = 1kHz in Input Noise Current Density (Note 8) 0.56 fA/Hz RIN Input Resistance Common Mode 1012 CIN Input Capacitance Differential Mode Common Mode f = 100kHz 3.5 3 pF pF Input Voltage Range Guaranteed by CMRR l 0 0V VCM 3.5V l 80 105 dB l 76 95 dB VCM CMRR Common Mode Rejection CMRR Match Channel-to-Channel (Note 5) 550 7 nVP-P 10 3.5 nV/Hz V 624012fe 5 LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS AVOL Large Signal Voltage Gain VO = 1V to 4V RL = 10k to VS/2 0C to 70C -40C to 85C MIN TYP MAX UNITS l l 425 300 200 1600 V/mV V/mV V/mV VO = 1.5V to 3.5V RL = 1k to VS/2 0C to 70C -40C to 85C l l 90 60 50 215 V/mV V/mV V/mV VOL Output Voltage Swing Low (Note 9) No Load ISINK = 1mA ISINK = 5mA l l l 7 40 190 30 75 325 mV mV mV VOH Output Voltage Swing High (Note 9) No Load ISOURCE = 1mA ISOURCE = 5mA l l l 11 45 190 30 75 325 mV mV mV PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 80 104 dB PSRR Match Channel-to-Channel (Note 5) l 74 100 dB Minimum Supply Voltage (Note 10) l 2.8 ISC Short-Circuit Current l 15 IS Supply Current per Amplifier LTC6241, LTC6242 0C to 70C -40C to 85C l l LTC6240 0C to 70C -40C to 85C l l V 30 mA 1.8 2.2 2.3 2.4 mA mA mA 2 2.4 2.5 2.6 mA mA mA GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k l 13 18 MHz SR Slew Rate (Note 11) AV = -2, RL = 1k l 5 10 V/s FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1k l 0.53 1.06 MHz ts Settling Time VSTEP = 2V, AV = -1, RL = 1k, 0.1% 1100 ns 624012fe 6 LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 4) LTC6241 S8 0C to 70C -40C to 85C l l LTC6242 GN 0C to 70C -40C to 85C l l LTC6240 0C to 70C -40C to 85C l l LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C l l VOS Match Channel-to-Channel (Note 5) LTC6241 S8 0C to 70C -40C to 85C l l LTC6242 GN 0C to 70C -40C to 85C l l LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C l l TC VOS Input Offset Voltage Drift (Note 6) IB Input Bias Current (Notes 4, 7) l LTC6241, LTC6242 LTC6240 IOS Input Offset Current (Notes 4, 7) LTC6241, LTC6242 LTC6240 VCM CMRR Input Voltage Range Common Mode Rejection Large Signal Voltage Gain TYP MAX UNITS 40 175 275 325 V V V 60 200 275 325 V V V 50 200 325 375 V V V 100 550 650 725 V V V 40 200 325 400 V V V 60 225 325 400 V V V 150 650 700 750 V V V 0.7 2.5 V/C 75 pA pA 1 75 pA pA 75 pA pA 1 75 pA pA 1.5 V 0.2 l 0.2 l 0.2 l 0.2 l Guaranteed by CMRR l 0 0V VCM 1.5V l 78 100 dB l 76 95 dB VO = 1V to 2V RL = 10k to VS/2 0C to 70C -40C to 85C l l 140 100 75 600 V/mV V/mV V/mV CMRR Match Channel-to-Channel (Note 5) AVOL MIN VOL Output Voltage Swing Low (Note 9) No Load ISINK = 1mA l l 3 65 30 110 mV mV VOH Output Voltage Swing High (Note 9) No Load ISOURCE = 1mA l l 4 70 30 120 mV mV PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 80 104 dB PSRR Match Channel-to-Channel (Note 5) l 74 100 dB Minimum Supply Voltage (Note 10) l 2.8 Short-Circuit Current l 3 ISC V 6 mA 624012fe 7 LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I, LTC6242HVC/I) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS IS Supply Current per Amplifier LTC6241, LTC6242 0C to 70C -40C to 85C l l LTC6240 0C to 70C -40C to 85C l l Frequency = 20kHz, RL = 1k l GBW Gain Bandwidth Product MIN 12 TYP MAX 1.4 1.7 1.8 1.9 mA mA mA 1.5 1.9 2 2.1 mA mA mA 17 UNITS MHz (LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 4) LTC6241 S8 0C to 70C -40C to 85C l l LTC6242 GN 0C to 70C -40C to 85C l l LTC6240 0C to 70C -40C to 85C l l LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C l l VOS Match Channel-to-Channel (Note 5) LTC6241 S8 0C to 70C -40C to 85C l l LTC6242 GN 0C to 70C -40C to 85C l l LTC6241 DD, LTC6242 DHC 0C to 70C -40C to 85C l l TC VOS Input Offset Voltage Drift (Note 6) IB Input Bias Current (Notes 4, 7) l LTC6241, LTC6242 LTC6240 IOS MIN Input Offset Current (Notes 4, 7) LTC6241, LTC6242 LTC6240 Input Noise Voltage 0.1Hz to 10Hz l l l l TYP MAX UNITS 50 175 275 325 V V V 60 200 275 325 V V V 60 250 350 400 V V V 100 550 650 725 V V V 50 200 325 400 V V V 60 225 325 400 V V V 150 650 700 750 V V V 0.7 2.5 V/C 75 pA pA 1 75 pA pA 75 pA pA 1 75 pA pA 0.5 0.5 0.2 0.2 550 nVP-P 624012fe 8 LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS en Input Noise Voltage Density f = 1kHz in Input Noise Current Density (Note 8) 0.56 fA/Hz RIN Input Resistance Common Mode 1012 CIN Input Capacitance Differential Mode Common Mode f = 100kHz 3.5 3 pF pF VCM Input Voltage Range Guaranteed by CMRR l -5 -5V VCM 3.5V l 83 105 dB dB CMRR Common Mode Rejection CMRR Match Channel-to-Channel (Note 5) AVOL Large Signal Voltage Gain MIN TYP MAX UNITS 7 10 nV/Hz 3.5 V l 76 95 VO = -3.5V to 3.5V RL = 10k 0C to 70C -40C to 85C l l 775 600 500 2700 V/mV V/mV V/mV RL = 1k 0C to 70C -40C to 85C l l 150 90 75 360 V/mV V/mV V/mV VOL Output Voltage Swing Low (Note 9) No Load ISINK = 1mA ISINK = 10mA l l l 15 45 360 30 75 550 mV mV mV VOH Output Voltage Swing High (Note 9) No Load ISOURCE = 1mA ISOURCE = 10mA l l l 15 45 360 30 75 550 mV mV mV PSRR Power Supply Rejection VS = 2.8V to 11V, VCM = 0.2V l 85 110 dB PSRR Match Channel-to-Channel (Note 5) l 82 106 dB Minimum Supply Voltage (Note 10) l 2.8 ISC Short-Circuit Current l 15 IS Supply Current per Amplifier V 35 mA LTC6241, LTC6242 0C to 70C -40C to 85C 2.5 3.2 3.3 3.7 l l mA mA mA LTC6240 0C to 70C -40C to 85C l l 2.7 3.3 3.4 3.8 mA mA mA l 13 18 MHz GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k SR Slew Rate (Note 11) AV = -2, RL = 1k l 5.5 10 V/s l 0.58 1.06 MHz 900 ns FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1k ts Settling Time VSTEP = 2V, AV = -1, RL = 1k, 0.1% 624012fe 9 LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The l denotes the specifications which apply from -40C to 125C, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 4) LTC6241 S8 LTC6242 GN LTC6240 VOS Match Channel-to-Channel (Note 5) LTC6241 S8 LTC6242 GN TC VOS Input Offset Voltage Drift (Note 6) IB Input Bias Current (Notes 4, 7) Input Offset Current (Notes 4, 7) l l l l l l LTC6241, LTC6242 LTC6240 IOS MIN LTC6241, LTC6242 LTC6240 TYP MAX UNITS 40 125 400 V V 50 150 400 V V 50 175 450 V V 40 160 400 V V 50 185 400 V V 0.7 2.5 V/C 1.5 pA nA 1 2.5 pA nA 150 pA pA 1 750 pA pA 0.2 l 0.2 l 0.2 l 0.2 l VCM Input Voltage Range Guaranteed by CMRR l 0 CMRR Common Mode Rejection 0V VCM 3.5V l 78 dB l 74 dB l 425 200 1600 V/mV V/mV l 90 40 215 V/mV V/mV CMRR Match Channel-to-Channel (Note 5) AVOL Large Signal Voltage Gain VO = 1V to 4V RL = 10k to VS/2 VO = 1.5V to 3.5V RL = 1k to VS/2 3.5 V VOL Output Voltage Swing Low (Note 9) No Load ISINK = 1mA ISINK = 5mA l l l 30 85 325 mV mV mV VOH Output Voltage Swing High (Note 9) No Load ISOURCE = 1mA ISOURCE = 5mA l l l 30 85 325 mV mV mV PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 78 dB PSRR Match Channel-to-Channel (Note 5) l 74 dB Minimum Supply Voltage (Note 10) l 2.8 V ISC Short-Circuit Current l 15 IS Supply Current per Amplifier LTC6241, LTC6242 LTC6240 l l l 12 mA 1.8 2.2 2.4 mA mA 2 2.4 2.8 mA mA GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k MHz SR Slew Rate (Note 11) AV = -2, RL = 1k l 4.5 V/s FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1k l 0.48 MHz 624012fe 10 LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The l denotes the specifications which apply from -40C to 125C, otherwise specifications are at TA = 25C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 4) LTC6241 S8 LTC6242 GN LTC6240 VOS Match Channel-to-Channel (Note 5) LTC6241 S8 LTC6242 GN TC VOS Input Offset Voltage Drift (Note 6) IB Input Bias Current (Notes 4, 7) Input Offset Current (Notes 4, 7) l l l l l l LTC6241, LTC6242 LTC6240 IOS MIN LTC6241, LTC6242 LTC6240 TYP MAX UNITS 40 175 400 V V 60 200 400 V V 50 200 450 V V 40 200 400 V V 60 225 400 V V 0.7 2.5 V/C 1.5 pA nA 1 2.5 pA nA 150 pA pA 1 750 pA pA 1.5 V 0.2 l 0.2 l 0.2 l 0.2 l VCM Input Voltage Range Guaranteed by CMRR l 0 CMRR Common Mode Rejection 0V VCM 1.5V l 75 dB l 74 dB l 140 65 CMRR Match Channel-to-Channel (Note 5) AVOL Large Signal Voltage Gain VO = 1V to 2V RL = 10k to VS/2 600 V/mV V/mV VOL Output Voltage Swing Low (Note 9) No Load ISINK = 1mA l l 30 130 mV mV VOH Output Voltage Swing High (Note 9) No Load ISOURCE = 1mA l l 30 130 mV mV PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 78 dB PSRR Match Channel-to-Channel (Note 5) l 74 dB Minimum Supply Voltage (Note 10) l 2.8 V l 2.5 ISC Short-Circuit Current IS Supply Current per Amplifier LTC6241, LTC6242 LTC6240 GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k l l l 10 mA 1.4 1.7 1.9 mA mA 1.5 1.9 2.1 mA mA MHz 624012fe 11 LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS (LTC6240HVH/LTC6241HVH/LTC6242HVH) The l denotes the specifications which apply from -40C to 125C, otherwise specifications are at TA = 25C. VS = 5V, VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 4) LTC6241 S8 LTC6242 GN LTC6240 VOS Match Channel-to-Channel (Note 5) LTC6241 S8 LTC6242 GN TC VOS Input Offset Voltage Drift (Note 6) IB Input Bias Current (Notes 4, 7) Input Offset Current (Notes 4, 7) l l l l l l LTC6241, LTC6242 LTC6240 IOS MIN LTC6241, LTC6242 LTC6240 TYP MAX UNITS 50 175 400 V V 60 200 400 V V 60 250 450 V V 50 200 400 V V 60 225 400 V V 0.7 2.5 V/C 1.5 pA nA 1 2.5 pA nA 150 pA pA 1 750 pA pA 0.5 l 0.5 l 0.2 l 0.2 l VCM Input Voltage Range Guaranteed by CMRR l -5 CMRR Common Mode Rejection -5V VCM 3.5V l 80 dB l 76 dB l 775 350 2700 V/mV V/mV l 150 60 360 V/mV V/mV CMRR Match Channel-to-Channel (Note 5) AVOL Large Signal Voltage Gain VO = -3.5V to 3.5V RL = 10k RL = 1k 3.5 V VOL Output Voltage Swing Low (Note 9) No Load ISINK = 1mA ISINK = 10mA l l l 30 85 600 mV mV mV VOH Output Voltage Swing High (Note 9) No Load ISOURCE = 1mA ISOURCE = 10mA l l l 30 85 600 mV mV mV PSRR Power Supply Rejection VS = 2.8V to 11V, VCM = 0.2V l 83 dB PSRR Match Channel-to-Channel (Note 5) l 82 dB Minimum Supply Voltage (Note 10) l 2.8 V ISC Short-Circuit Current l 15 mA IS Supply Current per Amplifier LTC6241, LTC6242 LTC6240 3.2 3.7 mA mA 2.7 3.3 3.8 mA mA 12 MHz AV = -2, RL = 1k l 5 V/s VOUT = 3VP-P, RL = 1k l 0.53 MHz Gain Bandwidth Product Frequency = 20kHz, RL = 1k SR Slew Rate (Note 11) Full Power Bandwidth (Note 12) l 2.5 l GBW FPBW l 624012fe 12 LTC6240/LTC6241/LTC6242 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. Note 3: The LTC6240C/LTC6240HVC/LTC6241C/LTC6241HVC, LTC6242C/ LTC6242HVC are guaranteed to meet specified performance from 0C to 70C. They are designed, characterized and expected to meet specified performance from -40C to 85C, but are not tested or QA sampled at these temperatures. The LTC6240I/LTC6240HVI, LTC6241I/LTC6241HVI, LTC6242I/LTC6242HVI are guaranteed to meet specified performance from -40C to 85C. All versions of the LTC6240H/LTC6241H/LTC6242H are guaranteed to meet specified performance from -40C to 125C. Note 4: ESD (Electrostatic Discharge) sensitive device. ESD protection devices are used extensively internal to the LTC6240/LTC6241/LTC6242; however, high electrostatic discharge can damage or degrade the device. Use proper ESD handling precautions. Note 5: Matching parameters are the difference between the two amplifiers A and D and between B and C of the LTC6242; between the two amplifiers of the LTC6241. CMRR and PSRR match are defined as follows: CMRR and PSRR are measured in V/V on the matched amplifiers. The difference is calculated between the matching sides in V/V. The result is converted to dB. Note 6: This parameter is not 100% tested. Note 7: Bias current at TA = 25C is 100% tested and guaranteed for the LTC6240 in the S8 package. The LTC6240S5, LTC6241 and LTC6242 are expected to achieve the same performance as the LTC6240S8. All parts are guaranteed to meet specifications over temperature. Note 8: Current noise is calculated from the formula: in = (2qIB)1/2 where q = 1.6 x 10-19 coulomb. The noise of source resistors up to 50G dominates the contribution of current noise. See also Typical Performance Characteristics curve Noise Current vs Frequency. Note 9: Output voltage swings are measured between the output and power supply rails. Note 10: Minimum supply voltage is guaranteed by the power supply rejection ratio test. Note 11: Slew rate is measured in a gain of -2 with RF = 1k and RG = 500. On the LTC6240/LTC6241/LTC6242, VS = 2.5V, VIN is 1V and VOUT slew rate is measured between -1V and +1V. On the LTC6240HV/ LTC6241HV/LTC6242HV, VIN is 2V and VOUT slew rate is measured between -2V and +2V. Note 12: Full-power bandwidth is calculated from the slew rate: FPBW = SR/VP-P. 624012fe 13 LTC6240/LTC6241/LTC6242 TYPICAL PERFORMANCE CHARACTERISTICS VOS Distribution LTC6241 VOS Temperature Coefficient Distribution LTC6241 VOS Distribution LTC6241 90 120 VS = 2.5V 80 SO-8 PACKAGE 16 VS = 2.5V DD PACKAGE 14 100 60 50 40 30 NUMBER OF UNITS 12 NUMBER OF UNITS NUMBER OF UNITS 70 80 60 40 20 10 0 -50 -30 -10 10 30 50 INPUT OFFSET VOLTAGE (V) 6 0 0 70 -350 -250 -150 -50 50 150 250 INPUT OFFSET VOLTAGE (V) 6241 G01 -1.0 -0.6 -0.2 0.2 0.6 1.0 DISTRIBUTION (V/C) 350 18 VS = 2.5V 14 NUMBER OF UNITS 20 15 10 Supply Current vs Supply Voltage VS = 5V, 0 VCM = 2.5V 2 LOTS -40C TO 125C SO-8 AND SOT23 PACKAGES 16 30 12 10 8 6 4 5 3.5 2 0 -110 -90 -70 -50 -30 -10 10 30 INPUT OFFSET VOLTAGE (V) 50 0 -0.6 70 300 0.2 0.6 1.0 1.4 DISTRIBUTION (V/C) 100 50 TA = 25C 0 -50 TA = -55C -100 -150 1000 2 8 6 10 4 TOTAL SUPPLY VOLTAGE (V) 700 600 100 10 TA = 85C 1 VS = 5V, 0V 500 400 300 200 TA = 25C TA = 125C 100 0 -100 -200 TA = 85C -300 -250 0.1 0 12 Input Bias Current vs Common Mode Voltage TA = 25C 6241 G07 0.5 6241 G06 VS = 5V, 0V -200 -300 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 INPUT COMMON MODE VOLTAGE (V) 1.0 0 TA = 125C TA = 125C TA = 125C 1.5 1.8 INPUT BIAS CURRENT (pA) 150 2.0 Input Bias Current vs Common Mode Voltage INPUT BIAS CURRENT (pA) 200 TA = -55C 2.5 6241 G05 VS = 5V, 0V 250 TA = 25C 3.0 0 -0.2 6241 G04 Offset Voltage vs Input Common Mode Voltage 1.8 6241 G03 VOS Temperature Coefficient Distribution LTC6240 25 1.4 6241 G02 VOS Distribution LTC6240 PERCENT OF UNITS 8 2 SUPPLY CURRENT PER AMP (mA) -70 OFFSET VOLTAGE (V) 10 4 20 35 VS = 2.5V 2 LOTS -55C TO 125C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 COMMON MODE VOLTAGE (V) 6241 G08 -400 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 COMMON MODE VOLTAGE (V) 6241 G09 624012fe 14 LTC6240/LTC6241/LTC6242 TYPICAL PERFORMANCE CHARACTERISTICS 100 VS = 10V VS = 5V 10 1 0.1 TA = 25C 1 TA = 125C 0.1 TA = -55C 0.01 0.001 0.1 25 35 45 55 65 75 85 95 105 115 125 TEMPERATURE (C) 10 VS = 5V, 0V OUTPUT HIGH SATURATION VOLTAGE (V) 10 VCM = VS/2 OUTPUT LOW SATURATION VOLTAGE (V) INPUT BIAS CURRENT (pA) 1000 Output Saturation Voltage vs Load Current (Output High) Output Saturation Voltage vs Load Current (Output Low) Input Bias Current vs Temperature 1 10 LOAD CURRENT (mA) 6241 G10 VS = 5V, 0V TA = 25C 1 TA = 125C TA = -55C 0.1 0.01 0.1 100 1 10 LOAD CURRENT (mA) 100 6241 G11 Gain Bandwidth and Phase Margin vs Temperature 30 GAIN BANDWIDTH 0 -55 -35 -15 VS = 1.5V 30 20 10 -20 VS = 1.5V -20 10k 100k 1M 10M FREQUENCY (Hz) 10k AV = -2 18 RF = 1k, RG = 500 CONDITIONS: SEE NOTE 12 SLEW RATE (V/s) VS = 5V FALLING VS = 2.5V FALLING VS = 5V RISING VS = 2.5V RISING GAIN BANDWIDTH 10 0 0 2 4 6 8 10 TOTAL SUPPLY VOLTAGE (V) 100 TA = 25C VS = 2.5V 1 TA = 25C VS = 2.5V 90 100 10 AV = 10 12 Common Mode Rejection Ratio vs Frequency AV = 2 AV = 1 0.10 6 4 -55 -35 -15 OUTPUT IMPEDANCE () 8 20 6241 G15 1k 16 10 30 Output Impedance vs Frequency 20 50 40 6241 G14 Slew Rate vs Temperature 14 -80 100M 60 PHASE MARGIN -40 -60 6241 G13 12 0 -10 5 25 45 65 85 105 125 TEMPERATURE (C) 40 20 VS = 5V 0 VS = 1.5V 10 60 VS = 5V GAIN 40 70 TA = 25C CL = 5pF RL = 1k COMMON MODE REJECTION (dB) VS = 5V 50 GAIN (dB) 30 40 60 PHASE (DEG) 40 VS = 1.5V 120 CL = 5pF 100 RL = 1k VCM = VS/2 80 PHASE 70 PHASE MARGIN (DEG) PHASE MARGIN 80 GAIN BANDWIDTH (MHz) 70 CL = 5pF RL = 1k 60 50 20 Gain Bandwidth and Phase Margin vs Supply Voltage Open Loop Gain vs Frequency PHASE MARGIN (DEG) GAIN BANDWIDTH (MHz) VS = 5V 6241 G12 80 70 60 50 40 30 20 10 0 5 25 45 65 85 105 125 TEMPERATURE (C) 6241 G16 0.01 10k 100k 1M FREQUENCY (Hz) 10M 6241 G17 -10 10k 100k 1M 10M FREQUENCY (Hz) 100M 6241 G18 624012fe 15 LTC6240/LTC6241/LTC6242 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Rejection Ratio vs Frequency Channel Separation vs Frequency 90 -20 POWER SUPPLY REJECTION RATIO (dB) TA = 25C VS = 2.5V AV = 1 -10 -40 -50 -60 -70 -80 -90 -100 -110 -120 10k TA = 25C VS = 2.5V 80 70 60 50 POSITIVE SUPPLY 40 30 20 NEGATIVE SUPPLY 1M 10M FREQUENCY (Hz) 100M 1k 10k 100k 1M FREQUENCY (Hz) OUTPUT SHORT-CIRCUIT CURRENT (mA) CHANGE IN OFFSET VOLTAGE (V) 60 40 TA = 25C 0 TA = -55C -40 TA = 125C -60 -80 -100 0 1 2 3 4 5 6 7 8 TOTAL SUPPLY VOLTAGE (V) 9 40 SINKING 30 100 10 TA = 25C 0 -10 -20 TA = 125C SOURCING -30 -40 80 RL = 10k 40 20 TA = -55C 0 2.0 2.5 3.0 3.5 4.0 4.5 POWER SUPPLY VOLTAGE (V) 0 5.0 80 20 TA = 25C VS = 5V 40 0 0 -40 -20 -60 1 2 3 4 OUTPUT VOLTAGE (V) 5 6241 G25 3.0 VS = 5V 400 60 20 2.5 Offset Voltage vs Output Current RL = 10k RL = 1k -20 0 1.0 1.5 2.0 OUTPUT VOLTAGE (V) 500 OFFSET VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) RL = 1k 0.5 6241 G24 300 40 RL = 100k 60 Open Loop Gain 100 RL = 10k TA = 25C VS = 3V, 0V 6241 G23 TA = 25C VS = 5V, 0V 60 100M 10M Open Loop Gain TA = 125C -50 1.5 10 80 100k 1M FREQUENCY (Hz) 6241 G21 TA = -55C 20 Open Loop Gain 100 10k 120 6241 G22 120 4 Output Short-Circuit Current vs Power Supply Voltage VCM = VS/2 -20 6 1k 50 20 8 6241 G20 Minimum Supply Voltage 80 10 0 100M 10M 6241 G19 100 CCM 12 2 10 0 100k VS = 1.5V 14 INPUT VOLTAGE (V) VOLTAGE GAIN (dB) -30 Input Capacitance vs Frequency 16 INPUT CAPACITANCE (pF) 0 TA = 125C 200 100 TA = 25C 0 -100 TA = -55C -200 -300 -400 -5 -4 -3 -2 -1 0 1 2 3 OUTPUT VOLTAGE (V) 4 5 6241 G26 -500 -50 -40 -30 -20 -10 0 10 20 30 40 50 OUTPUT CURRENT (mA) 6241 G27 624012fe 16 LTC6240/LTC6241/LTC6242 TYPICAL PERFORMANCE CHARACTERISTICS Warm-Up Drift vs Time 20 50 NOISE VOLTAGE (nV/Hz) VS = 5V 15 VS = 2.5V 5 VS = 1.5V 0 40 30 20 10 0 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 TIME AFTER POWER UP (s) 10 1 10k 100 1k FREQUENCY (Hz) 100k TIME (1s/DIV) 6241 G28 Series Output Resistance and Overshoot vs Capacitive Load 50 OVERSHOOT (%) NOISE CURRENT (fA/Hz) 75pF 1k 100 10 Minimum Output Series Resistance vs Capacitive Load 1000 60 TA = 25C VS = 2.5V VCM = 0V 1k - RS + 40 CL 30 RS = 10 20 RS = 50 1 10 VS = 2.5V AV = -1 0 0.1 100 1k 10k FREQUENCY (Hz) 10 100k 100 CAPACITIVE LOAD (pF) CL 30 RS = 10 20 RS = 50 3.0 10 VS = 2.5V AV = -2 0 10 100 CAPACITIVE LOAD (pF) 1000 6241 G34 TA = 25C VS = 5V 3.0 A = 1 V - 2.5 + VIN TA = 25C VS = 5V 2.5 AV = -1 VOUT 1k 1mV 1.5 2.0 1k VOUT 1k 1mV 1.5 1mV 1.0 10mV 0.5 10mV 10mV - + 1mV 0.5 1k VIN 2.0 1.0 10F 1F Settling Time vs Output Step (Inverting) SETTLING TIME (s) + 40 RS SETTLING TIME (s) - 1k 1 6241 G33 3.5 500 10 Settling Time vs Output Step (Non-Inverting) 75pF 50 100 6241 G32 Series Output Resistance and Overshoot vs Capacitive Load 60 VS = 2.5V <30% OVERSHOOT 0.1 10pF 100pF 1000pF 0.01F 0.1F CAPACITIVE LOAD 1000 6241 G31 OVERSHOOT (%) 6241 G30 6241 G29 Noise Current vs Frequency 1000 VS = 5V, 0V TA = 25C VS = 2.5V VCM = 0V VOLTAGE NOISE (200nV/DIV) TA = 25C 10 0.1Hz to 10Hz Voltage Noise Noise Voltage vs Frequency 60 OUTPUT SERIES RESISTANCE () CHANGE IN OFFSET VOLTAGE (V) 25 10mV 0 0 -4 -3 -2 -1 0 1 2 OUTPUT STEP (V) 3 4 6241 G35 -4 -3 -2 -1 0 1 2 OUTPUT STEP (V) 3 4 6241 G36 624012fe 17 LTC6240/LTC6241/LTC6242 TYPICAL PERFORMANCE CHARACTERISTICS Maximum Undistorted Output Signal vs Frequency Distortion vs Frequency -30 8 AV = -1 7 -50 -50 AV = +2 6 5 4 VS = 5V AV = 1 -40 V OUT = 2VP-P DISTORTION (dBc) 9 RL = 1k, 2ND -60 -70 RL = 1k, 3RD -80 -60 RL = 1k, 2ND -70 RL = 1k, 3RD -80 3 TA = 25C 2 VS = 5V HD2, HD3 < -40dBc 1 10k 100k 1M FREQUENCY (Hz) -90 10M -90 -100 10k 100k 1M FREQUENCY (Hz) 6241 G37 -100 10k -30 -50 -50 10M Small Signal Response VS = 5V AV = 2 -40 V OUT = 2VP-P DISTORTION (dBc) VS = 2.5V AV = 2 -40 V OUT = 2VP-P -60 RL = 1k, 2ND -70 RL = 1k, 3RD -90 RL = 1k, 2ND -60 0V -70 RL = 1k, 3RD -80 -90 -100 10k 100k 1M FREQUENCY (Hz) 6241 G39 Distortion vs Frequency -30 -80 10M 6241 G38 Distortion vs Frequency DISTORTION (dBc) Distortion vs Frequency -30 VS = 2.5V AV = 1 -40 V OUT = 2VP-P DISTORTION (dBc) OUTPUT VOLTAGE SWINGING (VP-P) 10 100k 1M FREQUENCY (Hz) 10M -100 10k 100k 1M FREQUENCY (Hz) 6241 G40 10M 6241 G41 Large Signal Response Large Signal Response 0V 6241 G42 VS = 2.5V AV = 1 RL = Output Overdrive Recovery 0V VIN (1V/DIV) 0V 0V VOUT (2V/DIV) VS = 5V AV = 1 RL = 6241 G43 VS = 2.5V AV = -1 RL = 1k 6241 G44 VS = 2.5V AV = 3 RL = 500ns/DIV 6241 G45 624012fe 18 LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION Amplifier Characteristics The amplifier input bias current is the leakage current of these ESD diodes. This leakage is a function of the temperature and common mode voltage of the amplifier, as shown in the Typical Performance Characteristics curves. Figure 1 is a simplified schematic of the amplifier, which has a pair of low noise input transistors M1 and M2. A simple folded cascode Q1, Q2 and R1, R2 allow the input stage to swing to the negative rail, while performing level shift to the differential drive generator. Low offset voltage is accomplished by laser trimming the input stage. Noise The LTC6240/LTC6241/LTC6242 exhibit exceptionally low 1/f noise in the 0.1Hz to 10Hz region. This 550nVP-P noise allows these op amps to be used in a wide variety of high impedance low frequency applications, where zero-drift amplifiers might be inappropriate due to their charge injection. Capacitor C1 reduces the unity cross frequency and improves the frequency stability without degrading the gain bandwidth of the amplifier. Capacitor CM sets the overall amplifier gain bandwidth. The differential drive generator supplies signals to transistors M3 and M4 that swing the output from rail-to-rail. In the frequency region above 1kHz the LTC6240/LTC6241/ LTC6242 also show good noise voltage performance. In this frequency region, noise can easily be dominated by the total source resistance of the particular application. Specifically, these amplifiers exhibit the noise of a 3.1k resistor, meaning it is desirable to keep the source and feedback resistance at or below this value, i.e. RS + RG||RFB 3.1k. Above this total source impedance, the noise voltage is not dominated by the amplifier. The photo of Figure 2 shows the output response to an input overdrive with the amplifier connected as a voltage follower. If the negative going input signal is less than a diode drop below V-, no phase inversion occurs. For input signals greater than a diode drop below V-, limit the current to 3mA with a series resistor RS to avoid phase inversion. Noise current can be estimated from the expression in = 2qIB, where q = 1.6 * 10-19 coulombs. Equating 4kTRf and R2qIBf shows that for source resistors below 50G the amplifier noise is dominated by the source resistance. See the Typical Performance Characteristics curve Noise Current vs Frequency. ESD The LTC6240/LTC6241/LTC6242 have reverse-biased ESD protection diodes on all input and outputs as shown in Figure 1. If these pins are forced beyond either supply, unlimited current will flow through these diodes. If the current is transient and limited to one hundred milliamps or less, no damage to the device will occur. VDD = +2.5V V+ ITAIL M3 CM V- V+ DESD1 V+ DESD2 VIN+ DESD5 M1 CLAMP DIFFERENTIAL DRIVE GENERATOR M2 DESD6 V- BIAS DESD3 VO C1 VIN- VSS = -2.5V VOUT AND VIN OF FOLLOWER WITH LARGE INPUT OVERDRIVE V- Q1 Q2 +2.5V RS M4 DESD4 VIN V - + V R1 + VOUT LTC6240 - R2 6241 F01 V- -2.5V 6241 F02 Figure 1. Simplified Schematic Figure 2. Unity Gain Follower Test Circuit 624012fe 19 LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION Proprietary design techniques are used to obtain simultaneous low 1/f noise and low input capacitance. Low input capacitance is important when the amplifier is used with high value source and feedback resistors. High frequency noise from the amplifier tail current source, ITAIL in Figure 1, couples through the input capacitance and appears across these large source and feedback resistors. As an example, the photodiode amplifier of Figure 15 on the last page of this data sheet shows the noise results from the LTC6241 and the results of a competitive CMOS amplifier. The LTC6241 output is the ideal noise of a 1M resistor at room temperature, 130nVHz. +2.5 + 1/4 LTC6242 1k - -2.5 1k 10 + 1/4 LTC6242 1k - VIN + 1/4 LTC6242 VO 1k - 1k 10 The circuit shown in Figure 3 can be used to achieve even lower noise voltage. By paralleling 4 amplifiers the noise voltage can be lowered by 4, or half as much noise. The - comes about from an RMS summing of uncorrelated noise sources. This circuit maintains extremely high input resistance, and has a 250 output resistance. For lower output resistance, a buffer amplifier can be added without influencing the noise. Stability The good noise performance of these op amps can be attributed to large input devices in the differential pair. Above several hundred kilohertz, the input capacitance rises and can cause amplifier stability problems if left unchecked. When the feedback around the op amp is resistive (RF), a pole will be created with RF, the source resistance, source capacitance (RS, CS), and the amplifier input capacitance. In low gain configurations and with RF and RS in even the kilohm range (Figure 4), this pole can create excess phase shift and possibly oscillation. A small capacitor CF in parallel with RF eliminates this problem. Low Noise Single-Ended Input to Differential Output Amplifier 1k 10 Half the Noise The circuit on the first page of the data sheet is a low noise single-ended input to differential output amplifier, with a 200k input impedance. The very low input bias current of the LTC6241 allows for these large input and feedback resistors. The 200k resistors, R1 and R2, along with C1 and C2 set the -3dB bandwidth to 80kHz. Capacitor C3 is used to cancel effects of input capacitance, while C4 adds phase lead to compensate the phase lag of the second amplifier. CF + 1/4 LTC6242 1k RF - 10 - RS 1k CIN CS OUTPUT + 6241 F04 6241 F03 Figure 3. Parallel Amplifier Lowers Noise by 2x Figure 4. Compensating Input Capacitance 624012fe 20 LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT VOLTAGE DENSITY (nV/Hz) The op amp's good input offset voltage match and low input bias current means that the typical differential output offset voltage is less than 40V. A noise spectrum plot of the differential output is shown in Figure 5. 140 VS = 2.5V TA = 25C 120 -3dB BW = 80kHz The guard ring should extend as far as necessary to shield the high impedance signal from any and all leakage paths. Figure 6 shows the use of a guard ring on the LTC6241 in a unity gain configuration. In this case the guard ring is connected to the output and is shielding the high impedance noninverting input from V-. Figure 7 shows the inverting gain configuration. A Digitally Programmable AC Difference Amplifier 100 The LTC6241 configured as a difference amplifier, can be combined with a programmable gain amplifier (PGA) to obtain a low noise high speed programmable difference amplifier. Figure 8 shows the LTC6241 based as a singlesupply AC amplifier. One LTC6241 op amp is used at the circuit's input as a standard four resistor difference amplifier. 80 60 40 20 0 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) LTC6241 S8 6241 F05 Figure 5. Differential Output Noise OUT+ NO SOLDER MASK OVER THE GUARD RING Achieving Low Input Bias Current The DD package is leadless and makes contact to the PCB beneath the package. Solder flux used during the attachment of the part to the PCB can create leakage current paths and can degrade the input bias current performance of the part. All inputs are susceptible because the backside paddle is connected to V- internally. As the input voltage changes or if V- changes, a leakage path can be formed and alter the observed input bias current. For lowest bias current, use the LTC6240/LTC6241 in the SO-8 and provide a guard ring around the inputs that are tied to a potential near the input voltage. IN- R IN+ LEAKAGE CURRENT V- GUARD RING LTC6241 F06 Figure 6. Sample Layout. Unity Gain Configuration, Using Guard Ring to Shield High Impedance Input from Board Leakage LTC6241 S8 OUT+ R Layout Considerations and a PCB Guard Ring In high source impedance applications such as pH probes, photodiodes, strain gauges, et cetera, the low input bias current of these parts requires a clean board layout to minimize additional leakage current into a high impedance signal node. A mere 100G of PC board resistance between a 5V supply trace and an input trace adds 50pA of leakage current, far greater then the input bias current of the operational amplifier. A guard ring around the high impedance input traces driven by a low impedance source equal to the input voltage prevents such leakage problems. NO LEAKAGE CURRENT R IN- VIN IN+ GND V- LTC6241 F07 Figure 7. Sample Layout. Inverting Gain Configuration, Using Guard Ring to Shield High Impedance Input from Board Leakage 624012fe 21 LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION V+ R3 C1 R1 G2 G1 G0 7 6 5 0.1F 8 V1 LTC6910-2 OUT AGND IN V- 2 3 4 1 + 1/2 LTC6241 - VOUT R2 100 R4 R7 C3 V2 C2 V+ R1 = R2 = R3 = R4 0.1F R5 - 1/2 LTC6241 1000pF + R6 20k 1 LT6650 2 5 VREF 1F 3 1k 4 Example Design: Design a programmable gain AC difference amplifier, with a bandwidth of at least 10Hz to 100kHz, an input impedance equal to or greater than 100k, and an output DC reference equal to 1V. V+ 1F DIGITAL INPUTS G2 G1 GO GAIN 0 0 1 1 0 0 1 1 0 -1 -2 -4 -8 -16 -32 -64 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 a. Select input resistors R1, R2, R3 and R4 equal to 100k. VOUT = (V1 - V2) GAIN + VREF R5 VREF = 0.4 * | +1 R6 R5 = 10k * 5 * VREF - 2 R6 = 20k -3d BANDWIDTH = fHIGH - fLOW fHIGH = contribute any significant error to the LT6650 reference voltage. The LT6650 VREF voltage has a maximum error of 2% with 1% resistors. The upper -3dB frequency of the amplifier is set by resistor R3 and capacitor C1 and is limited by the bandwidth of the PGA when operated at a gain of 64. Capacitor C2 is equal to C1 and is added to maintain good common mode rejection at high frequency. The lower -3dB frequency is set by the integrator resistor R7, capacitor C3, and the gain setting of the LTC6910-2 PGA. This lower -3dB zero frequency is multiplied by the PGA gain. The rail-to-rail output of the LTC6910-2 PGA allows for a maximum output peak-to-peak voltage equal to twice the VREF voltage. At the maximum gain setting of 64, the maximum peak-to-peak difference between inputs V1 and V2 is equal to twice VREF divided by 64. 1 GAIN = f 2 * P * R3 * C1 LOW 2 * P * R7 * C3 6241 F08 Figure 8. Wideband Difference Amplifier with High Input Impedance and Digitally Programmable Gain The low bias current and current noise of the LTC6241 allow the use of high valued input resistors, 100k or greater. Resistors R1, R2, R3 and R4 are equal and the gain of the difference amplifier is one. An LTC6910-2 PGA amplifies the difference amplifier output with inverting gains of -1, -2, -4, -8, -16, -32 and -64. The second LTC6241 op amp is used as an integrator to set the DC output voltage equal to the LT6650 reference voltage VREF. The integrator drives the PGA analog ground to provide a feedback loop, in addition to blocking any DC voltage through the PGA. The reference voltage of the LT6650 can be set to a voltage from 400mV to V+ - 350mV with resistors R5 and R6. If R6 is 20k or less, the error due to the LT6650 op amp bias current is negligible. The low voltage offset and drift of the LTC6241 integrator will not b. If the upper -3dB frequency is 100kHz then C1 = 1/(2 * R2 * f3dB) = 1/(6.28 * 100k * 100kHz) = 15pF (to the nearest 5% value) and C2 = C1 = 15pF. c. Select R7 equal to one 1M and set the lower -3dB frequency to 10Hz at the highest PGA gain of 64, then C3 = Gain/(2 * R7 * f3dB) = 64/(6.28 * 100k * 10Hz) = 1F. Lower gains settings will give a lower f3dB. d. Calculate the value of R5 to set the LT6650 reference equal to 1V; VREF = 0.4(R5/R6 + 1), so R5 = R6(2.5VREF - 1). For R6 = 20k, R5 = 30k With VREF = 1V the maximum input difference voltage is equal to 2V/64 = 31.2mV. 40nVpp Noise, 0.05V/C Drift, Chopped FET Amplifier Figure 9's circuit combines the 5V rail-to-rail performance of the LTC6241HV with a pair of extremely low noise JFETs configured in a chopper based carrier modulation scheme 624012fe 22 LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION to achieve an extraordinarily low noise and low DC drift. The performance of this circuit is suited for the demanding transducer signal conditioning situations such as high resolution scales and magnetic search coils. with the input chopper, proper amplitude and polarity information is presented to A2, the DC output amplifier. This stage integrates the square wave into a DC voltage, providing the output. The output is divided down (R2 and R1) and fed back to the input chopper where it serves as a zero signal reference. Gain, in this case 1000, is set by the R1-R2 ratio. Because A1 is AC coupled, its DC offset and drift do not affect the overall circuit offset, resulting in the extremely low offset and drift noted. The JFETs have an input RC damper that minimizes offset voltage contribution due to parasitic switch behavior, resulting in the 1V offset specification. The LTC1799's output is divided down to form a 2-phase 925Hz square wave clock. This frequency, harmonically unrelated to 60Hz, provides excellent immunity to harmonic beating or mixing effects which could cause instabilities. S1 and S2 receive complementary drive, causing A1 to see a chopped version of the input voltage. A1's square wave output is synchronously demodulated by S3 and S4. Because these switches are synchronously driven 5V TO LTC201 V+ PIN -5V TO LTC201 V- PIN 1F + + 5V 5V 18.5kHz V+ 74C90 / 10 DIV LTC1799 OUT RSET 5V 1F 74C74 / 2 Q Q 925Hz 54.2k* TO O1 POINTS 5V O1 TO O2 POINTS 8 898** 30.1 INPUT 898** 6 7 O2 S1 S2 0.01F 11 10 9 O2 1F 1 - LSK389 499** A1 LTC6241HV + 1F 3 2 S3 S4 10M -5V 240k 14 15 16 10k O1 1F * = 0.1% METAL FILM RESISTOR ** = 1% METAL FILM RESISTOR = LTC201 QUAD = LSK389 = LINEAR INTEGRATED SYSTEMS FREMONT, CA NOISE = 40nVP-P 0.1Hz TO 10Hz OFFSET = 1V DRIFT = 0.05V/C R2 +1 GAIN = 10 OPEN-LOOP GAIN = 10 9 I BIAS = 500pA - A2 LTC6241HV OUTPUT + R2 10k R1 10 6241 F09 Figure 9. Ultralow Noise Chopper Amplifier 624012fe 23 LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION The noise measured over a 50 second interval, in Figure 10, is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is attributed to the input JFET's die size and current density. 20nV/DIV 5s/DIV by the sensor is forced across the feedback capacitor by the op amp action. Because the feedback capacitor is 100 times smaller than the sensor, it will be forced to 100 times what would have been the sensor's open circuit voltage. So the circuit gain is 100. The benefit of this approach is that the signal gain of the circuit is independent of any cable capacitance introduced between the sensor and the amplifier. Hence this circuit is favored for remote accelerometers where the cable length may vary. Difficulties with the circuit are inaccuracy of the gain setting with the small capacitor, and low frequency cutoff due to the bias resistor working into the small feedback capacitor. 6241 F10 Figure 10. Noise in a 0.1Hz to 10Hz Bandwidth Low Noise Shock Sensor Amplifiers Figures 11 and 12 show the amplifiers realizing two different approaches to amplifying signals from a capacitive sensor. The sensor in both cases is a 770pF piezoelectric shock sensor accelerometer, which generates charge under physical acceleration. Figure 11 shows the classical "charge amplifier" approach. The LTC6240 is in the inverting configuration so the sensor looks into a virtual ground. All of the charge generated Figure 12 shows a noninverting amplifier approach. This approach has many advantages. First of all, the gain is set accurately with resistors rather than with a small capacitor. Second, the low frequency cutoff is dictated by the bias resistor working into the large 770pF sensor, rather than into a small feedback capacitor, for lower frequency response. Third, the noninverting topology can be paralleled and summed (as shown) for scalable reductions in voltage noise. The only drawback to this circuit is that the parasitic capacitance at the input reduces the gain slightly. This circuit is favored in cases where parasitic input capacitances such as traces and cables will be relatively small and invariant. VS+ + + SHOCK SENSOR MURATA-ERIE PKGS-00LD 770pF CABLE HAS UNKNOWN C LTC6240 - Cf 7.7pF Rf 1G BIAS RESISTOR VISHAY-TECHNO CRHV2512AF1007G (OR EQUIVALENT) 1/2 LTC6241HV SHOCK SENSOR MURATA-ERIE PKGS-00LD 770pF - 100 VOUT = 110mV/g MAIN GAIN-SETTING ELEMENT IS A CAPACITOR 1G Figure 11. Classical Inverting Charge Amplifier 10k VOUT 1k + 1/2 LTC6241HV BIAS RESISTOR VISHAY-TECHNO CRHV2512AF1007G (OR EQUIVALENT) - 100 6241 F11 1k VOUT = 110mV/g VS = 1.4V to 5.5V BW = 0.2Hz to 10kHz VS- 10k 6241 F12 Figure 12. Low Noise Noninverting Shock Sensor Amplifier 624012fe 24 LTC6240/LTC6241/LTC6242 APPLICATIONS INFORMATION 1M Transimpedance Amplifier with 43nV/Hz Output Noise By achieving an output swing of 50V before attenuation, the circuit provides an output swing to 5V after attenuation. The 10M resistor sets the gain of the TIA stage and has a noise density of 400nV/Hz. After attenuation, the effective TIA gain drops to 1M while the noise floor drops to 40nV/Hz, which clearly dominates the observed 43nV/Hz. Note the additional benefit that the offset voltage of the op amp is divided by 10. Worst-case output offset for this circuit is 150V over temperature. In a normal 1M transimpedance amplifier, like that shown on the back page of this data sheet, the output noise density must be at least 130nV/Hz at room temperature. This is true even should the op amp be perfectly noiseless, because the 1M resistor provides 130nV/Hz of voltage noise at room temperature independently of the op amp. The circuit of Figure 13 provides an overall transimpedance gain of 1M, but it has an output noise density of only 43nV/Hz, about 1/3 of the normal transimpedance amplifier. It does this by taking a higher initial transimpedance gain of 10M and then attenuating by a factor of 10. The transistor section provides voltage gain and works on a 54V supply voltage to guarantee adequate output swing. Reference Buffer Figure 14 shows the LTC6240 being utilized as a buffer in conjunction with the LT1019 reference. The passive R-C filter attenuates the reference noise and the LTC6240 provides a low noise buffer, resulting in an output noise of 8nV/Hz. 54V 33k 0.3pF MPSA06 10M 1% 5V + 3pF PHOTODIODE 10M GAIN (10V/A) 10k MPSA06 LTC6240HV - -1.5V -5V 100pF 10k 9.09k 1% 1/4W 2.4k 43k VOUT 1M GAIN (1V/A) 1k 1% 1k -5V 6241 F13 Figure 13. 1M Transimpedance Amplifier with 43nV/Hz Output Noise 5V LT1019-2.5 180nV/Hz 1M + 1F LTC6240HV 8nV/Hz - -5V 0.2 VOUT 10F CERAMIC OR FILM 6241 F14 Figure 14. Low Noise Reference Buffer 624012fe 25 LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm x 3mm) (Reference LTC DWG # 05-08-1698) 0.70 p0.05 3.5 p0.05 1.65 p0.05 2.10 p0.05 (2 SIDES) PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 2.38 p0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 p0.10 (4 SIDES) R = 0.125 TYP 5 0.40 p 0.10 8 1.65 p 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD8) DFN 0509 REV C 0.200 REF 0.75 p0.05 4 0.25 p 0.05 1 0.50 BSC 2.38 p0.10 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 624012fe 26 LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTION DHC Package 16-Lead Plastic DFN (5mm x 3mm) (Reference LTC DWG # 05-08-1706) 0.65 0.05 3.50 0.05 1.65 0.05 2.20 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 4.40 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5.00 0.10 (2 SIDES) R = 0.20 TYP 3.00 0.10 (2 SIDES) 9 0.40 0.10 16 1.65 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH (DHC16) DFN 1103 8 0.200 REF 1 0.25 0.05 0.50 BSC 0.75 0.05 4.40 0.10 (2 SIDES) 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 624012fe 27 LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 - .196* (4.801 - 4.978) .045 .005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .0165 .0015 .150 - .157** (3.810 - 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .0532 - .0688 (1.35 - 1.75) 2 3 4 5 6 7 8 .004 - .0098 (0.102 - 0.249) 0 - 8 TYP .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 - .012 (0.203 - 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 624012fe 28 LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTION S5 Package 5-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1635 Rev B) 0.62 MAX 0.95 REF 2.90 BSC (NOTE 4) 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 - 1.75 (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 - 0.45 TYP 5 PLCS (NOTE 3) 0.95 BSC 0.80 - 0.90 0.20 BSC 0.01 - 0.10 1.00 MAX DATUM `A' 0.30 - 0.50 REF 0.09 - 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.90 BSC S5 TSOT-23 0302 REV B 624012fe 29 LTC6240/LTC6241/LTC6242 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 - .197 (4.801 - 5.004) NOTE 3 .045 .005 .050 BSC 8 .245 MIN 7 6 5 .160 .005 .150 - .157 (3.810 - 3.988) NOTE 3 .228 - .244 (5.791 - 6.197) .030 .005 TYP 1 RECOMMENDED SOLDER PAD LAYOUT .010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254) 0- 8 TYP .016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN .053 - .069 (1.346 - 1.752) .014 - .019 (0.355 - 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 2 3 4 .004 - .010 (0.101 - 0.254) .050 (1.270) BSC SO8 0303 624012fe 30 LTC6240/LTC6241/LTC6242 REVISION HISTORY (Revision history begins at Rev E) REV DATE DESCRIPTION E 07/10 Update to Simplified Schematic (Figure 1) PAGE NUMBER 19 624012fe Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC6240/LTC6241/LTC6242 TYPICAL APPLICATION 150kHz 3RD ORDER BUTTERWORTH FILTER 1M TIA R1 866 + 1/2 LTC6241 - RF 1M R2 1.69k R3 2k C1 1500pF C2 1500pF C3 180pF +1.5V + 1/2 LTC6241 - SFH213FA OR EQUIVALENT (4pF) -1.5V 6241 TA02a CF 1pF -1.5V Figure 15. Ultralow Noise 1M 150kHz Photodiode Amplifier Competition Output Noise Spectrum. Op Amp Noise Dominates; Performance Compromised 30nV/Hz PER DIV 30nV/Hz PER DIV LTC6241 Output Noise Spectrum. 1M Resistor Noise Dominates; Ideal Performance 0V 1kHz 0V 10kHz/DIV 101kHz 1kHz 10kHz/DIV 101kHz 6241 TA02b 6241 TA02c RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1151 15V Zero-Drift Op Amp Dual High Voltage Operation 18V LT1792 Low Noise Precision JFET Op Amp 6nV/Hz Noise, 15V Operation LTC2050 Zero-Drift Op Amp 2.7 Volt Operation, SOT-23 LTC2051/LTC2052 Dual/Quad Zero-Drift Op Amp Dual/Quad Version of LTC2050 in MS8/GN16 Packages LTC2054/LTC2055 Single/Dual Zero-Drift Op Amp Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages LTC6244 Dual 50MHz Rail-to-Rail Op Amp 100V VOS(MAX), 1pA IBIAS, 40V/V, Slew Rate 624012fe 32 Linear Technology Corporation LT 0710 REV E * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2005