MC74VHCT244ADWRG - ON Semiconductor L.L.C.

May, 2011 − Rev. 7

1Publication Order Number:

MC74VHCT244A/D

MC74VHCT244A

Octal Bus Buffer/Line Driver

with 3-State Outputs

The MC74VHCT244A is an advanced high speed CMOS octal bus

buffer fabricated with silicon gate CMOS technology. It achieves high

speed operation similar to equivalent Bipolar Schottky TTL while

maintaining CMOS low power dissipation.

The MC74VHCT244A is a noninverting 3−state buffer, and has two

active−low output enables. This device is designed to be used with

3−state memory address drivers, etc.

The VHCT inputs are compatible with TTL levels. This device can

be used as a level converter for interfacing 3.3 V to 5.0 V, because it

has full 5.0 V CMOS level output swings.

The VHCT244A input and output (when disabled) structures

provide protection when voltages between 0 V and 5.5 V are applied,

regardless of the supply voltage. These input and output structures

help prevent device destruction caused by supply

voltage−input/output voltage mismatch, battery backup, hot insertion,

etc.

Features

•High Speed: tPD = 5.6 ns (Typ) at VCC = 5.0 V

•Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25°C

•TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V

•Power Down Protection Provided on Inputs and Outputs

•Balanced Propagation Delays

•Designed for 4.5 V to 5.5 V Operating Range

•Low Noise: VOLP = 1.1 V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300 mA

•ESD Performance:

Human Body Model > 2000 V;

Machine Model > 200 V

•Chip Complexity: 112 FETs or 28 Equivalent Gates

•These Devices are Pb−Free and are RoHS Compliant

SOEIAJ−20

SUFFIX M

CASE 967

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

74VHCT244

AWLYWWG

TSSOP−20

SUFFIX DT

CASE 948E

SOIC−20WB

SUFFIX DW

CASE 751D

VHCT

244A

ALYWG

VHCT244A

AWLYYWWG

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

MC74VHCT244A

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Figure 1. Logic Diagram

DATA

INPUTS

B4 17

218

3YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

NONINVERTING

OUTPUTS

OUTPUT

ENABLES

OEA

OEB

Figure 2. Pin Assignment

YB4

OEA

GND

YB1

YB2

YB3 5

YA2

YA1

OEB

VCC

YA4

YA3

FUNCTION TABLE

Inputs Outputs

OEA, OEB A, B YA, YB

L L

H H

X Z

MC74VHCT244A

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎÎ

–0.5 to +7.0

ÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎÎÎÎ

–0.5 to +7.0

ÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage Output in 3−State

High or Low State

ÎÎÎÎÎÎ

–0.5 to +7.0

–0.5 to VCC + 0.5

ÎÎ

ÎÎÎÎ

IIK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Diode Current

ÎÎÎÎÎÎ

−20

ÎÎ

ÎÎÎÎ

IOK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Diode Current (VOUT < GND; VOUT > VCC)

ÎÎÎÎÎÎ

±20

ÎÎ

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

±25

ÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

±75

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎÎÎÎ

500

450

ÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

–65 to +150

ÎÎ

°C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings

applied to the device are individual stress limit values (not normal operating conditions) and are

not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

†Derating −SOIC Packages: – 7 mW/°C from 65° to 125°C

TSSOP Package: − 6.1 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎ

4.5

ÎÎÎÎ

5.5

ÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎ

ÎÎÎÎ

5.5

ÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage Output in 3−State

High or Low State

ÎÎÎ

ÎÎÎÎ

5.5

VCC

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature

ÎÎÎ

−40

ÎÎÎÎ

+125

ÎÎ

°C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 5.0 V ± 0.5 V

ÎÎÎ

ÎÎÎÎ

ÎÎ

ns/V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

ÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎÎÎÎÎ

TA = 85 to 125°C

ÎÎ

Unit

ÎÎÎ

Min

ÎÎ

Typ

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎ

Minimum High−Level

Input Voltage

ÎÎÎÎÎÎ

ÎÎÎ

4.5 to

5.5

ÎÎÎ

2.0

ÎÎ

ÎÎÎ

ÎÎÎÎ

2.0

ÎÎÎ

2.0

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎ

Maximum Low−Level

Input Voltage

ÎÎÎÎÎÎ

ÎÎÎ

4.5 to

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

0.8

ÎÎÎÎ

ÎÎÎ

0.8

ÎÎÎ

ÎÎÎÎ

0.8

ÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎ

Minimum High−Level

Output Voltage

Vin = VIH or VIL

ÎÎÎÎÎÎ

IOH = −50 mA

ÎÎÎ

4.5

ÎÎÎ

4.4

ÎÎ

4.5

ÎÎÎ

ÎÎÎÎ

4.4

ÎÎÎ

4.4

ÎÎÎÎ

ÎÎ

ÎÎÎÎÎÎ

IOH = −8 mA

ÎÎÎ

4.5

ÎÎÎ

3.94

ÎÎ

ÎÎÎ

ÎÎÎÎ

3.80

ÎÎÎ

3.66

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎ

Maximum Low−Level

Output Voltage

Vin = VIH or VIL

ÎÎÎÎÎÎ

IOL = 50 mA

ÎÎÎ

4.5

ÎÎÎ

ÎÎ

0.0

ÎÎÎ

0.1

ÎÎÎÎ

ÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

0.1

ÎÎ

ÎÎÎÎÎÎ

IOL = 8 mA

ÎÎÎ

4.5

ÎÎÎ

ÎÎ

ÎÎÎ

0.36

ÎÎÎÎ

ÎÎÎ

0.44

ÎÎÎ

ÎÎÎÎ

0.52

ÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎ

Maximum Input

Leakage Current

ÎÎÎÎÎÎ

Vin = 5.5 V or GND

ÎÎÎ

0 to

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

±0.1

ÎÎÎÎ

ÎÎÎ

±1.0

ÎÎÎ

ÎÎÎÎ

±1.0

ÎÎ

ÎÎÎÎ

IOZ

ÎÎÎÎÎÎÎ

Maximum 3−State

Leakage Current

ÎÎÎÎÎÎ

Vin = VIL or VIH

Vout = VCC or GND

ÎÎÎ

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

±0.25

ÎÎÎÎ

ÎÎÎ

±2.5

ÎÎÎ

ÎÎÎÎ

2.5

ÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎ

Maximum Quiescent

Supply Current

ÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

4.0

ÎÎÎÎ

ÎÎÎ

40.0

ÎÎÎ

ÎÎÎÎ

40.0

ÎÎ

ÎÎÎÎ

ICCT

ÎÎÎÎÎÎÎ

Quiescent Supply

Current

ÎÎÎÎÎÎ

Per Input: VIN =3.4 V

Other Input: VCC or

GND

ÎÎÎ

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

1.35

ÎÎÎÎ

ÎÎÎ

1.50

ÎÎÎ

ÎÎÎÎ

1.65

ÎÎ

ÎÎÎÎ

IOPD

ÎÎÎÎÎÎÎ

Output Leakage

Current

ÎÎÎÎÎÎ

VOUT = 5.5 V

ÎÎÎ

ÎÎ

ÎÎÎ

0.5

ÎÎÎÎ

ÎÎÎ

5.0

ÎÎÎ

ÎÎÎÎ

ÎÎ

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74VHCT244A

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎÎÎÎÎ

TA = 85 to 125°C

ÎÎ

Unit

ÎÎÎ

Min

ÎÎ

Typ

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎ

Maximum

Propagation Delay

A to YA or B to YB

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 15 pF

CL = 50 pF

ÎÎÎ

ÎÎ

5.4

5.9

ÎÎÎ

7.4

8.4

ÎÎÎÎ

1.0

ÎÎÎ

8.5

9.5

ÎÎÎ

11.0

1.0

ÎÎÎÎ

9.5

10.5

ÎÎ

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎ

Output Enable Time

OEA to YA or OEB to

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 15 pF

RL = 1 kWCL = 50 pF

ÎÎÎ

ÎÎ

7.7

8.2

ÎÎÎ

10.4

11.4

ÎÎÎÎ

1.0

ÎÎÎ

12.0

13.0

ÎÎÎ

1.0

ÎÎÎÎ

13.5

14.5

ÎÎ

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎ

Output Disable Time

OEA to YA or OEB to

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 50 pF

RL = 1 kW

ÎÎÎ

ÎÎ

8.8

ÎÎÎ

11.4

ÎÎÎÎ

1.0

ÎÎÎ

13.0

ÎÎÎ

1.0

ÎÎÎÎ

14.5

ÎÎ

ÎÎÎÎ

tOSLH,

tOSHL

ÎÎÎÎÎÎÎ

Output to Output

Skew

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 50 pF

(Note 1)

ÎÎÎ

ÎÎ

ÎÎÎ

1.0

ÎÎÎÎ

ÎÎÎ

1.0

ÎÎÎ

ÎÎÎÎ

1.0

ÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)

Symbol Parameter

Typical @ 25°C, VCC = 5.0 V

Unit

Min Typ Max

CPD Power Dissipation Capacitance (Note 2) 18 pF

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Three−State Output Capacitance (Output in High−Impedance State)

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 8 (per bit). CPD is used to determine the no−load

dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)

Symbol Parameter

TA = 25°C

Unit

Typ Max

VOLP Quiet Output Maximum Dynamic VOL 0.9 1.1 V

VOLV Quiet Output Minimum Dynamic VOL −0.9 −1.1 V

VIHD Minimum High Level Dynamic Input Voltage 2.0 V

VILD Maximum Low Level Dynamic Input Voltage 0.8 V

ORDERING INFORMATION

Device Package Shipping†

MC74VHCT244ADWRG SOIC−20WB

(Pb−Free)

1000 / Tape & Reel

MC74VHCT244ADTG TSSOP−20* 75 Units / Rail

MC74VHCT244ADTRG TSSOP−20* 2500 / Tape & Reel

MC74VHCT244AMELG SOEIAJ−20

(Pb−Free)

2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC74VHCT244A

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Figure 3. Switching Waveform

Figure 4. Switching Waveform

OEA or OEB

YA or YB

YA or YB 1.5 V

tPZL tPLZ

tPZH tPHZ

3 V

HIGH

IMPEDANCE

VOL +0.3 V

VOH -0.3 V

HIGH

IMPEDANCE

GND

tPHL

YA or YB

A or B

tPLH

1.5 V

3 V

VOL

VOH

1.5 V

GND

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 5. Test Circuit

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 6. Test Circuit

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 kW

MC74VHCT244A

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PACKAGE DIMENSIONS

B20X

H10X

18X A1

SEATING

PLANE

hX 45_

0.25 M

0.25 S

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

SOIC−20 WB

DW SUFFIX

CASE 751D−05

ISSUE G

MC74VHCT244A

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PACKAGE DIMENSIONS

TSSOP−20

CASE 948E−02

ISSUE C

DIM

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

−T−

0.100 (0.004)

DGH

SECTION N−N

JJ1

−W−

SEATING

PLANE

−V−

−U−

0.10 (0.004) V S

20X REFK

L/2

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

--- ---

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

MC74VHCT244A

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PACKAGE DIMENSIONS

SOEIAJ−20

M SUFFIX

CASE 967−01

ISSUE A

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.15 0.25 0.006 0.010

12.35 12.80 0.486 0.504

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0.70 0.90 0.028 0.035

--- 0.81 --- 0.032

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

110

0.13 (0.005)

0.10 (0.004)

VIEW P

DETAIL P

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