5V, 3.3V, ISR™ High-Performance CPLD
s
Ultra37000 CPLD Fami
ly
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-03007 Rev. *B Revised May 7, 2003
Features
• In-System Reprogrammable™ (ISR™) CMOS CPLDs
—JTAG interface for reconfigura bili ty
—Design changes do not cause pinout changes
—Design changes do not cause timing changes
• High density
—32 to 512 macrocells
—32 to 264 I/O pins
—Five dedicated inputs including four clock pins
• Simple timing model
—No fanout delays
—No expander delays
—No dedicated vs. I/O pin delays
—No additional delay through PIM
—No penalty for using full 16 product terms
—No delay for steering or sharing product terms
• 3.3V and 5V versions
• PCI-compatible[1]
• Programmable bus-hold capabilities on all I/Os
• Intelligent product term allocator provides:
—0 to 16 product terms to any macrocell
—Product term steering on an individual basis
—Product term sharing among local macrocells
• Flexible clocking
—Four synchronous clocks per device
—Product term clocking
—Clock polarity control per logic block
• Consistent package/pinout offering across all densities
—Simplifies design migration
—Same pinout for 3.3V and 5.0V devices
• Packages
—44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,
BGA, and Fine-Pitch BGA packages
General Description
The Ult ra37000™ family of CMOS CPLDs pr ovides a range of
high-density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to
bring the flexibility , ease of use, and performance of the 22V10
to high-density CPLDs. T he architecture is based on a number
of logic bloc ks that are connected by a Programmable Inter-
connect Matrix (PIM). Each logic block features its own
produc t term array, prod uct term all ocator, and 16 macroc ells.
The PIM distribu tes signals from the logic block outputs a nd all
input pins to the logic block inputs.
All of t h e Ul t ra3 7 00 0 devi ce s a r e el ec t r ic al ly er as ab l e a nd I n -
System Reprogrammable (ISR), which simplifies both design
and manufacturing flows, thereby reducing costs. The ISR
feature provides the ability to reconfigure the devices without
having design changes cause pinout or timing changes. The
Cypress ISR function is implemented through a JTAG-
compliant serial interface. Data is shifted in and out through
the TDI and TDO pins, respectively. Because of the superior
rout abi lity an d simp le t iming model of the Ul tra370 00 devi ces,
ISR allo ws users to change ex isting log ic designs w hile sim ul-
taneously fixing pinout assignments and maintaining system
performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The
Ultra37000 family features user programmable bus-hold
capabilities on all I/Os.
Ultra37000 5.0V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. VCCO conn ection s provide th e
capability of interfacing to either a 5V or 3.3V bus. By
connecting the VCCO pins to 5V the user insures 5V TTL levels
on the out puts. If VCCO is connected to 3.3V the output levels
meet 3.3V J EDEC standard CMOS le vels and are 5V tolera nt.
These devices require 5V ISR programming.
Ultra37000V 3.3V Devices
Devi ces operating with a 3.3V suppl y require 3.3V on all VCCO
pins, reducing the device’s power consumption. These
devices support 3.3V JEDEC standard CMOS output levels,
and are 5V-tolerant. These devices allow 3.3V ISR
programming.
Note:
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 2 of 63
Selection Guide
5.0V Selection Guide
3.3V Selection Guide
General Information
Device Macrocells Dedicated
Inputs I/O Pins Speed (tPD) Speed (fMAX)
CY37032 32 5 32 6 200
CY37064 64 5 32/64 6 200
CY37128 128 5 64/128 6.5 167
CY37192 192 5 120 7.5 154
CY37256 256 5 128/160/192 7.5 154
CY37384 384 5 160/192 10 118
CY37512 512 5 160/192/264 10 118
Speed Bins
Device 200 167 154 143 125 100 83 66
CY37032 X X X
CY37064 X X X
CY37128 X X X
CY37192 X X X
CY37256 X X X
CY37384 X X
CY37512 X X X
Device-Package Offering and I/O Count
Device 44-
Lead
TQFP
44-
Lead
PLCC
44-
Lead
CLCC
84-
Lead
PLCC
84-
Lead
CLCC
100-
Lead
TQFP
160-
Lead
TQFP
160-
Lead
CQFP
208-
Lead
PQFP
208-
Lead
CQFP
256-
Lead
BGA
352-
Lead
BGA
CY37032 37 37
CY37064 37 37 37 69 69
CY37128 69 69 69 133
CY37192 125
CY37256 133 133 165 197
CY37384 165 197
CY37512 165 165 197 269
General Information
Device Macrocells Dedicated
Inputs I/O Pins Speed (tPD) Speed (fMAX)
CY37032V 32 5 32 8.5 143
CY37064V 64 5 32/64 8.5 143
CY37128V 128 5 64/80/128 10 125
CY37192V 192 5 120 12 100
CY37256V 256 5 128/160/192 12 100
CY37384V 384 5 160/192 15 83
CY37512V 512 5 160/192/264 15 83
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 3 of 63
Architecture Overview of Ultra37000 Family
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) consists of a
completely global routing matrix for signals from I/O pins and
feedbacks from the logic blocks. The PIM provides extremely
robust interconnection to avoid fitting and density limitations.
The inputs to the PIM consist of all I/O and dedicated input pins
and a ll m ac r oc el l fe ed ba c ks f rom w i thi n t h e log ic b lo ck s. Th e
number of PIM in puts increases with pin count and the number
of logic blocks . The output s from th e PIM are signal s routed to
the appropriate logic blocks. Each logic block receives 36
input s from the PIM and their complem ents, allow ing for 32-bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also
improves the routing capacity of the Ultra37000 family.
An important feature of the PIM is its simple timing. The propa-
gation delay through the PIM is accounted for in the timing
speci ficati ons fo r each devi ce. Th ere is no ad dition al del ay for
traveling through the PIM. In fact, all inputs travel through the
PIM. As a result, there are no route-dependent timing param-
eters on the Ultra37000 devices. The worst-case PIM delays
are incorporated in all appropriate Ultra37000 specifications.
Routing signals through the PIM is completely invisible to the
user . All routing is accomplished by so ftware—no hand routing
is necessary. Warp™ and third- party de velopm ent packa ges
automatically route designs for the Ultra37000 family in a
matter of minutes. Finally, the rich routing resources of the
Ultra37000 family accommodate last minute logic changes
while maintaining fixed pin assignments.
Logic Block
The logic block is the basic building block of the Ultra37000
archi tect ure. It consis ts of a pr oduct term arr ay, an intel ligent
product-term allocator, 16 macrocells, and a number of I/O
cells. The number of I/O cells varies depending on the device
used. Refer to Figure 1 for the block diagram.
Product Term Array
Each logic block features a 72 x 87 programmable product
term array. This array accepts 36 inputs from the PIM, which
originate from macrocell feedbacks and device pins. Active
LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 87 product
terms in the array can be created from any of the 72 inputs.
Of the 87 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Four of the remaining
seven pro duc t te rms i n th e l ogi c blo ck are ou tpu t en abl e (O E)
product terms. Each of the OE product terms controls up to
eight of the 16 macrocells and is selectable on an individual
macrocell basis. In other words, each I/O cell can select
between one of two OE product terms to control the output
buffer. The first two of these four OE product terms are
available to the upper half of the I/O macrocells in a logic block.
The oth er two O E produc t terms a re availabl e to th e lower ha lf
of the I/O macrocells in a logic block.
The next two product terms in each logic block are dedicated
asynchronous set and asynchronous reset product terms. The
final p roduct term is the produ ct term c lock. T he set, r eset, OE
and product term clock have polarity control to realize OR
functions in a single pass through the array.
Speed Bins
Device 200 167 154 143 125 100 83 66
CY37032V X X
CY37064V X X
CY37128V XX X
CY37192V XX
CY37256V XXX
CY37384V XX
CY37512V XXX
Shaded areas indicate preliminary speed bins.
Device-Package Offering & I/O Count
Device
44-
Lead
TQFP
44-
Lead
PLCC
44-
Lead
CLCC
48-
Lead
FBGA
84-
Lead
PLCC
84-
Lead
CLCC
100-
Lead
TQFP
100-
Lead
FBGA
160-
Lead
TQFP
160-
Lead
CQFP
208-
Lead
PQFP
208-
Lead
CQFP
256-
Lead
BGA
256-
Lead
FBGA
352-
Lead
BGA
400-
Lead
FBGA
CY37032V 37 37 37
CY37064V 37 37 37 37 69 69 69
CY37128V 69 69 69 85 133
CY37192V 125
CY37256V 133 133 165 197 197
CY37384V 165 197
CY37512V 165 165 197 269 269
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 4 of 63
Low-Power Option
Each logic block can operate in high-speed mode for critical
path performance, or in low-power mode for power conser-
vation . The logic bloc k mode is set by the user on a logi c block
by logic block basis.
Product Term Allocator
Through the product term allocator, software automatically
distributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 product terms are ava ilable from
the local product term array. The product term allocator
provides two important capabilities without affecting perfor-
mance: product term steering and product term sharing.
Produ ct Term Steeri ng
Product term steering is the process of assigning product
terms t o mac rocell s as neede d. For e xamp le, if o ne ma croce ll
requ ires ten produc t terms whi le anot her need s just th ree, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Ultra37000 devices,
prod uct terms are steere d on an ind ividu al bas is. Any n umber
between 0 and 16 product terms can be steered to any
macrocell. Note that 0 product terms is useful in cases where
a particular macrocell is unused or used as an input register.
Produ ct Term Sharing
Produ ct term sharing i s the process of using the same produ ct
term among multiple macrocells. For example, if more than
one output has one or more product terms in its equation that
are common to other outputs, those product terms are only
programmed once. The Ultra37000 product term allocator
allows sharing across groups of four output macrocells in a
variable fashion. The software automatically takes advantage
of this capability—the user does not have to intervene.
Note that neither product term sharing nor product term
steering have any effect on the speed of the product. All worst-
case steering and sharing configurations have been incorpo-
rated in the timing specifications for the Ultra37000 devices.
Ultra37000 Macrocell
Within each logic block there are 16 macrocells. Macrocells
can either be I/O Macrocells, which include an I/O Cell which
is associated with an I/O pin, or buried Macrocells, which do
not connect to an I/O. The combination of I/O Macrocells and
buried Macrocells varies from device to device.
Buried Macrocell
Figure 2 displays the architecture of buried macrocells. The
buried ma crocel l features a register tha t can be confi gured as
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered
latch.
The register can be asynchronously set or asynchronously
reset at the logic block level with the separate set and reset
product terms. Each of these pro duct terms features pr ogram-
mable polarity. This allows the registers to be set or reset
based on an AND expression or an OR expression.
Clocking of the register is very flexible. Four global
synchronous clocks and a product term clock are available to
clock the register. Furthermore, each clock features program-
mable polarity so that registers can be triggered on falling as
well as risin g edg es (see the Clo cking sec tio n). Cl oc k pol ari ty
is chosen at the logic bl ock level.
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input
Figure 1. Logic Block with 50% Buried Macrocells
I/O
CELL
0
PRODUCT
TERM
ALLOCATOR
I/O
CELL
14
MACRO-
CELL
0
MACRO-
CELL
1
MACRO-
CELL
14
0−16
PRODUCT
TERMS
72 x 87
PRODUCT TERM
ARRAY
8036
8
16
TO
PIM
FROM
PIM
7
32
MACRO-
CELL
15
2
to cells
2, 4, 6 8, 10, 12
0−16
PRODUCT
TERMS
0−16
PRODUCT
TERMS
0−16
PRODUCT
TERMS
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 5 of 63
register (D-type or latch) whose input comes from the I/O pin
associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macroc ell
Figure 2 illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried
macrocell with the addition of I/O capability . At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage
of allowing significant logic reduction to occur in many appli-
cations.
The U ltra37000 mac rocell featu res a feedba ck path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold , wh ich is an i mproved ver sion o f the p opula r intern al
pull-up resist or, is a weak latch c onnec ted to the pin tha t does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-
interface applications. Bus-hold additionally allows unused
device pins to remain unconnected on the board, which is
particularly useful during prototyping as designers can route
new signals to the device without cutting trace connections to
VCC or GND. For more information, see the application note
“Understanding Bus-Hold - A Feature of Cypress CPLDs.”
Programmable Slew Rate Control
Each out put has a pro grammabl e configu ration bit, whi ch set s
the output slew rate to fast or slow . For designs concerned with
meetin g FCC em issi ons st and ards the slo w edge pro vides for
lower system noise. For designs requiring very high perfor-
mance the fast edge rate provides maximum system perfor-
mance.
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 6 of 63
f
Figure 2. I/O and Buried Macrocells
Figure 3. Input Macrocell
C2 C3
DECODE
C2 C3
DECODE
0
1
2
3O
C6 C5
“0”
“1”
0
1O
D/T/L Q
R
P
0
1
2
3O
C0
0
1
O
C4
FEEDBACK TO PIM
FEEDBACK TO PIM
BLOCK RESET
0−16
TERMS
I/O MACROCELL
I/O CELL
FROM PTM
0
1
O
D/T/L Q
R
P
FROM PTM
1O
C7
FEEDBACK TO PIM
BURIED MACROCELL
0
ASYNCHRONOUS
PRODUCT
0−16
TERMS
PRODUCT
C1
4
0
1
2
3Q
4
C24
C0C1C24
C25
C25
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)
BLOCK PRESET
ASYNCHRONOUS
FAST
SLOW
C26
SLEW
0
1
0
1
0
1
0
1
OE0 OE1
0
1
2
3
O
C12 C13
TO PIM
DQ
DQ
DQ
LE
INPUT PIN
0
1
2O
C10
FROM CLOCK
POLARITY MUXES 3
C11
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Document #: 38-03007 Rev. *B Page 7 of 63
Clocking
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an
asynchronous product term clock PTCLK. Each input
macrocell has access to all four synchronous clocks.
Dedicated Inputs/Clocks
Five pin s on each memb er of the Ultra37 000 family are desig-
nated as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3 illustrates the architecture for input pins. Four input
options are available for the user: combinatorial, registered,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
Figure 4 illustrates the architecture for the input/clock pins.
Like the input pins, input/clock pins can be combinatorial,
registered, double-registered, or latched. In addition, these
pins feed the clocking structures throughout the device. The
clock path at the input has user-configurable polarity.
Produ ct Term Clocking
In addition to the four synchronous clocks, the Ultra37000
family also has a product term clock for asynchronous
clocking. Each logic block has an independent product term
clock which is available to all 16 macrocells. Each product term
clock also supports user configurable polarity selection.
Timing Model
One of t he mos t impo rtan t feature s of the Ul tra3 7000 fa mily is
the simplicity of its timing. All delays are worst case and
system performance is unaffected by the features used. Figure
5 illustrates the true timing model for the 167-MHz devices in
high speed mode. For combinatorial paths, any input to any
output incurs a 6.5-ns worst-case delay regardless of the
amoun t of logic us ed. For synch ronous syst ems, the inp ut set-
up tim e to the ou tput mac rocells for a ny input is 3.5 ns and the
clock to output time is also 4.0 ns. These measurements are
for any output and synchronous clock, regardless of the logic
used.
The Ultra3 700 0 featu r es:
• No fanout delays
• No expander delays
• No dedicated vs. I/O pin delays
• No additional delay through PIM
• No penalty for using 0–16 product terms
• No added delay for steering product terms
• No added delay for sharing product terms
• No routing delays
• No output bypass delays
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
JTAG and PCI Standards
PCI Compliance
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except
for the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37000 family’s simple and predictable
timing model ensures compliance with the PCI AC specifica-
tions independent of the design.
Figure 4. Input/Clock Macrocell
0
1
2
3
O
C10C11
TO PIM
DQ
DQ
DQ
LE
INPUT/CLOCK PIN
0
1
2O
FROM CLOCK
CLOCK PINS
0
1O
C12
TO CLOCK MUX ON
ALL INPUT MACROCELLS
TO CLOCK MUX
IN EACH
3
0
1
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
POLARITY INPUT
LOGIC BLOCK
C8 C9
C13, C14, C15 OR C16
O
Figure 5. Timing Model for CY37128
COMBINATORIAL SIGNAL
REGISTERED SIGNAL
D,T,L O
CLOCK
INPUT
INPUT
OUTPUT
OUTPUT
tS = 3.5 ns tCO = 4.5 ns
tPD = 6.5 ns
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 8 of 63
IEEE 1149.1-compliant JTAG
The Ultra37 000 fami ly has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR.
Boundary Scan
The Ultra37000 family supports Bypass, Sample/Preload,
Extest, Idcode, and Usercode boundary scan instructions. The
JTAG interface is shown in Figure 6.
In-System Repro gramm ing (ISR)
In-System Reprogramming is the comb ination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Ultra37000 family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
Development Software Support
Warp
W arp is a state-of-the-art compiler and complete CPLD design
tool. For design entry , Warp provides an IEEE-STD-1076/1164
VHDL tex t editor, an IEEE-STD-1 364 Verilog te xt editor, and a
graphical finite state machine editor. It provides optimized
synthesis and fitting by replacing basic circuits with ones pre-
optimized for the target device, by implementing logic in
unused memory and by perfe ct communication betwee n fitting
and synthesis. To facilitate design and debugging, Warp
provides graphical timing simulation and analysis.
Warp Professional™
Warp Professional contains several additional features. It
provides an extra method of design entry with its graphical
block diagram editor. It allows up to 5 ms timing simulation
instead of only 2 ms. It allows comp arison of waveforms before
and after desig n changes.
Warp Enterprise™
Warp Enterprise provides even more features. It provides
unlimited timing simulation and source-level behavioral
simul ation a s well as a debug ger. It has the abili ty to ge nerate
graphical HDL blocks from HDL text. It can even generate
testbenches.
Warp is available for PC and UNIX platforms. Some features
are no t avai lable in th e UNIX ve rsio n. For f urther info rmat ion
see the Warp for PC, War p for UNIX, Warp Professional and
Warp Enterprise data sheets on Cypress’s web site
(www.cypress.com).
Third-Party Software
Although Warp is a complete CPLD development tool on its
own, it interfaces with nearly every third party EDA tool. All
major third-party software vendors provide support for the
Ultra3700 0 f am ily o f de vi ce s. Refe r to the third-party s oft ware
data sheet or contact your local sales office for a list of
currentl y sup port ed third -p a r ty ve ndo rs.
Programming
There are four programming options available for Ultra37000
devices. The first method is to use a PC with the 37000
UltraISR programming cable and software. With this method,
the ISR pins of the Ultra37000 devices are routed to a
connector at the edge of the printed circuit board. The 37000
UltraISR programming cable is then connected between the
parallel port of the PC and this connector. A simple configu-
ration file instructs the ISR software of the programming
oper ations to be performed on each of the Ultra 37000 device s
in the s ystem. The ISR software th en automa tically co mpletes
all of the necessary data manipulations required to accomplish
the programming, reading, verifying, and other ISR functions.
For more information on the Cypress ISR Interface, see the
ISR Programming Kit data sheet (CY3700i).
The second method for programming Ultra37000 devices is on
automatic test equipment (ATE). This is accomplished through
a file cre ated by the ISR software. Chec k the Cypres s website
for the latest ISR software download information.
The third programming option for Ultra37000 devices is to
utilize the embedded controller or processor that already
exis ts in the s ystem. T he Ultra 37000 I SR softwa re assi sts in
this method by converting the device JEDEC maps into the
ISR se rial s tream that c ont ains the ISR ins tructi on inf ormati on
and the addresses and data of locations to be programmed.
The embedded controller then simply directs this ISR stream
to the chain of Ultra37000 devices to complete the desired
reconfiguring or diagnostic operations. Contact your local
sales office for information on availability of this option.
The fourth method for programming Ultra37000 devices is to
use the same programmer that is currently being used to
program FLASH370i devices.
For all pinout, electrical, and timing requirements, refer to
device data sheets. For ISR cable an d software specifications,
refer to the UltraISR kit data sheet (CY3700i).
Third-Party Programmers
As with development software, Cypress support is available
on a w ide va riety of t hird-pa rty pr ogramme rs. A ll maj or th ird-
party programmers (including BP Micro, Data I/O, and SMS)
support the Ultra37000 family.
Figure 6. JTAG Interface
Instruction Register
Boundary Scan
idcode
Usercode
ISR Prog.
Bypass Reg.
Data Registers
JTAG
TAP
CONTROLLER
TDO
TDI
TMS
TCK
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 9 of 63
Logic Block Diagrams
CY37032/CY37032V
LOGIC
BLOCK
B
LOGIC
BLOCK
A
36
16
36
16
Input Clock/
Input
16 I/Os 16 I/Os
I/O0−I/O15 I/O16−I/O31
4
4
4
16
16
TDI
TCK
TMS TDO
JTAG Tap
Controller
1
PIM
JTAGEN
LOGIC
BLOCK
D
LOGIC
BLOCK
C
LOGIC
BLOCK
A
LOGIC
BLOCK
B
36
16
36
16
36
16
36
16
Input
Clock/
Input
16 I/Os
16 I/Os
16 I/Os
16 I/Os
I/O0-I/O15
I/O16-I/O31
I/O48-I/O63
I/O32-I/O47
4
4
4
32
32
TDI
TCK
TMS TDO
JTAG Tap
Controller
1
PIM
CY37064/CY37064V (100-Lead TQFP)
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 10 of 63
Logic Block Diagrams (continued)
TDI
TCK
TMS TDO
JTAG Tap
Controller
CY37128/CY37128V (160-lead TQFP)
PIM
INPUT
MACROCELL
CLOCK
INPUTS
4 4
36
16 16
36
LOGIC
BLOCK 36
16 16
36
16 I/Os
36 36
36
16 16
36
16 16
64 64
41 INPUT/CLOCK
MACROCELLS
I/O0–I/O15 A
INPUTS
LOGIC
BLOCK
C
LOGIC
BLOCK
B
LOGIC
BLOCK
D
LOGIC
BLOCK
H
LOGIC
BLOCK
G
LOGIC
BLOCK
F
LOGIC
BLOCK
E
I/O16–I/O31
I/O32–I/O47
I/O28–I/O63
I/O112–I/O127
I/O96–I/O111
I/O80–I/O95
I/O64–I/O79
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
JTAGEN
LOGIC
BLOCK
H
LOGIC
BLOCK
L
LOGIC
BLOCK
I
LOGIC
BLOCK
J
LOGIC
BLOCK
K
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
G
LOGIC
BLOCK
F
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
PIM
Input Clock/
Input
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
10 I/Os
I/O
0
–I/O
9
I/O
10
–I/O
19
I/O
20
–I/O
29
I/O
30
–I/O
39
I/O
40
–I/O
49
I/O
50
–I/O
59
I/O
110
–I/O
119
I/O
100
–I/O
109
I/O
90
–I/O
99
I/O
80
–I/O
89
I/O
70
–I/O
79
I/O
60
–I/O
69
4
4
4
6060
TDI
TCK
TMS TDO
JTAG Tap
Controller
1
CY37192 /CY371 92V (160 -lead TQFP)
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 11 of 63
Logic Block Diagrams (continued)
CY37256/CY37256V (256-lead BGA)
LOGIC
BLOCK
G
LOGIC
BLOCK
H
LOGIC
BLOCK
I
LOGIC
BLOCK
J
LOGIC
BLOCK
L
LOGIC
BLOCK
P
LOGIC
BLOCK
M
LOGIC
BLOCK
N
LOGIC
BLOCK
O
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
K
LOGIC
BLOCK
F
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
PIM
Input Clock/
Input
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O0−I/O11
I/O12−I/O23
I/O24−I/O35
I/O36−I/O47
I/O48−I/O59
I/O60−I/O71
I/O72−I/O83
I/O84−I/O95
I/O180−I/O191
I/O168−I/O179
I/O156−I/O167
I/O144−I/O155
I/O132−I/O143
I/O120−I/O131
I/O108−I/O119
I/O96−I/O107
4
4
4
96
96
TDI
TCK
TMS TDO
JTAG Tap
Controller
1
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 12 of 63
Logic Block Diagrams (continued)
CY37384/CY37384V (256-Lead BGA)
LOGIC
BLOCK
AH
LOGIC
BLOCK
AI
LOGIC
BLOCK
BD
LOGIC
BLOCK
BE
LOGIC
BLOCK
BG
LOGIC
BLOCK
BL
LOGIC
BLOCK
BI
LOGIC
BLOCK
BJ
LOGIC
BLOCK
BK
LOGIC
BLOCK
AA
LOGIC
BLOCK
AB
LOGIC
BLOCK
AC
LOGIC
BLOCK
AD
LOGIC
BLOCK
AF
LOGIC
BLOCK
BF
LOGIC
BLOCK
AG
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
PIM
Input Clock/
Input
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O0−I/O11
I/O12−I/O23
I/O24−I/O35
I/O48−I/O59
I/O60−I/O71
I/O72−I/O83
I/O168−I/O191
I/O156−I/O179
I/O144−I/O167
I/O120−I/O143
I/O108−I/O131
4
4
4
96
96
TDI
TCK
TMS TDO
JTAG Tap
Controller
1
LOGIC
BLOCK
AJ
LOGIC
BLOCK
BC
16
16 12 I/Os
I/O96−I/O119
LOGIC
BLOCK
AK
LOGIC
BLOCK
BB
16
16
12 I/Os
I/O84−I/O95
LOGIC
BLOCK
AL
LOGIC
BLOCK
BA
16
16 12 I/Os
I/O96−I/O107
LOGIC
BLOCK
AE
LOGIC
BLOCK
BH
16
16
12 I/Os
12 I/Os
I/O36−I/O47
I/O132−I/O155
36
36
36
36
36
36
36
36
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 13 of 63
Logic Block Diagrams (continued)
CY37512/CY37512V (352-Lead BGA)
LOGIC
BLOCK
AG
LOGIC
BLOCK
AH
LOGIC
BLOCK
BI
LOGIC
BLOCK
BJ
LOGIC
BLOCK
BL
LOGIC
BLOCK
BP
LOGIC
BLOCK
BM
LOGIC
BLOCK
BN
LOGIC
BLOCK
BO
LOGIC
BLOCK
AA
LOGIC
BLOCK
AB
LOGIC
BLOCK
AC
LOGIC
BLOCK
AD
LOGIC
BLOCK
AE
LOGIC
BLOCK
BK
LOGIC
BLOCK
AF
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
36
36
16
36
16
36
16
36
16
36
16
36
16
36
16
Input Clock/ Input
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
0
−
I/O
11
I/O
12
−
I/O
23
I/O
24
−
I/O
35
I/O
36
−
I/O
47
I/O
48
−
I/O
59
I/O
60
−
I/O
71
I/O
72
−
I/O
83
I/O
84
−
I/O
95
I/O
252
−
I/O
263
I/O
240
−
I/O
251
I/O
228
−
I/O
239
I/O
216
−
I/O
227
I/O
204
−
I/O
215
4
4
4
TDI
TCK
TMS TDO
JTAG Tap
Controller
1
PIM
16
36
36
16
LOGIC
BLOCK
AI
LOGIC
BLOCK
BH
12 I/Os
I/O
96
−
I/O
107
16
36
36
16
LOGIC
BLOCK
AJ
LOGIC
BLOCK
BG
12 I/Os
12 I/Os
I/O
108
−
I/O
119
I/O
192
−
I/O
203
16
36
36
16
LOGIC
BLOCK
AK
LOGIC
BLOCK
BF
12 I/Os
I/O
120
−
I/O
131
16
36
36
16
LOGIC
BLOCK
AL
LOGIC
BLOCK
BE
12 I/OsI/O
180
−
I/O
191
16
36
36
16
LOGIC
BLOCK
AM
LOGIC
BLOCK
BD
12 I/OsI/O
168
−
I/O
179
16
36
36
16
LOGIC
BLOCK
AN
LOGIC
BLOCK
BC
12 I/OsI/O
156
−
I/O
167
16
36
36
16
LOGIC
BLOCK
AO
LOGIC
BLOCK
BB
12 I/OsI/O
144
−
I/O
155
16
36
36
16
LOGIC
BLOCK
AP
LOGIC
BLOCK
BA
12 I/OsI/O
132
−
I/O
143
16
132132
16
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 14 of 63
5.0V Device Characteristics
Maximum Ratings
(Abov e wh ic h th e us eful life ma y be imp aire d. For user gui de-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage.............................................4.5 to 5.5V
Current into Outputs ....................................................16 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range[2]
Range Ambient
Temperature[2] Junction
Temperature Output
Condition VCC VCCO
Commercial 0°C to +70°C 0°C to +90°C 5V 5V ± 0.25V 5V ± 0.25V
3.3V 5V ± 0.25V 3.3V ± 0.3V
Industrial –40°C to +85°C –40°C to +105°C 5V 5V ± 0.5V 5V ± 0.5V
3.3V 5V ± 0.5V 3.3V ± 0.3V
Military[3] –55°C to +125°C –55°C to +130°C 5V 5V ± 0.5V 5V ± 0.5V
3.3V 5V ± 0.5V 3.3V ± 0.3V
5.0V Device Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ. Max. Unit
VOH Output HIGH Voltage VCC = Min. IOH = –3.2 mA (Com’l/Ind)[4] 2.4 V
IOH = –2.0 mA (Mil)[4] 2.4 V
VOHZ Output HIGH Voltage with
Output Disabled[5] VCC = Max. IOH = 0 µA (Com’l)[6] 4.2 V
IOH = 0 µA (Ind/Mil)[6] 4.5 V
IOH = –100 µA (Com’l)[6] 3.6 V
IOH = –150 µA (Ind/Mil)[6] 3.6 V
VOL Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind)[4] 0.5 V
IOL = 12 mA (Mil)[4] 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs[7] 2.0 VCCmax V
VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs[7] –0.5 0.8 V
IIX Input Load Current VI = GND OR VCC, Bus-Hold Disabl ed –10 10 µA
IOZ Output Leakage Current VO = GND or VCC, Output Disabled, Bus-Hold Disabled –50 50 µA
IOS Output Short Circuit Current[8, 5] VCC = Max., VOUT = 0.5V –30 –160 mA
IBHL Input Bus-Hold LOW
Sustaining Curren t VCC = Min., VIL = 0.8V +75 µA
IBHH Input Bus-Hold HIGH
Sustaining Curren t VCC = Min., VIH = 2.0V –75 µA
IBHLO Input Bus-Hold LOW
Overdrive C urrent VCC = Max. +500 µA
IBHHO Input Bus-Hold HIGH
Overdrive C urrent VCC = Max. –500 µA
Notes:
2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the
Ultra37000 Family devices, please refer to the Application Note titled “An Introduction to In System Reprogramming with the Ultra37000.”
3. TA is the “Instant On” case temperature.
4. IOH = –2 mA, IOL = 2 mA for TDO.
5. Tested initially and after any design or process changes that may affect these parameters.
6. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled
during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 15 of 63
3.3V Device Characteristics
Maximum Ratings
(Abov e wh ic h th e us eful life ma y be imp aire d. For user gui de-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage.............................................3.0 to 3.6V
Current into Outputs ......................................................8 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Inductance[5]
Parameter Description Test
Conditions
44-
Lead
TQFP
44-
Lead
PLCC
44-
Lead
CLCC
84-
Lead
PLCC
84-
Lead
CLCC
100-
Lead
TQFP
160-
Lead
TQFP
208-
Lead
PQFP Unit
LMaximum Pin
Inductance VIN = 5.0V
at f = 1 MHz 252858911 nH
Capacitance[5]
Parameter Description Test Conditi ons Max. Unit
CI/O Input/Output Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C10 pF
CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C12 pF
CDP Dual Fun cti on Pins [9] VIN = 5.0V at f = 1 MHz at TA = 25°C16 pF
Endurance Characteristics[5]
Parameter Description Test Conditions Min. Typ. Unit
NMinimum Reprogramming Cycles Normal Programming Conditions[2] 1,000 10,000 Cycles
Operating Range[2]
Range Ambient Temperature[2] Junction Temperature VCC[10]
Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.3V
Industrial –40°C to +85°C –40°C to +105°C 3.3V ± 0.3V
Military[3] –55°C to +125°C –55°C to +130°C 3.3V ± 0.3V
3.3V Device Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min. IOH = –4 mA (Com’l)[4] 2.4 V
IOH = –3 mA (Mil)[4]
VOL Output LOW Voltage VCC = Min. IOL = 8 mA (Com’l)[4] 0.5 V
IOL = 6 mA (Mil)[4]
VIH Input HIGH Voltage Guaran teed Input Log ical HIGH V o ltage for
all Inputs[7] 2.0 5.5 V
VIL Input LOW Voltage Guaran tee d In pu t Lo gic al LO W Voltage f or
all Inputs[7] –0.5 0.8 V
IIX Input Load Current VI = GND OR VCC, Bus-Hold Disabled –10 10 µA
IOZ Output Leakage Current VO = GND or VCC, Output Disabled, Bus-
Hold Disabled –50 50 µA
IOS Output Short Circuit Current[8, 5] VCC = Max., VOUT = 0.5V –30 –160 mA
IBHL Input Bus-Hold LOW Sustaining
Current VCC = Min., VIL = 0.8V +75 µA
Notes:
9. Dual pins are I/O with JTAG pins.
10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: VCC is 3.3V± 0.16V.
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 16 of 63
IBHH Input Bus-Hold HIGH Sustaining
Current VCC = Min., VIH = 2.0V –75 µA
IBHLO Input Bus-Hold LOW Overdrive
Current VCC = Max. +500 µA
IBHHO Input Bus-Hold HIGH Overdrive
Current VCC = Max. –500 µA
Inductance[5]
Parameter Description Test
Conditions
44-
Lead
TQFP
44-
Lead
PLCC
44-
Lead
CLCC
84-
Lead
PLCC
84-
Lead
CLCC
100-
Lead
TQFP
160-
Lead
TQFP
208-
Lead
PQFP Unit
LMaximum Pin
Inductance VIN = 3.3V
at f = 1 MHz 252858911 nH
Capacitance[5]
Parameter Description Test Conditi ons Max. Unit
CI/O Input/Output Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C 8 pF
CCLK Clock Signal Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C12 pF
CDP Dual Fun cti ona l Pins[9] VIN = 3.3V at f = 1 MHz at TA = 25°C16 pF
Endurance Characteristics[5]
Parameter Description Test Conditions Min. Typ. Unit
NMinimum Reprogramming Cycles Normal Programming Conditions[2] 1,000 10,000 Cycles
3.3V Device Electrical Characteristics Over the Operating Range (continued)
Parameter Description Test Conditions Min. Max. Unit
AC Characterist ics
5.0V AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<2 ns
OUTPUT
238Ω(COM’L)
319Ω(MIL)
170Ω(COM’L)
236Ω(MIL)
99Ω(COM’L)
136Ω(MIL)
Equivalent to: THÉVENIN EQUIVALENT
2.08V (COM'L)
2.13V (MIL)
238Ω(COM'L)
319Ω(MIL)
170Ω(COM'L)
236Ω(MIL) <2 ns
(c)
5 OR 35 pF
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 17 of 63
3.3V AC Test Loads and Waveforms
AC Characterist ics
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<2 ns
OUTPUT
295Ω(COM’L)
393Ω(MIL)
340Ω(COM’L)
453Ω(MIL)
Equivalent to: THÉVENIN EQUIVALENT
1.77V (COM'L)
1.77V (MIL)
295Ω(COM'L)
393Ω(MIL)
340Ω(COM'L)
453Ω(MIL) <2 ns
(c)
270Ω(MIL)
158Ω(COM’L)
5 OR 35 pF
Parameter[11] VXOutput Waveform—Measurement Level
tER(–) 1.5V
tER(+) 2.6V
tEA(+) 1.5V
tEA(–) Vthe
(d) Test Waveforms
VOH VX
0.5V
VOL VX
0.5V
VXVO
H
0.5V
VXVOL
0.5V
Switching Characteristics Over the Operating Range[12]
Parameter Description Unit
Combinatorial Mode Parameters
tPD[13, 14, 15] Input to Combinatorial Output ns
tPDL[13, 14, 15] Input to Output Through Transparent Input or Output Latch ns
tPDLL[13, 14, 15] Input to Output Through Transparent Input and Output Latches ns
tEA[13 , 14, 15] Inp ut to Output Enab le ns
tER[11, 13] Input to Output Disa ble ns
Input Register Parameters
tWL Clock or Latch Enable Input LOW Ti me[8] ns
Notes:
11. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13. Logic Blocks operating in Low-Power Mode, add tLP to this spec.
14. Outputs using Slow Output Slew Rate, add tSLEW to this spec.
15. When VCCO = 3.3V, add t3.3IO to this spec.
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 18 of 63
tWH Clock or Latch Enable Input HIGH Time[8] ns
tIS Input Register or Latch Set-up Time ns
tIH Input Register or Latch Hold Time ns
tICO[13, 14, 15] Input Register Clock or Latch Enable to Combinatorial Output ns
tICOL[ 13, 14, 15] Input Register Clock or Latch Enable to Output Through Transparent Output Latch ns
Synchronous Clocking Parameters
tCO[14, 15] Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output ns
tS[13] Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable ns
tHRegister or Lat ch Data Hold Time ns
tCO2[13, 14, 15] O utput Synchron ous Clock (C LK0, CLK1, CLK2, or CLK3) or Latch Enable to C ombinat orial Output
Delay (Through Logic Array) ns
tSCS[13] Output Synchro nous Cloc k (CLK0, CLK 1, CL K2, or CLK 3) or Latch Ena ble to O utpu t Sy nc hro nou s
Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array) ns
tSL[13] Set-Up Time from Inp ut T hrough Transpar en t La tch to Ou tpu t R eg ist er Sy nc hron ou s C l ock (CL K0
CLK1, CLK2, or CLK3) or Latch Enable ns
tHL Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0,
CLK1, CLK2, or CLK3) or Latch Enable ns
Product Term Clocking Parameters
tCOPT[13, 14, 15] Product Term Clock or Latch Enable (PTCLK) to Output ns
tSPT Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) ns
tHPT Register or Latch Data Hold Time ns
tISPT[13] Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK) ns
tIHPT Buried Register Used as an Input Register or Latch Data Hold Time ns
tCO2PT[13, 14, 15] Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) ns
Pipelined Mode Parameters
tICS[13] Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to O utp ut R e gis ter S ync hro nou s
Clock (CLK0, CLK1, CLK2, or CLK3)ns
Operating Frequency Parameters
fMAX1 Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO)[5] MHz
fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH),
1/(tS+t
H), or 1/tCO)[5] MHz
fMAX3 Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)[5] MHz
fMAX4 Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH),
or 1/tSCS)[5] MHz
Reset/Preset Parameters
tRW Async hronous Re se t Width[5] ns
tRR[13] Asynchronous Reset Recovery Time[5] ns
tRO[13, 14, 15] Asynchronous Reset to Output ns
tPW Asynchro nou s Pres et Wid t h[5] ns
tPR[13] Asynchronous Preset Recovery Time[5] ns
tPO[13, 14, 15 ] Asynchronous Preset to Output ns
User Option Parameters
tLP Low Power Adder ns
tSLEW Slow Output Slew Rate Adder ns
t3.3IO 3.3V I/O Mode Timing Adder[5] ns
Switching Characteristics Over the Operating Range[12] (continued)
Parameter Description Unit
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 19 of 63
JTAG Timing Parameters
tS JTAG Set-up Time from TDI and TMS to TCK[5] ns
tH JTAG Hold Time on TDI and TMS[5] ns
tCO JTAG Falling Edge of TCK to TDO[5] ns
fJTAG Maximum JTAG Tap Controller Frequency[5] ns
Switching Characteristics Over the Operating Range[12] (continued)
Parameter Description Unit
Switching Characteristics Over the Op erating Range [12]
Parameter
200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Combinatorial Mode Parameters
tPD[13, 14, 15] 6 6.5 7.5 8.5 10 12 15 20 ns
tPDL[13, 14, 15] 11 12.5 14.5 16 16.5 17 19 22 ns
tPDLL[13, 14, 15] 12 13.5 15.5 17 17.5 18 20 24 ns
tEA[13 , 14, 15] 8 8.5 11 13 14 16 19 24 ns
tER[11, 13] 8 8.5 11 13 14 16 19 24 ns
Input Register Parameters
tWL 2.5 2.5 2.5 2.5 3 3 4 5 ns
tWH 2.5 2.5 2.5 2.5 3 3 4 5 ns
tIS 2222 2 2.5 3 4ns
tIH 2222 2 2.5 3 4ns
tICO[13, 14, 15] 11 11 11 12.5 12.5 16 19 24 ns
tICOL[ 13, 14, 15] 12 12 12 14 16 18 21 26 ns
Synchronous Clocking Parameters
tCO [14, 15] 444.56 6.5
[16] 6.5[17] 8[18] 10 ns
tS[13] 44555.5
[16] 6[17] 8[18] 10 ns
tH0000 0 0 0 0ns
tCO2[13, 14, 15] 9.5 10 11 12 14 16 19 24 ns
tSCS[13] 566.57 8
[16] 10 12 15 ns
tSL[13] 7.5 7.5 8.5 9 10 12 15 15 ns
tHL 0000 0 0 0 0ns
Product Term Clocking Parameters
tCOPT[13, 14, 15] 7101013 13 13 1520ns
tSPT 2.5 2.5 2.5 3 5 5.5 6 7 ns
tHPT 2.5 2.5 2.5 3 5 5.5 6 7 ns
tISPT[13] 00000000ns
tIHPT 6 6.5 6.5 7.5 9 11 14 19 ns
tCO2PT[13, 14,
15] 12 14 15 19 19 21 24 30 ns
Pipeli ned Mo de Parame ters
tICS[13] 56678
[16] 10 12 15 ns
Notes:
16. The following values correspond to the CY37512 and CY37384 devices: tCO = 5 ns, tS = 6.5 ns, tSCS = 8.5 ns, tICS = 8.5 ns, fMAX1 = 118 MHz.
17. The following values correspond to the CY37192V and CY37256V devices: tCO = 6 ns, tS = 7 ns, fMAX2 = 143 MHz, fMAX3 = 77 MHz, and fMAX4 = 100 MHz;
and for the CY37512 devices: tS = 7 ns.
18. The following values correspond to the CY37512V and CY37384V devices: tCO = 6.5 ns, tS = 9.5 ns, and fMAX2 = 105 MHz.
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 20 of 63
Operating Frequency Parameters
fMAX1 200 167 154 143 125[16] 100 83 66 MHz
fMAX2 200 200 200 167 154 153[17] 125[18] 100 MHz
fMAX3 125 125 105 91 83 80[17] 62.5 50 MHz
fMAX4 167 167 154 125 118 100 83 66 MHz
Reset/Preset Parameters
tRW 8888 10 12 15 20ns
tRR[13] 10 10 10 10 12 14 17 22 ns
tRO[13, 14, 15] 12 13 13 14 15 18 21 26 ns
tPW 8888 10 12 15 20ns
tPR[13] 10 10 10 10 12 14 17 22 ns
tPO[13, 14, 15 ] 12 13 13 14 15 18 21 26 ns
User Option Parameters
tLP 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns
tSLEW 3333 3 3 33ns
t3.3IO[19] 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns
JTAG Timing Parameters
tS JTAG 00000000ns
tH JTAG 20 20 20 20 20 20 20 20 ns
tCO JTAG 20 20 20 20 20 20 20 20 ns
fJTAG 20 20 20 20 20 20 20 20 MHz
Switching Characteristics Over the Op erating Range [12] (continued)
Parameter
200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Switching Waveforms
Note:
19. Only applicable to the 5V devices.
tPD
INPUT
COMBINATORIAL
OUTPUT
Combinatorial Output
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Document #: 38-03007 Rev. *B Page 21 of 63
Switching Waveforms (continued)
Registered Output with Synchronous Clocking
tS
INPUT
SYNCHRONOUS
tCO
REGISTERED
OUTPUT
tH
SYNCHRONOUS
tWL
tWH
tCO2
REGISTERED
OUTPUT
CLOCK
CLOCK
Registered Output with Product Term Clocking
tSPT
INPUT
PROD UCT TER M
tCOPT
REGISTERED
OUTPUT
tHPT
CLOCK
Input Going Through the Array
Registered Output with Product Term Clocking
tISPT
INPUT
PROD UCT TER M
tCO2PT
REGISTERED
OUTPUT
tIHPT
CLOCK
Input Coming From Adjacent Buried Register
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Document #: 38-03007 Rev. *B Page 22 of 63
Switching Waveforms (continued)
Latched Output
tSL
INPUT
LATCH ENABLE
tCO
LATCHED
OUTPUT
tHL
tPDL
Registered Input
tIS
REGISTERED
INPUT
INPUT REGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tIH
CLOCK
tWL
tWH
Clock to Clock
INPUT REGISTER
CLOCK
OUTPUT
REGISTER CLOCK
tSCS
tICS
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Document #: 38-03007 Rev. *B Page 23 of 63
Switching Waveforms (continued)
Latched Input
tIS
LATCHED INPUT
LATCH ENABLE
tICO
COMBINATORIAL
OUTPUT
tIH
tPDL
tWL
tWH
LATCH ENABLE
Latched Input and Output
tICS
LATCHED INPUT
OUTPUT LATCH
ENABLE
LATCHED
OUTPUT
tPDLL
LATCH ENABLE
tWL
tWH
tICOL
INPUT LATCH
ENABLE
tSL tHL
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Document #: 38-03007 Rev. *B Page 24 of 63
Switching Waveforms (continued)
Asynchronous Reset
INPUT
tRO
REGISTERED
OUTPUT
CLOCK
tRR
tRW
Asynchronous Preset
INPUT
tPO
REGISTERED
OUTPUT
CLOCK
tPR
tPW
Output Enable/Disable
INPUT
tER
OUTPUTS
tEA
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Document #: 38-03007 Rev. *B Page 25 of 63
Power Consumption
Typical 5.0V Power Consumption
CY37032
CY37064
0
10
20
30
40
50
60
0 50 100 150 200 250
Frequency (M Hz)
Icc (mA)
High S pee d
Low Power
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
0
10
20
30
40
50
60
70
80
90
0 20 40 60 80 100 120 140 160 180
Frequency (MHz)
Icc (mA)
Low Power
High Speed
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Document #: 38-03007 Rev. *B Page 26 of 63
CY37128
CY37192
Typical 5.0V Power Consumption (continued)
0
20
40
60
80
100
120
140
160
0 20 40 60 80 100 120 140 160 180
Frequency (MHz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
0
50
100
150
200
250
300
0 20 40 60 80 100 120 140 160 180
Frequency (MHz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
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Document #: 38-03007 Rev. *B Page 27 of 63
CY37256
CY37384
Typical 5.0V Power Consumption (continued)
0
50
100
150
200
250
300
0 20 40 60 80 100 120 140 160 180
Frequency (MHz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
0
50
100
150
200
250
300
350
400
450
500
0 20406080100120140160
Frequency (MHz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 28 of 63
CY37512
Typical 5.0V Power Consumption (continued)
0
100
200
300
400
500
600
0 20 40 60 80 100 120 140 160
Frequency (MHz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
Typical 3.3V Power Consumption
CY37032V
0
5
10
15
20
25
30
0 20 40 60 80 100 120 140 160
Frequency (M Hz)
Icc (mA)
Low Powe r
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 29 of 63
CY37064V
CY37128V
Typical 3.3V Power Consumption (continued)
0
5
10
15
20
25
30
35
40
45
0 20406080100120140
Frequen cy (M H z)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, T A = Room Temperature
0
10
20
30
40
50
60
70
80
0 20 40 60 80 100 120 140
Frequency (M Hz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
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Document #: 38-03007 Rev. *B Page 30 of 63
CY37192V
CY37256V
Typical 3.3V Power Consumption (continued)
0
20
40
60
80
100
120
0 20 40 60 80 100 120
Frequency (M Hz)
Icc (mA)
Low Pow er
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
0
20
40
60
80
100
120
140
0 20 40 60 80 100 120
Frequency (M Hz)
Icc (mA)
Low P ower
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
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Document #: 38-03007 Rev. *B Page 31 of 63
CY37384V
CY37512V
Typical 3.3V Power Consumption (continued)
0
20
40
60
80
100
120
140
160
180
200
0 102030405060708090
Freq uency (M H z)
Icc (mA)
Low Pow er
H igh S peed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
0
50
100
150
200
250
0 102030405060708090
Frequency (M Hz)
Icc (mA)
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 32 of 63
Pin Configurations[20]
Note:
20. For 3.3V versions (Ultra37000V), VCCO = VCC.
44-pin TQFP (A44)
Top View
I/O2
GND
VCCO
I/O3
I/O4
I/O1
I/O0
I/O29
I/O30
I/O31
I/O28
I/O27/TDI
I/O26
I/O25
I/O24
CLK1/I4
GND
I3
CLK3/I2
I/O23
I/O22
I/O21
GND
I/O20
VCC
I/O18
I/O17
I/O16
I/O15
I/O14
I/O12
I/O5/TCK
I/O6
I/O7
CLK2/I0
GND
CLK0/I1
I/O8
I/O9
I/O10
I/O11
8
9
7
10
11
3
4
2
5
6
1
18 19 20 222113 14 15 171612
31
30
29
32
33
26
25
24
27
28
23
44 43 42 4041 39 38 37 3536 34
I/O13/TMS
I/O19 /TDO
JTAGEN
44-pin PLCC (J67) / CLCC (Y67)
Top View
I/O27/TDI
I/O26
I/O25
I/O24
CLK1/I4
GND
I3
CLK3/I2
I/O23
I/O22
I/O21
I/O5/TCK
I/O6
I/O7
CLK2/I0
JTAGEN
GND
CLK0/I1
I/O8
I/O9
I/O10
I/O11
GND
I/O20
I/O2
GND
VCCO
VCC
I/O3
I/O4
I/O1
I/O0
I/O29
I/O30
I/O31
I/O28
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
65 34 2
8
9
7
10
11
44
18
15
16
14
13
12
17 19 20 2221 23 24 2726 2825
31
30
29
32
33
34
39
37
38
36
35
43 42 4041
/TMS
/TDO
1
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 33 of 63
Note:
21. This pin is a N/C, but Cypress recommends that you connect it to VCC to ensure future compatibility.
Pin Configurations[20] (continued)
48-ball Fine-Pitch BGA (BA50)
Top View
12345678
AI/O
5
TCK VCC I/O3I/O1I/O31 I/O30 VCC I/O27
TDI
BV
CC I/O4I/O2I/O0I/O29 I/O28 I/O26 CLK1/ I4
CCLK
2/ I0I/O7I/O6GND GND I/O25 I/O24 I3
DJTAG
EN I/O8I/O9GND GND I/O22 I/O23 CLK3/ I2
ECLK
0/ I1I/O12 I/O11 I/O10 I/O16 I/O20 I/O21 VCC
FI/O
13
TMS VCC I/O14 I/O15 I/O17 I/O18 VCC I/O19
TDO
I/O
I/O14
I/O15 I/O 48
Top View
84-lead PLCC (J83) / CLCC (Y84)
98 67 5
13
14
12
11
4948
58
59
60
23
24
26
25
27
15
16
4746
43
28
33
20
21
19
18
17
22
34 3736 38 4241 43
40
66
65
63
64
62
61
67
68
69
74
72
73
71
70
84 8182 80 79
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O 55
I/O 54 /TDI
I/O 53
I/O 52
I/O 51
GND
I/O 49
CLK3/I4
VCCO
CLK2/I3
I/O 45
I/O 44
GND
I/O
I/O 8
I/O 9
I/O
10 /TCK
I/O11
I/O12
I/O13
CLK0/I0
VCCO
CLK1/I1
I/O16
I/O17
I/O18
I/O19
I/O20
53525150
30
29
31
32
I/O
I/O
I/O
I/O
54
55
56
57 I/O 43
I/O 42
I/O 41
I/O 40
7778 76 75
I/O21
I/O22
I/O23
GND
I/O
I/O 50
I/O 47
I/O 46
GND
24
I/O25
/TMS
I/O27
I/O28
I/O29
I/O30
I/O31
VCCO
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
I2
7
6
5
4
3
2
1
VCCO
I/O0
VCC
63
I/O 62
61
60
59
58
57
56
JTAGEN
I/O26
/TDO
10
35 39 44 45
83
21
[2
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 34 of 63
Pin Configurations[20] (continued)
Top View
100-lead TQFP (A100)
100 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
4039
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84 TDI
NC
VCCO
I/O55
I/O54
I/O53
I/O52
CLK 3/I4
I/O50
I/O48
GND
NC
I/O47
I/O46
I/O49
GND
TMS
TCK
GND
I/O 8
I/O 9
I/O10
I/O11
I/O15
VCCO
GND
CLK1/I1
I/O16
I/O17
CLK0/I0
9091
I/O51
VCCO
CLK 2/I3
I/O14
N/C
I/O12
I/O13
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
GND
NC
GND
NC
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
VCCO
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 48 49 50
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
VCCO
VCC
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I2
NC
VCCO
TDO
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
2
1
VCCO
I/O 0
VCC
NC
63
I/O 62
61
60
59
58
57
56
VCCO
N/C
99
37 47
[21 ]
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 35 of 63
Pin Configurations[20] (continued)
100-ball Fine-Pitch BGA (BB100) for CY37064V
Top View
100-ball Fine-Pitch BGA (BB100) for CY37128V
Top View
12345678910
A NC NC I/O7I/O5I/O2I/O62 I/O60 I/O58 I/O57 I/O56
BI/O
9I/O8I/O6I/O4I/O1I/O63 VCC I/O59 I/O55 NC
CI/O
10 TCK VCC I/O3NC NC I/O61 VCC TDI I/O54
D I/O11 NC I/O12 I/O13 I/O0NC I/O51 I/O52 CLK3
/ I4
I/O53
EI/O
14 CLK0
/ I0
I/O15 NC GND GND I/O48 I/O49 CLK2
/ I3
I/O50
FI/O
17 NC NC I/O16 GND GND NC NC I2I/O47
GI/O
22 CLK1
/ I1
I/O21 I/O19 I/O18 I/O46 I/O45 I/O44 NC I/O43
HI/O
23 TMS VCC I/O20 NC I/O32 I/O42 VCC TDO I/O41
J NC I/O26 I/O28 NC I/O31 I/O33 I/O35 I/O37 I/O39 I/O40
KI/O
24 I/O25 I/O27 I/O29 I/O30 I/O34 I/O36 I/O38 NC NC
12345678910
A NC I/O9I/O8I/O6I/O3I/O76 I/O74 I/O72 I/O71 I/O70
B I/O11 I/O10 I/O7I/O5I/O2I/O77 VCC I/O73 I/O68 I/O69
CI/O
12 I/O13
TCK VCC I/O4I/O1I/O78 I/O75 VCC I/O67
TDI I/O66
DI/O
14 NC I/O15 I/O16 I/O0I/O79 I/O63 I/O64 CLK3
/ I4
I/O65
EI/O
17 CLK0
/ I0
I/O18 I/O19 GND GND I/O60 I/O61 CLK2
/ I3
I/O62
FI/O
22 JTAG
EN I/O21 I/O20 GND GND I/O59 I/O58 I2I/O57
GI/O
27 CLK1
/ I1
I/O26 I/O24 I/O23 I/O56 I/O55 I/O54 NC I/O53
HI/O
28 I/O33
TMS VCC I/O25 I/O39 I/O40 I/O52 VCC I/O47
TDO I/O51
JI/O
29 I/O32 I/O35 VCC I/O38 I/O41 I/O43 I/O45 I/O48 I/O50
KI/O
30 I/O31 I/O34 I/O36 I/O37 I/O42 I/O44 I/O46 I/O49 NC
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 36 of 63
Pin Configurations[20] (continued)
I/O77 124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
43
44
160
45
159
46
158
47
157
48
156
49
155
50
154
51
153
52
152
53
151
54
150
55
149
56
148
57
147
58
146
59
145
60
144
61
143
62
142
63
141
64
65
66
67
68
140
69
139
70
138
71
137
72
136
73
135
74
134
75
133
76
132
77
131
78
130
79
129
80
128
81
127
82
126
160-Lead TQFP (A160) / CQFP (U162)
125
84
83
42
GND
I/O16
I/O17
I/O18
I/O19
I/O20/TCK
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
GND
CLK0/I0
VCCO
GND
CLK1/I1
GND
GND
GND
GND
GND
VCCO
I/O48
I/O49
I/O50
I/O51
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I2
VCCO
VCC
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
I/O72
I/O73
I/O74
I/O75
I/O78
I/O79
VCCO
GND
I/O80
I/O81
I/O82
I/O83
I/O84
I/O85
I/O86
I/O87
GND
I/O88
I/O89
I/O90
I/O91
I/O92
I/O93
I/O94
I/O95
I/O96
I/O97
I/O98
I/O99
I/O100
I/O101
I/O102
I/O103
GND
GND
CLK2/I3
VCCO
CLK3/I4
I/O104
I/O105
I/O106
I/O107
I/O108/TDI
I/O109
I/O110
I/O111
VCCO
GND
GND
VCC
GND
I/O112
GND
VCCO
VCCO
I/O113
I/O114
I/O115
I/O116
I/O117
I/O118
I/O119
I/O120
I/O121
I/O122
I/O123
I/O124
I/O125
I/O126
I/O127
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
JTAGEN
I/O52/TMS
I/O76/TDO
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
41
for CY37128(V) and CY37256(V)
Top View
Ultra37000 CPLD Fami
ly
Document #: 38-03007 Rev. *B Page 37 of 63
Pin Configurations[20] (continued)
I/O72 124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
43
44
160
45
159
46
158
47
157
48
156
49
155
50
154
51
153
52
152
53
151
54
150
55
149
56
148
57
147
58
146
59
145
60
144
61
143
62
142
63
141
64
65
66
67
68
140
69
139
70
138
71
137
72
136
73
135
74
134
75
133
76
132
77
131
78
130
79
129
80
128
81
127
82
126
160-Lead TQFP (A160) for CY37192(V)
125
84
83
42
GND
NC
I/O16
I/O17
I/O18
TCK
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
GND
CLK0/I0
VCCO
GND
CLK1/I1
GND
GND
GND
GND
GND
VCCO
NC
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I2
VCCO
VCC
I/O60
I/O61
I/O62
I/O63
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
I/O73
I/O74
VCCO
GND
NC
I/O75
I/O76
I/O77
I/O78
I/O79
I/O80
I/O81
GND
I/O82
I/O83
I/O84
I/O85
I/O86
I/O87
I/O88
I/O89
I/O90
I/O91
I/O92
I/O93
I/O94
I/O95
I/O96
I/O97
GND
GND
CLK2/I3
VCCO
CLK3/I4
I/O98
I/O99
I/O100
I/O101
TDI
I/O102
I/O103
I/O104
VCCO
GND
GND
VCC
GND
NC
GND
VCCO
VCCO
I/O105
I/O106
I/O107
I/O108
I/O109
I/O110
I/O111
I/O112
I/O113
I/O114
I/O115
I/O116
I/O117
I/O118
I/O119
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
NC
TMS
TDO
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
41
Top View
Ultra37000 CPLD Fami
ly
Document #: 38-03007 Rev. *B Page 38 of 63
Pin Configurations[20] (continued)
I/O152
I/O154
I/O153
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
41
42
43
44
45
46
47
48
49
50
51
52
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
208
167
166
165
164
163
162
161
160
159
158
157
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
53
92
93
94
95
96
97
98
99
100
101
102
103
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
155
115
114
113
112
111
110
109
108
107
106
105
156
104
207
208-Lead PQFP (N208) / CQFP (U208)
Top View
I/O139
I/O138
I/O137
I/O136
I/O135
TDI
I/O134
I/O133
I/O132
I/O131
I/O130
GND
I/O129
I/O128
I/O127
I/O126
I/O125
I/O124
I/O123
I/O122
I/O121
I/O120
CLK3/
I4
VCC
GND
VCCO
GND
CLK2/
I3
I/O119
I/O118
I/O117
I/O116
I/O115
NC
I/O114
I/O113
I/O112
I/O111
I/O110
VCCO
GND
I/O109
I/O108
I/O107
I/O106
I/O105
I/O104
I/O103
I/O102
I/O101
I/O100
GND
I/O61
I/O62
I/O63
I/O64
TMS
I/O65
I/O66
I/O67
I/O68
I/O69
GND
I/O70
I/O71
I/O72
I/O73
I/O74
NC
I/O75
I/O76
I/O77
I/O78
I/O79
I2
VCC0
GND
VCC
I/O80
I/O81
I/O82
I/O83
I/O84
I/O85
I/O86
I/O87
I/O88
I/O89
GND
I/O90
I/O91
GND
I/O92
I/O93
I/O94
GND
TDO
I/O95
I/O96
I/O97
I/O98
I/O99
VCC0
I/O60
I/O21
I/O22
I/O23
I/O24
TCK
I/O25
I/O26
I/O27
I/O28
I/O29
GND
I/O30
I/O31
I/O32
I/O33
I/O34
NC
I/O35
I/O36
I/O37
I/O38
I/O39
CLK0/I0
VCCO
GND
NC
CLK1/I1
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
GND
I/O50
I/O20
I/O51
I/O52
I/O53
I/O54
NC
I/O55
I/O56
I/O57
I/O58
I/O59
VCC0
GND
VCC0
I/O19
I/O18
I/O17
I/O16
I/O15
NC
I/O14
I/O13
I/O12
I/O11
I/O10
GND
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC0
GND
VCC
NC
I/O159
I/O158
I/O157
I/O156
I/O155
NC
I/O151
I/O150
VCC
GND
I/O149
I/O148
I/O147
I/O146
I/O145
I/O144
I/O143
I/O142
I/O141
I/O140
NC
GND
Ultra37000 CPLD Fami
ly
Document #: 38-03007 Rev. *B Page 39 of 63
Pin Configurations[20] (continued)
256-Ball PBGA (BG256)
Top View
1234567891011121314151617181920
A GND I/O21 NC I/O16 I/O12 I/O9I/O7I/O4I/O0I/O190 I/O189 I/O186 I/O182 NC I/O178 I/O175 NC NC I/O169 I/O168 A
B I/O23 I/O20 I/O19 I/O18 I/O15 I/O11 I/O8I/O5I/O1I/O191 I/O187 I/O185 I/O181 NC NC I/O174 I/O171 I/O170 NC I/O166 B
C NC NC I/O22 NC I/O17 I/O14 I/O10 I/O6I/O2NC I/O188 I/O184 I/O180 I/O179 I/O176 I/O173 I/O172 I/O167 I/O165 I/O162 C
D I/O24 NC NC GND NC VCCO I/O13 GND I/O3NC VCC I/O183 GND I/O177 VCCO NC GND I/O164 TDI I/O160 D
E I/O27 I/O26 I/O25 NC I/O163 I/O161 I/O159 I/O156 E
F I/O30 TCK I/O28 VCCO VCCO I/O158 NC I/O154 F
G I/O33 I/O32 I/O31 I/O29 I/O157 I/O155 I/O153 I/O152 G
H I/O35 NC I/O34 GND GND GND GND GND GND GND GND I/O151 I/O150 I/O149 H
J I/O39 I/O38 I/O37 I/O36 GND GND GND GND GND GND I/O148 I/O147 I/O146 I/O145 J
K I/O42 I/O40 I/O41 VCC GND GND GND GND GND GND I/O144 CLK3/I4NC NC K
L I/O43 I/O44 I/O45 I/O46 GND GND GND GND GND GND VCC CLK2/I3I/O143 NC L
M I/O47 CLK0/I0CLK1/I1I/O48 GND GND GND GND GND GND I/O139 I/O140 I/O141 I/O142 M
N I/O49 I/O50 I/O51 GND GND GND GND GND GND GND GND I/O136 I/O137 I/O138 N
P I/O52 I/O53 I/O55 I/O58 I/O131 I/O133 I/O134 I/O135 P
R I/O54 I/O56 I/O59 VCCO VCCO I/O130 NC I/O132 R
T I/O57 I/O60 I/O62 I/O65 I/O124 I/O127 I/O128 I/O129 T
U I/O61 I/O63 I/O66 GND I/O76 VCCO I/O82 GND I/O91 VCC I/O98 I/O102 GND I/O112 VCCO NC GND I/O123 I/O122 I/O126 U
V I/O64 I/O67 I/O69 I/O75 I/O78 I/O81 I/O85 I/O88 I/O92 I2I/O97 I/O101 I/O105 I/O109 I/O113 TDO I/O114 I/O117 I/O121 I/O125 V
W I/O68 I/O70 I/O72 I/O74 I/O79 I/O83 I/O86 I/O89 I/O93 I/O95 I/O96 I/O100 I/O104 I/O107 I/O110 NC NC I/O115 I/O118 I/O120 W
Y I/O71 I/O73 I/O77 TMS I/O80 I/O84 I/O87 I/O90 I/O94 NC NC I/O99 I/O103 I/O106 I/O108 I/O111 NC NC I/O116 I/O119 Y
1234567891011121314151617181920
Ultra37000 CPLD Fami
ly
Document #: 38-03007 Rev. *B Page 40 of 63
Pin Configurations[20] (continued)
256-Ball Fine-Pitch BGA (BB256)
Top View
12345678910111213141516
A GND GND I/O26 I/O24 I/O20 VCC I/O11 GND GND I/O18
6VCC I/O17
7I/O17
2I/O16
7GND GND
B GND I/O27 I/O25 I/O23 I/O19 I/O15 I/O10 GND GND I/O18
5I/O18
1I/O17
6I/O17
1I/O16
6I/O16
5GND
C I/O29 I/O28 NC I/O22 I/O18 I/O14 I/O9I/O4I/O19
1I/O18
4I/O18
0I/O17
5I/O17
0NC I/O16
3I/O16
4
D I/O32 I/O31 I/O30 NC I/O17 I/O13 I/O8I/O3I/O19
0I/O18
3I/O17
9I/O17
4I/O16
9I/O16
0I/O16
1I/O16
2
E I/O35 I/O34 I/O33 I/O21 I/O16 I/O12 I/O7I/O2I/O18
9VCC I/O17
8I/O17
3I/O16
8I/O15
7I/O15
8I/O15
9
FV
CC I/O38 I/O37 I/O36 TCK VCC I/O6I/O1I/O18
8I/O18
2VCC TDI I/O15
4I/O15
5I/O15
6VCC
G I/O43 I/O42 I/O41 I/O40 VCC I/O39 I/O5I/O0I/O18
7I/O14
8I/O14
9CLK3
/I4
I/O15
0I/O15
1I/O15
2I/O15
3
H GND GND I/O47 I/O46 CLK0
/I0
I/O45 I/O44 GND GND I/O14
4I/O14
5CLK2
/I3
I/O14
6I/O14
7GND GND
J GND GND I/O51 I/O50 NC I/O49 I/O48 GND GND I/O14
0I/O14
1I2I/O14
2I/O14
3GND GND
K I/O57 I/O56 I/O55 I/O54 CLK1
/I1
I/O53 I/O52 I/O91 I/O96 I/O10
1I/O13
5VCC I/O13
6I/O13
7I/O13
8I/O13
9
LV
CC I/O60 I/O59 I/O58 TMS VCC I/O86 I/O92 I/O97 I/O10
2VCC TDO I/O13
2I/O13
3I/O13
4VCC
M I/O63 I/O62 I/O61 I/O72 I/O77 I/O82 VCC I/O93 I/O98 I/O10
3I/O10
8I/O11
2I/O11
7I/O12
9I/O13
0I/O13
1
N I/O66 I/O65 I/O64 I/O73 I/O78 I/O83 I/O87 I/O94 I/O99 I/O10
4I/O10
9I/O11
3NC I/O12
6I/O12
7I/O12
8
P I/O68 I/O67 NC I/O74 I/O79 I/O84 I/O88 I/O95 I/O10
0I/O10
5I/O11
0I/O11
4I/O11
8NC I/O12
4I/O12
5
R GND I/O69 I/O70 I/O75 I/O80 I/O85 I/O89 GND GND I/O10
6I/O11
1I/O11
5I/O11
9I/O12
1I/O12
3GND
T GND GND I/O71 I/O76 I/O81 VCC I/O90 GND GND I/O10
7VCC I/O11
6I/O12
0I/O12
2GND GND
Ultra37000 CPLD Fami
ly
Document #: 38-03007 Rev. *B Page 41 of 63
Pin Configurations[20] (continued)
352-Lead BGA (BG352)
Top View
1234567891011121314151617181920212223242526
A GND GND I/O19 I/O15 I/O13 I/O34 I/O31 I/O28 I/O25 I/O10 I/O7I/O4I/O1I/O263 I/O260 I/O257 I/O254 I/O239 I/O237 I/O232 I/O229 I/O250 I/O248 I/O244 GND GND
B GND NC I/O18 I/O17 I/O14 I/O35 I/O32 I/O29 I/O26 I/O11 I/O8I/O5I/O2VCC I/O261 I/O258 I/O255 I/O252 I/O234 I/O231 I/O228 I/O249 I/O246 I/O245 I/O240 GND
C I/O23 I/O38 I/O37 I/O16 I/O12 I/O33 I/O30 I/O27 I/O24 I/O9I/O6I/O3I/O0I/O262 I/O259 I/O256 I/O253 I/O238 I/O235 I/O233 I/O230 I/O251 I/O247 I/O225 I/O224 I/O227
D I/O39 I/O40 I/O36 NC NC I/O21 I/O20 VCCO VCCO NC GND GND VCCO VCCO GND GND NC VCCO VCCO I/O236 I/O243 NC NC I/O226 I/O222 I/O223
E I/O42 TCK I/O41 NC NC TDI I/O221 I/O220
F I/O45 I/O44 I/O43 I/O22 I/O242 I/O219 I/O218 I/O217
G I/O48 I/O47 I/O46 I/O63 I/O241 I/O216 I/O215 I/O214
H I/O49 I/O50 I/O51 VCCO VCCO I/O211 I/O212 I/O213
J I/O52 I/O53 I/O54 VCCO VCCO I/O208 I/O209 I/O210
K I/O55 I/O56 I/O57 NC NC I/O205 I/O206 I/O207
L I0 I/O59 I/O58 GND GND GND GND GND GND GND GND I/O204 I4 I/O197
M I/O61 I/O60 I1 GND GND GND GND GND GND GND GND I3 I/O203 I/O202
N I/O64 VCC I/O62 VCCO GND GND GND GND GND GND VCCO I/O201 I/O200 I/O199
P I/O65 I/O66 I/O67 VCCO GND GND GND GND GND GND VCCO I/O196 VCC I/O198
R I/O68 I/O69 I/O70 GND GND GND GND GND GND GND GND I/O193 I/O194 I/O195
T I/O71 I/O84 I/O85 GND GND GND GND GND GND GND GND I/O178 I/O179 I/O192
U I/O88 I/O87 I/O86 NC NC I/O177 I/O176 I/O175
V I/O91 I/O90 I/O89 VCCO VCCO I/O174 I/O173 I/O172
W I/O94 I/O93 I/O92 VCCO VCCO I/O171 I/O170 I/O169
Y I/O95 I/O72 I/O73 I/O110 I/O153 I/O190 I/O191 I/O168
AA I/O74 I/O75 I/O76 I/O111 I/O152 I/O187 I/O188 I/O189
AB I/O77 I/O78 I/O79 N/C NC I/O184 I/O185 I/O186
AC I/O81 I/O80 I/O108 N/C NC I/O112 I/O113 VCCO VCCO NC GND GND VCCO VCCO GND GND NC VCCO VCCO I/O150 I/O151 NC NC I/O155 I/O183 I/O182
AD I/O109 I/O82 I/O83 I/O117 I/O97 I/O100 I/O102 I/O105 I/O120 I/O123 I/O126 I/O129 I2 I/O133 I/O136 I/O139 I/O142 I/O157 I/O159 I/O161 I/O163 I/O166 I/O146 I/O180 I/O181 I/O154
AE GND NC I/O115 I/O116 I/O119 I/O98 I/O101 I/O103 I/O106 I/O121 I/O124 I/O127 VCC I/O130 I/O134 I/O137 I/O140 I/O143 I/O160 I/O162 I/O165 I/O144 I/O147 I/O148 NC GND
AF GND GND I/O114 I/O118 I/O96 I/O99 TMS I/O104 I/O107 I/O122 I/O125 I/O128 I/O131 I/O132 I/O135 I/O138 I/O141 I/O156 I/O158 TDO I/O164 I/O167 I/O145 I/O149 GND GND
Ultra37000 CPLD Fami
ly
Document #: 38-03007 Rev. *B Page 42 of 63
Pin Configurations[20] (continued)
400-Ball Fine-Pitch BGA (BB400)
Top View
A GNDGNDNCI/O
17 I/O16 I/O14 I/O29 VCC I/O11 GND GND I/O25
7VCC I/O23
9I/O23
3I/O23
2I/O23
0NC GND GND
B GND GND GND NC I/O15 I/O13 I/O28 VCC I/O10 GND GND I/O25
6VCC I/O23
8I/O23
1I/O22
9NC GND GND GND
C NC GND GND GND I/O20 I/O12 I/O27 VCC I/O9GND GND I/O25
5VCC I/O23
7I/O22
8I/O24
5GND GND GND NC
DI/O
44 NC GND I/O21 I/O19 I/O18 I/O26 I/O25 I/O8GND GND I/O25
4I/O23
5I/O23
6I/O25
1I/O24
4I/O24
3GND NC I/O22
7
EI/O
46 I/O43 I/O23 I/O22 NC I/O35 I/O34 I/O24 I/O7I/O4I/O26
3I/O25
3I/O23
4I/O25
0I/O24
8NC I/O24
1I/O24
2I/O22
5I/O22
6
FI/O
47 I/O45 I/O42 I/O41 I/O40 NC I/O33 I/O32 I/O6I/O3I/O26
2I/O25
2I/O24
9I/O24
7I/O22
0I/O22
1I/O24
0I/O22
2I/O22
3I/O22
4
GI/O
53 I/O52 I/O51 I/O50 I/O39 I/O38 I/O37 I/O31 I/O5I/O2I/O26
1VCC I/O24
6I/O21
7I/O21
8I/O21
9I/O21
2I/O21
3I/O21
4I/O21
5
HV
CC VCC VCC I/O49 I/O48 I/O36 TCK VCC I/O30 I/O1I/O25
9I/O26
0VCC TDI I/O21
6I/O21
0I/O21
1VCC VCC VCC
JI/O
59 I/O58 I/O57 I/O56 I/O55 I/O54 VCC I/O62 I/O60 I/O0I/O25
8I/O20
2I/O20
3CLK
3 /I4I/O20
4I/O20
5I/O20
6I/O20
7I/O20
8I/O20
9
K GND GND GND GND I/O65 I/O64 CLK
0 /I0I/O63 I/O61 GND GND I/O19
8I/O19
9CLK
2 /I3I/O20
0I/O20
1GND GND GND GND
L GND GND GND GND I/O69 I/O68 NC I/O67 I/O66 GND GND I/O19
3I/O19
5I2I/O19
6I/O19
7GND GND GND GND
MI/O
89 I/O88 I/O87 I/O86 I/O85 I/O84 CLK
1 /I1I/O71 I/O70 I/O12
6I/O13
2I/O19
2I/O19
4VCC I/O17
4I/O17
5I/O17
6I/O17
7I/O17
8I/O17
9
NV
CC VCC VCC I/O91 I/O90 I/O72 TMS VCC I/O12
8I/O12
7I/O13
3I/O16
2VCC TDO I/O18
0I/O16
8I/O16
9VCC VCC VCC
PI/O
95 I/O94 I/O93 I/O92 I/O75 I/O74 I/O73 I/O11
4VCC I/O12
9I/O13
4I/O13
7I/O16
3I/O18
1I/O18
2I/O18
3I/O17
0I/O17
1I/O17
2I/O17
3
RI/O
80 I/O79 I/O78 I/O10
8I/O77 I/O76 I/O11
5I/O11
7I/O12
0I/O13
0I/O13
5I/O13
8I/O16
4I/O16
5NC I/O18
4I/O18
5I/O18
6I/O18
9I/O19
1
TI/O
82 I/O81 I/O11
0I/O10
9NC I/O11
6I/O11
8I/O10
2I/O12
1I/O13
1I/O13
6I/O13
9I/O15
6I/O16
6I/O16
7NC I/O15
4I/O15
5I/O18
7I/O19
0
UI/O
83 NC GND I/O11
1I/O11
2I/O11
9I/O10
4I/O10
3I/O12
2GND GND I/O14
0I/O15
7I/O15
8I/O15
0I/O15
1I/O15
3GND NC I/O18
8
V NC GND GND GND I/O11
3I/O96 I/O10
5VCC I/O12
3GND GND I/O14
1VCC I/O15
9I/O1
44 I/O15
2GND GND GND NC
W GND GND GND NC I/O97 I/O99 I/O10
6VCC I/O12
4GND GND I/O14
2VCC I/O16
0I/O14
5I/O14
7NC GND GND GND
Y GNDGNDNCI/O
98 I/O10
0I/O10
1I/O10
7VCC I/O12
5GND GND I/O14
3VCC I/O16
1I/O14
6I/O14
8I/O14
9NC GND GND
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 43 of 63
Ordering Information
5.0V Ordering Inf o rmation
Macro-
cells Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
32 200 CY37032P44-200AC A44 44- Lea d Thin Qu ad Fla t Pack Commercial
CY37032P44-200JC J67 44-Lead Plastic Leaded Chip Carrier
154 CY37032P44-154AC A44 44-Lead Thin Quad Flat Pack Commercial
CY37032P44-154JC J67 44-Lead Plastic Leaded Chip Carrier
CY3703 2P4 4-15 4AI A44 44-Lead Thin Quad Fla t Pack Industrial
CY37032P44-154JI J67 44-Lead Plastic Leaded Chip Carrier
125 CY37032P44-125AC A44 44-Lead Thin Quad Flat Pack Commercial
CY37032P44-125JC J67 44-Lead Plastic Leaded Chip Carrier
CY3703 2P4 4-12 5AI A44 44-Lead Thin Quad Fla t Pack Industrial
CY37032P44-125JI J67 44-Lead Plastic Leaded Chip Carrier
64 200 CY37064P44-200AC A44 44- Lea d Thin Qu ad Fla t Pack Commercial
CY37064P44-200JC J67 44-Lead Plastic Leaded Chip Carrier
CY37064P84-200JC J83 84-Lead Plastic Leaded Chip Carrier
CY37064P100-200AC A100 100-Lead Thin Quad Flat Pack
C Y 3 7 5 1 2 V P 4 0 0 - 8 3 B B C
C
ypress Semiconductor ID
F
amily Type
37 = Ultra37000 Family
M
acrocell Density
32 = 32 Macrocells 256 = 256 Macrocells
64 = 64 Macrocells 384 = 384 Macrocells
128 = 128 Macrocells 512 = 512 Macrocells
192 = 192 Macrocells
Speed
125 = 125 MHz
200 = 200 MHz 100 = 100 MHz
167 = 167 MHz 83 = 83 MHz
154 = 154 MHz 66 = 66 MHz
143 = 143 MHz
Package Type
A = Thin Quad Flat Pack (TQFP)
U = Ceramic Quad Flat Pack (CQFP)
N = Plastic Quad Flat Pack (PQFP)
NT = Thermally Enhanced Plastic Quad Flat Pack
(EQFP)
J = Plastic Leaded Chip Carrier (PLCC)
Y = Ceramic Leaded Chip Carrier (CLCC)
BG = Ball Grid Array (BGA)
BA = Fine-Pitch Ball Grid Array (FBGA)
0.8mm Lead Pitch
BB = Fine-Pitch Ball Grid Array (FBGA)
1.0mm Lead Pitch
Operating Conditions
Commercial 0°C to +70°C
Industrial -40°C to +85°C
Military -55°C to +125°C
O
perating Reference Voltage
V = 3.3V Supply Voltage
(5.0V if not specified)
P
in Count
P44 = 44 Leads
P48 = 48 Leads
P84 = 84 Leads
P100 = 100 Leads
P160 = 160 Leads
P208 = 208 Leads
P256 = 256 Leads
P352 = 352 Leads
P400 = 400 Leads
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 44 of 63
64 154 CY37064P44-154AC A44 44- Lea d Thin Qu ad Fla t Pack Commercial
CY37064P44-154JC J67 44-Lead Plastic Leaded Chip Carrier
CY37064P84-154JC J83 84-Lead Plastic Leaded Chip Carrier
CY37064P100-154AC A100 100-Lead Thin Quad Flat Pack
CY37064P44-154AI A44 44- Lea d Thin Qu ad Fla t Pack Industrial
CY37064P44-154JI J67 44-Lead Plastic Leaded Chip Carrier
CY37064P84-154JI J83 84-Lead Plastic Leaded Chip Carrier
CY37064P100-154AI A100 100-Lead Thin Quad Flat Pack
5962-9951902QYA Y67 44-Lead Ceramic Leadless Chip Carrier Military
125 CY37064P44-125AC A44 44-Lead Thin Quad Flat Pack Commercial
CY37064P44-125JC J67 44-Lead Plastic Leaded Chip Carrier
CY37064P84-125JC J83 84-Lead Plastic Leaded Chip Carrier
CY37064P100-125AC A100 100-Lead Thin Quad Flat Pack
CY37064P44-125AI A44 44- Lea d Thin Qu ad Fla t Pack Industrial
CY37064P44-125JI J67 44-Lead Plastic Leaded Chip Carrier
CY37064P84-125JI J83 84-Lead Plastic Leaded Chip Carrier
CY37064P100-125AI A100 100-Lead Thin Quad Flat Pack
5962-9951901QYA Y67 44-Lead Ceramic Leadless Chip Carrier Military
128 167 CY37128P84-167JC J83 84-Lead Plastic Leaded Chip Carrier Commercial
CY37128P100-167AC A100 100-Lead Thin Quad Flat Pack
CY37128P160-167AC A160 160-Lead Thin Quad Flat Pack
125 CY37128P84-125JC J83 84-Lead Plastic Leaded Chip Carrier Commercial
CY37128P100-125AC A100 100-Lead Thin Quad Flat Pack
CY37128P160-125AC A160 160-Lead Thin Quad Flat Pack
CY37128P84-125JI J83 84-Lead Plastic Leaded Chip Carrier Industrial
CY37128P100-125AI A100 100-Lead Thin Quad Flat Pack
CY37128P160-125AI A160 160-Lead Thin Quad Flat Pack
5962-9952102QYA Y84 84-Lead Ceramic Leaded Chip Carrier Military
100 CY37128P84-100JC J83 84-Lead Plastic Leaded Chip Carrier Commercial
CY37128P100-100AC A100 100-Lead Thin Quad Flat Pack
CY37128P160-100AC A160 160-Lead Thin Quad Flat Pack
CY37128P84-100JI J83 84-Lead Plastic Leaded Chip Carrier Industrial
CY37128P100-100AI A100 100-Lead Thin Quad Flat Pack
CY37128P160-100AI A160 160-Lead Thin Quad Flat Pack
5962-9952101QYA Y84 84-Lead Ceramic Leaded Chip Carrier Military
192 154 CY37192P160-154AC A160 160-Lead Thin Quad Flat Pack Commercial
125 CY37192P160-125AC A160 160-Lead Thin Quad Flat Pack Commercial
CY37192P160-125AI A160 160-Lead Thin Quad Flat Pack Industrial
83 CY37192P160-83AC A160 160-Lead Thin Quad Flat Pack Commercial
CY37192P160-83AI A160 160-Lead Thin Quad Flat Pack Industrial
5.0V Ordering Inf o rmation (continued)
Macro-
cells Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 45 of 63
256 154 CY37256P160-154AC A160 160-Lead Thin Quad Flat Pack Commercial
CY37256P208-154NC N208 208-Lead Plastic Quad Flat Pack
CY37256P256-154BGC BG256 256-Lead Ba ll Grid Array
125 CY37256P160-125AC A160 160-Lead Thin Quad Flat Pack Commercial
CY37256P208-125NC N208 208-Lead Plastic Quad Flat Pack
CY37256P256-125BGC BG256 256-Lead Ba ll Grid Array
CY37256P160-125AI A160 160-Lead Thin Quad Flat Pack Industrial
CY37256P208-125NI N208 208-Lead Plastic Quad Flat Pack
CY37256P256-125BGI BG256 256-Lead Ball Grid Array
5962-9952302QZC U162 160-Lead Ceramic Quad Flat Pack Military
83 CY37256P160-83AC A160 160-Lead Thin Quad Flat Pack Commercial
CY37256P208-83NC N208 208-Lead Plastic Quad Flat Pack
CY37256P256-83BGC BG256 256-Lead Ball Grid Array
CY37256P160-83AI A160 160-Lead Thin Quad Flat Pack Industrial
CY37256P208-83NI N208 208-Lead Plastic Quad Flat Pack
CY37256P256-83BGI BG256 256-Lead Ball Grid Array
5962-9952301QZC U162 160-Lead Ceramic Quad Flat Pack Military
384 125 CY37384P208-125NC N208 208-Lead Plastic Quad Flat Pack Commercial
CY37384P256-125BGC BG256 256-Lead Ba ll Grid Array
83 CY37384P208-83NC N208 208-Lead Plastic Quad Flat Pack Commercial
CY37384P256-83BGC BG256 256-Lead Ball Grid Array
CY37384P208-83NI N208 208-Lead Plastic Quad Flat Pack Industrial
CY37384P256-83BGI BG256 256-Lead Ball Grid Array
512 125 CY37512P208-125NC N208 208-Lead Plastic Quad Flat Pack Commercial
CY37512P256-125BGC BG256 256-Lead Ba ll Grid Array
CY37512P352-125BGC BG352 352-Lead Ba ll Grid Array
100 CY37512P208-100NC N208 208-Lead Plastic Quad Flat Pack Commercial
CY37512P256-100BGC BG256 256-Lead Ba ll Grid Array
CY37512P352-100BGC BG352 352-Lead Ba ll Grid Array
CY37512P208-100NI N208 208-Lead Plastic Quad Flat Pack Industrial
CY37512P256-100BGI BG256 256-Lead Ball Grid Array
CY37512P352-100BGI BG352 352-Lead Ball Grid Array
5962-9952502QZC U208 208-Lead Ceramic Quad Flat Pack Military
83 CY37512P208-83NC N208 208-Lead Plastic Quad Flat Pack Commercial
CY37512P256-83BGC BG256 256-Lead Ball Grid Array
CY37512P352-83BGC BG352 352-Lead Ball Grid Array
CY37512P208-83NI N208 208-Lead Plastic Quad Flat Pack Industrial
CY37512P256-83BGI BG256 256-Lead Ball Grid Array
CY37512P352-83BGI BG352 352-Lead Ball Grid Array
5962-9952501QZC U208 208-Lead Ceramic Quad Flat Pack Military
5.0V Ordering Inf o rmation (continued)
Macro-
cells Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 46 of 63
3.3V Ordering Inf o rmation
Macro-
cells Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
32 143 CY37032VP44-143AC A44 44-L ea d Thin Qu ad Fla t Pack Commercial
CY37032VP44-143JC J67 44-Lead Plastic Leaded Chip Carrier
CY37032VP48-143BAC BA50 48-Lead Fine Pitch Ball Grid Array
100 CY37032VP44-100AC A44 44-Lead Thin Qu ad Fla t Pack Commercial
CY37032VP44-100JC J67 44-Lead Plastic Leaded Chip Carrier
CY37032VP48-100BAC BA50 48-Lead Fine Pitch Ball Grid Array
CY3703 2VP4 4-10 0AI A44 44-Lead Thin Quad Flat Pack Industri al
CY37032VP44-100JI J67 44-Lead Plastic Leaded Chip Carrier
CY37032VP48-100BAI BA50 48-Lead Fine Pitch Ball Grid Array
64 143 CY37064VP44-143AC A44 44-Lead Thin Quad Flatpack Commercial
CY37064VP44-143JC J67 44-Lead Plastic Leaded Chip Carrier
CY37064VP48-143BAC BA50 48-Lead Fine-Pitch Ball Grid Array
CY37064VP84-143JC J83 84-Lead Plastic Leaded Chip Carrier
CY37064VP100-143AC A100 100-Lead Thin Quad Flatpack
CY37064VP100-143BBC BB100 100-Lead Fine-Pitch Ball Grid Array
100 CY37064VP44-100AC A44 44-Lead Thin Quad Flatpack Commercial
CY37064VP44-100JC J67 44-Lead Plastic Leaded Chip Carrier
CY37064VP48-100BAC BA50 48-Lead Fine-Pitch Ball Grid Array
CY37064VP84-100JC J83 84-Lead Plastic Leaded Chip Carrier
CY37064VP100-100AC A100 100-Lead Thin Quad Flatpack
CY37064VP100-100BBC BB100 100-Lead Fine-Pitch Ball Grid Array
CY37064VP44-100AI A44 44-Lead Thin Quad Flatpack Industrial
CY37064VP44-100JI J67 44-Lead Plastic Leaded Chip Carrier
CY37064VP48-100BAI BA50 48-Lead Fine-Pitch Ball Grid Array
CY37064VP84-100JI J83 84-Lead Plastic Leaded Chip Carrier
CY37064VP100-100BBI BB100 100-Lead Fine-Pitch Ball Grid Array
CY37064VP100-100AI A100 100-Lead Thin Quad Flatpack
5962-9952001QYA Y67 44-Lead Ceramic Leaded Chip Carrier Military
128 125 CY37128VP84-125JC J83 84-Lead Plastic Leaded Chip Carrier Commercial
CY37128VP100-125AC A100 100-Lead Thin Quad Flat Pack
CY37128VP100-125BBC BB100 100-Lead Fine-Pitch Ball Grid Array
CY37128VP160-125AC A160 160-Lead Thin Quad Flat Pack
83 CY37128VP84-83JC J83 84-Lead Plastic Leaded Chip Carrier Commercial
CY37128VP100-83AC A100 100-Lead Thin Quad Flat Pack
CY37128VP100-83BBC BB100 100-Lead Fine-Pitch Ball Grid Array
CY37128VP160-83AC A160 160-Lead Thin Quad Flat Pack
CY37128VP84-83JI J83 84-Lead Plastic Leaded Chip Carrier Industrial
CY37128VP100-83AI A100 100-Lead Thin Quad Flat Pack
CY37128VP100-83BBI BB100 100-Lead Fine-Pitch Ball Grid Array
CY37128VP160-83AI A160 160-Lead Thin Quad Flat Pack
5962-9952201QYA Y84 84-Lead Ceramic Leaded Chip Carrier Military
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 47 of 63
192 100 CY37192VP160-100AC A160 160-Lead Thin Quad Flat Pack Commercial
66 CY37192VP160-66AC A160 160-Lead Thin Quad Flat Pack Commercial
CY37192VP160-66AI A160 160-Lead Thin Quad Flat Pack Industrial
256 100 CY37256VP160-100AC A160 160-Lead Thin Quad Flat Pack Commercial
CY37256VP208-100NC N208 208-Lead Plastic Quad Flat Pack
CY37256VP256-100BGC BG256 256-Lead Ball Grid Array
CY37256VP256-100BBC BB256 256-Lead Fine-Pitch Ball Grid Array
66 CY37256VP160-66AC A160 160-Lead Thin Quad Flat Pack Commercial
CY37256VP208-66NC N208 208-Lead Plastic Quad Flat Pack
CY37256VP256-66BGC BG256 256-Lead Ball Grid Array
CY37256VP256-66BBC BB256 256-Lead Fine-Pitch Ball Grid Array
CY37256VP160-66AI A160 160-Lead Thin Quad Flat Pack Industrial
CY37256VP256-66BGI BG256 256-Lead Ball Grid Array
CY37256VP256-66BBI BB256 256-Lead Fine-Pitch Ball Grid Array
5962-9952401QZC U162 160-Lead Ceramic Quad Flat Pack Military
384 83 CY37384VP208-83NC N208 208-Lead Plastic Quad Flat Pack Commercial
CY37384VP256-83BGC BG256 256-Lead Ball Grid Array
66 CY37384VP208-66NC N208 208-Lead Plastic Quad Flat Pack Commercial
CY37384VP256-66BGC BG256 256-Lead Ball Grid Array
CY37384VP208-66NI N208 208-Lead Plastic Quad Flat Pack Industrial
CY37384VP256-66BGI BG256 256-Lead Ball Grid Array
512 83 CY37512VP208-83NC N208 208-Lead Plastic Quad Flat Pack Commercial
CY37512VP256-83BGC BG256 256-Lead Ball Grid Array
CY37512VP352-83BGC BG352 352-Lead Ball Grid Array
CY37512VP400-83BBC BB400 400-Lead Fine-Pitch Ball Grid Array
66 CY37512VP208-66NC N208 208-Lead Plastic Quad Flat Pack Commercial
CY37512VP256-66BGC BG256 256-Lead Ball Grid Array
CY37512VP352-66BGC BG352 352-Lead Ball Grid Array
CY37512VP400-66BBC BB400 400-Lead Fine-Pitch Ball Grid Array
CY37512VP208-66NI N208 208-Lead Plastic Quad Flat Pack Industrial
CY37512VP256-66BGI BG256 256-Lead Ball Grid Array
CY37512VP352-66BGI BG352 352-Lead Ball Grid Array
CY37512VP400-66BBI BB400 400-Lead Fine-Pitch Ball Grid Array
5962-9952601QZC U208 208-Lead Ceramic Quad Flat Pack Military
3.3V Ordering Inf o rmation (continued)
Macro-
cells Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 48 of 63
Package Diagrams
44-lead Thin Plastic Quad Flat Pack A44
51-85064-*B
44-Lead Plastic Leaded Chip Carrier J67
51-85003-*A
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 49 of 63
Package Diagrams (continued)
44-Pin Ceramic Leaded Chip Carrier Y67
51-80014-**
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 50 of 63
Package Diagrams (continued)
48-Ball (7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch) Thin BGA BA48D
51-85109-*C
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 51 of 63
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
51-85006-*A
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 52 of 63
Package Diagrams (continued)
84-Pin Ceramic Leaded Chip Carrier Y84
51-80095-*A
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 53 of 63
Package Diagrams (continued)
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 54 of 63
Package Diagrams (continued)
100-B a ll T hi n Bal l Gri d Ar ray (11 x 11 x 1.4 mm) B B1 00
51-85107-*B
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 55 of 63
Package Diagrams (continued)
160-Pin Thin Plastic Quad Flat Pack (24 x 24 x 1.4 mm) (TQFP) A160
51-85049-*B
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 56 of 63
Package Diagrams (continued)
160-Lead Ceramic Quad Flatpack (Cavity Up) U162
51-80106-**
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 57 of 63
Package Diagrams (continued)
208-Lead Plastic Quad Flatpack N208
51-85069-*B
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 58 of 63
Package Diagrams (continued)
51-80105-*A
208-Lead Ceramic Quad Flatpack (Cavity Up) U208
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 59 of 63
Package Diagrams (continued)
256-Bal l FBGA (17 x 17 mm) BB 256
51-85108-*C
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 60 of 63
Package Diagrams (continued)
388-L ead PBGA (35 x 35 x 2. 33 mm) BG388
51-85103-*C
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 61 of 63
Warp is a re giste red trad emark , and In-Syst em Rep rogrammab le, ISR, Warp Profess ional, Warp Ente rprise, and Ul tra3700 0 are
trade marks, of Cypress Sem iconducto r .V iewDr aw and Speed W ave are tra demarks o f View Logic. W indows is a registere d trade-
mark of Microsoft Corporation. A ll product and company names ment ioned in this document are the trademarks of their respective
holders.
Package Diagrams (continued)
400-Ball FBGA (21 x 21 x 1.4 mm) BB400
51-85111-*A
Ultra37000 CPLD Famil
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Document #: 38-03007 Rev. *B Page 62 of 63
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. C ypress Semicond uctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Addendum
3.3V Operating Range
(CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC)
Range Ambient Temperature[2] Junction Temperature VCC
Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.16V
Ultra37000 CPLD Fami
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Document #: 38-03007 Rev. *B Page 63 of 63
Document History Page
Document Title: Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs
Document Number: 38-03007
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 106272 04/18/01 SZV Change from Spec number: 38-00475 to 38-03007
*A 124942 03/21/03 OOR Updated 3.3V Vcc requ irements for –144 spee ds
Added an Addendum
*B 126262 05/09/03 TEH Changed pinout for CY37128V BB100 package
