Figure 4: Typical Waveforms for VIN = 48 V to 5 V/7 A (1000kHz) Buck converter CH1: VPWM Input voltage - CH2: (IOUT) Switch node current - CH4: (VOUT) Switch node voltage NOTE. The EPC9010 development board does not have any current or thermal protection on board. Figure 3: Proper Measurement of Switch Node - OUT Minimize loop EFFICIENT POWER CONVERSION EPC The EPC9010 development board showcases the EPC2016 eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The EPC9010 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Place probe in large via at OUT Ground probe against TP3 THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION Figure 1: Block Diagram of EPC9010 Development Board PWM Input - (For Efficiency Measurement) VDD Logic and Dead-time Adjust LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator - VIN V OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply + <70 V A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V 0, 100 Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com PWM Input External Circuit Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com Quick Start Procedure EPC Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Development board EPC9010 is easy to set up to evaluate the performance of the EPC2016 eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: 0, 100 www.epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. Do not use probe ground lead Contact us: Development Board EPC9010 Quick Start Guide 100 V Half-Bridge with Gate Drive, Using EPC2016 DESCRIPTION www.epc-co.com The EPC9010 development board is a 100 V maximum device voltage, 7 A maximum output current, half bridge with onboard gate drives, featuring the EPC2016 enhancement mode (eGaN(R)) field effect transistor (FET). The purpose of this development board is to simplify the evaluation process of the EPC2016 eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. The EPC9010 development board is 2" x 1.5" and contains two EPC2016 eGaN FET in a half bridge configuration using Texas Instruments LM5113 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC2016s eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER EPC Products are distributed exclusively through Digi-Key. www.digikey.com Development Board / Demonstration Board Notification The EPC9010 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. CONDITIONS MIN MAX UNITS 7 12 V V VDD Gate Drive Input Supply Range VIN Bus Input Voltage Range 70* VOUT Switch Node Output Voltage 100 V IOUT Switch Node Output Current 7* A VPWM PWM Logic Input Voltage Threshold 3.5 6 V 0 1.5 Input `High' Input `Low' V Minimum `High' State Input Pulse Width VPWM rise and fall time < 10ns 60 ns Minimum `Low' State Input Pulse Width VPWM rise and fall time < 10ns 200# ns * Assumes inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to `refresh' high side bootstrap supply voltage. Figure 4: Typical Waveforms for VIN = 48 V to 5 V/7 A (1000kHz) Buck converter CH1: VPWM Input voltage - CH2: (IOUT) Switch node current - CH4: (VOUT) Switch node voltage NOTE. The EPC9010 development board does not have any current or thermal protection on board. Figure 3: Proper Measurement of Switch Node - OUT Minimize loop EFFICIENT POWER CONVERSION EPC The EPC9010 development board showcases the EPC2016 eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The EPC9010 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Place probe in large via at OUT Ground probe against TP3 THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION Figure 1: Block Diagram of EPC9010 Development Board PWM Input - (For Efficiency Measurement) VDD Logic and Dead-time Adjust LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator - VIN V OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply + <70 V A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V 0, 100 Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com PWM Input External Circuit Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com Quick Start Procedure EPC Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Development board EPC9010 is easy to set up to evaluate the performance of the EPC2016 eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: 0, 100 www.epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. Do not use probe ground lead Contact us: Development Board EPC9010 Quick Start Guide 100 V Half-Bridge with Gate Drive, Using EPC2016 DESCRIPTION www.epc-co.com The EPC9010 development board is a 100 V maximum device voltage, 7 A maximum output current, half bridge with onboard gate drives, featuring the EPC2016 enhancement mode (eGaN(R)) field effect transistor (FET). The purpose of this development board is to simplify the evaluation process of the EPC2016 eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. The EPC9010 development board is 2" x 1.5" and contains two EPC2016 eGaN FET in a half bridge configuration using Texas Instruments LM5113 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC2016s eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER EPC Products are distributed exclusively through Digi-Key. www.digikey.com Development Board / Demonstration Board Notification The EPC9010 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. CONDITIONS MIN MAX UNITS 7 12 V V VDD Gate Drive Input Supply Range VIN Bus Input Voltage Range 70* VOUT Switch Node Output Voltage 100 V IOUT Switch Node Output Current 7* A VPWM PWM Logic Input Voltage Threshold 3.5 6 V 0 1.5 Input `High' Input `Low' V Minimum `High' State Input Pulse Width VPWM rise and fall time < 10ns 60 ns Minimum `Low' State Input Pulse Width VPWM rise and fall time < 10ns 200# ns * Assumes inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to `refresh' high side bootstrap supply voltage. NOTE. The EPC9010 development board does not have any current or thermal protection on board. Figure 4: Typical Waveforms for VIN = 48 V to 5 V/7 A (1000kHz) Buck converter CH1: VPWM Input voltage - CH2: (IOUT) Switch node current - CH4: (VOUT) Switch node voltage The EPC9010 development board showcases the EPC2016 eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The EPC9010 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Figure 3: Proper Measurement of Switch Node - OUT EFFICIENT POWER CONVERSION EPC Minimize loop Place probe in large via at OUT Ground probe against TP3 THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Do not use probe ground lead 0, 100 Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION Figure 1: Block Diagram of EPC9010 Development Board EPC PWM Input - (For Efficiency Measurement) PWM Input VDD Logic and Dead-time Adjust LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator OUT VIN Half-Bridge with Bypass External Circuit - VIN V Switch Node + IIN VIN Supply + <70 V A + Gate Drive Supply (Note Polarity) VDD Supply - 0, 100 7 V - 12 V Contact us: Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com DESCRIPTION Development Board EPC9010 Quick Start Guide www.epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). Turn on the controller / PWM input source and probe switching node to see switching operation. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. 1. 2. 3. 4. 5. 6. 7. 8. Development board EPC9010 is easy to set up to evaluate the performance of the EPC2016 eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: Quick Start Procedure www.epc-co.com The EPC9010 development board is a 100 V maximum device voltage, 7 A maximum output current, half bridge with onboard gate drives, featuring the EPC2016 enhancement mode (eGaN(R)) field effect transistor (FET). The purpose of this development board is to simplify the evaluation process of the EPC2016 eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. 100 V Half-Bridge with Gate Drive, Using EPC2016 The EPC9010 development board is 2" x 1.5" and contains two EPC2016 eGaN FET in a half bridge configuration using Texas Instruments LM5113 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC2016s eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER V EPC Products are distributed exclusively through Digi-Key. www.digikey.com DD Switch Node Output Voltage VOUT Bus Input Voltage Range VIN I CONDITIONS Gate Drive Input Supply Range Switch Node Output Current OUT VPWM Development Board / Demonstration Board Notification The EPC9010 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. PWM Logic Input Voltage Threshold MIN 7 MAX 12 70* 100 7* 0 Input `Low' 3.5 Input `High' VPWM rise and fall time < 10ns Minimum `Low' State Input Pulse Width VPWM rise and fall time < 10ns Minimum `High' State Input Pulse Width 6 1.5 60 UNITS V V V A V V ns ns 200# * Assumes inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to `refresh' high side bootstrap supply voltage. EPC reserves the right at any time, without notice, to change said circuitry and specifications. NOTE. The EPC9010 development board does not have any current or thermal protection on board. Figure 4: Typical Waveforms for VIN = 48 V to 5 V/7 A (1000kHz) Buck converter CH1: VPWM Input voltage - CH2: (IOUT) Switch node current - CH4: (VOUT) Switch node voltage The EPC9010 development board showcases the EPC2016 eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The EPC9010 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Figure 3: Proper Measurement of Switch Node - OUT EFFICIENT POWER CONVERSION EPC Minimize loop Place probe in large via at OUT Ground probe against TP3 THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Do not use probe ground lead 0, 100 Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION Figure 1: Block Diagram of EPC9010 Development Board EPC PWM Input - (For Efficiency Measurement) PWM Input VDD Logic and Dead-time Adjust LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator OUT VIN Half-Bridge with Bypass External Circuit - VIN V Switch Node + IIN VIN Supply + <70 V A + Gate Drive Supply (Note Polarity) VDD Supply - 0, 100 7 V - 12 V Contact us: Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com DESCRIPTION Development Board EPC9010 Quick Start Guide www.epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). Turn on the controller / PWM input source and probe switching node to see switching operation. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. 1. 2. 3. 4. 5. 6. 7. 8. Development board EPC9010 is easy to set up to evaluate the performance of the EPC2016 eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: Quick Start Procedure www.epc-co.com The EPC9010 development board is a 100 V maximum device voltage, 7 A maximum output current, half bridge with onboard gate drives, featuring the EPC2016 enhancement mode (eGaN(R)) field effect transistor (FET). The purpose of this development board is to simplify the evaluation process of the EPC2016 eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. 100 V Half-Bridge with Gate Drive, Using EPC2016 The EPC9010 development board is 2" x 1.5" and contains two EPC2016 eGaN FET in a half bridge configuration using Texas Instruments LM5113 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC2016s eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER V EPC Products are distributed exclusively through Digi-Key. www.digikey.com DD Switch Node Output Voltage VOUT Bus Input Voltage Range VIN I CONDITIONS Gate Drive Input Supply Range Switch Node Output Current OUT VPWM Development Board / Demonstration Board Notification The EPC9010 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. PWM Logic Input Voltage Threshold MIN 7 MAX 12 70* 100 7* 0 Input `Low' 3.5 Input `High' VPWM rise and fall time < 10ns Minimum `Low' State Input Pulse Width VPWM rise and fall time < 10ns Minimum `High' State Input Pulse Width 6 1.5 60 UNITS V V V A V V ns ns 200# * Assumes inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to `refresh' high side bootstrap supply voltage. EPC reserves the right at any time, without notice, to change said circuitry and specifications. Table 2 : Bill of Material Item Qty Reference Part Description Manufacturer / Part # 1 4 C4, C10, C11, C13 Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D 2 2 C6, C7 Capacitor, 100pF, 5%, 50V, NP0 TDK, C1608C0G1H101J 3 1 C12 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1608X5R1E104K 4 2 C16, C17 Capacitor, 2.2uF, 10%, 100V, X5R Taiyo Yuden, HMK325B7225K 5 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7 6 3 J1, J2, J9 Connector 2pins of Tyco, 4-103185-0 7 1 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF 8 2 Q1, Q2 eGaN(R) FET EPC, EPC2016 9 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0 10 2 R2, R15 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00 11 1 R4 Resistor, 22 Ohm, 1%, 1/8W Stackpole, RMCF0603FT22R0 12 1 R5 Resistor, 47 Ohm, 1%, 1/8W Stackpole, RMCF0603FT47R0 13 2 R11, R12 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00 14 2 TP1, TP2 Test Point Keystone Elect, 5015 15 1 TP3 Connector 1/40th of Tyco, 4-103185-0 16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X 17 1 U2 I.C., Gate driver Texas Instruments, LM5113 18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC 19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X 20 0 R13, R14 Optional Resistor 21 0 C15, C19 Optional Capacitor 22 0 D5, D6 Optional Diode 23 0 P1, P2 Optional Potentiometer 1 2 4 3 5 6 A A 7 - 12 Vdc J1 1 2 CON2 C10 1uF, 25V 8 U3 IN 7 NC MCP1703 OUT 1 NC 2 6 NC NC 3 GND 4 NC C11 1uF, 25V C4 1uF, 25V 9 GND 5 VCC VCC 1 2 3 4 U1 A VDD B 70V Max B 4 3 2 1 R1 10k Y R11 0.1uF, 25V U4 A P2 Optional PWM2 22.0 2 J4 CON4 Optional C17 C16 2.2uF, 100V 2.2uF, 100V D6 Optional Optional C15 SDM03U40 R5 R12 47.0 R15 Zero SW OUT GND C6 100p D2 R14 J3 CON4 4 3 2 1 HB VDD U2 LM5113 LOH SDM03U40 R4 HOH D1 Y NC7SZ08L6X C 1uF, 25V C13 LOL GND 2 VSS P1 Optional B 1 2 3 4 VDD HS R2 Zero J6 CON4 Q1 EPC2016 Zero C12 HOL Zero Q2 EPC2016 R13 Optional C7 100p C TP3 (Optional) 1 C19 Optional CON1 J7 CON4 1 2 3 4 GND NC7SZ00L6X LI 1 2 CON2 J9 1 2 CON2 HI J2 J5 CON4 1 PWM1 B TP2 Keystone 5015 4 3 2 1 1 GND J8 CON4 TP1 Keystone 5015 D D Figure 5: Development Board EPC9010 Schematic 1 2 3 4 5 6 Table 2 : Bill of Material Item Qty Reference Part Description Manufacturer / Part # 1 4 C4, C10, C11, C13 Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D 2 2 C6, C7 Capacitor, 100pF, 5%, 50V, NP0 TDK, C1608C0G1H101J 3 1 C12 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1608X5R1E104K 4 2 C16, C17 Capacitor, 2.2uF, 10%, 100V, X5R Taiyo Yuden, HMK325B7225K 5 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7 6 3 J1, J2, J9 Connector 2pins of Tyco, 4-103185-0 7 1 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF 8 2 Q1, Q2 eGaN(R) FET EPC, EPC2016 9 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0 10 2 R2, R15 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00 11 1 R4 Resistor, 22 Ohm, 1%, 1/8W Stackpole, RMCF0603FT22R0 12 1 R5 Resistor, 47 Ohm, 1%, 1/8W Stackpole, RMCF0603FT47R0 13 2 R11, R12 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00 14 2 TP1, TP2 Test Point Keystone Elect, 5015 15 1 TP3 Connector 1/40th of Tyco, 4-103185-0 16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X 17 1 U2 I.C., Gate driver Texas Instruments, LM5113 18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC 19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X 20 0 R13, R14 Optional Resistor 21 0 C15, C19 Optional Capacitor 22 0 D5, D6 Optional Diode 23 0 P1, P2 Optional Potentiometer 1 2 4 3 5 6 A A 7 - 12 Vdc J1 1 2 CON2 C10 1uF, 25V 8 U3 IN 7 NC MCP1703 OUT 1 NC 2 6 NC NC 3 GND 4 NC C11 1uF, 25V C4 1uF, 25V 9 GND 5 VCC VCC 1 2 3 4 U1 A VDD B 70V Max B 4 3 2 1 R1 10k Y R11 0.1uF, 25V U4 A P2 Optional PWM2 22.0 2 J4 CON4 Optional C17 C16 2.2uF, 100V 2.2uF, 100V D6 Optional Optional C15 SDM03U40 R5 R12 47.0 R15 Zero SW OUT GND C6 100p D2 R14 J3 CON4 4 3 2 1 HB VDD U2 LM5113 LOH SDM03U40 R4 HOH D1 Y NC7SZ08L6X C 1uF, 25V C13 LOL GND 2 VSS P1 Optional B 1 2 3 4 VDD HS R2 Zero J6 CON4 Q1 EPC2016 Zero C12 HOL Zero Q2 EPC2016 R13 Optional C7 100p C TP3 (Optional) 1 C19 Optional CON1 J7 CON4 1 2 3 4 GND NC7SZ00L6X LI 1 2 CON2 J9 1 2 CON2 HI J2 J5 CON4 1 PWM1 B TP2 Keystone 5015 4 3 2 1 1 GND J8 CON4 TP1 Keystone 5015 D D Figure 5: Development Board EPC9010 Schematic 1 2 3 4 5 6 Figure 4: Typical Waveforms for VIN = 48 V to 5 V/7 A (1000kHz) Buck converter CH1: VPWM Input voltage - CH2: (IOUT) Switch node current - CH4: (VOUT) Switch node voltage NOTE. The EPC9010 development board does not have any current or thermal protection on board. Figure 3: Proper Measurement of Switch Node - OUT Minimize loop EFFICIENT POWER CONVERSION EPC The EPC9010 development board showcases the EPC2016 eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The EPC9010 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Place probe in large via at OUT Ground probe against TP3 THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION Figure 1: Block Diagram of EPC9010 Development Board PWM Input - (For Efficiency Measurement) VDD Logic and Dead-time Adjust LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator - VIN V OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply + <70 V A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V 0, 100 Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com PWM Input External Circuit Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com Quick Start Procedure EPC Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Development board EPC9010 is easy to set up to evaluate the performance of the EPC2016 eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: 0, 100 www.epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT). 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. Do not use probe ground lead Contact us: Development Board EPC9010 Quick Start Guide 100 V Half-Bridge with Gate Drive, Using EPC2016 DESCRIPTION www.epc-co.com The EPC9010 development board is a 100 V maximum device voltage, 7 A maximum output current, half bridge with onboard gate drives, featuring the EPC2016 enhancement mode (eGaN(R)) field effect transistor (FET). The purpose of this development board is to simplify the evaluation process of the EPC2016 eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. The EPC9010 development board is 2" x 1.5" and contains two EPC2016 eGaN FET in a half bridge configuration using Texas Instruments LM5113 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC2016s eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) SYMBOL PARAMETER EPC Products are distributed exclusively through Digi-Key. www.digikey.com Development Board / Demonstration Board Notification The EPC9010 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. CONDITIONS MIN MAX UNITS 7 12 V V VDD Gate Drive Input Supply Range VIN Bus Input Voltage Range 70* VOUT Switch Node Output Voltage 100 V IOUT Switch Node Output Current 7* A VPWM PWM Logic Input Voltage Threshold 3.5 6 V 0 1.5 Input `High' Input `Low' V Minimum `High' State Input Pulse Width VPWM rise and fall time < 10ns 60 ns Minimum `Low' State Input Pulse Width VPWM rise and fall time < 10ns 200# ns * Assumes inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to `refresh' high side bootstrap supply voltage.