74ABT841DB,118 - NXP Semiconductors

1. General description

The 74ABT841 high performance BiCMOS device combines low static and dynamic

power dissipation with high speed and high output drive.

The 74ABT841 bus interface register is designed to provide extra data width for wider

data/address paths of buses carrying parity.

The 74ABT841 consists of ten D-type latches with 3-state outputs. The flip-flop s appear

transparent to the data when latch enable (LE) is HIGH. This allows asynchronous

operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW

transition, the data that meets the set-up and hold time is latched.

Data appears on the bus when the output enable (OE) is LOW. When OE is HIGH the

output is in the high-impedance state.

2. Features and benefits

High speed parallel latches

Extra dat a width for wide address/data paths or buses carrying parity

Ideal where high speed, light loading, or increased fan-in are required with MOS

microprocessors

Broadside pinout

Output capability: +64 mA and 32 mA

Power-up 3-state

Power-up reset

Latch-up protection exceeds 500 mA per JESD78B class II level A

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

74ABT841

10-bit bus interface latch; 3-state

Rev. 4 — 7 November 2011 Product data sheet

Product data sheet Rev. 4 — 7 November 2011 2 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Temperature

range Name Description Version

74ABT841D 40 C to +85 CSO24 plastic small outline package; 24 leads;

body width 7.5 mm SOT137-1

74ABT841DB 40 C to +85 CSSOP24 plastic shrink small outline package; 24 leads;

body width 5.3 mm SOT340-1

74ABT841PW 40 C to +85 CTSSOP24 plastic thin shrink small outline package; 24 leads;

body width 4.4 mm SOT355-1

Fig 1. Logic symbol Fig 2. IEC logic symbol

001aae911

1OE

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

D0 D1 D2 D3 D4 D5 D6 D7

23 22 21 20 19 18 17 16

23456789

13 LE

13 C1

223

322

421

520

619

718

817

916

10 15

11 14

001aae912

Fig 3. Logic diag ram

001aae913

Q1 Q4

45623 7891011

21 20 1923

22 18 17 16 15 14

Product data sheet Rev. 4 — 7 November 2011 3 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 4. Pin configuratio n

74ABT841

OE VCC

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

D8 Q8

D9 Q9

GND LE

001aae910

Table 2. Pin description

Symbol Pin Description

OE 1output enable input (active LOW)

D0 to D9 2, 3, 4, 5, 6, 7, 8, 9,10, 11 data input

GND 12 ground (0 V)

LE 13 latch enable input (active falling edge)

Q0 to Q9 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 data output

VCC 24 positive supply voltage

Product data sheet Rev. 4 — 7 November 2011 4 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

6. Functional description

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;

 = HIGH-to-LOW clock transition;

NC = no change;

X = don’t care;

Z = high-impedance OFF-state.

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.

Table 3. Function table[1]

Input Output Operating mode

OE LE nD Q0 to Q9

LHLLtransparent

L H H H

Ll L latched

Lh H

H X X Z high-impedance

LLXNC hold

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +7.0 V

VIinput voltage [1] 1.2 +7.0 V

VOoutput voltage ou t pu t in OFF-st at e or HIGH-state [1] 0.5 +5.5 V

IIK input clamping current VI < 0 V 18 -mA

IOK output clamping current VO < 0 V 50 -mA

IOoutput current output in LOW-state -128 mA

Tjjunction temperature [2] -150 C

Tstg storage temperature 65 +150 C

Product data sheet Rev. 4 — 7 November 2011 5 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 4.5 -5.5 V

VIinput voltage 0 - VCC V

VIH HIGH-level input voltage 2.0 --V

VIL LOW-level input voltage --0.8 V

IOH HIGH-level output current 32 --mA

IOL LOW-level output current --64 mA

t/Vinput transition rise and fall rate 0- 5ns/V

Tamb ambient temperature in free air 40 -+85 C

Table 6. Static characteristics

Symbol Parameter Conditions 25 C40 C to +85 CUnit

Min Typ Max Min Max

VIK input clamping voltage VCC = 4.5 V; IIK = 18 mA 1.2 0.9 -1.2 - V

VOH HIGH-level output

voltage VI = VIL or VIH

VCC = 4.5 V; IOH = 3 mA 2.5 3.5 -2.5 - V

VCC = 5.0 V; IOH = 3 mA 3.0 4.0 -3.0 - V

VCC = 4.5 V; IOH = 32 mA 2.0 2.6 -2.0 - V

VOL LOW-level output

voltage VCC = 4.5 V; IOL = 64 mA;

VI = VIL or VIH

-0.42 0.55 -0.55 V

VOL(pu) power-up LOW-level

output voltage VCC = 5.5 V; IO = 1 mA;

VI = GND or VCC

[1] -0.13 0.55 -0.55 V

IIinput leakage current VCC = 5.5 V; VI = GND or 5.5 V

control pins -0.01 1.0 -1.0 A

data pins -5100 -100A

IOFF power-off leakage

current VCC = 0 V; VI or VO  4.5 V - 5.0 100 -100 A

IO(pu/pd) power-up/power-down

output current VCC = 2.0 V; VO = 0.5 V;

VI = GND or VCC; OEn HIGH [2] -5.0 50 -50 A

IOZ OFF-state output current VCC = 5.5 V; VI = VIL or VIH

VO = 2.7 V - 5.0 50 -50 A

VO = 0.5 V - 5.0 50 -50 A

ILO output leakage current HIGH-state; VO = 5.5 V;

VCC = 5.5 V; VI = GND or VCC

-5.0 50 -50 A

IOoutput current VCC = 5.5 V; VO = 2.5 V [3] 180 100 50 180 50 mA

Product data sheet Rev. 4 — 7 November 2011 6 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

[2] This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V  10 %, a

transition time of up to 100 s is permitted.

[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

[4] This is the increase in supply current for each input at 3.4 V.

10. Dynamic characteristics

ICC supply current VCC = 5.5 V; VI = GND or VCC

outputs HIGH-state -0.5 250 -250 A

outputs LOW-state -25 38 -38 mA

outputs disabled -0.5 250 -250 A

ICC additional supply current per input pin; VCC = 5.5 V; one

input at 3.4 V; other inputs at VCC

or GND

[4] -0.5 1.5 -1.5 mA

CIinput capacitance VI = 0 V or VCC - 4 - - - pF

COoutput capacitance outputs disabled; VO = 0 V or VCC - 7 - - - pF

Table 6. Static characteristics …continued

Symbol Parameter Conditions 25 C40 C to +85 CUnit

Min Typ Max Min Max

Table 7. Dynamic characteristics

GND = 0 V; for test circuit, see Figure 9.

Symbol Parameter Conditions 25 C; VCC = 5.0 V 40 C to +70 C;

VCC = 5.0 V  0.5 V Unit

Min Typ Max Min Max

tPLH LOW to HIGH

propagation delay Dn to Qn; see Figure 5 2.1 4.1 5.5 2.1 6.2 ns

LE to Qn; see Figure 62.1 4.1 5.9 2.1 6.5 ns

tPHL HIGH to LOW

propagation delay Dn to Qn; see Figure 5 2.0 4.0 5.5 2.0 6.2 ns

LE to Qn; see Figure 62.8 4.6 6.2 2.8 6.7 ns

tPZH OFF-state to HIGH

propagation delay OE to Qn; see Figure 7 1.0 3.0 4.5 1.0 5.3 ns

tPZL OFF-state to LOW

propagation delay OE to Qn; see Figure 7 2.2 4.1 5.6 2.2 6.3 ns

tPHZ HIGH to OFF-state

propagation delay OE to Qn; see Figure 7 2.7 4.7 6.2 2.7 7.1 ns

tPLZ LOW to OFF-state

propagation delay OE to Qn; see Figure 7 2.8 4.6 6.1 2.8 6.5 ns

tsu(H) set-up time HIGH Dn to LE; see Figure 8 2.5 1.0 -2.5 -ns

tsu(L) set-up time LOW Dn to LE; see Figure 8 1.5 0 - 1.5 -ns

th(H) hold time HIGH Dn to LE; see Figure 8 1.5 0.2 -1.5 -ns

th(L) hold time LOW Dn to LE; see Figure 8 +1.0 0.8 -1.0 -ns

tWH pulse width HIGH LE; see Figure 6 3.3 1.9 -3.3 -ns

tWL pulse width LOW LE; see Figure 6 3.3 1.9 -3.3 -ns

Product data sheet Rev. 4 — 7 November 2011 7 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

11. Waveforms

VM = 1.5 V

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 5. Propagation delay for data to output

001aae916

PLH

PHL

GND

VM = 1.5 V

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6. Propagation delay, latch enable input to output and enable pulse width

001aae914

PHL

PLH

GND

VM = 1.5 V

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. 3-state output (Qn) enable and dis a bl e tim e s

001aal299

tPLZ

tPHZ

outputs

disabled outputs

enabled

VOH − 0.3 V

VOL + 0.3 V

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

OE input

VOL

VOH

3.5 V

GND

tPZL

tPZH

Product data sheet Rev. 4 — 7 November 2011 8 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

VM = 1.5 V

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 8. Data set-up and hold times

001aae918

GND

su(H)

h(H)

su(L)

h(L)

GND

a. Input pulse definition b. Test circuit

Test data and VEXT levels are given in Table 8.

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = Test voltage for switching times.

Fig 9. Test circuit for measuring switching times

001aai298

VMVM

10 %

90 % 90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

90 %

10 % 10 %

VEXT

VCC

VIVO

mna616

DUT

Table 8. Test data

Input Load VEXT

VIfItWtr, tfCLRLtPHL, tPLH tPZH, t PHZ tPZL, tPLZ

3.0 V 1 MHz 500 ns  2.5 ns 50 pF 500 open open 7.0 V

Product data sheet Rev. 4 — 7 November 2011 9 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

12. Package outline

Fig 10. Package outline SOT137-1 (SO24)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 15.6

15.2 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT137-1

detail X

vMA

(A )

0.25

075E05 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.61

0.60 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

99-12-27

03-02-19

Product data sheet Rev. 4 — 7 November 2011 10 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

Fig 11. Package outline SOT340-1 (SSOP24)

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.38

0.25 0.20

0.09 8.4

8.0 5.4

5.2 0.65 1.25

7.9

7.6 0.9

0.7 0.8

0.4 8

0.13 0.10.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

1.03

0.63

SOT340-1 MO-150 99-12-27

03-02-19

detail X

vMA

(A )

112

24 13

0.25

pin 1 index

0 2.5 5 mm

scale

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

max.

Product data sheet Rev. 4 — 7 November 2011 11 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

Fig 12. Package outline SOT355-1 (TSSOP24)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 7.9

7.7 4.5

4.3 0.65 6.6

6.2 0.4

0.3 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT355-1 MO-153 99-12-27

03-02-19

0.25 0.5

0.2

112

24 13

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

max.

1.1

Product data sheet Rev. 4 — 7 November 2011 12 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

13. Abbreviations

14. Revision history

Table 9. Abbreviations

Acronym Description

BiCMOS Bipolar Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74ABT841 v.4 20111107 Product data sheet -74ABT841 v.3

Modifications: •Legal pages updated.

74ABT841 v.3 20100325 Product data sheet -74ABT841 v.2

74ABT841 v.2 20100302 Product data sheet -74ABT841

74ABT841 19950906 Product specification - -

Product data sheet Rev. 4 — 7 November 2011 13 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

15. Legal information

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[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

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Preliminary [short] dat a sheet Qualification This document contains data from the preliminar y specification.

Product [short] dat a sheet Production This document cont ains the product specification.

Product data sheet Rev. 4 — 7 November 2011 14 of 15

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

Non-automotive qualified products — Unless this data sheet expressly

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the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor tested

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16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74ABT841

10-bit bus interface latch; 3-state

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 November 2011

Document identifier: 74ABT841

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

16 Contact information. . . . . . . . . . . . . . . . . . . . . 14

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15