Ultra37000™ CPLD Family
Document #: 38-03007 Rev. ** Page 5 of 67
Low-Power Option
Each logic block can operate in high-speed mode for critical
path performance, or in low-power mode for power conserva-
tion. The logic block mode is set by the user on a logic block
by logic block basis.
Product Term Allocator
Through the product term allocator , software automatically dis-
tributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 prod uct terms are available from
the local product term array. The product term allocator pro-
vides two important capabilities without affecting performance:
product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to mac rocell s as nee ded . For exam ple, i f one macroc ell
requires ten produ ct terms whil e anoth er needs jus t thr ee, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other . On Ultra37000 devices, prod-
uct terms are steered on an individual basis. Any number be-
tween 0 and 16 product terms can be steered to any macrocell.
Note that 0 prod uct terms is u sef ul in cases wh ere a partic ular
macrocell is unused or used as an input register.
Product Term Sharing
Product term sharing is the p rocess of using the same product
term among multiple macrocells. For example, if more than
one output has one or more product terms in its equation that
are common to other outputs, those product terms are only
programmed once. The Ultra37000 product term allocator al-
lows sharing a cross g roups of fo ur output macro cells in a vari-
able fashion. The software automatically takes advantage of
this capability—the user does not have to intervene.
Note th at nei ther pro duct t erm shari ng nor prod uct term steer-
ing hav e any effe ct on the spe ed of the produc t. All worst-cas e
steering and sharing configuration s have been incorporated i n
the timing specifications for the Ultra37000 devices.
Ultra37000 Macroce ll
Within each logic block there are 16 macrocells. Macrocells
can either be I/O Macrocells, which include an I/O Cell which
is associated with an I/O pin, or buried Macrocells, which do
not connect to an I/O. The combination of I/O Macrocells and
buried Macrocells varies from device to device.
Buried Macrocell
Figure 2 displays the architecture of buried macrocells. The
buried m ac r ocell featu res a reg is ter that ca n be con f ig ure d a s
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered
latch.
The regis ter can be asynchro nously s et or asyn chronous ly re-
set at the logic block level with the separate set and reset prod-
uct terms. Each of these product terms features programma-
ble polarity. This allows the registers to be set or reset based
on an AND expression or an OR expression.
Clocking of the register is very flex ible. Four global synchro-
nous cl ocks and a product term clock are available to cl ock the
register. Furthermore, each clock features programmable po-
larity so that registers can be triggered on falling as well as
rising edges (see the Clocking section). Clock polarity is cho-
sen at the logic block level.
The buried macrocell also supports input register capability.
The buri ed macro cell ca n be con figure d to act as an inpu t reg-
ister (D-type or latch) whose input comes from the I/O pin as-
sociat ed wi th the neigh boring macro cell. The ou tput of all b ur-
ied macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 2 illustrates the architecture of the I/O macrocell. The
I/O mac rocell support s the sa me func tions as th e buried mac-
rocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active H IGH signal s. This ha s the adde d advantag e of
allowing significant logic reduction to occur in many applica-
tions.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up re sisto r, is a weak latc h conn ected to the pin that doe s
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-in-
terface applications. Bus-hold additionally allows unused de-
vice pi ns to remain un connecte d on the board , which i s partic-
ularly useful during prototyping as designers can route new
signals to the device without cutting trace connections to VCC
or GND. For more information, see the application note “Un-
derstanding Bus-Hold − A Feature of Cypress CPLDs.”
Programmable Slew Rate Control
Each outp ut has a pr ogrammab le config uration bit , which set s
the output slew rate to fast or slow . For designs concerned with
meeting FCC em issi ons st andards the sl ow ed ge prov ides f or
lower system noise. For designs requiring very high perfor-
mance the fast edge rate provides maximum system perfor-
mance.