1. General description
The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. The device features an output
enable (OE) input for easy cascading and a send/receive (DIR) input for direction control.
OE controls the outputs so that the buses are effectively isolated.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 Vand 5 V applications.
The 74LVCH245A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when VCC = 0 V
Bus hold on all data inputs (74LVCH245A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Rev. 7 — 5 April 2012 Product data sheet
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 2 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
3. Ordering information
4. Functional diagram
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC245AD 40 C to +125 C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74LVCH245AD
74LVC245ADB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74LVCH245ADB
74LVC245APW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74LVCH245APW
74LVC245ABQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enh anced
very thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
74LVCH245ABQ
74LVC245ABX 40 C to +125 C DHXQFN20U plastic dual in-line compatible thermal enhanced
extremely thin quad flat package; no leads; 20
terminals; UTLP based; body 2.5 4.5 0.5 mm
SOT1045-1
74LVCH245ABX
Fig 1. Logic diagram Fig 2. IEC logic symbol
2
1DIR
18
19
B0
B1
B2
B3
B4
B5
B6
B7
3
17
4
16
5
15
6
14
7
13
8
12
9
A0
A1
A2
A3
A4
A5
A6
A7
11
OE
mna174
173
1
19
2
1
16
4
15
5
14
6
13
7
12
8
119
18
G3
3EN1
3EN2
2
mna175
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 3 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration for SO20 and (T)SSOP20 Fig 4. Pin configuration for DHVQFN20 and
DHXQFN20U
74LVC245A
74LVCH245A
DIR VCC
A0 OE
A1 B0
A2 B1
A3 B2
A4 B3
A5 B4
A6 B5
A7 B6
GND B7
001aak292
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
001aak293
74LVC245A
74LVCH245A
Transparent top view
B6
A6
A7
B5
A5 B4
A4 B3
A3 B2
A2 B1
A1 B0
A0 OE
GND
B7
DIR
V
CC
912
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area
GND
(1)
Table 2. Pin description
Symbol Pin Description
DIR 1 direction control
A0 to A7 2, 3, 4, 5, 6, 7, 8, 9 data input/output
GND 10 ground (0 V)
B0 to B7 18, 17, 16, 15, 14, 13, 12, 11 data input/output
OE 19 output enable input (active LOW)
VCC 20 supply voltage
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 4 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance OFF-state.
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C derate linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN20 and DHXQFN20U packages: above 60 C derate linearly with 4.5 mW/K.
Table 3. Function selection[1]
Inputs Inputs/outputs
OE DIR An Bn
L L An = Bn inputs
L H inputs Bn = An
HXZZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clampi n g cu rre nt VI<0V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO>V
CC or VO<0V - 50 mA
VOoutput voltage output HIGH or LOW [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.5 V
IOoutput current VO=0V toV
CC -50 mA
ICC supply cur ren t - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[3] -500mW
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 5 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - 3.6 V
VIinput voltage 0 - 5.5 V
VOoutput voltage output HIGH or LOW 0 - VCC V
output 3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.2 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage
VI=V
IH or VIL
IO=100 A;
VCC = 1.65 V to 3.6 V VCC 0.2 - - VCC 0.3 - V
IO=4mA; V
CC = 1.65 V 1.2 - - 1.05 - V
IO=8mA; V
CC = 2.3 V 1.8 - - 1.65 - V
IO=12 mA; VCC = 2.7 V 2.2 - - 2.05 - V
IO=18 mA; VCC = 3.0 V 2.4 - - 2.25 - V
IO=24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage
VI=V
IH or VIL
IO=100A;
VCC = 1.65 V to 3.6 V --0.2 - 0.3V
IO=4mA; V
CC = 1.65 V - - 0 .45 - 0.65 V
IO=8mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=12mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=24mA; V
CC = 3.0 V - - 0.55 - 0.8 V
IIinput leakage
current VI= 5.5 V or G ND;
VCC =3.6V [2] -0.1 5-20 A
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 6 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25C.
[2] The bus hold circuit is switched off when VI>V
CC allowing 5.5 V on the input terminal.
[3] For I/O ports the parameter IOZ includes the input leakage current.
[4] Valid for data inputs of bus hold parts only (74LVCH245A). Note that control inputs do not have a bus hold circuit.
[5] The specified sustaining current at the data input holds the input below the specified VI level.
[6] The specified overdrive current at the data input forces the data input to the opposite input state.
IOZ OFF-state
output current VI=V
IH or VIL;
VO=5.5VorGND;
VCC =3.6V
[3] -0.1 5-20 A
IOFF power-off
leakage
current
VIor VO=5.5V; V
CC = 0.0
V-0.1 10 - 20 A
ICC supply
current VI=V
CC or GND; IO=0A;
VCC =3.6V -0.110 - 40A
ICC additional
supply
current
per input pin;
VI=V
CC 0.6 V; IO=0A;
VCC = 2.7 V to 3.6 V
- 5 500 - 5000 A
CIinput
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-4.0- - -pF
CI/O input/output
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-10- - -pF
IBHL bus hold
LOW current VCC = 1.65; VI = 0.58 V [4][5] 10 - - 10 - A
VCC = 2.3; VI = 0.7 V 30 - - 25 - A
VCC = 3.0; VI = 0.8 V 75 - - 60 - A
IBHH bus hold
HIGH current VCC = 1.65; VI = 1.07 V [4][5] 10 - - 10 - A
VCC = 2.3; VI = 1.7 V 30 - - 25 - A
VCC = 3.0; VI = 2.0 V 75 - - 60 - A
IBHLO bus hold
LOW
overdrive
current
VCC = 1.95 V 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V [4][6] 500 - - 500 - A
IBHHO bus hold
HIGH
overdrive
current
VCC = 1.95 V 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V [4][6] 500 - - 500 - A
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 7 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
10. Dynamic characteristics
[1] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs.
Table 7. Dynamic characteristics
Vo ltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[2] Max Min Max
tpd propagation
delay nAn to nBn; nBn to nAn; see Figure 5 [1]
VCC = 1.2 V - 17.0 - - - ns
VCC = 1.65 V to 1.95 V 1.5 6.5 14.6 1.5 16.9 ns
VCC = 2.3 V to 2.7 V 1.0 3.4 7.6 1.0 8.7 n s
VCC = 2.7 V 1.5 3.4 7.3 1.5 9.5 ns
VCC = 3.0 V to 3.6 V 1.5 2.9 6.3 1.5 8.0 ns
ten enable time nOE to nAn, nBn; see Figure 6 [1]
VCC = 1.2 V - 22.0 - - - ns
VCC = 1.65 V to 1.95 V 1.9 8.3 19.5 1.9 22.5 ns
VCC = 2.3 V to 2.7 V 1.5 4.6 10.7 1.5 12.4 ns
VCC = 2.7 V 1.5 4.8 9.5 1.5 12.0 ns
VCC = 3.0 V to 3.6 V 1.5 3.7 8.5 1.5 11.0 ns
tdis disable time nOE to nAn, nBn; see Figure 6 [1]
VCC = 1.2 V - 12.0 - - - ns
VCC = 1.65 V to 1.95 V 2.9 5.5 12.3 2.9 14.2 ns
VCC = 2.3 V to 2.7 V 1.0 3.1 7.1 1.0 8.2 ns
VCC = 2.7 V 1.5 3.9 8.0 1.5 10.0 ns
VCC = 3.0 V to 3.6 V 1.7 3.6 7.0 1.7 9.0 ns
tsk(o) output skew
time [3] - - 1.0 - 1.5 ns
CPD power
dissipation
capacitance
per input; VI=GNDtoV
CC [4]
VCC = 1.65 V to 1.95 V - 7.7 - - - pF
VCC = 2.3 V to 2.7 V - 11.3 - - - pF
VCC = 3.0 V to 3.6 V - 14.4 - - - pF
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 8 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
11. AC waveforms
See Table 8 for measurement points
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. Input (An, Bn) to output (Bn, An) propagation delays and output transition times
mna176
An, Bn input
Bn, An output
t
PLH
t
PHL
GND
V
I
V
M
V
M
V
M
V
M
V
OH
V
OL
See Table 8 for measurement points
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Enable and disable times
mna367
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 8. Measurement points
Supply voltage VMInput
VCC VItr=t
fVXVY
1.2 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V
1.65 V to 1.95 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V
2.3 V to 2.7 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V
2.7V 1.5V 2.7V 2.5 ns VOL + 0.3 V VOH 0.3 V
3.0V to 3.6V 1.5V 2.7V 2.5 ns VOL + 0.3 V VOH 0.3 V
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 9 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
CL
RT
RL
RL
G
Table 9. Test data
Supply voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
1.65 V to 1.95 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND
2.7V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 10 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
12. Package outline
Fig 8. Package outline SOT163-1 (SO20)
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 11 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Fig 9. Package outline SOT339-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 12 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Fig 10. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 13 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Fig 11. Package outline SOT764-1 (DHVQFN20)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 14 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Fig 12. Package outline SOT1045-1 (DHXQFN20U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT1045-1 - - -- - -
SOT1045-1
07-12-01
09-08-04
UNIT A
max
mm 0.5 0.05
0.00 0.30
0.18 3.35
3.05 2.6
2.4 1.35
1.05 0.5 0.45
0.25 0.13
0.05 0.05
A1
DIMENSIONS (mm are the original dimensions)
DHXQFN20U: plastic dual in-line compatible thermal enhanced extremely thin quad flat package;
no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm
b D
4.6
4.4
DhE Ehe e1
3.5
L L1v
0.1
w y
0.05
y1
0.1
C
y
C
y1
X
b
terminal 1
index area e1
e
e
AC B
vMCw M
Dh
Eh
L1
L
29
10
1
20
19 12
11
terminal 1
index area
B A
D
E
detail X
A1
A
0 2.5 5 mm
scale
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 15 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Mo del
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC_ LVCH245A v.7 20120405 Product data sheet - 74LVC_LVCH245A v.6
Modifications: •Table note 4 of Table 6: corrected (errata)
74LVC_ LVCH245A v.6 20111125 Product data sheet - 74LVC_LVCH245A v.5
Modifications: •Table 4, Table 5, Table 6, Table 7, and Table 9: values added for lower voltage ranges.
74LVC_ LVCH245A v.5 20090825 Product data sheet - 74LVC_LVCH245A v.4
74LVC_ LVCH245A v.4 20090703 Product data sheet - 74LVC_LVCH245A v.3
74LVC_LVCH245A v.3 20030507 Product specification - 74LVC245A_74LVCH245A v.2
74LVC2 45A_74LVCH245A v.2 20020620 Product specification - 74LVC245A_74LVCH245A v.1
74LVC2 45A_74LVCH245A v.1 19971219 Product specification - -
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 16 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full dat a
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-crit ical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors prod ucts in such equipment or
applications and theref ore such inclusi on and/o r use is at the cu stome r’s own
risk.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipme nt, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expect ed
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contain s t he product specification.
74LVC_LVCH245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 5 April 2012 17 of 18
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 April 2012
Document i dentifier: 74 L VC_LVCH245A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16 Contact information. . . . . . . . . . . . . . . . . . . . . 17
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18