M32C/80 Group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
page 1
65fo5002,10.voN01.1.veR 0110-8300B30JER
REJ03B0038-0110
Rev.1.10
Nov. 01, 2005
1. Overview
The M32C/80 Group microcomputer is a single-chip control unit that utilizes high-performance silicon gate
CMOS technology with the M32C/80 series CPU core. The M32C/80 Group is available in 100-pin plastic
molded LQFP/QFP package.
With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabili-
ties to process complex instructions by less bytes and execute instructions at higher speed.
It incorporates a multiplier and DMAC adequate for office automation, communication devices and industrial
equipments and other high-speed processing applications.
The M32C/80 Group is ROMless device.
Use the M32C/80 Group in microprocessor mode after reset.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
65fo5002,10.voN01.1.veR 0110-8300B30JER
1. Overview
page 2
puorG08/C23M
1.2 Performance Overview
Table 1.1 lists performance overview of the M32C/80 Group.
Table 1.1 M32C/80 Group Performance
Item Performance
CPU Basic Instructions 108 instructions
Minimum Instruction Execution Time 31.3 ns ( f(BCLK)=32 MHz, VCC1=4.2 to 5.5 V )
41.7 ns ( f(BCLK)=24 MHz, VCC1=3.0 to 5.5 V )
Operating Mode
Single-chip mode, Memory expansion mode, Microprocessor mode
Memory Space 16 Mbytes
Memory Capacity See Table 1.2
Peripheral
I/O Port 47 I/O pins (when using 16-bit bus) and 1 input pin
function Multifunction Timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Intelligent I/O Communication Function 2 channels
Serial I/O 5 channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus(1), I2C Bus(2)
A/D Converter 10-bit A/D converter: 1 circuit, 10 channels
D/A Converter 8 bits x 2 channels
DMAC 4 channels
DMAC II Can be activated by all peripheral function interrupt sources
Immediate transfer, operation and chain transfer function
CRC Calculation Circuit CRC-CCITT
X/Y Converter 16 bits x 16 bits
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt 34 internal sources and 8 external sources, 5 software sources
Interrupt priority level: 7
Clock Generation Circuit 4 circuits
Main Clock oscillation circuit (*), Sub clock oscillation circuit (*),
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor
Oscillation Stop Detect Function Main clock oscillation stop detect circuit
Electrical
Supply Voltage VCC1=4.2 to 5.5 V, VCC2=3.0 to VCC1 (f(BCLK)=32 MHz)
Charact- VCC1=3.0 to 5.5 V, VCC2=3.0 to VCC1 (f(BCLK)=24 MHz)
eristics Power Consumption 22 mA (VCC1=VCC2=5 V, f(BCLK)=32 MHz)
17 mA (VCC1=VCC2=3.3 V, f(BCLK)=24 MHz)
10 µA (VCC1=VCC2=3.3 V, f(BCLK)=32 kHz, in wait mode)
Operating AmbientTemperature –20 to 85oC, –40 to 85oC(optional)
Package 100-pin plastic molded LQFP/QFP
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
All options are on a request basis.
65fo5002,10.voN01.1.veR 0110-8300B30JER
1. Overview
page 3
puorG08/C23M
1.3 Block Diagram
Figure 1.1 shows a block diagram of the M32C/80 Group microcomputer.
Figure 1.1 M32C/80 Group Block Diagram
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT Multiplier
M32C/80 series CPU core
Clock Generating Circuit
X
IN
- X
OUT
X
CIN
- X
COUT
On-chip Oscillator
PLL Frequency Synthesizer
A/D Converter
1 circuit
Standard: 8 inputs
Maximum: 10 inputs
UART/
Clock Synchronous Serial I/O
5 channels
X/Y converter
16 bits X 16 bits CRC Calcilation Circuit (CCITT)
X
16
+X
12
+X
5
+1
Timer (16 bits)
Timer A: 5 channels
Timer B: 6 channels
Three-phase Motor Control Circuit
Watchdog Timer (15 bits)
D/A Converter
8 bits X 2 channels
Peripheral Functions
RAM
Memory
Port P0
8
Port P6
8
Port P7
8
DMAC
DMACII
Intelligent I/O
Communication Function
2 channels
<
V
CC2>
Port P8
7
P8
5
Port P9
8
Port P10
8
<VCC1>
Port P1
8
Port P2
8
Port P3
8
Port P4
8
Port P5
8
(1) (2) (1) (1) (1) (1)
NOTES:
1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode.
2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor mode
and all external data buses are selected as 8-bit buses.
65fo5002,10.voN01.1.veR 0110-8300B30JER
1. Overview
page 4
puorG08/C23M
Figure 1.2 Product Numbering System
1.4 Product Information
Table 1.2 lists the product information. Figure 1.2 shows the product numbering system.
Table 1.2 M32C/80 Group As of November, 2005
Package type:
FP = Package PRQP0100JB-A (100P6S-A)
GP = Package PLQP0100KB-A (100P6Q-A)
Memory type:
S = ROMless version
M 3 0 8 0 0 S A G P - B L
M32C/80 Group
M16C Family
RAM capacity, pin count, etc
On-chip boot loader
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65fo5002,10.voN01.1.veR 0110-8300B30JER
1. Overview
page 5
puorG08/C23M
1.5 Pin Assignment
Figures 1.3 and 1.4 show pin assignments (top view).
Figure 1.3 Pin Assignment
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
M32C/80 GROUP
SRxD4 / SDA4 / TxD4 / ANEX1 / P9
6
CLK4 / ANEX0 / P9
5
SS4 / RTS4 / CTS4 / TB4
IN
/ DA1 / P9
4
SS3 / RTS3 / CTS3 / TB3
IN
/ DA0 / P9
3
SRxD3 / SDA3 / TxD3 / TB2
IN
/ P9
2
STxD3 / SCL3 / RxD3 / TB1
IN
/ P9
1
CLK3 / TB0
IN
/ P9
0
BYTE
CNVss
X
CIN
/ P8
7
X
COUT
/ P8
6
RESET
X
OUT
Vss
X
IN
Vcc1
NMI / P8
5
INT2 / P8
4
INT1 / P8
3
INT0 / P8
2
U / TA4
IN
/ P8
1
ISRxD0 / U / TA4
OUT
/ P8
0
ISCLK0 / TA3
IN
/ P7
7
ISTxD0 / TA3
OUT
/ P7
6
ISRxD1 / W / TA2
IN
/ P7
5
ISCLK1 / W / TA2
OUT
/ P7
4
ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1
IN
/ P7
3
CLK2 / V / TA1
OUT
/ P7
2
STxD2 / SCL2 / RxD2 / TA0
IN
/ TB5
IN
/ P7
1
SRxD2 / SDA2 / TxD2 / TA0
OUT
/ P7
0
P4
4
/ CS3 / A
20
P4
5
/ CS2 / A
21
P4
6
/ CS1 / A
22
P4
7
/ CS0 / A
23
P5
0
/ WRL / WR
P5
1
/ WRH / BHE
P5
2
/ RD
P5
3
/ CLK
OUT
/ BCLK / ALE
P5
4
/ HLDA / ALE
P5
5
/ HOLD
P5
6
/ ALE
P5
7
/ RDY
P6
0
/ CTS0 / RTS0 / SS0
P6
1
/ CLK0
P6
2
/ RxD0 / SCL0 / STxD0
P6
3
/ TxD0 / SDA0 / SRxD0
P6
4
/ CTS1 / RTS1 / SS1
P6
5
/ CLK1
P6
6
/ RxD1 / SCL1 / STxD1
P6
7
/ TxD1 / SDA1 / SRxD1
P1
0
/ D
8
P1
1
/ D
9
P1
2
/ D
10
P1
3
/ D
11
P1
4
/ D
12
P1
5
/ D
13
/ INT3
P1
6
/ D
14
/ INT4
P1
7
/ D
15
/ INT5
P2
0
/ A
0
( / D
0
)
P2
1
/ A
1
( / D
1
)
P2
2
/ A
2
( / D
2
)
P2
3
/ A
3
( / D
3
)
P2
4
/ A
4
( / D
4
)
P2
5
/ A
5
( / D
5
)
P2
6
/ A
6
( / D
6
)
P2
7
/ A
7
( / D
7
)
Vss
P3
0
/ A
8
( / D
8
)
Vcc2
P3
1
/ A
9
( / D
9
)
P3
2
/ A
10
( / D
10
)
P3
3
/ A
11
( / D
11
)
P3
4
/ A
12
( / D
12
)
P3
5
/ A
13
( / D
13
)
P3
6
/ A
14
( / D
14
)
P3
7
/ A
15
( / D
15
)
P4
0
/ A
16
P4
1
/ A
17
P4
2
/ A
18
P4
3
/ A
19
D
7
/ P0
7
D
6
/ P0
6
D
5
/ P0
5
D
4
/ P0
4
D
3
/ P0
3
D
2
/ P0
2
D
1
/ P0
1
D
0
/ P0
0
KI
3
/ AN
7
/ P10
7
KI
2
/ AN
6
/ P10
6
KI
1
/ AN
5
/ P10
5
KI
0
/ AN
4
/ P10
4
AN
3
/ P10
3
AN
2
/ P10
2
AN
1
/ P10
1
AVss
AN
0
/ P10
0
V
REF
AVcc
RxD4 / AD
TRG
/ P9
7
STxD4 / SCL4 /
<V
CC2
>
<V
CC1
>
NOTE:
1. P7
0
and P7
1
are ports for the N-channel open drain output.
PRQP0100JB-A
(100P6S-A)
65fo5002,10.voN01.1.veR 0110-8300B30JER
1. Overview
page 6
puorG08/C23M
Figure 1.4 Pin Assignment
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
30
29
28
27
26
76
77
78
79
80
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
M32C/80 GROUP
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
SRxD3 / SDA3 / TxD3 / TB2IN / P92
STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
BYTE
CNVss
XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc1
NMI / P85
INT2 / P84
INT1 / P83
INT0 / P82
U / TA4IN / P81
ISRxD0 / U / TA4OUT / P80
ISCLK0 / TA3IN / P77
ISTxD0 / TA3OUT / P76
ISRxD1 / W / TA2IN / P75
ISCLK1 / W / TA2OUT / P74
ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
P42 / A18
P43 / A19
P44 / CS3 / A20
P45 / CS2 / A21
P46 / CS1 / A22
P47 / CS0 / A23
P50 / WRL / WR
P51 / WRH / BHE
P52 / RD
P53 / CLKOUT / BCLK / ALE
P54 / HLDA / ALE
P55 / HOLD
P56 / ALE
P57 / RDY
P60 / CTS0 / RTS0 / SS0
P61 / CLK0
P62 / RxD0 / SCL0 / STxD0
P63 / TxD0 / SDA0 / SRxD0
P64 / CTS1 / RTS1 / SS1
P65 / CLK1
P66 / RxD1 / SCL1 / STxD1
P67 / TxD1 / SDA1 / SRxD1
P70 / TA0OUT / TxD2 / SDA2 / SRxD2
P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2
P72 / TA1OUT / V / CLK2
P13 / D11
P14 / D12
P15 / D13 / INT3
P16 / D14 / INT4
P17 / D15 / INT5
P20 / A0 ( / D0 )
P21 / A1 ( / D1 )
P22 / A2 ( / D2 )
P23 / A3 ( / D3 )
P24 / A4 ( / D4 )
P25 / A5 ( / D5 )
P26 / A6 ( / D6 )
P27 / A7 ( / D7 )
Vss
P30 / A8 ( / D8 )
Vcc2
P31 / A9 ( / D9 )
P32 / A10 ( / D10 )
P33 / A11 ( / D11 )
P34 / A12 ( / D12 )
P35 / A13 ( / D13 )
P36 / A14 ( / D14 )
P37 / A15 ( / D15 )
P40 / A16
P41 / A17
D10 / P12
D9 / P11
D8 / P10
D7 / P07
D6 / P06
D5 / P05
D4 / P04
D3 / P03
D2 / P02
D1 / P01
D0 / P00
KI3 / AN7 / P107
KI2 / AN6 / P106
KI1 / AN5 / P105
KI0 / AN4 / P104
AN3 / P103
AN2 / P102
AN1 / P101
AVss
AN0 / P100
VREF
AVcc
STxD4 / SCL4 / RxD4 / ADTRG / P97
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
CLK4 / ANEX0 / P95
<
V
CC2><
V
CC2>
<
V
CC1><
V
CC1>
NOTE:
1. P7
0
and P7
1
are ports for the N-channel open drain output.
PLQP0100KB-A
(100P6Q-A)
65fo5002,10.voN01.1.veR 0110-8300B30JER
1. Overview
page 7
puorG08/C23M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE
CNV
SS
X
CIN
X
COUT
RESET
X
OUT
V
SS
X
IN
V
CC1
P9
6
P9
5
P9
4
P9
3
P9
2
P9
1
P9
0
P8
7
P8
6
P8
5
P8
4
P8
3
P8
2
P8
1
P8
0
P7
7
P7
6
P7
5
P7
4
P7
3
P7
2
P7
1
P7
0
P6
7
P6
6
P6
5
P6
4
P6
3
P6
2
P6
1
P6
0
P5
7
P5
6
P5
5
P5
4
P5
3
P5
2
P5
1
P5
0
P4
7
P4
6
P4
5
P4
4
NMI
INT2
INT1
INT0
TB4
IN
TB3
IN
TB2
IN
TB1
IN
TB0
IN
TA4
IN
/U
TA4
OUT
/U
TA3
IN
TA3
OUT
TA2
IN
/W
TA2
OUT
/W
TA1
IN
/V
TA1
OUT
/V
TB5
IN
/TA0
IN
TA0
OUT
TxD4/SDA4/SRxD4
CLK4
CTS4/RTS4/SS4
CTS3/RTS3/SS3
TxD3/SDA3/SRxD3
RxD3/SCL3/STxD3
CLK3
CTS2/RTS2/SS2
CLK2
RxD2/SCL2/STxD2
TxD2/SDA2/SRxD2
TxD1/SDA1/SRxD1
RxD1/SCL1/STxD1
CLK1
CTS1/RTS1/SS1
TxD0/SDA0/SRxD0
RxD0/SCL0/STxD0
CLK0
CTS0/RTS0/SS0
ANEX1
ANEX0
DA1
DA0
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
RDY
ALE
HOLD
HLDA/ALE
CLK
OUT
/BCLK/ALE
RD
WRH/BHE
WRL/WR
CS0/A
23
CS1/A
22
CS2/A
21
CS3/A
20
Package
Pin No
FP GP
Control
pins Port Timer
pins UART
pins Bus control
pins
Analog
pins
Interrupt
pins Intelligent I/O
pins
ISRxD0
ISCLK0
ISTxD0
ISRxD1
ISCLK1
ISTxD1
Table 1.3 Pin Characteristics
65fo5002,10.voN01.1.veR 0110-8300B30JER
1. Overview
page 8
puorG08/C23M
Table 1.3 Pin Characteristics (Continued)
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
V
CC2
V
SS
AV
SS
AV
CC
P4
3
P4
2
P4
1
P4
0
P3
7
P3
6
P3
5
P3
4
P3
3
P3
2
P3
1
P3
0
P2
7
P2
6
P2
5
P2
4
P2
3
P2
2
P2
1
P2
0
P1
7
P1
6
P1
5
P1
4
P1
3
P1
2
P1
1
P1
0
P0
7
P0
6
P0
5
P0
4
P0
3
P0
2
P0
1
P0
0
P10
7
P10
6
P10
5
P10
4
P10
3
P10
2
P10
1
P10
0
P9
7
AN
7
AN
6
AN
5
AN
4
AN
3
AN
2
AN
1
AN
0
V
REF
AD
TRG
A
19
A
18
A
17
A
16
A
15
(/D
15
)
A
14
(/D
14
)
A
13
(/D
13
)
A
12
(/D
12
)
A
11
(/D
11
)
A
10
(/D
10
)
A
9
(/D
9
)
A
8
(/D
8
)
A
7
(/D
7
)
A
6
(/D
6
)
A
5
(/D
5
)
A
4
(/D
4
)
A
3
(/D
3
)
A
2
(/D
2
)
A
1
(/D
1
)
A
0
(/D
0
)
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
INT5
INT4
INT3
KI
3
KI
2
KI
1
KI
0
RxD4/SCL4/STxD4
FP GP
Package
pin No Control
pins Port Timer
pins UART
pins Bus control
pins
Analog
pins
Interrupt
pins Intelligent I/O
pins
65fo5002,10.voN01.1.veR 0110-8300B30JER
1. Overview
page 9
puorG08/C23M
Apply 3.0 to 5.5 V to both VCC1 and VCC2 pins. Apply 0 V to the
VSS pin. VCC1 ≥ VCC2(1)
Supplies power for the A/D converter. Connect the AVCC pin to
VCC1 and the AVSS pin to VSS
The microcomputer is in a reset state when "L" is applied to the
____________
RESET pin
Connect this pin to VCC1
Switches the data bus in external memory space 3. The data
bus is 16 bits long when the this pin is held "L" and 8 bits long
when the this pin is held "H". Set it to either one.
Inputs and outputs data (D0 to D7) while accessing an external
memory space with separate bus
Inputs and outputs data (D8 to D15) while accessing an external
memory space with 16-bit separate bus
Outputs address bits (A0 to A22)
Outputs inversed address bit A23
Inputs and outputs data (D0 to D7) and outputs 8 low-order
address bits (A0 to A7) by time-sharing while accessing an
external memory space with multiplexed bus
Inputs and outputs data (D8 to D15) and outputs 8 middle-order
address bits (A8 to A15) by time-sharing while accessing an
external memory space with multiplexed bus
______ ______
Output CS0 to CS3 that are chip-select signals specifying an external space
_______ ________ ______ ________ _____ _______ ________
Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and WRH
______ _______
can be switched with WR and BHE by program
________ _________ _____
WRL, WRH and RD are selected:
If external data bus is 16 bits wide, data is writtenn to an even
_______
address when WRL is held "L". ________
Data is written to an odd address when WRH is held "L".
_____
Data is read when RD is held "L".
______ ________ _____
WR, BHE and RD are selected ______
Data is written to external memory space when WR is held "L".
_____
Data is read when RD is held "L". ________
An odd address is accessed when BHE is held "L".
______ ________ _____
Select WR, BHE and RD for an external 8-bit data bus
ALE is a signal latching address __________
The microcomputer is placed in a hold state while the HOLD pin
is held "L"
Outputs an "L" siganl while the microcomputer is placed in a hold state
Bus is placed in a wait state while the RDY pin is held "L"
VCC1, VCC2
VSS
AVCC
AVSS
____________
RESET
CNVSS
BYTE
D0 to D7
D8 to D15
A0 to A22
______
A23
A0/D0 to
A7/D7
A8/D8 to
A15/D15
______ ______
CS0 to CS3
________ ______
WRL/WR
_________ ________
WRH/BHE
_____
RD
ALE
__________
HOLD
__________
HLDA
________
RDY
Power supply
Analog power
supply input
Reset input
CNVSS
External data
bus width
select input
Bus control
pins
I
I
I
I
I
I/O
I/O
O
O
I/O
I/O
O
O
O
I
O
I
-
VCC1
VCC1
VCC1
VCC1
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
Supply
Signal name Pin name I/O type Description
voltage
1.6 Pin Description
Table 1.4 Pin Description
I: Input O: Output I/O: Input and output
NOTE:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
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1. Overview
page 10
puorG08/C23M
XIN
XOUT
XCIN
XCOUT
BCLK
CLKOUT
_______ _______
INT0 to INT2
_______ _______
INT3 to INT5
_______
NMI
_____ _____
KI0 to KI3
TA0OUT to
TA4OUT
TA0IN to
TA4IN
TB0IN to
TB5IN
__ __
U, U, V, V,
__
W, W
_________
CTS0 to
_________
CTS4
_________
RTS0 to
_________
RTS4
CLK0 to
CLK4
RxD0 to
RxD4
TxD0 to
TxD4
SDA0 to
SDA4
SCL0 to
SCL4
STxD0 to
STxD4
SRxD0 to
SRxD4
______ _______
SS0 to SS4
Main clock input
Main clock
output
Sub clock input
Sub clock
output
BCLK output
Clock output
______
INT interrupt
input
_______
NMI interrupt input
Key input interrupt
Timer A
Timer B
Three-phase motor
control output
Serial I/O
I2C mode
Serial I/O
special function
VCC1
VCC1
VCC1
VCC1
VCC2
VCC2
VCC1
VCC2
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
I
O
I
O
O
O
I
I
I
I/O
I
I
O
I
O
I/O
I
O
I/O
I/O
I
I
I
I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT. To apply
external clock, input the clock from XIN and leave XOUT open
I/O pins for a sub clock oscillation circuit. Connect a crystal
oscillator between XCIN and XCOUT. To apply external clock,
input the clock from XCIN and leave XCOUT open
Outputs BCLK signal
Outputs clock having thesame frequency as fC, f8, or f32
______
Input pins for the INT interrupt
_______
Input pin for the NMI interrupt
Input pins for the key input interrupt
I/O pins for the timer A0 to A4
(TA0OUT is a pin for the N-channel open drain output.)
Input pins for the timer A0 to A4
Input pins for the timer B0 to B5
output pins for the three-phase motor control timer
Input pins for data transmission control
Output pins for data reception control
Inputs and outputs the transfer clock
Inputs serial data
Outputs serial data (TxD2 is a pin for the N-channel open drain
output.)
Inputs and outputs serial data (SDA2 is a pin for for the N-
channel open drain output.)
Inputs and outputs the transfer clock (SCL2 is a pin for the N-
channel open drain output.)
Outputs serial data when slave mode is selected (SDA2 is a pin
for the N-channel open drain output.)
Inputs serial data when slave mode is selected
Input pins to control serial I/O special function
Supply
Signal name Pin name I/O type Description
voltage
Table 1.4 Pin Description (Continued)
I: Input O: Output I/O: Input and output
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1. Overview
page 11
puorG08/C23M
VREF
AN0 to AN7
___________
ADTRG
ANEX0
ANEX1
DA0, DA1
ISCLK0
ISCLK1
ISTxD0
ISTxD1
ISRxD0
ISRxD1
P0
0
to P0
7(1)
P1
0
to P1
7(2)
P2
0
to P2
7(1)
P3
0
to P3
7(1)
P4
0
to P4
7(1)
P5
0
to P5
7(1)
P60 to P67
P70 to P77
P90 to P97
P100 to P107
P80 to P84,
P86, P87
P85
Reference
voltage input
A/D converter
D/A converter
Intelligent I/O
communication
function
I/O port
-
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC2
VCC1
VCC1
VCC1
Applies reference voltage for the A/D converter and D/A converter
Analog input pins for the A/D converter
Input pin for an external A/D trigger
Extended analog input pin for the A/D converter and output pin in
external op-amp connection mode
Extended analog input pin for the A/D converter
Output pin for the D/A converter
Inputs and outputs clock for the intelligent I/O communication
fucntion
Outputs data for the intelligent I/O communication fucntion
Inputs data for the intelligent I/O communication fucntion
I/O ports fro CMOS. Each port can be programmed for nput or
output under the control of the direction register. An input port
can be set, by program, for a pull-up resistor available or for no
pull-up resistor available in 4-bit units
I/O ports having equivalent functions to P0
(P70 and P71 are ports for the N-channel open drain output.)
I/O ports having equivalent functions to P0
_______ _______
Shares a pin with NMI. NMI input state can be got by reading P8
5
I
I
I
I/O
I
O
I/O
O
I
I/O
I/O
I/O
I
Supply
Signal name Pin name I/O type Description
voltage
Table 1.5 Pin Description (Continued)
I: Input O: Output I/O: Input and output
NOTES:
1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode. They
cannot be used as I/O ports.
2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor
mode and all external data buses are selected as 8-bit buses.
Page 12
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puorG08/C23M
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers.
The register bank is comprised of 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers.
Two sets of register banks are provided.
Figure 2.1 CPU Register
b23
R0H R0L
R1H R1L
R2
R3
b31
R2
R3
A0
A1
SB
FB
USP
ISP
INTB
PC
High-speed Interrupt Registers
b15 b0
b23
SVF
SVP
VCT
DMAC-associated Registers
b7 b0
b23
DMD0
DCT0
DCT1
b15
DRC0
DRC1
DMA0
DMA1
DMD1
DRA0
DRA1
Data Register
(1)
Address Register
(1)
Static Base Register
(1)
Frame Base Register
(1)
User Stack Pointer
Interrupt Stack Pointer
Interrupt Table Register
Program Counter
Flag Save Register
PC Save Register
Vector Register
DMA Mode Register
DMA Transfer Count Register
DMA Transfer Count Reload Register
DMA Memory Address Register
DMA SFR Address Register
DMA Memory Address Reload Register
NOTE:
1. The register bank is comprised of these registers. Two sets of register banks are provided.
General Registers
b15 b0
b15 b0
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Space
Processor Interrupt Priority Level
Reserved Space
FLG Flag Register
IPL U I O B S Z D C
b7b8
DSA0
DSA1
Page 13
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puorG08/C23M
2. Central Processing Unit (CPU)
2.1 General Registers
2.1.1 Data Registers (R0, R1, R2 and R3)
R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be
split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers.
R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and
R3.
2.1.2 Address Registers (A0 and A1)
A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arith-
metic and logic operations.
2.1.3 Static Base Register (SB)
SB is a 24-bit register for SB-relative addressing.
2.1.4 Frame Base Register (FB)
FB is a 24-bit register for FB-relative addressing.
2.1.5 Program Counter (PC)
PC, 24 bits wide, indicates the address of an instruction to be executed.
2.1.6 Interrupt Table Register (INTB)
INTB is a 24-bit register indicating the starting address of an relocatable interrupt vector table.
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP
and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even
addresses to execute an interrupt sequence efficiently.
2.1.8 Flag Register (FLG)
FLG is a 16-bit register indicating a CPU state.
2.1.8.1 Carry Flag (C)
The C flag indicates whether carry or borrow has occurred after executing an instruction.
2.1.8.2 Debug Flag (D)
The D flag is for debug only. Set to "0".
2.1.8.3 Zero Flag (Z)
The Z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0".
2.1.8.4 Sign Flag (S)
The S flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0".
Page 14
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puorG08/C23M
2. Central Processing Unit (CPU)
2.1.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
2.1.8.6 Overflow Flag (O)
The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".
2.1.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is
set to "0" when an interrupt is acknowledged.
2.1.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.1.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
When writing to a reserved space, set to "0". When reading, its content is indeterminate.
2.2 High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows:
- Flag save register (SVF)
- PC save register (SVP)
- Vector register (VCT)
2.3 DMAC-Associated Registers
Registers associated with DMAC are as follows:
- DMA mode register (DMD0, DMD1)
- DMA transfer count register (DCT0, DCT1)
- DMA transfer count reload register (DRC0, DRC1)
- DMA memory address register (DMA0, DMA1)
- DMA SFR address register (DSA0, DSA1)
- DMA memory address reload register (DRA0, DRA1)
Page 15
3. Memory
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puorG08/C23M
3. Memory
Figure 3.1 shows a memory map of the M32C/80 Group.
The M32C/80 Group provides 16-Mbyte address space addressed from 00000016 to FFFFFF16.
The fixed interrupt vectors are allocated from address FFFFDC16 to FFFFFF16. It stores the starting ad-
dress of each interrupt routine.
The internal RAM is allocated from address 00040016 to higher. For example, a 8-Kbyte internal RAM is
allocated from address 00040016 to 0023FF16. Besides storing data, it becomes stacks when the subrou-
tine is called or an interrupt is acknowledged.
SFRs, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O,
timers, is allocated from address 00000016 to 0003FF16. All blank spaces within SFRs are reserved and
cannot be accessed by users.
The special page vector table is addressed from FFFE0016 to FFFFDB16. It is used for the JMPS instruc-
tion and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.
In microprocessor mode, some spaces are reserved and cannot be accessed by users.
SFRs
Internal RAM
Reserved Space
External Space BRK Instruction
Overflow
Undefined Instruction
FFFFFF
16
NMI
000000
16
000400
16
0023FF
16
010000
16
FFFFFF
16
Special Page
Vector Table
Address Match
Watchdog Timer
(1)
Reset
NOTE:
1. Watchdog timer interrupt and oscillation stop detection interrupt share vectors.
FFFFDC
16
FFFE00
16
Figure 3.1 Memory Map
Page 16
4. Special Function Registers (SFRs)
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puorG08/C23M
Address Register Symbol Value after RESET
000016
000116
000216
000316
000416 Processor Mode Register(1) PM0
0000 0011
2
(CNVss pin ="H")
000516 Processor Mode Register 1 PM1 0016
000616 System Clock Control Register 0 CM0 0000 10002
000716 System Clock Control Register 1 CM1 0010 00002
000816
000916 Address Match Interrupt Enable Register AIER 0016
000A16 Protect Register PRCR XXXX 00002
XXXX 10002(BYTE pin ="L")
000B16 External Data Bus Width Control Register DS
XXXX 00002(BYTE pin ="H")
000C16 Main Clock Division Register MCD XXX0 10002
000D16 Oscillation Stop Detection Register CM2 0016
000E16 Watchdog Timer Start Register WDTS XX16
000F16 Watchdog Timer Control Register WDC 000X XXXX2
001016
001116 Address Match Interrupt Register 0 RMAD0 00000016
001216
001316 Processor Mode Register 2 PM2 0016
001416
001516 Address Match Interrupt Register 1 RMAD1 00000016
001616
001716
001816
001916 Address Match Interrupt Register 2 RMAD2 00000016
001A16
001B16
001C16
001D16 Address Match Interrupt Register 3 RMAD3 00000016
001E16
001F16
002016
002116
002216
002316
002416
002516
002616 PLL Control Register 0 PLC0 0001 X0102
002716 PLL Control Register 1 PLC1 000X 00002
002816
002916 Address Match Interrupt Register 4 RMAD4 00000016
002A16
002B16
002C16
002D16 Address Match Interrupt Register 5 RMAD5 00000016
002E16
002F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTE:
1. The PM01 and PM00 bits in the PM0 register maintain values set before reset, even after software reset or watch-
dog timer reset has been performed.
4. Special Function Registers (SFRs)
Page 17
4. Special Function Registers (SFRs)
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puorG08/C23M
Address Register Symbol Value after RESET
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916 Address Match Interrupt Register 6 RMAD6 00000016
003A16
003B16
003C16
003D16 Address Match Interrupt Register 7 RMAD7 00000016
003E16
003F16
004016
004116
004216
004316
004416
004516
004616
004716
004816 External Space Wait Control Register 0 EWCR0 X0X0 00112
004916 External Space Wait Control Register 1 EWCR1 X0X0 00112
004A16 External Space Wait Control Register 2 EWCR2 X0X0 00112
004B16 External Space Wait Control Register 3 EWCR3 X0X0 00112
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 18
4. Special Function Registers (SFRs)
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Address Register Symbol Value after RESET
006016
006116
006216
006316
006416
006516
006616
006716
006816 DMA0 Interrupt Control Register DM0IC XXXX X0002
006916 Timer B5 Interrupt Control Register TB5IC XXXX X0002
006A16 DMA2 Interrupt Control Register DM2IC XXXX X0002
006B16 UART2 Receive /ACK Interrupt Control Register S2RIC XXXX X0002
006C16 Timer A0 Interrupt Control Register TA0IC XXXX X0002
006D16 UART3 Receive /ACK Interrupt Control Register S3RIC XXXX X0002
006E16 Timer A2 Interrupt Control Register TA2IC XXXX X0002
006F16 UART4 Receive /ACK Interrupt Control Register S4RIC XXXX X0002
007016 Timer A4 Interrupt Control Register TA4IC XXXX X0002
007116 UART0/UART3 Bus Conflict Detect Interrupt Control Register BCN0IC/BCN3IC XXXX X0002
007216 UART0 Receive/ACK Interrupt Control Register S0RIC XXXX X0002
007316 A/D0 Conversion Interrupt Control Register AD0IC XXXX X0002
007416 UART1 Receive/ACK Interrupt Control Register S1RIC XXXX X0002
007516 Intelligent I/O Interrupt Control Register 0 IIO0IC XXXX X0002
007616 Timer B1 Interrupt Control Register TB1IC XXXX X0002
007716 Intelligent I/O Interrupt Control Register 2 IIO2IC XXXX X0002
007816 Timer B3 Interrupt Control Register TB3IC XXXX X0002
007916 Intelligent I/O Interrupt Control Register 4 IIO4IC XXXX X0002
007A16 INT5 Interrupt Control Register INT5IC XX00 X0002
007B16
007C16 INT3 Interrupt Control Register INT3IC XX00 X0002
007D16
007E16 INT1 Interrupt Control Register INT1IC XX00 X0002
007F16
008016
008116
008216
008316
008416
008516
008616
008716
008816 DMA1 Interrupt Control Register DM1IC XXXX X0002
008916 UART2 Transmit /NACK Interrupt Control Register S2TIC XXXX X0002
008A16 DMA3 Interrupt Control Register DM3IC XXXX X0002
008B16 UART3 Transmit /NACK Interrupt Control Register S3TIC XXXX X0002
008C16 Timer A1 Interrupt Control Register TA1IC XXXX X0002
008D16 UART4 Transmit /NACK Interrupt Control Register S4TIC XXXX X0002
008E16 Timer A3 Interrupt Control Register TA3IC XXXX X0002
008F16 UART2 Bus Conflict Detect Interrupt Control Register BCN2IC XXXX X0002
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 19
4. Special Function Registers (SFRs)
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Address Register Symbol Value after RESET
009016 UART0 Transmit /NACK Interrupt Control Register S0TIC XXXX X0002
009116 UART1/UART4 Bus Conflict Detect Interrupt Control Register BCN1IC/BCN4IC XXXX X0002
009216 UART1 Transmit/NACK Interrupt Control Register S1TIC XXXX X0002
009316 Key Input Interrupt Control Register KUPIC XXXX X0002
009416 Timer B0 Interrupt Control Register TB0IC XXXX X0002
009516 Intelligent I/O Interrupt Control Register 1 IIO1IC XXXX X0002
009616 Timer B2 Interrupt Control Register TB2IC XXXX X0002
009716 Intelligent I/O Interrupt Control Register 3 IIO3IC XXXX X0002
009816 Timer B4 Interrupt Control Register TB4IC XXXX X0002
009916
009A16 INT4 Interrupt Control Register INT4IC XX00 X0002
009B16
009C16 INT2 Interrupt Control Register INT2IC XX00 X0002
009D16
009E16 INT0 Interrupt Control Register INT0IC XX00 X0002
009F16 Exit Priority Control Register RLVL XXXX 00002
00A016 Interrupt Request Register 0 IIO0IR 0000 000X2
00A116 Interrupt Request Register 1 IIO1IR 0000 000X2
00A216 Interrupt Request Register 2 IIO2IR 0000 000X2
00A316 Interrupt Request Register 3 IIO3IR 0000 000X2
00A416 Interrupt Request Register 4 IIO4IR 0000 000X2
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016 Interrupt Enable Register 0 IIO0IE 0016
00B116 Interrupt Enable Register 1 IIO1IE 0016
00B216 Interrupt Enable Register 2 IIO2IE 0016
00B316 Interrupt Enable Register 3 IIO3IE 0016
00B416 Interrupt Enable Register 4 IIO4IE 0016
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 20
4. Special Function Registers (SFRs)
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Address Register Symbol Value after RESET
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816 XXXX XXXX2
SI/O Receive Buffer Register 0 G0RB
00E916 XXX0 XXXX2
00EA16 Transmit Buffer/Receive Data Register 0 G0TB/G0DR XX16
00EB16
00EC16 Receive Input Register 0 G0RI XX16
00ED16 SI/O Communication Mode Register 0 G0MR 0016
00EE16 Transmit Output Register 0 G0TO XX16
00EF16 SI/O Communication Control Register 0 G0CR 0000 X0112
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 21
4. Special Function Registers (SFRs)
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Address Register Symbol Value after RESET
00F016 Data Compare Register 00 G0CMP0 XX16
00F116 Data Compare Register 01 G0CMP1 XX16
00F216 Data Compare Register 02 G0CMP2 XX16
00F316 Data Compare Register 03 G0CMP3 XX16
00F416 Data Mask Register 00 G0MSK0 XX16
00F516 Data Mask Register 01 G0MSK1 XX16
00F616 Communication Clock Select Register CCS XXXX 00002
00F716
00F816 XX16
Receive CRC Code Register 0 G0RCRC
00F916 XX16
00FA16 0016
Transmit CRC Code Register 0 G0TCRC
00FB16 0016
00FC16 SI/O Expansion Mode Register 0 G0EMR 0016
00FD16 SI/O Expansion Receive Control Register 0 G0ERC 0016
00FE16 SI/O Special Communication Interrupt Detect Register 0 G0IRF 0016
00FF16 SI/O Expansion Transmit Control Register 0 G0ETC 0000 0XXX2
010016
010116
010216
010316
010416
010516
010616
010716
010816
010916
010A16
010B16
010C16
010D16
010E16
010F16
011016
011116
011216
011316
011416
011516
011616
011716
011816
011916
011A16
011B16
011C16
011D16
011E16
011F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 22
4. Special Function Registers (SFRs)
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
Address Register Symbol Value after RESET
012016
012116
012216
012316
012416
012516
012616
012716
012816 XXXX XXXX2
SI/O Receive Buffer Register 1 G1RB
012916 XXX0 XXXX2
012A16 Transmit Buffer/Receive Data Register 1 G1TB/G1DR XX16
012B16
012C16 Receive Input Register 1 G1RI XX16
012D16 SI/O Communication Mode Register 1 G1MR 0016
012E16 Transmit Output Register 1 G1TO XX16
012F16 SI/O Communication Control Register 1 G1CR 0000 X0112
013016 Data Compare Register 10 G1CMP0 XX16
013116 Data Compare Register 11 G1CMP1 XX16
013216 Data Compare Register 12 G1CMP2 XX16
013316 Data Compare Register 13 G1CMP3 XX16
013416 Data Mask Register 10 G1MSK0 XX16
013516 Data Mask Register 11 G1MSK1 XX16
013616
013716
013816 XX16
Receive CRC Code Register 1 G1RCRC
013916 XX16
013A16 0016
Transmit CRC Code Register 1 G1TCRC
013B16 0016
013C16 SI/O Expansion Mode Register 1 G1EMR 0016
013D16 SI/O Expansion Receive Control Register 1 G1ERC 0016
013E16 SI/O Special Communication Interrupt Detection Register 1 G1IRF 0016
013F16 SI/O Expansion Transmit Control Register 1 G1ETC 0000 0XXX2
014016
014116
014216
014316
014416
014516
014616
014716
014816
014916
014A16
014B16
014C16
014D16
to
02AF16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 23
4. Special Function Registers (SFRs)
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
Address Register Symbol Value after RESET
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
02C016 XX16
X0 Register Y0 Register X0R,Y0R
02C116 XX16
02C216 XX16
X1 Register Y1 Register X1R,Y1R
02C316 XX16
02C416 XX16
X2 Register Y2 Register X2R,Y2R
02C516 XX16
02C616 XX16
X3 Register Y3 Register X3R,Y3R
02C716 XX16
02C816 XX16
X4 Register Y4 Register X4R,Y4R
02C916 XX16
02CA16 XX16
X5 Register Y5 Register X5R,Y5R
02CB16 XX16
02CC16 XX16
X6 Register Y6 Register X6R,Y6R
02CD16 XX16
02CE16 XX16
X7 Register Y7 Register X7R,Y7R
02CF16 XX16
02D016 XX16
X8 Register Y8 Register X8R,Y8R
02D116 XX16
02D216 XX16
X9 Register Y9 Register X9R,Y9R
02D316 XX16
02D416 XX16
X10 Register Y10 Register X10R,Y10R
02D516 XX16
02D616 XX16
X11 Register Y11 Register X11R,Y11R
02D716 XX16
02D816 XX16
X12 Register Y12 Register X12R,Y12R
02D916 XX16
02DA16 XX16
X13 Register Y13 Register X13R,Y13R
02DB16 XX16
02DC16 XX16
X14 Register Y14 Register X14R,Y14R
02DD16 XX16
02DE16 XX16
X15 Register Y15 Register X15R,Y15R
02DF16 XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 24
4. Special Function Registers (SFRs)
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
Address Register Symbol Value after RESET
02E016 X/Y Control Register XYC XXXX XX002
02E116
02E216
02E316
02E416 UART1 Special Mode Register 4 U1SMR4 0016
02E516 UART1 Special Mode Register 3 U1SMR3 0016
02E616 UART1 Special Mode Register 2 U1SMR2 0016
02E716 UART1 Special Mode Register U1SMR 0016
02E816 UART1 Transmit/Receive Mode Register U1MR 0016
02E916 UART1 Bit Rate Register U1BRG XX16
02EA16 XX16
UART1 Transmit Buffer Register U1TB
02EB16 XX16
02EC16 UART1 Transmit/Receive Control Register 0 U1C0 0000 10002
02ED16 UART1 Transmit/Receive Control Register 1 U1C1 0000 00102
02EE16 XX16
UART1 Receive Buffer Register U1RB
02EF16 XX16
02F016
02F116
02F216
02F316
02F416 UART4 Special Mode Register 4 U4SMR4 0016
02F516 UART4 Special Mode Register 3 U4SMR3 0016
02F616 UART4 Special Mode Register 2 U4SMR2 0016
02F716 UART4 Special Mode Register U4SMR 0016
02F816 UART4 Transmit/Receive Mode Register U4MR 0016
02F916 UART4 Bit Rate Register U4BRG XX16
02FA16 XX16
UART4 Transmit Buffer Register U4TB
02FB16 XX16
02FC16 UART4 Transmit/Receive Control Register 0 U4C0 0000 10002
02FD16 UART4 Transmit/Receive Control Register 1 U4C1 0000 00102
02FE16 XX16
UART4 Receive Buffer Register U4RB
02FF16 XX16
030016 Timer B3, B4, B5 Count Start Flag TBSR 000X XXXX2
030116
030216 XX16
Timer A1-1 Register TA11
030316 XX16
030416 XX16
Timer A2-1 Register TA21
030516 XX16
030616 XX16
Timer A4-1 Register TA41
030716 XX16
030816 Three-Phase PWM Control Register 0 INVC0 0016
030916 Three-Phase PWM Control Register 1 INVC1 0016
030A16 Three-Phase Output Buffer Register 0 IDB0 XX11 11112
030B16 Three-Phase Output Buffer Register 1 IDB1 XX11 11112
030C16 Dead Time Timer DTT XX16
030D16 Timer B2 Interrupt Generation Frequency Set Counter ICTB2 XX16
030E16
030F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 25
4. Special Function Registers (SFRs)
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
Address Register Symbol Value after RESET
031016 XX16
Timer B3 Register TB3
031116 XX16
031216 XX16
Timer B4 Register TB4
031316 XX16
031416 XX16
Timer B5 Register TB5
031516 XX16
031616
031716
031816
031916
031A16
031B16 Timer B3 Mode Register TB3MR 00XX 00002
031C16 Timer B4 Mode Register TB4MR 00XX 00002
031D16 Timer B5 Mode Register TB5MR 00XX 00002
031E16
031F16 External Interrupt Request Source Select Register IFSR 0016
032016
032116
032216
032316
032416 UART3 Special Mode Register 4 U3SMR4 0016
032516 UART3 Special Mode Register 3 U3SMR3 0016
032616 UART3 Special Mode Register 2 U3SMR2 0016
032716 UART3 Special Mode Register U3SMR 0016
032816 UART3 Transmit/Receive Mode Register U3MR 0016
032916 UART3 Bit Rate Register U3BRG XX16
032A16 XX16
UART3 Transmit Buffer Register U3TB
032B16 XX16
032C16 UART3 Transmit/Receive Control Register 0 U3C0 0000 10002
032D16 UART3 Transmit/Receive Control Register 1 U3C1 0000 00102
032E16 XX16
UART3 Receive Buffer Register U3RB
032F16 XX16
033016
033116
033216
033316
033416 UART2 Special Mode Register 4 U2SMR4 0016
033516 UART2 Special Mode Register 3 U2SMR3 0016
033616 UART2 Special Mode Register 2 U2SMR2 0016
033716 UART2 Special Mode Register U2SMR 0016
033816 UART2 Transmit/Receive Mode Register U2MR 0016
033916 UART2 Bit Rate Register U2BRG XX16
033A16 XX16
UART2 Transmit Buffer Register U2TB
033B16 XX16
033C16 UART2 Transmit/Receive Control Register 0 U2C0 0000 10002
033D16 UART2 Transmit/Receive Control Register 1 U2C1 0000 00102
033E16 XX16
UART2 Receive Buffer Register U2RB
033F16 XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 26
4. Special Function Registers (SFRs)
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTE:
1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has
been performed.
Address Register Symbol Value after RESET
034016 Count Start Flag TABSR 0016
034116 Clock Prescaler Reset Flag CPSRF 0XXX XXXX2
034216 One-Shot Start Flag ONSF 0016
034316 Trigger Select Register TRGSR 00 16
034416 Up/Down Flag UDF 00 16
034516
034616 XX16
Timer A0 Register TA0
034716 XX16
034816 XX16
Timer A1 Register TA1
034916 XX16
034A16 XX16
Timer A2 Register TA2
034B16 XX16
034C16 XX16
Timer A3 Register TA3
034D16 XX16
034E16 XX16
Timer A4 Register TA4
034F16 XX16
035016 XX16
Timer B0 Register TB0
035116 XX16
035216 XX16
Timer B1 Register TB1
035316 XX16
035416 XX16
Timer B2 Register TB2
035516 XX16
035616 Timer A0 Mode Register TA0MR 0016
035716 Timer A1 Mode Register TA1MR 0016
035816 Timer A2 Mode Register TA2MR 0016
035916 Timer A3 Mode Register TA3MR 0016
035A16 Timer A4 Mode Register TA4MR 0016
035B16 Timer B0 Mode Register TB0MR 00XX 00002
035C16 Timer B1 Mode Register TB1MR 00XX 00002
035D16 Timer B2 Mode Register TB2MR 00XX 00002
035E16 Timer B2 Special Mode Register TB2SC XXXX XXX02
035F16 Count Source Prescaler Register(1) TCSPR 0XXX 00002
036016
036116
036216
036316
036416 UART0 Special Mode Register 4 U0SMR4 0016
036516 UART0 Special Mode Register 3 U0SMR3 0016
036616 UART0 Special Mode Register 2 U0SMR2 0016
036716 UART0 Special Mode Register U0SMR 0016
036816 UART0 Transmit/Receive Mode Register U0MR 0016
036916 UART0 Bit Rate Register U0BRG XX 16
036A16 XX16
UART0 Transmit Buffer Register U0TB
036B16 XX16
036C16 UART0 Transmit/Receive Control Register 0 U0C0 0000 10002
036D16 UART0 Transmit/Receive Control Register 1 U0C1 0000 00102
036E16 XX16
UART0 Receive Buffer Register U0RB
036F16 XX16
Page 27
4. Special Function Registers (SFRs)
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
Address Register Symbol Value after RESET
037016
037116
037216
037316
037416
037516
037616
037716
037816 DMA0 Request Source Select Register DM0SL 0X00 00002
037916 DMA1 Request Source Select Register DM1SL 0X00 00002
037A16 DMA2 Request Source Select Register DM2SL 0X00 00002
037B16 DMA3 Request Source Select Register DM3SL 0X00 00002
037C16 XX16
CRC Data Register CRCD
037D16 XX16
037E16 CRC Input Register CRCIN XX16
037F16
038016
XXXX XXXX
2
A/D0 Register 0 AD00
038116 0000 00002
038216 XX16
A/D0 Register 1 AD01
038316 XX16
038416 XX16
A/D0 Register 2 AD02
038516 XX16
038616 XX16
A/D0 Register 3 AD03
038716 XX16
038816 XX16
A/D0 Register 4 AD04
038916 XX16
038A16 XX16
A/D0 Register 5 AD05
038B16 XX16
038C16 XX16
A/D0 Register 6 AD06
038D16 XX16
038E16 XX16
A/D0 Register 7 AD07
038F16 XX16
039016
039116
039216
039316
039416 A/D0 Control Register 2 AD0CON2 XX0X XXX02
039516 A/D0 Control Register 3 AD0CON3 XXXX X0002
039616 A/D0 Control Register 0 AD0CON0 0016
039716 A/D0 Control Register 1 AD0CON1 0016
039816 D/A Register 0 DA0 XX16
039916
039A16 D/A Register 1 DA1 XX16
039B16
039C16 D/A Control Register DACON XXXX XX002
039D16
039E16
039F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 28
4. Special Function Registers (SFRs)
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
Address Register Symbol Value after RESET
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716 Function Select Register D1 PSD1 X0XX XX002
03A816
03A916
03AA16
03AB16
03AC16
03AD16 Function Select Register C3 PSC3 X0XX XXXX2
03AE16
03AF16 Function Select Register C PSC 00X0 00002
03B016 Function Select Register A0 PS0 0016
03B116 Function Select Register A1 PS1 0016
03B216 Function Select Register B0 PSL0 0016
03B316 Function Select Register B1 PSL1 0016
03B416 Function Select Register A2 PS2 00X0 00002
03B516 Function Select Register A3 PS3 0016
03B616 Function Select Register B2 PSL2 00X0 00002
03B716 Function Select Register B3 PSL3 0016
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016 Port P6 Register P6 XX16
03C116 Port P7 Register P7 XX16
03C216 Port P6 Direction Register PD6 0016
03C316 Port P7 Direction Register PD7 0016
03C416 Port P8 Register P8 XX16
03C516 Port P9 Register P9 XX16
03C616 Port P8 Direction Register PD8 00X0 00002
03C716 Port P9 Direction Register PD9 0016
03C816 Port P10 Register P10 XX16
03C916
03CA16 Port P10 Direction Register PD10 0016
03CB16
03CC16
03CD16
03CE16
03CF16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Page 29
4. Special Function Registers (SFRs)
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
Address Register Symbol Value after RESET
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16 Pull-Up Control Register 2 PUR2 0016
03DB16 Pull-Up Control Register 3 PUR3 0016
03DC16
03DD16
03DE16
03DF16
03E016 Port P0 Register(1) P0 XX16
03E116 Port P1 Register(1) P1 XX16
03E216 Port P0 Direction Register(1) PD0 0016
03E316 Port P1 Direction Register(1) PD1 0016
03E416 Port P2 Register(1) P2 XX16
03E516 Port P3 Register(1) P3 XX16
03E616 Port P2 Direction Register(1) PD2 0016
03E716 Port P3 Direction Register(1) PD3 0016
03E816 Port P4 Register(1) P4 XX16
03E916 Port P5 Register(1) P5 XX16
03EA16 Port P4 Direction Register(1) PD4 0016
03EB16 Port P5 Direction Register(1) PD5 0016
03EC16
03ED16
03EE16
03EF16
03F016 Pull-up Control Register 0 PUR0 0016
03F116 Pull-up Control Register 1 PUR1 XXXX 00002
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16 Port Control Register PCR XXXX XXX02
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTE:
1. Pins, functioning as bus control pins, cannot be selected as I/O ports.
Page 30
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
puorG08/C23M
5. Electrical Characteristics
Table 5.1 Absolute Maximum Ratings
lobmySretemaraPnoitidnoCeulaVtinU
V1CC V, 2CC egatloVylppuSV1CC VA= CC 0.6ot3.0- V
V2CC egatloVylppuS-Vot3.0- 1CC V
VA CC egatloVylppuSgolanAV1CC VA= CC 0.6ot3.0- V
VIegatloVtupnIVNC,TESER SS 6P,ETYB, 06P- 77P, 27P- 7,
8P 08P- 79P, 09P- 701P, 001P- 7V, FER X, NI
Vot3.0- 1CC 3.0+V
0P 00P- 71P, 01P- 72P, 02P- 73P, 03P- 7,
4P 04P- 75P, 05P- 7Vot3.0- 2CC 3.0+
7P 07P, 10.6ot3.0-
VOegatloVtuptuO6P06P- 77P, 27P- 78P, 08P- 48P, 68P, 7,
9P 09P- 701P, 001P- 7X, TUO
Vot3.0- 1CC 3.0+V
0P 00P- 71P, 01P- 72P, 02P- 73P, 03P- 7,
4P 04P- 75P, 05P- 7
Vot3.0- 2CC 3.0+
7P 07P, 10.6ot3.0-
dPnoitapissiDrewoP C°52=rpoT005Wm
rpoTerutarepmeTtneibmAgnitarepO /58ot02- 58ot04- )1( C°
gtsTerutarepmeTegarotS 051ot56-C°
:ETON 58ot04-foegnarerutarepmetfieciffoselasruotcatnoC.1 .deriuqersiC°
Page 31
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
puorG08/C23M
Table 5.2 Recommended Operating Conditions
(VCC1= VCC2=3.0V to 5.5V at Topr=– 20 to 85oC unless otherwise specified)
lobmySretemaraP dradnatS tinU
.niM.pyT.xaM
V
1CC
V,
2CC
V(egatloVylppuS
1CC
V
2CC
)0.30.55.5V
VA
CC
egatloVylppuSgolanA V
1CC
V
V
SS
egatloVylppuS 0V
VA
SS
egatloVylppuSgolanA 0V
V
HI
)"H"(hgiHtupnI egatloV 2P
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
5P,
0
5P-
7
V8.0
2CC
V
2CC
V
6P
0
6P-
7
7P,
2
7P-
7
8P,
0
8P-
7)3(
9P,
0
9P-
7
01P,
0
01P-
7
X,
NI
,
VNC,TESER
SS
ETYB, V8.0
1CC
V
1CC
7P
0
7P,
1
V8.0
1CC
0.6
0P
0
0P-
7
1P,
0
1P-
7
)edompihc-elgnisni(V8.0
2CC
V
2CC
0P
0
0P-
7
1P,
0
1P-
7
)edomrosecorporcimdnaedomnoisnapxeyromemni( V5.0
2CC
V
2CC
V
LI
)"L"(woLtupnI egatloV P2
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
5P,
0
5P-
7
0V2.0
2CC
V
6P
0
6P-
7
7P,
0
7P-
7
8P,
0
8P-
7)3(
9P,
0
9P-
7
01P,
0
01P-
7
X,
NI
,
VNC,TESER
SS
ETYB, 0V2.0
1CC
0P
0
0P-
7
1P,
0
1P-
7
)edompihc-elgnisni(0V2.0
2CC
0P
0
0P-
7
1P,
0
1P-
7
)edomrosecorporcimdnaedomnoisnapxeyromemni( 0V61.0
2CC
I
)kaep(HO
hgiHtuptuOkaeP tnerruC)"H"(
)2(
0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
5P,
0
5P-
7
,
6P
0
6P-
7
7P,
2
7P-
7
8P,
0
8P-
4
8P,
6
8P,
7
9P,
0
9P-
7
,
01P
0
01P-
7
0.01-Am
I
)gva(HO
tuptuOegarevA tnerruC)"H"(hgiH
)1(
0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
5P,
0
5P-
7
,
6P
0
6P-
7
7P,
2
7P-
7
8P,
0
8P-
4
8P,
6
8P,
7
9P,
0
9P-
7
,
01P
0
01P-
7
0.5-Am
I
)kaep(LO
woLtuptuOkaeP tnerruC)"L"(
)2(
0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
5P,
0
5P-
7
,
6P
0
6P-
7
7P,
0
7P-
7
8P,
0
8P-
4
8P,
6
8P,
7
9P,
0
9P-
7
,
01P
0
01P-
7
0.01Am
I
)gva(LO
woLtuptuOegarevA tnerruC)"L"(
)1(
0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
5P,
0
5P-
7
,
6P
0
6P-
7
7P,
0
7P-
7
8P,
0
8P-
4
8P,
6
8P,
7
9P,
0
9P-
7
,
01P
0
01P-
7
0.5Am
:SETON .sm001sitnerructuptuoegarevanehwseulavlacipyT.1 IlatoT.2
)kaep(LO
8P,2P,1P,0Prof
6
8P,
7
.sselroAm08ebtsum01Pdna,9P,
IlatoT
)kaep(LO
8Pdna,7P,6P,5P,4P,3Prof
0
8Pot
4
.sselroAm08ebtsum
IlatoT
)kaep(HO
.sselroAm04-ebtsum2Pdna,1P,0Prof
IlatoT
)kaep(HO
8Prof
6
8P,
7
.sselroAm04-ebtsum01Pdna,9P,
IlatoT
)kaep(HO
.sselroAm04-ebtsum5Pdna,4P,3Prof
IlatoT
)kaep(HO
8Pdna,7P,6Prof
0
8Pot
4
.sselroAm04-ebtsum
.3V
HI
Vdna
LI
8Profecnerefer
7
8Pnehwseilppa
7
.troptupnielbammargorpasadesusi
8PnehwylppatonseodtI
7
Xsadesusi
NIC
.
≥
Page 32
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
puorG08/C23M
Table 5.2 Recommended Operating Conditions (Continued)
(VCC1=VCC2=3.0V to 5.5V at Topr=–20 to 85oC unless otherwise specified)
lobmySretemaraP dradnatS tinU
.niM.pyT.xaM
(f KLCB )ycneuqerFnoitarepOUPCV1CC V5.5ot2.4=023zHM
V1CC V5.5ot0.3=042zHM
X(f NI )ycneuqerFtupnIkcolCniaMV1CC V5.5ot2.4=023zHM
V1CC V5.5ot0.3=042zHM
X(f NIC )ycneuqerFkcolCbuS 867.2305zHk
(f gniR )(ycneuqerFrotallicsOpihc-nO52=rpoT)C°5.012zHM
(f LLP )ycneuqerFkcolCLLPV1CC V5.5ot2.4=0123zHM
V1CC V5.5ot0.3=0142zHM
t)LLP(US rezisehtnySycneuqerFLLPezilibatSotemiTtiaWV1CC V0.5=5sm
V1CC V3.3=01sm
Page 33
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
5. Electrical Characteristics
VCC1=VCC2=5V
Table 5.3 Electrical Characteristics
(V
CC1
=V
CC2
=4.2 to 5.5V, V
SS
=0V at Topr= –20 to 85
o
C, f(BCLK)=32MH
Z
unless otherwise specified)
lobmySretemaraPnoitidnoC dradnatS tinU
.niM.pyT.xaM
V
HO
)"H"(hgiHtuptuO egatloV 0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
,
5P
0
5P-
7
I
HO
Am5-= V
CC
-2
0.2 V
CC
2
V
6P
0
6P-
7
7P,
2
7P-
7
8P,
0
8P-
4
8P,
6
8P,
7
9P,
0
-
9P
7
01P,
0
01P-
7
I
HO
Am5-= V
CC
-1
0.2 V
CC
1
0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
,
5P
0
5P-
7
I
HO
002-= µAV
CC
-2
3.0 V
CC
2
V
6P
0
6P-
7
7P,
2
7P-
7
8P,
0
8P-
4
8P,
6
8P,
7
9P,
0
-
9P
7
01P,
0
01P-
7
I
HO
002-= µAV
CC
-1
3.0 V
CC
1
X
TUO
I
HO
Am1-=0.3V
CC
1
V
X
TUOC
rewoPhgiH deilppadaoloN5.2V
rewoPwoL deilppadaoloN6.1
V
LO
)"L"(woLtuptuO egatloV 0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
,
5P
0
5P-
7
6P,
0
6P-
7
7P,
0
7P-
7
8P,
0
8P-
4
8P,
6
,
8P
7
9P,
0
9P-
7
01P,
0
01P-
7
I
LO
Am5=0.2V
0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
,
5P
0
5P-
7
6P,
0
6P-
7
7P,
0
7P-
7
8P,
0
8P-
4
8P,
6
,
8P
7
9P,
0
9P-
7
01P,
0
01P-
7
I
LO
002= µA54.0V
X
TUO
I
LO
Am1=0.2V
X
TUOC
rewoPhgiH deilppadaoloN0V
rewoPwoL deilppadaoloN0
V
+T
V-
-T
siseretsyH 0AT,YDR,DLOH
NI
4AT-
NI
0BT,
NI
5BT-
NI
,
DA,5TNI-0TNI
GRT
,4KLC-0KLC,4STC-0STC,
0AT
TUO
4AT-
TUO
,4DxR-0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS
2.00.1V
TESER2.08.1V
I
HI
)"H"(hgiHtupnI tnerruC 0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
,
5P
0
5P-
7
6P,
0
6P-
7
7P,
0
7P-
7
8P,
0
8P-
7
9P,
0
9P-
7
,
01P
0
01P-
7
X,
NI
VNC,TESER,
SS
ETYB,
V
I
V5=0.5 µA
I
LI
)"L"(woLtupnI tnerruC 0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
,
5P
0
5P-
7
6P,
0
6P-
7
7P,
0
7P-
7
8P,
0
8P-
7
9P,
0
9P-
7
,
01P
0
01P-
7
X,
NI
VNC,TESER,
SS
ETYB,
V
I
V0=0.5- µA
R
PULLUP
ecnatsiseRpu-lluP 0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
,
5P
0
5P-
7
6P,
0
6P-
7
7P,
2
7P-
7
8P,
0
8P-
4
8P,
6
,
8P
7
9P,
0
9P-
7
01P,
0
01P-
7
V
I
V0=0204761kΩ
fR
NIX
ecnatsiseRkcabdeeFX
NI
5.1MΩ
fR
NICX
ecnatsiseRkcabdeeFX
NIC
51MΩ
V
MAR
egatloVybdnatSMARedompotsnI0.2V
I
CC
tnerruCylppuSrewoP,edompihc-elgnisnI tfelerasniptuptuo sniprehtodnanepo Votdetcennocera
SS
.
,evawerauqS,zHM23=)KLCB(f noisividoN 2206Am
,edomtiawnI,zHk23=)KLCB(f C°52=rpoT 01 µA
,spotskcolcelihW52=rpoTC°8.05
µA
,spotskcolcelihW58=rpoTC°02 µA
Page 34
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
5. Electrical Characteristics
VCC1=VCC2=5V
lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU
.niM.pyT.xaM
-noituloseRV
FER
V=
1CC
01stiB
LNIrorrEytiraenilnoNlargetnIV
FER
V=
1CC
V=
2CC
V5=
NA
0
NAot
7
,,0XENA
1XENA 3± BSL
BSL
pma-polanretxE edomnoitcennoc 7± BSL
BSL
LNDrorrEytiraenilnoNlaitnereffiD 1±BSL
-rorrEtesffO 3±BSL
-rorrEniaG 3±BSL
R
REDDAL
reddaLrotsiseRV
=FER
V
1CC
804kΩ
t
VNOC
emiTnoisrevnoCtib-01
)2,1(
60.2 µs
t
VNOC
emiTnoisrevnoCtib-8
)2,1(
57.1 µs
t
PMAS
emiTgnilpmaS
)1(
881.0 µs
V
FER
egatloVecnerefeR 2V
1CC
V
V
AI
egatloVtupnIgolanA 0V
FER
V
:SETON X(fediviD.1
NI
peekot,zHM61gnideecxefi,) φ.sselrozHM61taycneuqerfDA
.noitcnufdlohdnaelpmasehtgnisuhtiW.2
lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU
.niM.pyT.xaM
-noituloseR 8stiB
-ycaruccAetulosbA 0.1%
t
US
emiTputeS 3 µs
R
O
ecnatsiseRtuptuO 40102kΩ
I
FERV
tnerruCtupnIylppuSrewoPecnerefeR)1etoN(5.1Am
:ETON gniebton,retrevnocA/Dehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwtnemerusaeM.1 00"ottessi,desu
61
.dedulcxesiretrevnocD/AehtnireddalrotsiserehT."
I
FERV
Von("0"ottessiretsiger1NOC0DAehtnitibTUCVehtfineveswolf
FER
.)noitcennoc
Table 5.4 A/D Conversion Characteristics (VCC1=VCC2=AVCC=VREF=4.2 to 5.5V, Vss= AVSS = 0V at
Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)
Table 5.5 D/A Conversion Characteristics
(VCC1=VCC2=VREF=4.2 to 5.5V, VSS=AVSS=0V
at Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)
Page 35
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
5. Electrical Characteristics
VCC1=VCC2=5V
lobmySretemaraP dradnatS tinU
.niM.xaM
1cat
)BD-DR(
)dradnatsDR(emiTsseccAtupnIataD )1etoN(sn
1cat
)BD-DA(
)dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(sn
2cat
)BD-DR(
)subdrxelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emiTsseccAtupnIataD )1etoN(sn
2cat
)BD-DA(
)subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDA(emiTsseccAtupnIataD )1etoN(sn
ust
)KLCB-BD(
emiTputeStupnIataD 62sn
ust
)KLCB-YDR(
emiTputeStupnIYDR 62sn
ust
)KLCB-DLOH(
emiTputeStupnIDLOH 03sn
ht
)BD-DR(
emiTdloHtupnIataD 0sn
ht
)YDR-KLCB(
emiTdloHtupnIYDR 0sn
ht
)DLOH-KLCB(
emiTdloHtupnIDLOH 0sn
dt
)ADLH-KLCB(
emiTyaleDtuptuOADLH 52sn
:ETON atresnI.selcycsublanretxednaycnceuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 (f,ycneuqerfnoitarepoehtrewolroetatstiaw
KLCB
.evitagensieulavdetaluclacehtfi,)
lobmySretemaraP dradnatS tinU
.niM.xaM
ctemiTelcyCtupnIkcolClanretxE 52.13sn
wt
)H(
htdiW)"H"(hgiHtupnIkcolClanretxE 57.31sn
wt
)L(
htdiW)"L"(woLtupnIkcolClanretxE 57.31sn
rtemiTesiRkcolClanretxE 5sn
ftemiTllaFkcolClanretxE 5sn
Timing Requirements
(VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr=–20 to 85oC unless otherwise specified)
Table 5.6 External Clock Input
Table 5.7 Memory Expansion Mode and Microprocessor Mode
tac1(RD – DB) =f(BCLK) X 2 – 35
10 X m
9
[ns] (if external bus cycle is aφ + bφ, m=(bx2)+1)
tac2(AD – DB) =f(BCLK) X 2 – 35
10 X p
9
[ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1)
– 35
10 X n
9
[ns] (if external bus cycle is aφ + bφ, n=a+b)
f(BCLK)
tac1(AD – DB) =
tac2(RD – DB) = f(BCLK) X 2 – 35
10 X m
9
[ns] (if external bus cycle is aφ + bφ, m=(bx2)-1)
Page 36
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
5. Electrical Characteristics
VCC1=VCC2=5V
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)AT(
iAT
NI
emiTelcyCtupnI 001sn
wt
)HAT(
iAT
NI
htdiW)"H"(hgiHtupnI 04sn
wt
)LAT(
iAT
NI
htdiW)"L"(woLtupnI 04sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)AT(
iAT
NI
emiTelcyCtupnI 004sn
wt
)HAT(
iAT
NI
htdiW)"H"(hgiHtupnI 002sn
wt
)LAT(
iAT
NI
htdiW)"L"(woLtupnI 002sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)AT(
iAT
NI
emiTelcyCtupnI 002sn
wt
)HAT(
iAT
NI
htdiW)"H"(hgiHtupnI 001sn
wt
)LAT(
iAT
NI
htdiW)"L"(woLtupnI 001sn
lobmySretemaraP dradnatS tinU
.niM.xaM
wt
)HAT(
iAT
NI
htdiW)"H"(hgiHtupnI 001sn
wt
)LAT(
iAT
NI
htdiW)"L"(woLtupnI 001sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)PU(
iAT
TUO
emiTelcyCtupnI 0002sn
wt
)HPU(
iAT
TUO
htdiW)"H"(hgiHtupnI 0001sn
wt
)LPU(
iAT
TUO
htdiW)"L"(woLtupnI 0001sn
ust
)NIT-PU(
iAT
TUO
emiTputeStupnI 004sn
ht
)PU-NIT(
iAT
TUO
emiTdloHtupnI 004sn
Timing Requirements
(VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr=–20 to 85oC unless otherwise specified)
Table 5.8 Timer A Input (Count Source Input in Event Counter Mode)
Table 5.9 Timer A Input (Gate Input in Timer Mode)
Table 5.10 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Table 5.11 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Table 5.12 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Page 37
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
5. Electrical Characteristics
VCC1=VCC2=5V
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)BT(
iBT
NI
)egdeenonodetnuoc(emiTelcyCtupnI 001sn
wt
)HBT(
iBT
NI
)egdeenonodetnuoc(htdiW)"H"(hgiHtupnI 04sn
wt
)LBT(
iBT
NI
)egdeenonodetnuoc(htdiW)"L"(woLtupnI 04sn
ct
)BT(
iBT
NI
)segdehtobnodetnuoc(emiTelcyCtupnI 002sn
wt
)HBT(
iBT
NI
)segdehtobnodetnuoc(htdiW)"H"(hgiHtupnI 08sn
wt
)LBT(
iBT
NI
)segdehtobnodetnuoc(htdiW)"L"(woLtupnI 08sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)BT(
iBT
NI
emiTelcyCtupnI 004sn
wt
)HBT(
iBT
NI
htdiW)"H"(hgiHtupnI 002sn
wt
)LBT(
iBT
NI
htdiW)"L"(woLtupnI 002sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)BT(
iBT
NI
emiTelcyCtupnI 004sn
wt
)HBT(
iBT
NI
htdiW)"H"(hgiHtupnI 002sn
wt
)LBT(
iBT
NI
htdiW)"L"(woLtupnI 002sn
lobmySretemaraP dradnatS tinU
.niMxaM
ct
)DA(
DA
GRT
)reggirtrofderiuqer(emiTelcyCtupnI 0001sn
wt
)LDA(
DA
GRT
htdiW)"L"(woLtupnI 521sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)KC(
emiTelcyCtupnIiKLC 002sn
wt
)HKC(
htdiW)"H"(hgiHtupnIiKLC 001sn
wt
)LKC(
htdiW)"L"(woLtupnIiKLC 001sn
dt
)Q-C(
emiTyaleDtuptuOiDxT 08sn
ht
)Q-C(
emiTdloHiDxT 0sn
ust
)C-D(
emiTputeStupnIiDxR 03sn
ht
)Q-C(
emiTdloHtupnIiDxR 09sn
lobmySretemaraP dradnatS tinU
.niM.xaM
wt
)HNI(
htdiW)"H"(hgiHtupnIiTNI 052sn
wt
)LNI(
htdiW)"L"(woLtupnIiTNI 052sn
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.13 Timer B Input (Count Source Input in Event Counter Mode)
Table 5.14 Timer B Input (Pulse Period Measurement Mode)
Table 5.15 Timer B Input (Pulse Width Measurement Mode)
Table 5.16 A/D Trigger Input
Table 5.17 Serial I/O
_______
Table 5.18 External Interrupt INTi Input
Page 38
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
5. Electrical Characteristics
VCC1=VCC2=5V
lobmySretemaraP tnemerusaeM noitidnoC dradnatS tinU
.niM.xaM
dt )DA-KLCB( emiTyaleDtuptuOsserddA 81sn
ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 3-sn
ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA 0sn
ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(sn
dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81sn
ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 3-sn
ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC 0sn
ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )1etoN(sn
dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81sn
ht )DR-KLCB( emiTdloHtuptuOlangiSDR 5-sn
dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81sn
ht )RW-KLCB( emiTdloHtuptuOlangiSRW 5-sn
dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(sn
ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(sn
wt )RW( htdiWtuptuORW )2etoN(sn
t
d(DB – WR)
= f
(BCLK)
– 20 [ns]
t
h(WR – DB)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – AD)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – CS)
=f
(BCLK)
X 2
10
9
– 10 [ns]
t
w(WR)
=f
(BCLK)
X 2
10 X n
9
– 15 [ns]
1. Values can be obtained from the following equations, according to BCLK frequency.
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles.
(if external bus cycle is aφ + bφ, n=(bx2)-1)
10 X m
9
(if external bus cycle is aφ + bφ, m= b)
NOTES:
See Figure 5.1
Switching Characteristics
(VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.19 Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space)
Page 39
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
5. Electrical Characteristics
VCC1=VCC2=5V
lobmySretemaraP tnemerusaeM noitidnoC dradnatS tinU
.niM.xaM
dt
)DA-KLCB(
emiTyaleDtuptuOsserddA 81sn
ht
)DA-KLCB(
)dradnatsKLCB(emiTdloHtuptuOsserddA 3-sn
ht
)DA-DR(
)dradnatsDR(emiTdloHtuptuOsserddA )1etoN(sn
ht
)DA-RW(
)dradnatsRW(emiTdloHtuptuOsserddA )1etoN(sn
dt
)SC-KLCB(
emiTyaleDtuptuOlangiStceleS-pihC 81sn
ht
)SC-KLCB(
)dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 3-sn
ht
)SC-DR(
)dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC )1etoN(sn
ht
)SC-RW(
)dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )1etoN(sn
dt
)DR-KLCB(
emiTyaleDtuptuOlangiSDR 81sn
ht
)DR-KLCB(
emiTdloHtuptuOlangiSDR 5-sn
dt
)RW-KLCB(
emiTyaleDtuptuOlangiSRW 81sn
ht
)RW-KLCB(
emiTdloHtuptuOlangiSRW 5-sn
dt
)RW-BD(
)dradnatsRW(emiTyaleDtuptuOataD )2etoN(sn
ht
(-RW)BD
)dradnatsRW(emiTdloHtuptuOataD )1etoN(sn
dt
)ELA-KLCB(
)dradnatsKLCB(emiTyaleDtuptuOlangiSELA 81sn
ht
)ELA-KLCB(
)dradnatsKLCB(emiTdloHtuptuOlangiSELA 5-sn
dt
)ELA-DA(
)dradnatssserdda(emiTyaleDtuptuOlangiSELA )3etoN(sn
ht
)DA-ELA(
)dradnatssserdda(emiTdloHtuptuOlangiSELA )4etoN(sn
zdt
)DA-DR(
emiTtratStaolFtuptuOsserddA 8sn
t
d(DB – WR)
= 10 X m
9
– 25 [ns] (if external bus cycle is aφ + bφ, m= (bx2)-1)
t
h(RD – AD)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – AD)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(RD – CS)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – CS)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – DB)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
d(AD – ALE)
= f
(BCLK)
X 2
9
– 20 [ns] (if external bus cycle is aφ + bφ, n= a)
t
h(ALE – AD)
= f
(
BCLK
)
X 2
9
– 10 [ns] (if external bus cycle is aφ + bφ, n= a)
f
(BCLK)
X 2
1. Values can be obtained from the following equations, according to BCLK frequency.
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
3. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
10 X m
10 X n
4. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
10 X n
NOTES:
See Figure 5.1
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.20 Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
Page 40
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
5. Electrical Characteristics
VCC1=VCC2=5V
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
30pF
Figure 5.1 P0 to P10 Measurement Circuit
Page 41
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
puorG08/C23M
Figure 5.2 VCC1=VCC2=5V Timing Diagram (1)
BCLK
RD
18ns.max
-5ns.min
Hi-Z
DB
0ns.min
0ns.min
t
su(DB-BCLK)
t
d(BCLK-RD)
26ns.min
(1)
CSi
t
d(BCLK-CS)
18ns.max
(1)
ADi t
h(BCLK-AD)
-3ns.min
t
h(BCLK-CS)
-3ns.min
BHE
tcyc
t
d(BCLK-AD) 0ns.min
t
ac1(AD-DB)
(2)
WR,WRL,
WRH
18ns.max
-5ns.min
BCLK
CSi
t
d(BCLK-CS)
18ns.max
ADi
t
d(BCLK-AD)
18ns.max -3ns.min
-3ns.min
tcyc
BHE
DBi
t
d(BCLK-WR)
t
h(WR-DB)
(3)
t
d(DB-WR)
=(tcyc x m-20)ns.min
(if external bus cycle is aφ+bφ, m=b)
t
h(WR-DB)
=(tcyc/2-10)ns.min
t
h(WR-AD)
=(tcyc/2-10)ns.min
t
h(WR-CS)
=(tcyc/2-10)ns.min
t
w(WR)
=(tcyc/2 x n-15)ns.min
(
if external bus c
y
cle is a
φ
+b
φ
,
n=
(
bx2
)
-1
)
Vcc
1
=Vcc
2
=5V
t
h(BCLK-RD)
t
h(RD-DB)
t
h(RD-AD)
t
h(RD-CS)
t
h(BCLK-WR)
t
h(BCLK-AD)
t
h(BCLK-CS)
t
h(WR-CS)
(3)
t
h(WR-AD)
(3)
t
w(WR)
(3)
t
ac1(RD-DB)
(2)
18ns.max
(1)
[ Read Timing ] (1φ +1φ Bus Cycle)
[ Write timing ] (1φ +1φ Bus Cycle)
NOTE:
3. Varies with operation frequency: Measurement Conditions:
• VCC1=VCC2=4.2 to 5.5V
• Input high and low voltage: V
IH
=2.5V, V
IL
=0.8V
• Output high and low voltage: V
OH
=2.0V, V
OL
=0.8V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for t
d(BCLK-AD)
+t
su(DB-BCLK)
.
2. Varies with operation frequency:
t
ac1(RD-DB)
=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)+1)
t
ac1(AD-DB)
=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n=a+b)
t
d(DB-WR)
(3)
tcyc= 10
f
(BCLK)
9
Page 42
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
puorG08/C23M
Figure 5.3 VCC1=VCC2=5V Timing Diagram (2)
BCLK
CSi
ADi
RD -5ns.min
BHE
ADi
/DBi
26ns.min
t
d(BCLK-RD)
t
su(DB-BCLK)
t
ac2(RD-DB)
t
dz(RD-AD)
8ns.max
ALE
t
d(BCLK-ALE)
18ns.max
t
d(BCLK-CS)
t
d(AD-ALE)
t
h(ALE-AD)
t
h(BCLK-RD)
t
h(RD-AD)
t
h(RD-DB)
t
d(BCLK-AD)
t
h(BCLK-CS)
t
h(RD-CS)
t
h(BCLK-ALE)
tcyc
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
-5ns.min
BCLK
CSi
ADi
BHE
ADi
/DBi
WR,WRL,
WRH
t
h(WR-CS)
ALE
t
h(BCLK-WR)
t
d(DB-WR)
18ns.max
t
ac2(AD-DB)
[ Read Timing ] (2φ +2φ Bus Cycle)
Address
(1)
(1)
(1)
t
d(AD-ALE)
=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a)
t
h(ALE-AD)
=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a)
t
h(RD-AD)
=(tcyc/2-10)ns.min, t
h(RD-CS)
=(tcyc/2-10)ns.min
t
ac2(RD-DB)
=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1)
t
ac2(AD-DB)
=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1)
NOTE:
1. Varies with operation frequency:
Data input Address
(1)
[ Write Timing ] (2φ +2φ Bus Cycle)
Address Data output Address
(2)
(2)
t
d(AD-ALE)
=(tcyc/2 x n - 20)ns.min
(if external bus cycle is aφ + bφ, n=a)
t
h(ALE-AD)
=(tcyc/2 x n -10)ns.min
(if external bus cycle is aφ + bφ, n=a)
t
h(WR-AD)
=(tcyc/2-10)ns.min,
t
h(WR-CS)
=(tcyc/2-10)ns.min, t
h(WR-DB)
=(tcyc/2-10)ns.min
t
d(DB-WR)
=(tcyc/2 x m-25)ns.min
(
if external bus c
y
cle is a
φ
+ b
φ
, m=
(
b x 2
)
-1
)
NOTE:
2. Varies with operation frequency: Measurement Conditions:
• V
CC1
=V
CC2
=4.2 to 5.5V
• Input high and low voltage:
V
IH
=2.5V, V
IL
=0.8V
• Output high and low voltage:
V
OH
=2.0V, V
OL
=0.8V
Vcc
1
=Vcc
2
=5V
-3ns.min
(1)
t
h(BCLK-AD)
-3ns.min
0ns.min
(1)
18ns.max
-5ns.min
18ns.max
18ns.max
t
h(WR-DB)
(2) t
h(BCLK-AD)
-3ns.min
t
h(WR-AD)
18ns.max
t
d(BCLK-WR)
18ns.max
t
d(BCLK-AD)
t
d(AD-ALE)
(2)
t
d(BCLK-CS)
18ns.max
t
d(BCLK-ALE) -5ns.min
t
h(BCLK-ALE)
tcyc
(2)
t
h(BCLK-CS)
-3ns.min
t
h(ALE-AD)
(2)
tcyc= 10
f
(BCLK)
9
Page 43
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
puorG08/C23M
t
su(D–C)
TAi
IN
Input
TAi
OUT
Input
In event counter mode
TBi
IN
Input
CLKi
TxDi
RxDi
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
tw
(TBH)
t
w(TBL)
t
c(AD)
t
w(ADL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
t
h(T
IN
–UP)
t
su(UP–T
IN
)
TAi
IN
Input
(When counting on the falling edge)
TAi
IN
Input
(When counting on the rising edge)
TAi
OUT
Input
(Counter increment/
decrement input)
INTi Input
AD
TRG
Input
Vcc
1
=Vcc
2
=5V
NMI input
2 CPU clock cycles +
300ns or more
("L" width)
2 CPU clock cycles +
300ns or more
Figure 5.4 VCC1=VCC2=5V Timing Diagram (3)
Page 44
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
puorG08/C23M
th(BCLK–HOLD)
tsu(HOLD–BCLK)
td(BCLK–HLDA)
td(BCLK–HLDA)
Hi–Z
Measurement Conditions
• V
CC1
=V
CC2
=4.2 to 5.5V
• Input high and low voltage: V
IH
=4.0V, V
IL
=1.0V
• Output high and low voltage: V
OH
=2.5V, V
OL
=2.5V
Memory Expansion Mode and Microprocessor Mode
BCLK
HOLD Input
HLDA Output
P0, P1, P2,
P3, P4,
P5
0
to P5
2
RDY input
tsu(RDY–BCLK) th(BCLK–RDY)
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
Vcc
1
=Vcc
2
=5V
Figure 5.5 VCC1=VCC2=5V Timing Diagram (4)
Page 45
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
VCC1=VCC2=3.3V
puorG08/C23M
Table 5.21 Electrical Characteristics
(V
CC1
=V
CC2
=3.0 to 3.6V, V
SS
=0V at Topr = –20 to 85
o
C,
f(BCLK)=24MH
Z
unless otherwise specified)
lobmySretemaraPnoitidnoC dradnatS tinU
.niM.pyT.xaM
V
HO
)"H"(hgiHtuptuO egatloV 0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
,
5P
0
5P-
7
I
HO
Am1-=V
2CC
6.0-V
2CC
V
6P
0
6P-
7
7P,
2
7P-
7
8P,
0
8P-
4
8P,
6
8P,
7
9P,
0
-
9P
7
01P,
0
01P-
7
V
1CC
6.0-V
1CC
V
X
TUO
I
HO
Am1.0-=7.2V
1CC
V
X
TUOC
rewoPhgiH deilppadaoloN5.2V
rewoPwoL deilppadaoloN6.1V
V
LO
)"L"(woLtuptuO egatloV 0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
-
4P
7
5P,
0
5P-
7
6P,
0
6P-
7
7P,
0
7P-
7
8P,
0
8P-
4
,
8P
6
8P,
7
9P,
0
9P-
7
01P,
0
01P-
7
I
LO
Am1=5.0V
X
TUO
I
LO
Am1.0=5.0V
X
TUOC
rewoPhgiH deilppadaoloN0V
rewoPwoL deilppadaoloN0V
V
+T
V-
-T
siseretsyH 0AT,YDR,DLOH
NI
4AT-
NI
0BT,
NI
5BT-
NI
,
DA,5TNI-0TNI
GRT
-0KLC,4STC-0STC,
0AT,4KLC
TUO
4AT-
TUO
-0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS,4DxR
2.00.1V
TESER2.08.1V
I
HI
)"H"(hgiHtupnI tnerruC 0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
-
4P
7
5P,
0
5P-
7
6P,
0
6P-
7
7P,
0
7P-
7
8P,
0
8P-
7
,
9P
0
9P-
7
01P,
0
01P-
7
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NI
VNC,TESER,
SS
,
ETYB
V
I
V3=0.4 µA
I
LI
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0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
-
4P
7
5P,
0
5P-
7
6P,
0
6P-
7
7P,
0
7P-
7
8P,
0
8P-
7
,
9P
0
9P-
7
01P,
0
01P-
7
X,
NI
VNC,TESER,
SS
,
ETYB
V
I
V0=0.4- µA
R
PULLUP
ecnatsiseRpu-lluP 0P
0
0P-
7
1P,
0
1P-
7
2P,
0
2P-
7
3P,
0
3P-
7
4P,
0
4P-
7
,
5P
0
5P-
7
6P,
0
6P-
7
7P,
2
7P-
7
8P,
0
8P-
4
8P,
6
,
8P
7
9P,
0
9P-
7
01P,
0
01P-
7
V
I
V0=0407005kΩ
fR
NIX
ecnatsiseRkcabdeeFX
NI
0.3MΩ
fR
NICX
ecnatsiseRkcabdeeFX
NIC
0.03MΩ
V
MAR
egatloVybdnatSMARedompotsni0.2V
I
CC
ylppuSrewoP tnerruC :noitidnoctnemerusaeM ,edompihc-elgnisnI nepotfelerasniptuptuo erasniprehtodna Votdetcennoc
SS
.
,evawerauqS,zHM42=)KLCB(f noisividoN 7153Am
,edomtiawnI,zHk23=)KLCB(f 52=rpoTC°01 µA
,spotskcolcelihW52=rpoTC°8.05
µA
,spotskcolcelihW58=rpoTC°05 µA
Page 46
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
VCC1=VCC2=3.3V
puorG08/C23M
Table 5.22 A/D Conversion Characteristics (VCC1=VCC2=AVCC=VREF= 3.0 to 3.6V, VSS=AVSS=0V
at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified)
Table 5.23 D/A Conversion Characteristics (
V
CC1
=V
CC2
=
VREF=3.0 to 3.6V, VSS=AVSS=0V
at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified)
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.niM.pyT.xaM
-noituloseRV
FER V= 1CC 01stiB
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1CC V= 2CC V= FER V3.3=2±BSL
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RREDDAL reddaLrotsiseRVFER V= 1CC 0.804kΩ
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US
emiTputeS 3 µs
R
O
ecnatsiseRtuptuO 40102kΩ
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Page 47
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
VCC1=VCC2=3.3V
puorG08/C23M
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.24 External Clock Input
Table 5.25 Memory Expansion Mode and Microprocessor Mode
lobmySretemaraP dradnatS tinU
.niM.xaM
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wt
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wt
)L(
htdiW)"L"(woLtupnIkcolClanretxE 81sn
rtemiTesiRkcolClanretxE 5sn
ftemiTllaFkcolClanretxE 5sn
lobmySretemaraP dradnatS tinU
.niM.xaM
1cat
)BD-DR(
)dradnatsDR(emiTsseccAtupnIataD )1etoN(sn
1cat
)BD-DA(
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2cat
)BD-DR(
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ust
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emiTputeStupnIataD 03sn
ust
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emiTputeStupnIYDR 04sn
ust
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emiTputeStupnIDLOH 06sn
ht
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emiTdloHtupnIataD 0sn
ht
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emiTdloHtupnIYDR 0sn
ht
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emiTdloHtupnIDLOH 0sn
dt
)ADLH-KLCB(
emiTyaleDtuptuOADLH 52sn
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KLCB
.evitagensieulavdetaluclacehtfi,)
tac1(RD – DB) =f(BCLK) X 2 – 35
10 X m
9
[ns] (if external bus cycle is aφ + bφ, m=(bx2)+1)
tac2(AD – DB) =f(BCLK) X 2 – 35
10 X p
9
[ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1)
– 35
10 X n
9
[ns] (if external bus cycle is aφ + bφ, n=a+b)
f(BCLK)
tac1(AD – DB) =
tac2(RD – DB) = f(BCLK) X 2 – 35
10 X m
9
[ns] (if external bus cycle is aφ + bφ, m=(bx2)-1)
Page 48
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
VCC1=VCC2=3.3V
puorG08/C23M
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS= 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.26 Timer A Input (Count Source Input in Event Counter Mode)
Table 5.27 Timer A Input (Gate Input in Timer Mode)
Table 5.28 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Table 5.29 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Table 5.30 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
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emiTelcyCtupnI 001sn
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NI
emiTelcyCtupnI 004sn
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NI
htdiW)"L"(woLtupnI 002sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)AT(
iAT
NI
emiTelcyCtupnI 002sn
wt
)HAT(
iAT
NI
htdiW)"H"(hgiHtupnI 001sn
wt
)LAT(
iAT
NI
htdiW)"L"(woLtupnI 001sn
lobmySretemaraP dradnatS tinU
.niM.xaM
wt
)HAT(
iAT
NI
htdiW)"H"(hgiHtupnI 001sn
wt
)LAT(
iAT
NI
htdiW)"L"(woLtupnI 001sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)PU(
iAT
TUO
emiTelcyCtupnI 0002sn
wt
)HPU(
iAT
TUO
htdiW)"H"(hgiHtupnI 0001sn
wt
)LPU(
iAT
TUO
htdiW)"L"(woLtupnI 0001sn
ust
)NIT-PU(
iAT
TUO
emiTputeStupnI 004sn
ht
)PU-NIT(
iAT
TUO
emiTdloHtupnI 004sn
Page 49
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
VCC1=VCC2=3.3V
puorG08/C23M
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.31 Timer B Input (Count Source Input in Event Counter Mode)
Table 5.32 Timer B Input (Pulse Period Measurement Mode)
Table 5.33 Timer B Input (Pulse Width Measurement Mode)
Table 5.34 A/D Trigger Input
Table 5.35 Serial I/O
_______
Table 5.36 External Interrupt INTi Input
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)BT(
iBT
NI
)egdeenonodetnuoc(emiTelcyCtupnI 001sn
wt
)HBT(
iBT
NI
)egdeenonodetnuoc(htdiW)"H"(hgiHtupnI 04sn
wt
)LBT(
iBT
NI
)egdeenonodetnuoc(htdiW)"L"(woLtupnI 04sn
ct
)BT(
iBT
NI
)segdehtobnodetnuoc(emiTelcyCtupnI 002sn
wt
)HBT(
iBT
NI
)segdehtobnodetnuoc(htdiW)"H"(hgiHtupnI 08sn
wt
)LBT(
iBT
NI
)segdehtobnodetnuoc(htdiW)"L"(woLtupnI 08sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)BT(
iBT
NI
emiTelcyCtupnI 004sn
wt
)HBT(
iBT
NI
htdW)"H"(hgiHtupnI 002sn
wt
)LBT(
iBT
NI
htdiW)"L"(woLtupnI 002sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)BT(
iBT
NI
emiTelcyCtupnI 004sn
wt
)HBT(
iBT
NI
htdiW)"H"(hgiHtupnI 002sn
wt
)LBT(
iBT
NI
htdiW)"L"(woLtupnI 002sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)DA(
DA
GRT
)reggirtrofderiuqer(emiTelcyCtupnI 0001sn
wt
)LDA(
DA
GRT
htdiW)"L"(woLtupnI 521sn
lobmySretemaraP dradnatS tinU
.niM.xaM
ct
)KC(
emiTelcyCtupnIiKLC 002sn
wt
)HKC(
htdiW)"H"(hgiHtupnIiKLC 001sn
wt
)LKC(
htdiW)"L"(woLtupnIiKLC 001sn
dt
)Q-C(
emiTyaleDtuptuOiDxT 08sn
ht
)Q-C(
emiTdloHiDxT 0sn
ust
)C-D(
emiTputeStupnIiDxR 03sn
ht
)Q-C(
emiTdloHtupnIiDxR 09sn
lobmySretemaraP dradnatS tinU
.niM.xaM
wt
)HNI(
htdiW)"H"(hgiHtupnIiTNI 052sn
wt
)LNI(
htdiW)"L"(woLtupnIiTNI 052sn
Page 50
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
VCC1=VCC2=3.3V
puorG08/C23M
lobmySretemaraP tnemerusaeM noitidnoC dradnatS tinU
.niM.xaM
dt )DA-KLCB( emiTyaleDtuptuOsserddA 81sn
ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 0sn
ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA 0sn
ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(sn
dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81sn
ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 0sn
ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC 0sn
ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )1etoN(sn
dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81sn
ht )DR-KLCB( emiTdloHtuptuOlangiSDR 3-sn
dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81sn
ht )RW-KLCB( emiTdloHtuptuOlangiSRW 0sn
dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(sn
ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(sn
wt )RW( htdiWtuptuORW )2etoN(sn
t
d(DB – WR)
= f
(BCLK)
10 x m
9
– 20 [ns] (if external bus cycle is aφ + bφ, m=b)
t
h(WR – DB)
= f
(BCLK)
X 2
10
9
– 20 [ns]
t
h(WR – AD)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – CS)
=f
(BCLK)
X 2
10
9
– 10 [ns]
t
w(WR)
=f
(BCLK)
X 2
10 x n
9
– 15 [ns] (if external bus cycle is aφ + bφ, n=(b x 2)-1)
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles.
See Figure 5.1
Switching Characteristics
(VCC1=VCC2=3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.37 Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space)
Page 51
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
VCC1=VCC2=3.3V
puorG08/C23M
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.38 Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
lobmySretemaraP tnemerusaeM noitidnoC dradnatS tinU
.niM.xaM
dt )DA-KLCB( emiTyaleDtuptuOsserddA 81sn
ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 0sn
ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )1etoN(sn
ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(sn
dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81sn
ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 0sn
ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC )1etoN(sn
ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )1etoN(sn
dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81sn
ht )DR-KLCB( emiTdloHtuptuOlangiSDR 3-sn
dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81sn
ht )RW-KLCB( emiTdloHtuptuOlangiSRW 0sn
dt )RW-BD( )dradnatsRW(emiTyaledtuptuOataD )2etoN(sn
ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(sn
dt )ELA-KLCB( )dradnatsKLCB(emiTyaleDtuptuOlangiSELA 81sn
ht )ELA-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiSELA 2-sn
dt )ELA-DA( )dradnatssserdda(emiTyaleDtuptuOlangiSELA )3etoN(sn
ht )DA-ELA( )dradnatssserdda(emiTdloHtuptuOlangiSELA )4etoN(sn
zdt )DA-DR( emiTtratStaolFtuptuOsserddA 8sn
t
d(DB – WR)
= 10 X m
9
– 25 [ns] (if external bus cycle is aφ + bφ, m=(b+2)-1)
t
h(RD – AD)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – AD)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(RD – CS)
= f
(BCLK)
X 2
10
9
–10 [ns]
t
h(WR – CS)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – DB)
= f
(BCLK)
X 2
10
9
– 20 [ns]
t
d(AD – ALE)
= f
(BCLK)
X 2
10 x n
9
– 20 [ns] (if external bus cycle is aφ + bφ, n=a)
t
h(ALE – AD)
= f
(BCLK)
X 2
10 x n
9
– 10 [ns] (if external bus cycle is aφ + bφ, n=a)
f
(BCLK)
X 2
NOTES:
1. Values can be obtained by the following equations, according to BLCK frequency.
2. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles.
3. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles.
4. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles.
See Figure 5.1
Page 52
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
puorG08/C23M
Figure 5.6 VCC1=VCC2=3.3V Timing Diagram (1)
BCLK
RD 18ns.max
-3ns.min
Hi-Z
DB
0ns.min
0ns.min
td(BCLK-RD)
30ns.min(1)
tac1(RD-DB)(2)
CSi
td(BCLK-CS)
18ns.max(1)
ADi 18ns.max(1) th(BCLK-AD)
0ns.min
th(BCLK-CS)
0ns.min
BHE
tcyc
td(BCLK-AD)
tac1(AD-DB)(2)
WR,WRL,
WRH
18ns.max
0ns.min
BCLK
CSi 18ns.max
ADi 18ns.max 0ns.min
0ns.min
tcyc
BHE
DBi
td(BCLK-WR)
th(BCLK-RD)
th(RD-DB)
th(RD-AD)
tsu(DB-BCLK)
th(RD-CS)
0ns.min
th(BCLK-WR)
td(BCLK-CS)
td(BCLK-AD) th(BCLK-AD)
th(BCLK-CS)
th(WR-CS)(3)
td(DB-WR)(3) th(WR-DB)(3)
th(WR-AD)(3)
[Read Timing] (1φ + 1φ Bus Cycles)
[Write Timing] (1φ + 1φ Bus Cycles)
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
tw(WR)(3)
Vcc1=Vcc2=3.3V
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency.
tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2) + 1)
tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n = a + b)
td(DB-WR)=(tcyc x m-20)ns.min
(if external bus cycle is aφ + bφ, m=b)
th(WR-DB)=(tcyc/2-20)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(if external bus cycle is aφ + bφ, n=(bx2)-1)
NOTE:
3. Varies with operation frequency. Measurement Conditions
• VCC1=VCC2=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
tcyc= 10
f(BCLK)
9
Page 53
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
5. Electrical Characteristics
BCLK
CSi
ADi
RD -3ns.min
BHE
ADi
/DBi
30ns.min
td(BCLK-RD)
tsu(DB-BCLK)
tdz(RD-AD)
8ns.max
ALE
td(BCLK-ALE)
18ns.max
td(AD-ALE) th(ALE-AD)
th(BCLK-RD) th(RD-AD)
td(BCLK-AD)
th(BCLK-CS)
th(RD-CS)
th(BCLK-ALE)
tcyc
Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space and using the multiplexed bus)
0ns.min
BCLK
CSi
ADi
BHE
ADi
/DBi
WR,WRL,
WRH
ALE
th(BCLK-WR)
18ns.max
tac2(AD-DB)
[ Read Timing ] (2φ +2φ Bus Cycles)
Address
(1) (1)
(1)
(1)
(1)
td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a)
th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1)
tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1)
NOTE:
1. Varies with operation frequency:
(1)
[ Write Timing ] (2φ +2φ Bus Cycles)
Address Address
td(AD-ALE)=(tcyc/2 x n - 20)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n -10)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(WR-AD)=(tcyc/2-10)ns.min,
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-20)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
(if external bus cycle is aφ + bφ, m=(b x 2)-1)
NOTE:
2. Varies with operation frequency: Measurement Conditions:
• VCC1=VCC2=3.0 to 3.6V
• Input high and low voltage:
VIH=1.5V, VIL=0.5V
• Output high and low voltage:
VOH=1.5V, VOL=1.5V
Vcc1=Vcc2=3.3V
18ns.max
td(BCLK-WR) th(WR-AD)(2)
th(BCLK-AD)
0ns.min
Data output
th(ALE-AD)
-2ns.min
td(BCLK-ALE) th(BCLK-ALE)
18ns.max
18ns.max
0ns.min
th(WR-CS)
td(AD-ALE)
td(BCLK-CS)
td(BCLK-AD)
th(BCLK-CS)
td(DB-WR) th(WR-DB)
tcyc
(2) (2)
(2)
(2) (2)
18ns.max
18ns.max
18ns.max
0ns.min
0ns.min
tac2(RD-DB)
-2ns.min
td(BCLK-CS)
th(RD-DB) th(BCLK-AD)
0ns.min
Data input Address
tcyc= 10
f(BCLK)
9
Figure 5.7 VCC1=VCC2=3.3V Timing Diagram (2)
Page 54
65fo5002,10.voN01.1.veR 0110-8300B30JER
5. Electrical Characteristics
puorG08/C23M
Figure 5.8 VCC1=VCC2=3.3V Timing Diagram (3)
t
su(D–C)
TAi
IN
Input
TAi
OUT
Input
In event counter mode
TBi
IN
Input
CLKi
TxDi
RxDi
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(AD)
t
w(ADL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
t
h(T
IN
–UP)
t
su(UP–T
IN
)
TAi
IN
Input
(When counting on falling edge)
TAi
IN
Input
(When counting on rising edge)
TAi
OUT
Input
(Counter increment/
decrement input)
INTi Input
AD
TRG
Input
Vcc
1
=Vcc
2
=3.3V
NMI input
2 CPU clock cycles +
300ns or more
("L" width)
2 CPU clock cycles +
300ns or more
Page 55
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
5. Electrical Characteristics
Figure 5.9 VCC1=VCC2=3.3V Timing Diagram (4)
Measurement Conditions:
• V
CC1
=V
CC2
=3.0 to 3.6V
• Input high and low voltage: V
IH
=2.4V, V
IL
=0.6V
• Output high and low voltage: V
OH
=1.5V, V
OL
=1.5V
Memory Expansion Mode and Microprocessor Mode
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5
0
to P5
2
RDY input
t
su(RDY–BCLK)
t
h(BCLK–RDY)
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
Hi–Z
t
h(BCLK–HOLD)
t
su(HOLD–BCLK)
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
Vcc
1
=Vcc
2
=3.3V
Page 56
65fo5002,10.voN01.1.veR 0110-8300B30JER
puorG08/C23M
Package Dimensions
Terminal cross section
b
1
c
1
b
p
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
y
Index mark
x
125
26
50
51
75
76
100
F
*1
*3
*2
Z
E
Z
D
E
D
H
D
H
E
b
p
Detail F
L
1
A
2
A
1
L
A
c
L
1
Z
E
Z
D
c
1
b
1
b
p
A
1
H
E
H
D
y0.08
e0.5
c
0° 8°
x
L0.35 0.5 0.65
0.05 0.1 0.15
A1.7
15.8 16.0 16.2
15.8 16.0 16.2
A
2
1.4
E13.9 14.0 14.1
D13.9 14.0 14.1
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.15 0.20 0.25
0.09 0.145 0.20
0.08
1.0
1.0
0.18
0.125
1.0
Previous CodeJEITA Package Code RENESAS Code
PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV MASS[Typ.]
0.6gP-LQFP100-14x14-0.50
e
Package Dimensions
0.80.5
0.825
0.575
Z
E
Z
D
b
p
A
1
H
E
H
D
y0.10
e0.65
c0°10°
L0.4 0.6 0.8
00.1 0.2
A3.05
16.5 16.8 17.1
22.5 22.8 23.1
A
2
2.8
E13.8 14.0 14.2
D19.8 20.0 20.2
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.25 0.3 0.4
0.13 0.15 0.2
P-QFP100-14x20-0.65 1.6g
MASS[Typ.]
100P6S-APRQP0100JB-A
RENESAS CodeJEITA Package Code Previous Code
y
Index mark
100
81
80 51
50
31
30
1F
*2
*1
*3
Z
E
Z
D
eb
p
A
H
D
D
E
H
E
c
Detail F
A
1
A
2
L
INCLUDE TRIM OFFSET.
DIMENSION "*3" DOES NOT
NOTE)
DO NOT INCLUDE MOLD FLASH.
DIMENSIONS "*1" AND "*2"1.
2.
REVISION HISTORY
Rev. Date Description
Page Summary
M32C/80 Group Datasheet
A-1
0.10 Sep., 02 New Document –
0.11 Sep., 02 Table 1.1.1 “CAN” deleted 3
0.12 Nov., 02 Table 1.1.1
“4.2 to 5.5V” --> “3.0 to 5.5V”
"3.0 to 3.6V (f(XIN)=20MHz without software wait)" deleted
"26mA (f(XIN)=20MHz without software wait,Vcc=3.3V)" deleted
3
1. Overview changed
1.2 Performance Outline changed
1.3 Block Diagram added
1.5 Pin Assignments changed
Table 1.3 Pin Characteristics for 100-Pin Package changed
1.6 Pin Description added
2. Central Processing Unit (CPU) added
3. Memory added
4. Special Function Registers (SFR) added
0.30 Aug., 02 –
All pages Words standardized: On-chip oscillator, A/D converter and D/A converter
Overview
2, 3 • Table 1.1 and 1.2 M32C/80 Group Performance
"When using 16-bit bus" added to I/O ports
"Option" deleted from Serial I/O, I2C bus, and IEBus
"Voltage Detection Circuit" added
Value added to "Power Consumption"
"Flash Memory" added
4• 1.3 Block Diagram Description deleted
5• Figure 1.2 ROM/RAM Capacity deleted
• Table 1.3 M32C/85 Group Note1 deleted
11 • Table 1.5 Pin Description Note 1 added to I/O ports
Memory
23 • Chapter Description modified
• Figure 3.1 Memory Map modified
SFR
16- •"X: Nothing is assigned" modified to "X: Indeterminate"
• "?: Indeterminate” modified to "X: Indeterminate"
• "Users cannot use any symbols with *" deleted
• Register names, symbols, value after RESET of addresses 001716, 001B16,
001F16, 002B16, 002F16, 004C16, and 004D16 deleted
• Value after RESET in the PM0 register revised
16 • Note 3 deleted
29 • Note 1 added to addresses 03E016 to 03EB16
0.40 Jun., 04
1.00 Nov., 04
REVISION HISTORY
Rev. Date Description
Page Summary
M32C/80 Group Datasheet
A-2
Electrical Characteristics
30- • This capter added
All pages
Package code chnaged: 100P6Q-A to PLQP0100KB-A and 100P6S-A to PRQP0100JB-A
Overview
1• Note that the M32C/80 Group is ROMless device added
2•
Table 1.1 M32C/80 Group Performance Item "HDLC Data Processing" changed
to "Intelligent I/O Communication Function"; item "Flash Memory" deleted
3• Figure 1.1 M32C/80 Group Block Diagram Notes 1 and 2 added
9• Table 1.4 Pin Description Supply voltage for analog power supply input modi-
______
fied "-" to "VCC1"; description for CNVSS changed; supply voltage for INT inter-
rupt input modified; note for I/O ports added
Memory
15 • Figure 3.1 Memory Map Disgram changed; note added
Special Function Registers (SFRs)
16 • Note 2 deleted
17 • Values after RESET in the RMAD6 and RMAD7 registers modified
19 • Value after RESET in the RLVL register modified
20 • Value after RESET in the G0RB register modified
21 • Values after RESET in the G0EMR, G0ERC, and G0IRF registers modified
26 • Value after RESET in the TCSPR register modified; note 1 added
27, 28 • Register names, symbols, and value after RESET of addresses 039216 and
03AC16 deleted
28 • Value after RESET in the PSC register modified
Electrical Characteristics
30- • Ports P11 to P15 deleted
32 • Table 5.2 Recpmmended Operating Conditions f(BCLK) standard added
33 • Table 5.3 Electrical Characteristics Max. standard for ICC modified
34 • Table 5.4 A/D Conversion Characteristics AN00 to AN07 deleted from
"
INL
"
row
35 • Table 5.7 Memory Expansion Mode and Microprocessor Mode Expressions
on note 1 corrected
41 • Figure 5.2 VCC1=VCC2=5V Timing Diagram (1) Expression for tcyc added; note 3
corrected
42 • Figure 5.3 VCC1=VCC2=5V Timing Diagram (2) Expression for tcyc added; notes
1 and 2 corrected
46 • Table 5.22 A/D Conversion Characteristics Min. standard for VREF modified
47 • Table 5.25 Memory Expansion Mode and Microprocessor Mode Expres-
sions on note 1 corrected
52 • Figure 5.6 VCC1=VCC2=3.3V Timing Diagram (1) Expression for tcyc added; note
3 corrected
1.10 Nov., 05
REVISION HISTORY
Rev. Date Description
Page Summary
M32C/80 Group Datasheet
A-3
53 • Figure 5.7 VCC1=VCC2=3.3V Timing Diagram (2) Expression for tcyc added;
notes 1 and 2 corrected
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