Precision Micropower,
Low Dropout Voltage References
Data Sheet REF19x Series
Rev. L
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1996–2011 Analog Devices, Inc. All rights reserved.
FEATURES
Temperature coefficient: 5 ppm/°C maximum
High output current: 30 mA
Low supply current: 45 μA maximum
Initial accuracy: ±2 mV maximum1
Sleep mode: 15 μA maximum
Low dropout voltage
Load regulation: 4 ppm/mA
Line regulation: 4 ppm/V
Short-circuit protection
APPLICATIONS
Portable instruments
ADCs and DACs
Smart sensors
Solar powered applications
Loop-current-powered instruments
GENERAL DESCRIPTION
The REF19x series precision band gap voltage references use a
patented temperature drift curvature correction circuit and
laser trimming of highly stable, thin-film resistors to achieve a
very low temperature coefficient and high initial accuracy.
The REF19x series is made up of micropower, low dropout
voltage (LDV) devices, providing stable output voltage from
supplies as low as 100 mV above the output voltage and
consuming less than 45 μA of supply current. In sleep mode,
which is enabled by applying a low TTL or CMOS level to the
SLEEP pin, the output is turned off and supply current is
further reduced to less than 15 μA.
The REF19x series references are specified over the extended
industrial temperature range (−40°C to +85°C) with typical
performance specifications over −40°C to +125°C for
applications, such as automotive.
All electrical grades are available in an 8-lead SOIC package; the
PDIP and TSSOP packages are available only in the lowest
electrical grade.
TEST PINS
Test Pin 1 and Test Pin 5 are reserved for in-package Zener zap.
To achieve the highest level of accuracy at the output, the Zener
zapping technique is used to trim the output voltage. Because
each unit may require a different amount of adjustment, the
resistance value at the test pins varies widely from pin to pin
and from part to part. The user should leave Pin 1 and Pin 5
unconnected.
REF19x
SERIES
TOP VIEW
(Not to Scale)
TP
1
V
S2
SLEEP
3
GND
4
NC
NC
OUTPUT
TP
8
7
6
5
00371-001
NOTES
1. NC = NO CONNECT.
2. TP PINS ARE FACTORY TEST
POINTS, NO USER CONNECTION.
Figure 1. 8-Lead SOIC_N and TSSOP Pin Configuration
(S Suffix and RU Suffix)
REF19x
SERIES
TOP VIEW
(Not to Scale)
TP
1
V
S2
SLEEP
3
GND
4
NC
NC
OUTPUT
TP
8
7
6
5
00371-002
NOTES
1. NC = NO CONNECT.
2. TP PINS ARE FACTORY TEST
POINTS, NO USER CONNECTION.
Figure 2. 8-Lead PDIP Pin Configuration
(P Suffix)
Table 1. Nominal Output Voltage
Part Number Nominal Output Voltage (V)
REF191 2.048
REF192 2.50
REF193 3.00
REF194 4.50
REF195 5.00
REF196 3.30
REF198 4.096
1 Initial accuracy does not include shift due to solder heat effect (see the
Applications Information section).
REF19x Series Data Sheet
Rev. L | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Test Pins ............................................................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Electrical Characteristics—REF191 @ TA = 25°C.................... 4
Electrical Characteristics—REF191 @ −40°C ≤ +85°C........... 5
Electrical Characteristics—REF191 @
−40°C ≤ TA ≤ +125°C................................................................... 6
Electrical Characteristics—REF192 @ TA = 25°C.................... 6
Electrical Characteristics—REF192 @ −40°C ≤ TA ≤ +85°C
......................................................................................................... 7
Electrical Characteristics—REF192 @ −40°C ≤ TA ≤ +125°C
......................................................................................................... 7
Electrical Characteristics—REF193 @ TA = 25°C.................... 8
Electrical Characteristics—REF193 @ −40°C ≤ TA ≤ +85°C
......................................................................................................... 8
Electrical Characteristics—REF193 @ TA ≤ −40°C ≤ +125°C
......................................................................................................... 9
Electrical Characteristics—REF194 @ TA = 25°C.................... 9
Electrical Characteristics—REF194 @ −40°C ≤ TA ≤ +85°C
....................................................................................................... 10
Electrical Characteristics—REF194 @ −40°C ≤ TA ≤ +125°C
....................................................................................................... 10
Electrical Characteristics—REF195 @ TA = 25°C.................. 11
Electrical Characteristics—REF195 @ −40°C ≤ TA ≤ +85°C
....................................................................................................... 11
Electrical Characteristics—REF195 @ −40°C ≤ TA ≤ +125°C
....................................................................................................... 12
Electrical Characteristics—REF196 @ TA = 25°C.................. 12
Electrical Characteristics—REF196 @ −40°C ≤ TA ≤ +85°C
....................................................................................................... 13
Electrical Characteristics—REF196 @ −40°C ≤ TA ≤ +125°C
....................................................................................................... 13
Electrical Characteristics—REF198 @ TA = 25°C.................. 14
Electrical Characteristics—REF198 @ −40°C ≤ TA ≤ +85°C
....................................................................................................... 14
Electrical Characteristics—REF198 @ −40°C ≤ TA ≤ 125°C15
Absolute Maximum Ratings ......................................................... 16
Thermal Resistance.................................................................... 16
ESD Caution................................................................................ 16
Typical Performance Characteristics ........................................... 17
Applications Information.............................................................. 20
Output Short-Circuit Behavior ................................................ 20
Device Power Dissipation Considerations.............................. 20
Output Voltage Bypassing......................................................... 20
Sleep Mode Operation............................................................... 20
Basic Voltage Reference Connections ..................................... 20
Membrane Switch-Controlled Power Supply............................. 20
Solder Hear Effect ...................................................................... 21
Current-Boosted References with Current Limiting............. 21
Negative Precision Reference Without Precision Resistors.. 22
Stacking Reference ICs for Arbitrary Outputs ....................... 22
Precision Current Source .......................................................... 23
Switched Output 5 V/3.3 V Reference..................................... 23
Kelvin Connections.................................................................... 24
Fail-Safe 5 V Reference.............................................................. 24
Low Power, Strain Gage Circuit ............................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 27
Data Sheet REF19x Series
Rev. L | Page 3 of 28
REVISION HISTORY
9/11—Rev. K to Rev. L
Change to Condition Column for Dropout Voltage Parameter,
Table 2 ................................................................................................. 4
Change to Condition Column for Dropout Voltage Parameter,
Table 3 ................................................................................................. 5
Change to Operating Temperature Range, Table 23 ................... 16
7/10—Rev. J to Rev. K
Add Note 1, Features Section ........................................................... 1
Changes to Note 1, Table 2 ............................................................... 4
Changes to Note 1, Table 5 ............................................................... 6
Changes to Note 1, Table 8 ............................................................... 8
Changes to Note 1, Table 11 ............................................................. 9
Changes to Note 1, Table 14 ........................................................... 11
Changes to Note 1, Table 17 ........................................................... 12
Changes to Note 1, Table 20 ........................................................... 14
Moved Figure 22 .............................................................................. 20
Added Figure 23, Solder Heat Effect Section, and Figure 24;
Renumbered Sequentially .............................................................. 21
Moved Negative Precision Reference Without Precision
Resistors Section .............................................................................. 22
Moved Precision Current Source Section .................................... 23
Moved Kelvin Connections Section ............................................. 24
Moved Figure 32 .............................................................................. 25
Updated Outline Dimensions ........................................................ 26
Changes to Ordering Guide ........................................................... 27
3/08—Rev. I to Rev. J
Changes to General Description ..................................................... 1
Changes to Specifications Section ................................................... 4
Deleted Wafer Test Limits Section ................................................ 14
Changes to Table 23, Thermal Resistance Section, and
Table 24 ............................................................................................. 16
Changes to Figure 6 ......................................................................... 17
Changes to Device Power Dissipation
Considerations Section ................................................................... 20
Changes to Current-Boosted References with Current
Limiting Section .............................................................................. 21
Changes to Precision Current Source Section ............................ 22
Changes to Figure 28 ...................................................................... 23
Changes to Figure 30 ...................................................................... 24
Changes to Low Power, Strain Gage Circuit Section .................. 25
Changes to Ordering Guide ........................................................... 27
9/06—Rev. H to Rev. I
Updated Format ................................................................. Universal
Changes to Table 25 ........................................................................ 16
Changes to Figure 6 ........................................................................ 16
Changes to Figure 10, Figure 12, Figure 14, and Figure 26 ....... 17
Changes to Figure 18 ...................................................................... 18
Changes to Figure 20 ...................................................................... 19
Changes to Figure 23 ...................................................................... 20
Changes to Figure 25 ...................................................................... 21
Updated Outline Dimensions ........................................................ 25
Changes to Ordering Guide ........................................................... 26
6/05—Rev. G to Rev. H
Updated Format ................................................................. Universal
Changes to Caption in Figure 7 ..................................................... 16
Updated Outline Dimensions ........................................................ 25
Changes to Ordering Guide ........................................................... 26
7/04—Rev. F to Rev. G
Changes to Ordering Guide ............................................................. 4
3/04—Rev. E to Rev. F
Updated Absolute Maximum Rating .............................................. 4
Changes to Ordering Guide ........................................................... 14
Updated Outline Dimensions ........................................................ 24
1/03—Rev. D to Rev. E
Changes to Figure 3 and Figure 4 ................................................. 15
Changes to Output Short Circuit Behavior ................................. 17
Changes to Figure 20 ...................................................................... 17
Changes to Figure 26 ...................................................................... 19
Updated Outline Dimensions ........................................................ 23
1/96—Revision 0: Initial Version
REF19x Series Data Sheet
Rev. L | Page 4 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—REF191 @ TA = 25°C
@ VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY1 V
O
E Grade IOUT = 0 mA 2.046 2.048 2.050 V
F Grade 2.043 2.053 V
G Grade 2.038 2.058 V
LINE REGULATION2 ΔVO/ΔVIN
E Grade 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2 ΔVO/ΔVLOAD
E Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 4 10 ppm/mA
F and G Grades 6 15 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 3.0 V, ILOAD = 2 mA 0.95 V
V
S = 3.3 V, ILOAD = 10 mA 1.25 V
V
S = 3.6 V, ILOAD = 30 mA 1.55 V
LONG-TERM STABILITY3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 20 μV p-p
1 Initial accuracy does not include shift due to solder heat effect (see the Applications Information section).
2 Line and load regulation specifications include the effect of self-heating.
3 Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
Data Sheet REF19x Series
Rev. L | Page 5 of 28
ELECTRICAL CHARACTERISTICS—REF191 @ −40°C ≤ +85°C
@ VS = 3.3 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 3.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
E Grade IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade3 10 25 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
E Grade 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
E Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA 5 15 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 3.0 V, ILOAD = 2 mA 0.95 V
V
S = 3.3 V, ILOAD = 10 mA 1.25 V
V
S = 3.6 V, ILOAD = 25 mA 1.55 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
REF19x Series Data Sheet
Rev. L | Page 6 of 28
ELECTRICAL CHARACTERISTICS—REF191 @ −40°C ≤ TA ≤ +125°C
@ VS = 3.3 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 4.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
E Grade IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade3 10 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
E Grade 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 ppm/V
F and G Grades 20 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
E Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 10 ppm/mA
F and G Grades 20 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 3.3 V, ILOAD = 10 mA 1.25 V
V
S = 3.6 V, ILOAD = 20 mA 1.55 V
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS—REF192 @ TA = 25°C
@ VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 5.
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY1 V
O
E Grade IOUT = 0 mA 2.498 2.500 2.502 V
F Grade 2.495 2.505 V
G Grade 2.490 2.510 V
LINE REGULATION2 ΔVO/ΔVIN
E Grade 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2 ΔVO/ΔVLOAD
E Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 4 10 ppm/mA
F and G Grades 6 15 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 3.5 V, ILOAD = 10 mA 1.00 V
V
S = 3.9 V, ILOAD = 30 mA 1.40 V
LONG-TERM STABILITY3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 25 μV p-p
1 Initial accuracy does not include shift due to solder heat effect (see the Applications Information section).
2 Line and load regulation specifications include the effect of self-heating.
3 Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
Data Sheet REF19x Series
Rev. L | Page 7 of 28
ELECTRICAL CHARACTERISTICS—REF192 @ −40°C ≤ TA ≤ +85°C
@ VS = 3.3 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 6.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
E Grade IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade3 10 25 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
E Grade 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
E Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA 5 15 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 3.5 V, ILOAD = 10 mA 1.00 V
V
S = 4.0 V, ILOAD = 25 mA 1.50 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS—REF192 @ −40°C ≤ TA ≤ +125°C
@ VS = 3.3 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 7.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
E Grade IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade3 10 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
E Grade 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 ppm/V
F and G Grades 20 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
E Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 10 ppm/mA
F and G Grades 20 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 3.5 V, ILOAD = 10 mA 1.00 V
V
S = 4.0 V, ILOAD = 20 mA 1.50 V
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
REF19x Series Data Sheet
Rev. L | Page 8 of 28
ELECTRICAL CHARACTERISTICS—REF193 @ TA = 25°C
@ VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 8.
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY1 V
O
G Grade IOUT = 0 mA 2.990 3.0 3.010 V
LINE REGULATION2 ΔVO/ΔVIN
G Grade 3.3 V, ≤ VS ≤ 15 V, IOUT = 0 mA 4 8 ppm/V
LOAD REGULATION2 ΔVO/ΔVLOAD
G Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 6 15 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 3.8 V, ILOAD = 10 mA 0.80 V
V
S = 4.0 V, ILOAD = 30 mA 1.00 V
LONG-TERM STABILITY3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 30 μV p-p
1 Initial accuracy does not include shift due to solder heat effect (see the Applications Information section).
2 Line and load regulation specifications include the effect of self-heating.
3 Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
ELECTRICAL CHARACTERISTICS—REF193 @ −40°C ≤ TA ≤ +85°C
@ VS = 3.3 V, TA = −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 9.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
G Grade3 I
OUT = 0 mA 10 25 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
G Grade 3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 20 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
G Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA 10 20 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 3.8 V, ILOAD = 10 mA 0.80 V
V
S = 4.1 V, ILOAD = 30 mA 1.10 V
SLEEP PIN
Logic High Input Voltage VH 2.4
V
Logic High Input Current IH
−8 μA
Logic Low Input Voltage VL
0.8 V
Logic Low Input Current IL
−8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
Data Sheet REF19x Series
Rev. L | Page 9 of 28
ELECTRICAL CHARACTERISTICS—REF193 @ TA ≤ −40°C ≤ +125°C
@ VS = 3.3 V, –40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 10.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
G Grade3 I
OUT = 0 mA 10 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
G Grade 3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA 20 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
G Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 10 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 3.8 V, ILOAD = 10 mA 0.80 V
V
S = 4.1 V, ILOAD = 20 mA 1.10 V
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS—REF194 @ TA = 25°C
@ VS = 5.0 V, TA = 25°C, unless otherwise noted.
Table 11.
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY1 V
O
E Grade IOUT = 0 mA 4.498 4.5 4.502 V
G Grade 4.490 4.510 V
LINE REGULATION2 ∆VO/∆VIN
E Grade 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
G Grade 4 8 ppm/V
LOAD REGULATION2 ∆VO/∆VLOAD
E Grade VS = 5.8 V, 0 mA ≤ IOUT ≤ 30 mA 2 4 ppm/mA
G Grade 4 8 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 5.00 V, ILOAD = 10 mA 0.50 V
V
S = 5.8 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY3 DVO 1000 hours @ 125°C 2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 45 μV p-p
1 Initial accuracy does not include shift due to solder heat effect (see the Applications Information section).
2 Line and load regulation specifications include the effect of self-heating.
3 Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
REF19x Series Data Sheet
Rev. L | Page 10 of 28
ELECTRICAL CHARACTERISTICS—REF194 @ −40°C ≤ TA ≤ +85°C
@ VS = 5.0 V, TA = −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 12.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
E Grade IOUT = 0 mA 2 5 ppm/°C
G Grade3 10 25 ppm/°C
LINE REGULATION4 ∆VO/∆VIN
E Grade 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
G Grade 10 20 ppm/V
LOAD REGULATION4 ∆VO/∆VLOAD
E Grade VS = 5.80 V, 0 mA ≤ IOUT ≤ 25 mA 5 15 ppm/mA
G Grade 10 20 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 5.00 V, ILOAD = 10 mA 0.5 V
V
S = 5.80 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS—REF194 @ −40°C ≤ TA ≤ +125°C
@ VS = 5.0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 13.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
E Grade IOUT = 0 mA 2 ppm/°C
G Grade3 10 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
E Grade 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
G Grade 10 ppm/V
LOAD REGULATION ΔVO/ΔVLOAD
E Grade VS = 5.80 V, 0 mA ≤ IOUT ≤ 20 mA 5 ppm/mA
Grade 10 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 5.10 V, ILOAD = 10 mA 0.60 V
V
S = 5.95 V, ILOAD = 20 mA 1.45 V
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
Data Sheet REF19x Series
Rev. L | Page 11 of 28
ELECTRICAL CHARACTERISTICS—REF195 @ TA = 25°C
@ VS = 5.10 V, TA = 25°C, unless otherwise noted.
Table 14.
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY1 V
O
E Grade IOUT = 0 mA 4.998 5.0 5.002 V
F Grade 4.995 5.005 V
G Grade 4.990 5.010 V
LINE REGULATION2 ΔVO/ΔVIN
E Grade 5.10 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2 ΔVO/ΔVLOAD
E Grade VS = 6.30 V, 0 mA ≤ IOUT ≤ 30 mA 2 4 ppm/mA
F and G Grades 4 8 ppm/mA
DROPOUT VOLTAGE VS − VO VS = 5.50 V, ILOAD = 10 mA 0.50 V
V
S = 6.30 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 50 μV p-p
1 Initial accuracy does not include shift due to solder heat effect (see the Applications Information section).
2 Line and load regulation specifications include the effect of self-heating.
3 Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
ELECTRICAL CHARACTERISTICS—REF195 @ −40°C ≤ TA ≤ +85°C
@ VS = 5.15 V, TA = −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 15.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
E Grade IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade3 10 25 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
E Grade 5.15 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
E Grade VS = 6.30 V, 0 mA ≤ IOUT ≤ 25 mA 5 10 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 5.50 V, ILOAD = 10 mA 0.50 V
V
S = 6.30 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
REF19x Series Data Sheet
Rev. L | Page 12 of 28
ELECTRICAL CHARACTERISTICS—REF195 @ −40°C ≤ TA ≤ +125°C
@ VS = 5.20 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 16.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
E Grade IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade3 10 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
E Grade 5.20 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
F and G Grades 10 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
E Grade VS = 6.45 V, 0 mA ≤ IOUT ≤ 20 mA 5 ppm/mA
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE VS − VO VS = 5.60 V, ILOAD = 10 mA 0.60 V
V
S = 6.45 V, ILOAD = 20 mA 1.45 V
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS—REF196 @ TA = 25°C
@ VS = 3.5 V, TA = 25°C, unless otherwise noted.
Table 17.
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY1 V
O
G Grade IOUT = 0 mA 3.290 3.3 3.310 V
LINE REGULATION2 ΔVO/ΔVIN
G Grade 3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA 4 8 ppm/V
LOAD REGULATION2 ΔVO/ΔVLOAD
G Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 6 15 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 4.1 V, ILOAD = 10 mA 0.80 V
V
S = 4.3 V, ILOAD = 30 mA 1.00 V
LONG-TERM STABILITY3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 33 μV p-p
1 Initial accuracy does not include shift due to solder heat effect (see the Applications Information section).
2 Line and load regulation specifications include the effect of self-heating.
3 Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
Data Sheet REF19x Series
Rev. L | Page 13 of 28
ELECTRICAL CHARACTERISTICS—REF196 @ −40°C ≤ TA ≤ +85°C
@ VS = 3.5 V, TA = –40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 18.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
G Grade3 I
OUT = 0 mA 10 25 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
G Grade 3.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 20 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
G Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA 10 20 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 4.1 V, ILOAD = 10 mA 0.80 V
V
S = 4.3 V, ILOAD = 25 mA 1.00 V
SLEEP PIN
Logic High Input Voltage VH 2.4
V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/V0(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS—REF196 @ −40°C ≤ TA ≤ +125°C
@ VS = 3.50 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 19.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
G Grade3 I
OUT = 0 mA 10 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
G Grade 3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA 20 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
G Grade VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 20 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 4.1 V, ILOAD = 10 mA 0.80 V
V
S = 4.4 V, ILOAD = 20 mA 1.10 V
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
REF19x Series Data Sheet
Rev. L | Page 14 of 28
ELECTRICAL CHARACTERISTICS—REF198 @ TA = 25°C
@ VS = 5.0 V, TA = 25°C, unless otherwise noted.
Table 20.
Parameter Symbol Condition Min Typ Max Unit
INITIAL ACCURACY1 V
O
E Grade IOUT = 0 mA 4.094 4.096 4.098 V
F Grade 4.091 4.101 V
G Grade 4.086 4.106 V
LINE REGULATION2 ΔVO/ΔVIN
E Grade 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2 ΔVO/ΔVLOAD
E Grade VS = 5.4 V, 0 mA ≤ IOUT ≤ 30 mA 2 4 ppm/mA
F and G Grades 4 8 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 4.6 V, ILOAD = 10 mA 0.502 V
V
S = 5.4 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY3 DVO 1000 hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 40 μV p-p
1 Initial accuracy does not include shift due to solder heat effect (see the Applications Information section).
2 Line and load regulation specifications include the effect of self-heating.
3 Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
ELECTRICAL CHARACTERISTICS—REF198 @ −40°C ≤ TA ≤ +85°C
@ VS = 5.0 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 21.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
E Grade IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade3 10 25 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
E Grade 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
E Grade VS = 5.4 V, 0 mA ≤ IOUT ≤ 25 mA 5 10 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 4.6 V, ILOAD = 10 mA 0.502 V
V
S = 5.4 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH −8 μA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL −8 μA
SUPPLY CURRENT No load 45 μA
Sleep Mode No load 15 μA
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
Data Sheet REF19x Series
Rev. L | Page 15 of 28
ELECTRICAL CHARACTERISTICS—REF198 @ −40°C ≤ TA ≤ +125°C
@ VS = 5.0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 22.
Parameter Symbol Condition Min Typ Max Unit
TEMPERATURE COEFFICIENT1, 2 TCVO/°C
E Grade IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade3 10 ppm/°C
LINE REGULATION4 ΔVO/ΔVIN
E Grade 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
F and G Grades 10 ppm/V
LOAD REGULATION4 ΔVO/ΔVLOAD
E Grade VS = 5.6 V, 0 mA ≤ IOUT ≤ 20 mA 5 ppm/mA
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE VS − VO V
S = 4.7 V, ILOAD = 10 mA 0.60 V
V
S = 5.6 V, ILOAD = 20 mA 1.50 V
1 For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.
2 TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.
TCVO = (VMAX − VMIN)/VO(TMAX − TMIN)
3 Guaranteed by characterization.
4 Line and load regulation specifications include the effect of self-heating.
REF19x Series Data Sheet
Rev. L | Page 16 of 28
ABSOLUTE MAXIMUM RATINGS
Table 23.
Parameter Rating
Supply Voltage −0.3 V to +18 V
Output to GND −0.3 V to VS + 0.3 V
Output to GND Short-Circuit Duration Indefinite
Storage Temperature Range
PDIP, SOIC Package −65°C to +150°C
Operating Temperature Range
REF19x −40°C to +125°C
Junction Temperature Range
PDIP, SOIC Package −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for worst-case conditions; that is, θJA is specified
for the device in socket for PDIP and is specified for the device
soldered in the circuit board for the SOIC and TSSOP packages.
Table 24.
Package Type θJA θJC Unit
8-Lead PDIP (N) 103 43 °C/W
8-Lead SOIC (R) 158 43 °C/W
8-Lead TSSOP (RU) 240 43 °C/W
ESD CAUTION
Data Sheet REF19x Series
Rev. L | Page 17 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
00371-003
TEMPERATURE (°C)
100–50 –25 0 25 50 75
OUTPUT VOLTAGE (V)
5.004
5.003
5.001
5.002
5.000
4.999
4.998
4.997
4.996
3 TYPICAL PARTS
5.15V < V
IN
< 15V
Figure 3. REF195 Output Voltage vs. Temperature
00371-004
I
LOAD
(mA)
300 5 10 15 20 25
LOAD REGULATION (ppm/V)
32
24
28
20
16
12
4
8
0
–40°C
+25°C
5.15V ≤ V
S
≤ 15V
+85°C
Figure 4. REF195 Load Regulator vs. ILOAD
V
IN
(V)
1646 8 101214
LINE REGUL
A
TION (ppm/mA)
20
16
12
8
4
0
+85°C
+25°C
–40°C
0mA ≤ I
OUT
≤ 25mA
00371-005
Figure 5. REF195 Line Regulator vs. VIN
T
C
V
OUT
(ppm/°C)
20–20 –10–15 0–5 10 155
PERCENTAGE OF PARTS
50
45
40
30
35
20
25
10
5
15
0
BASED ON 600
UNITS, 4 RUNS
–40°C ≤ T
A
≤ +85°C
00371-006
Figure 6. TCVOUT Distribution
00371-007
TEMPERATURE (°C)
100–50 –25 0 25 50 75
SUPPLY CURRENT (
μ
A)
40
35
30
25
20
15
10
5
0
NORMAL MODE
SLEEP MODE
Figure 7. Supply Current vs. Temperature
TEMPERATURE (°C)
100–50–250 255075
SLEEP PIN CURRENT (µA)
–
6
–5
–4
–3
–1
–2
0
V
L
V
H
00371-008
Figure 8. SLEEP Pin Current vs. Temperature
REF19x Series Data Sheet
Rev. L | Page 18 of 28
00371-009
FREQUENCY (Hz)
1M10 100 1k 10k 100k
RIPPLE REJECTION (dB)
–20
0
–60
–40
–80
–120
–100
Figure 9. Ripple Rejection vs. Frequency
REF19x
1kΩ
REF
10μF
VIN
= 15V OUTPUT
1kΩ
10μF
1μF10μF
2 6
4
00371-010
Figure 10. Ripple Rejection vs. Frequency Measurement Circuit
00371-011
FREQUENCY (Hz)
10M10 100 10k1k 100k 1M
Z
O
(Ω)
4
3
2
1
0
V
G
= 2V p-p
V
S
= 4V
V
IN
= 7V 200V
1μF1μF
REF19x
2 6
4
Z
Figure 11. Output Impedance vs. Frequency
O
FF
ON
100µs20mV
5V
10%
0%
90%
100%
00371-012
Figure 12. Load Transient Response
V
IN
= 15V
0
10mA
1μF
REF19x
4
2
6
00371-013
Figure 13. Load Transient Response Measurement Circuit
2V
2V
1mA
LOAD
30mA
LOAD
100µs
10%
100%
0%
90%
00371-014
Figure 14. Power-On Response Time
VIN = 7V 1μF
REF19x
4
2
6
00371-015
Figure 15. Power-On Response Time Measurement Circuit
Data Sheet REF19x Series
Rev. L | Page 19 of 28
1V 2ms
5V
ON
OFF
VOUT
IL = 1mA
IL = 10mA
10%
100%
0%
90%
00371-016
5V
200mV 200µs
10%
100%
0%
90%
00371-018
Figure 16. SLEEP Response Time Figure 18. Line Transient Response
VOUT
V
IN = 15V
1μF
REF19x
3
2
6
4
00371-017
00371-019
REF195 DROPOUT VOLTAGE (V)
0.90 0.20.1 0.4 0.50.3 0.6 0.7 0.8
LOAD CURRENT (mA)
35
30
25
15
20
5
10
0
Figure 17. SLEEP Response Time Measurement Circuit
Figure 19. Load Current vs. REF195 Dropout Voltage
REF19x Series Data Sheet
Rev. L | Page 20 of 28
APPLICATIONS INFORMATION
OUTPUT SHORT-CIRCUIT BEHAVIOR
The REF19x family of devices is totally protected from damage
due to accidental output shorts to GND or to VS. In the event of
an accidental short-circuit condition, the reference device shuts
down and limits its supply current to 40 mA.
V
S
OUTPUT
SLEEP (SHUTDOWN)
GND
0
0371-020
Figure 20. Simplified Schematic
DEVICE POWER DISSIPATION CONSIDERATIONS
The REF19x family of references is capable of delivering load
currents to 30 mA with an input voltage that ranges from 3.3 V
to 15 V. When these devices are used in applications with large
input voltages, exercise care to avoid exceeding the maximum
internal power dissipation of these devices. Exceeding the
published specifications for maximum power dissipation or
junction temperature can result in premature device failure.
The following formula should be used to calculate the maximum
junction temperature or dissipation of the device:
JA
A
J
D
TT
Pθ
−
=
where TJ and TA are the junction and ambient temperatures,
respectively; PD is the device power dissipation; and θJA is the
device package thermal resistance.
OUTPUT VOLTAGE BYPASSING
For stable operation, low dropout voltage regulators and references
generally require a bypass capacitor connected from their VOUT
pins to their GND pins. Although the REF19x family of references is
capable of stable operation with capacitive loads exceeding 100 μF,
a 1 μF capacitor is sufficient to guarantee rated performance.
The addition of a 0.1 μF ceramic capacitor in parallel with the
bypass capacitor improves load current transient performance.
For best line voltage transient performance, it is recommended
that the voltage inputs of these devices be bypassed with a 10 μF
electrolytic capacitor in parallel with a 0.1 μF ceramic capacitor.
SLEEP MODE OPERATION
All REF19x devices include a sleep capability that is TTL/CMOS-
level compatible. Internally, a pull-up current source to VS is
connected at the SLEEP pin. This permits the SLEEP pin to be
driven from an open collector/drain driver. A logic low or a 0 V
condition on the SLEEP pin is required to turn off the output
stage. During sleep, the output of the references becomes a high
impedance state where its potential would then be determined
by external circuitry. If the sleep feature is not used, it is
recommended that the SLEEP pin be connected to VS (Pin 2).
BASIC VOLTAGE REFERENCE CONNECTIONS
The circuit in Figure 21 illustrates the basic configuration for
the REF19x family of references. Note the 10 μF/0.1 μF bypass
network on the input and the 1 μF/0.1 μF bypass network on
the output. It is recommended that no connections be made to
Pin 1, Pin 5, Pin 7, and Pin 8. If the sleep feature is not required,
Pin 3 should be connected to VS.
NC
NC
V
S
SLEEP
NC
NC
OUTPUT
0.1µF10µF
REF19x
NC = NO CONNECT
8
7
6
5
1
2
3
4
1µF
TANT
0.1µF
+
00371-021
Figure 21. Basic Voltage Reference Connections
MEMBRANE SWITCH-CONTROLLED POWER SUPPLY
With output load currents in the tens of mA, the REF19x family of
references can operate as a low dropout power supply in hand-held
instrument applications. In the circuit shown in Figure 22, a
membrane on/off switch is used to control the operation of the
reference. During an initial power-on condition, the SLEEP pin is
held to GND by the 10 kΩ resistor. Recall that this condition (read:
three-state) disables the REF19x output. When the membrane on
switch is pressed, the SLEEP pin is momentarily pulled to VS,
enabling the REF19x output. At this point, current through the 10 kΩ
resistor is reduced and the internal current source connected to the
SLEEP pin takes control. Pin 3 assumes and remains at the same
potential as VS. When the membrane off switch is pressed, the
SLEEP pin is momentarily connected to GND, which once
again disables the REF19x output.
ON
OFF
10kΩ
1kΩ
5%
NC
NC
V
S
NC
NC
OUTPUT
REF19x
NC = NO CONNECT
8
7
6
5
1
2
3
4
1µF
TANT
+
00371-022
Figure 22. Membrane Switch Controlled Power Supply
Data Sheet REF19x Series
Rev. L | Page 21 of 28
t
S
t
L
T
L
T
P
25
TIME 25°C TO PEAK
T
SMAX
PREHEAT AREA
MAXIMUM RAMP DOWN RATE = 6°C/s
MAXIMUM RAMP UP RATE = 3°C/s
T
SMIN
T
C
= –5°C
t
P
SUPPLIER
t
P
SUPPLIER
T
P
≥ T
C
T
C
T
C
= –5°C
USER
t
P
USER
T
P
≤ T
C
TEMPERATUR
E
TIME
00371-123
Figure 23. Classification Profile (Not to Scale)
SOLDER HEAT EFFECT
The mechanical stress and heat effect of soldering a part to a
PCB can cause output voltage of a reference to shift in value.
The output voltage of REF195 shifts after the part undergoes the
extreme heat of a lead-free soldering profile, like the one shown
in Figure 23. The materials that make up a semiconductor device
and its package have different rates of expansion and contraction.
The stress on the dice has changed position, causing shift on the
output voltage, after exposed to extreme soldering temperatures.
This shift is similar but more severe than thermal hysteresis.
Typical result of soldering temperature effect on REF19x output
value shift is shown in Figure 24. It shows the output shift due
to soldering and does not include mechanical stress.
0
0371-124
6
5
4
3
2
1
0
–0.16
–0.14
–0.12
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0.16
0.14
NUMBER OF UNITS
SHIFT DUE TO SOLDER HEAT EFFECT (%)
Figure 24. Output Shift due to Solder Heat Effect
CURRENT-BOOSTED REFERENCES WITH CURRENT
LIMITING
Whereas the 30 mA rated output current of the REF19x series is
higher than is typical of other reference ICs, it can be boosted to
higher levels, if desired, with the addition of a simple external
PNP transistor, as shown in Figure 25. Full-time current limiting is
used to protect the pass transistor against shorts.
U1
REF196
(SEE TABLE)
R4
2Ω
R1
1kΩ
R2
1.5kΩ
Q2
2N3906
C2
100µF
25V
D1
R3
1.82kΩ
C1
10µF/25V
(TANTALUM)
S
F
C3
0.1µF F
S
R1
Q1
TIP32A
(SEE TEXT)
+
V
S
= 6
TO 9V
(SEE TEXT)
V
S
COMMON
V
C
V
OUT
COMMON
OUTPUT TABLE
U1
REF192
REF193
REF196
REF194
REF195
V
OUT
(V)
2.5
3.0
3.3
4.5
5.0
+V
OUT
3.3V
@ 150mA
2
6
+
1N4148
(SEE TEXT
ON SLEEP)
3
+
4
00371-023
Figure 25. Boosted 3.3 V Referenced with Current Limiting
In this circuit, the power supply current of reference U1 flowing
through R1 to R2 develops a base drive for Q1, whose collector
provides the bulk of the output current. With a typical gain of 100
in Q1 for 100 mA to 200 mA loads, U1 is never required to furnish
more than a few mA, so this factor minimizes temperature-related
drift. Short-circuit protection is provided by Q2, which clamps
the drive to Q1 at about 300 mA of load current, with values as
shown in Figure 25. With this separation of control and power
functions, dc stability is optimum, allowing most advantageous
use of premium grade REF19x devices for U1. Of course, load
REF19x Series Data Sheet
Rev. L | Page 22 of 28
management should still be exercised. A short, heavy, low dc
resistance (DCR) conductor should be used from U1 to 6 to the VOUT
Sense Point S, where the collector of Q1 connects to the load, Point F.
Because of the current limiting configuration, the dropout voltage
circuit is raised about 1.1 V over that of the REF19x devices, due to
the VBE of Q1 and the drop across Current Sense Resistor R4.
However, overall dropout is typically still low enough to allow
operation of a 5 V to 3.3 V regulator/reference using the REF196 for
U1 as noted, with a VS as low as 4.5 V and a load current of 150 mA.
The requirement for a heat sink on Q1 depends on the maximum
input voltage and short-circuit current. With VS = 5 V and a
300 mA current limit, the worst-case dissipation of Q1 is 1.5 W,
less than the TO-220 package 2 W limit. However, if smaller TO-39
or TO-5 package devices, such as the 2N4033, are used, the current
limit should be reduced to keep maximum dissipation below
the package rating. This is accomplished by simply raising R4.
A tantalum output capacitor is used at C1 for its low equivalent
series resistance (ESR), and the higher value is required for stability.
Capacitor C2 provides input bypassing and can be an ordinary
electrolytic.
Shutdown control of the booster stage is an option, and when used,
some cautions are needed. Due to the additional active devices
in the VS line to U1, a direct drive to Pin 3 does not work as with an
unbuffered REF19x device. To enable shutdown control, the
connection from U1 to Q2 is broken at the X, and Diode D1
then allows a CMOS control source, VC, to drive U1 to 3 for on/off
operation. Startup from shutdown is not as clean under heavy
load as it is in basic REF19x series, and can require several
milliseconds under load. Nevertheless, it is still effective and
can fully control 150 mA loads. When shutdown control is
used, heavy capacitive loads should be minimized.
NEGATIVE PRECISION REFERENCE WITHOUT
PRECISION RESISTORS
In many current-output CMOS DAC applications where the output
signal voltage must be the same polarity as the reference voltage, it
is often necessary to reconfigure a current-switching DAC into
a voltage-switching DAC using a 1.25 V reference, an op amp,
and a pair of resistors. Using a current-switching DAC directly
requires an additional operational amplifier at the output to
reinvert the signal. A negative voltage reference is then desirable
because an additional operational amplifier is not required for
either reinversion (current-switching mode) or amplification
(voltage-switching mode) of the DAC output voltage. In general,
any positive voltage reference can be converted into a negative
voltage reference using an operational amplifier and a pair of
matched resistors in an inverting configuration. The disadvantage
to this approach is that the largest single source of error in the
circuit is the relative matching of the resistors used.
The circuit illustrated in Figure 26 avoids the need for tightly
matched resistors by using an active integrator circuit. In this
circuit, the output of the voltage reference provides the input
drive for the integrator. To maintain circuit equilibrium, the
integrator adjusts its output to establish the proper relationship
between the VOUT and GND references. Thus, any desired negative
output voltage can be selected by substituting for the appropriate
reference IC. The sleep feature is maintained in the circuit with
the simple addition of a PNP transistor and a 10 kΩ resistor.
100Ω
1µF
1kΩ1µF
–VREF
REF19x
VS
GND
OUTPUT
100kΩ
SLEEP
TTL/CMOS
A1 = 1/2 OP295,
1/2 OP291
V
S
10kΩ
2N3906
3 6
2
4
SLEEP
10kΩ
+5V
–5V
A1
00371-024
Figure 26. Negative Precision Voltage Reference Uses No Precision Resistors
One caveat to this approach is that although rail-to-rail output
amplifiers work best in the application, these operational amplifiers
require a finite amount (mV) of headroom when required to provide
any load current; consider this issue when choosing the negative
supply for the circuit.
STACKING REFERENCE ICs FOR ARBITRARY
OUTPUTS
Some applications may require two reference voltage sources that
are a combined sum of standard outputs. The circuit in Figure 27
shows how this stacked output reference can be implemented.
Two reference ICs are used, fed from a common unregulated input,
VS. The outputs of the individual ICs are connected in series, as
shown in Figure 27, which provide two output voltages, VOUT1 and
VOUT2. VOUT1 is the terminal voltage of U1, whereas VOUT2 is the
sum of this voltage and the terminal voltage of U2. U1 and U2
are chosen for the two voltages that supply the required outputs
(see Table 1). If, for example, both U1 and U2 are REF192s, the
two outputs are 2.5 V and 5.0 V.
R1
3.9kΩ
(SEE TEXT)
C1
0.1µF
+V
S
V
S
> V
OUT2
+ 0.15V
V
IN
COMMON V
OUT
COMMON
OUTPUT TABLE
U1/U2
REF192/REF192
REF192/REF194
REF192/REF195
V
OUT1
(V)
2.5
2.5
2.5
V
OUT2
(V)
5.0
7.0
7.5
+V
OUT2
C2
1µF
C3
0.1µF +V
OUT1
C4
1µF
U2
REF19x
(SEE TABLE)
2
63
4
U1
REF19x
(SEE TABLE)
2
63
4
+
+
V
O
(U2)
V
O
(U1)
00371-025
Figure 27. Stacking Voltage References with the REF19x
Data Sheet REF19x Series
Rev. L | Page 23 of 28
Although this concept is simple, some cautions are needed. Because
the lower reference circuit must sink a small bias current from U2
(50 μA to 100 μA), plus the base current from the series PNP output
transistor in U2, either the external load of U1 or R1 must provide
a path for this current. If the U1 minimum load is not well defined,
Resistor R1 should be used, set to a value that conservatively passes
600 μA of current with the applicable VOUT1 across it. Note that the
two U1 and U2 reference circuits are locally treated as macrocells,
each having its own bypasses at input and output for best stability.
Both U1 and U2 in this circuit can source dc currents up to
their full rating. The minimum input voltage, VS, is determined by
the sum of the outputs, VOUT2, plus the dropout voltage of U2.
A related variation on stacking two 3-terminal references is shown
in Figure 28, where U1, a REF192, is stacked with a 2-terminal
reference diode, such as the AD589. Like the 3-terminal stacked
reference shown in Figure 27, this circuit provides two outputs,
VOUT1 and VOUT2, which are the individual terminal voltages of D1
and U1, respectively. Here this is 1.235 V and 2.5 V, which provides a
VOUT2 of 3.735 V. When using 2-terminal reference diodes, such as
D1, the rated minimum and maximum device currents must be
observed, and the maximum load current from VOUT1 can be no
greater than the current setup by R1 and VO (U1). When VO
(U1) is equal to 2.5 V, R1 provides a 500 μA bias to D1, so the
maximum load current available at VOUT1 is 450 μA or less.
D1
AD589
R1
4.99kΩ
(SEE TEXT)
C1
0.1μF
+V
S
V
S
> V
OUT2
+ 0.15V
V
IN
COMMON
V
OUT
COMMON
+V
OUT2
3.735V
C2
1μF
+V
OUT1
1.235V
C3
1μF
U1
REF192
2
63
4
+
+
V
O
(U1)
V
O
(D1)
00371-026
Figure 28. Stacking Voltage References with the REF192
PRECISION CURRENT SOURCE
In low power applications, the need often arises for a precision
current source that can operate on low supply voltages. As
shown in Figure 29, any one of the devices in the REF19x family
of references can be configured as a precision current source.
The circuit configuration illustrated is a floating current source
with a grounded load. The output voltage of the reference is
bootstrapped across RSET, which sets the output current into the
load. With this configuration, circuit precision is maintained for
load currents in the range from the reference’s supply current
(typically 30 μA) to approximately 30 mA. The low dropout
voltage of these devices maximizes the current source’s output
voltage compliance without excess headroom.
I
SY
ADJUST
R1
R
SET
P1
R
L
I
OUT
FOR EXAMPLE, REF195: V
OUT
= 5V
I
OUT
= 5mA
R1 = 953Ω
P1 = 100Ω, 10-TURN
V
S
1µF
REF19x
2
3
4
6
V
IN
≥ I
OUT
× R
L
(MAX) + V
SY
(MIN)
I
OUT
= V
OUT
+ I
SY
(REF19x)
R
SET
V
OUT
>> I
SY
R
SET
V
S
GND
OUTPUTSLEEP
00371-027
Figure 29. A Low Dropout, Precision Current Source
SWITCHED OUTPUT 5 V/3.3 V REFERENCE
Applications often require digital control of reference voltages,
selecting between one stable voltage and a second. With the
sleep feature inherent to the REF19x series, switched output
reference configurations are easily implemented with little
additional hardware.
The circuit in Figure 30 shows the general technique, which takes
advantage of the output wire-OR capability of the REF19x device
family. When off, a REF19x device is effectively an open circuit
at the output node with respect to the power supply. When on, a
REF19x device can source current up to its current rating, but
sink only a few μA (essentially, just the relatively low current of the
internal output scaling divider). Consequently, when two devices
are wired together at their common outputs, the output voltage
is the same as the output voltage for the on device. The off state
device draws a small standby current of 15 μA (maximum), but
otherwise does not interfere with operation of the on device, which
can operate to its full current rating. Note that the two devices in
the circuit conveniently share both input and output capacitors,
and with CMOS logic drive, it is power efficient.
U3B
74HC04
U3A
74HC04
V
C
V
OUT
(V)
5.0
3.3
4.5
5.0
V
C
*
HIGH
LOW
HIGH
LOW
U1/U2
REF195/
REF196
REF194/
REF195
*CMOS LOGIC LEVELS
+V
S
= 6V
V
IN
COMMON V
OUT
COMMON
C1
0.1µF
+V
OUT
C2
1µF
U1
REF19x
(SEE TABLE)
2
3
4
U2
REF19x
(SEE TABLE)
2
3
4
+
6
6
1324
OUTPUT T
A
BLE
00371-028
Figure 30. Switched Output Reference
REF19x Series Data Sheet
Rev. L | Page 24 of 28
2
3
1
+V
OUT
SENSE
+V
OUT
FORCE
R
LW
1µF 100kΩR
L
REF19x
V
S
GND
OUTPUT
A1 = 1/2 OP295
1/2 OP292
OP183
V
S
6
2
4
SLEEP
V
S
R
LW
A1
3
00371-029
Using dissimilar REF19x series devices with this configuration
allows logic selection between the U1/U2-specified terminal
voltages. For example, with U1 (a REF195) and U2 (a REF196),
as noted in the table in Figure 30, changing the CMOS-compatible
VC logic control voltage from high to low selects between a nominal
output of 5.0 V and 3.3 V, and vice versa. Other REF19x family
units can also be used for U1/U2, with similar operation in a
logic sense, but with outputs as per the individual paired devices
(see the table in Figure 30). Of course, the exact output voltage
tolerance, drift, and overall quality of the reference voltage is
consistent with the grade of individual U1 and U2 devices.
Figure 31. Low Dropout, Kelvin-Connected Voltage Reference
FAIL-SAFE 5 V REFERENCE
Some critical applications require a reference voltage to be
maintained at a constant voltage, even with a loss of primary
power. The low standby power of the REF19x series and the
switched output capability allow a fail-safe reference con-
figuration to be implemented rather easily. This reference
maintains a tight output voltage tolerance for either a primary
power source (ac line derived) or a standby (battery derived)
power source, automatically switching between the two as the
power conditions change.
Due to the nature of the wire-OR, one application caveat should
be understood about this circuit. Because U1 and U2 can only
source current effectively, negative going output voltage changes,
which require the sinking of current, necessarily take longer than
positive going changes. In practice, this means that the circuit is
quite fast when undergoing a transition from 3.3 V to 5 V, but the
transition from 5 V to 3.3 V takes longer. Exactly how much
longer is a function of the load resistance, RL, seen at the output and
the typical 1 μF value of C2. In general, a conservative transition
time is approximately several milliseconds for load resistances
in the range of 100 Ω to 1 kΩ. Note that for highest accuracy at
the new output voltage, several time constants should be allowed
(for example, >7.6 time constants for <1/2 LSB error @ 10 bits).
The circuit in Figure 32 illustrates this concept, which borrows
from the switched output idea of Figure 30, again using the
REF19x device family output wire-OR capability. In this case,
because a constant 5 V reference voltage is desired for all condi-
tions, two REF195 devices are used for U1 and U2, with their
on/off switching controlled by the presence or absence of the
primary dc supply source, VS. VBAT is a 6 V battery backup
source that supplies power to the load only when VS fails. For
normal (VS present) power conditions, VBAT sees only the 15 μA
(maximum) standby current drain of U1 in its off state.
KELVIN CONNECTIONS
In many portable applications where the PCB cost and area go
hand-in-hand, circuit interconnects are very often narrow. These
narrow lines can cause large voltage drops if the voltage reference is
required to provide load currents to various functions. The inter-
connections of a circuit can exhibit a typical line resistance of
0.45 mΩ/square (for example, 1 oz. Cu).
In operation, it is assumed that for all conditions, either U1 or
U2 is on, and a 5 V reference output is available. With this
voltage constant, a scaled down version is applied to the
Comparator IC U3, providing a fixed 0.5 V input to the negative
input for all power conditions. The R1 to R2 divider provides a
signal to the U3 positive input proportionally to VS, which
switches U3 and U1/U2, dependent upon the absolute level of
VS. In Figure 32, Op Amp U3 is configured as a comparator
with hysteresis, which provides clean, noise-free output
switching. This hysteresis is important to eliminate rapid
switching at the threshold due to VS ripple. Furthermore, the
device chosen is the AD820, a rail-to-rail output device. This
device provides high and low output states within a few mV of
VS, ground for accurate thresholds, and compatible drive for U2
for all VS conditions. R3 provides positive feedback for circuit
hysteresis, changing the threshold at the positive input as a
function of the output of U3.
In applications where these devices are configured as low dropout
voltage regulators, these wiring voltage drops can become a large
source of error. To circumvent this problem, force and sense
connections can be made to the reference through the use of an
operational amplifier, as shown in Figure 31. This method provides
a means by which the effects of wiring resistance voltage drops can
be eliminated. Load currents flowing through wiring resistance
produce an I-R error (ILOAD × RWIRE) at the load. However, the
Kelvin connection overcomes the problem by including the
wiring resistance within the forcing loop of the op amp. Because
the op amp senses the load voltage, op amp loop control forces
the output to compensate for the wiring error and to produce
the correct voltage at the load. Depending on the reference
device chosen, operational amplifiers that can be used in this
application are the OP295, OP292, and OP183.
Data Sheet REF19x Series
Rev. L | Page 25 of 28
R5
100kΩ
R6
100Ω
R3
10MΩ
U3
AD820
C4
0.1µF
R2
100kΩ
R1
1.1MΩ
Q1
2N3904
+
V
BAT
V
S
, V
BAT
COMMON V
OUT
COMMON
C2
0.1µF
C1
0.1µF
5.000V
C3
1µF
U1
REF195
(SEE TABLE)
2
3
4
U2
REF195
(SEE TABLE)
2
3
4
+
6
6
+V
S
R4
900kΩ
4
2
7
6
3
+
–
0
0371-030
Figure 32. Fail-Safe 5 V Reference
For VS levels lower than the lower threshold, the output of U3 is
low, thus U2 and Q1 are off and U1 is on. For VS levels higher
than the upper threshold, the situation reverses, with U1 off and
both U2 and Q1 on. In the interest of battery power conserva-
tion, all of the comparison switching circuitry is powered from
VS and is arranged so that when VS fails, the default output
comes from U1.
For the R1 to R3 values, as shown in Figure 32, lower/upper VS
switching thresholds are approximately 5.5 V and 6 V, respec-
tively. These can be changed to suit other VS supplies, as can the
REF19x devices used for U1 and U2, over a range of 2.5 V to
5 V of output. U3 can operate down to a VS of 3.3 V, which is
generally compatible with all REF19x family devices.
LOW POWER, STRAIN GAGE CIRCUIT
As shown in Figure 33, the REF19x family of references can be
used in conjunction with low supply voltage operational ampli-
fiers, such as the OP492 or the OP747, in a self-contained strain
gage circuit in which the REF195 is used as the core. Other
references can be easily accommodated by changing circuit
element values. The references play a dual role, first as the
voltage regulator to provide the supply voltage requirements of
the strain gage and the operational amplifiers, and second as a
precision voltage reference for the current source used to
stimulate the bridge. A distinct feature of the circuit is that it
can be remotely controlled on or off by digital means via
the SLEEP pin.
500Ω
0.1%
57kΩ
1% 0.1μF
10kΩ
1%
0.1μF
1/4
OP492
10μF
REF195
2.21kΩ
20kΩ
1%
10kΩ
1%
20kΩ
1%
20kΩ
1%
20kΩ
1%
0.01μF
10μF
100Ω
OUTPUT
2N2222
+1μF
+
62
4
+
–
1
4
11
2
3
1/4
OP492
+
–
7
5
6
1/4
OP492
+
–
14
12
13
1/4
OP492
+
–
8
10
9
10kΩ
1%
00371-031
Figure 33. Low Power, Strain Gage Circuit
REF19x Series Data Sheet
Rev. L | Page 26 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 34. 8-Lead Plastic Dual In-Line Package [PDIP]
P-Suffix (N-8)
Dimensions shown in inches and (millimeters)
85
41
PIN 1
0.65 BSC
SEATING
PLANE
0.15
0.05
0.30
0.19
1.20
MAX
0.20
0.09
8°
0°
6.40 BSC
4.50
4.40
4.30
3.10
3.00
2.90
COPLANARIT
Y
0.10
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA
Figure 35. 8-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 36. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
S-Suffix (R-8)
Dimensions shown in millimeters and (inches)
Data Sheet REF19x Series
Rev. L | Page 27 of 28
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity
REF191ES −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF191ES-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF191ESZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF191ESZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF191GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF191GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF191GSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF191GSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF192ES −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192ES-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF192ES-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF192ESZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192ESZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF192ESZ-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF192FS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192FS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF192FS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF192FSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192FSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF192FSZ-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF192GPZ −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF192GRUZ −40°C to +85°C 8-Lead TSSOP RU-8
REF192GRUZ-REEL7 −40°C to +85°C 8-Lead TSSOP RU-8 1,000
REF192GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF192GS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF192GSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF192GSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF192GSZ-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF193GSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF193GSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF194ES −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF194ESZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF194ESZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF194GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF194GS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF194GSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF194GSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF194GSZ-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF195ES −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195ES-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF195ESZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195ESZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF195FS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195FS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF195FSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195FSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF195GPZ −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF195GRU-REEL7 −40°C to +85°C 8-Lead TSSOP RU-8 1,000
REF195GRUZ −40°C to +85°C 8-Lead TSSOP RU-8
REF195GRUZ-REEL7 −40°C to +85°C 8-Lead TSSOP RU-8 1,000
REF19x Series Data Sheet
Rev. L | Page 28 of 28
Model1 Temperature Range Package Description Package Option Ordering Quantity
REF195GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF195GS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF195GSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF195GSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF195GSZ-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF196GRUZ-REEL7 −40°C to +85°C 8-Lead TSSOP RU-8 1,000
REF196GSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF196GSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF196GSZ-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF198ES −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198ES-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF198ESZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198ESZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF198ESZ-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 1,000
REF198FS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF198FSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198FSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF198GRUZ −40°C to +85°C 8-Lead TSSOP RU-8
REF198GRUZ-REEL7 −40°C to +85°C 8-Lead TSSOP RU-8 2,500
REF198GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
REF198GSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
REF198GSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8) 2,500
1 Z = RoHS Compliant Part.
©1996–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00371-0-9/11(L)