74LVC02AD,112 - NEXPERIA - searchdatasheet.com

74LVC02A

Quad 2-input NOR gate

Rev. 9 — 24 August 2020 Product data sheet

1. General description

The 74LVC02A provides four 2-input NOR gates.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices

as translators in mixed 3.3 V and 5 V applications.

2. Features and benefits

•5 V tolerant inputs for interfacing with 5 V logic

•Wide supply voltage range from 1.2 V to 3.6 V

•CMOS low power consumption

•Direct interface with TTL levels

•Complies with JEDEC standard:

•JESD8-7A (1.65 V to 1.95 V)

•JESD8-5A (2.3 V to 2.7 V)

•JESD8-C/JESD36 (2.7 V to 3.6 V)

•ESD protection:

•HBM JESD22-A114F exceeds 2000 V

•MM JESD22-A115-B exceeds 200 V

•CDM JESD22-C101E exceeds 1000 V

•Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

74LVC02AD -40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74LVC02ADB -40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT337-1

74LVC02APW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package;

14 leads; body width 4.4 mm

SOT402-1

74LVC02ABQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal

enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 × 3 × 0.85 mm

SOT762-1

Nexperia 74LVC02A

Quad 2-input NOR gate

4. Functional diagram

mna216

1B 1Y

2B 2Y

3B 3Y

810

4B 4Y

11 13

Fig. 1. Logic symbol

mna217

Fig. 2. IEC logic symbol

mna215

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

74LVC02A

1Y VCC

1A 4Y

1B 4B

2Y 4A

2A 3Y

2B 3B

GND 3A

001aac919

Fig. 4. Pin configuration for SOT108-1 (SO14),

SOT337-1 (SSOP14) and SOT402-1 (TSSOP14)

001aac920

74LVC02A

Transparent top view

2B 3B

2A 3Y

2Y 4A

1B 4B

1A 4Y

GND

6 9

5 10

4 11

3 12

2 13

terminal 1

index area

GND(1)

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 5. Pin configuration for SOT762-1 (DHVQFN14)

5.2. Pin description

Table 2. Pin description

Symbol Pin Description

1Y to 4Y 1, 4, 10, 13 data output

1A to 4A 2, 5, 8, 11 data input

1B to 4B 3, 6, 9,12 data input

GND 7 ground (0 V)

VCC 14 supply voltage

Product data sheet Rev. 9 — 24 August 2020 2 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

6. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care

Input nA Input nB Output nY

LLH

X H L

H X L

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +6.5 V

IIK input clamping current VI < 0 V -50 - mA

VIinput voltage [1] -0.5 +6.5 V

IOK output clamping current VO > VCC or VO < 0 V - ±50 mA

VOoutput voltage output in HIGH or LOW-state [2] -0.5 VCC + 0.5 V

IOoutput current VO = 0 V to VCC - ±50 mA

ICC supply current - 100 mA

IGND ground current -100 - mA

Ptot total power dissipation Tamb = -40 °C to +125 °C [3] - 500 mW

Tstg storage temperature -65 +150 °C

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.

For SOT337-1 (SSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.

For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.

For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

1.65 - 3.6 VVCC supply voltage

functional 1.2 - - V

VIinput voltage 0 - 5.5 V

VOoutput voltage output HIGH or LOW state 0 - VCC V

Tamb ambient temperature -40 - +125 °C

VCC = 1.65 V to 2.7 V 0 - 20 ns/VΔt/ΔV input transition rise and fall rate

VCC = 2.7 V to 3.6 V 0 - 10 ns/V

Product data sheet Rev. 9 — 24 August 2020 3 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ[1] Max Min Max

Unit

VCC = 1.2 V 1.08 - - 1.08 - V

VCC = 1.65 V to 1.95 V 0.65 × VCC - - 0.65 × VCC - V

VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V

VIH HIGH-level

input voltage

VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V

VCC = 1.2 V - - 0.12 - 0.12 V

VCC = 1.65 V to 1.95 V - - 0.35 × VCC - 0.35 × VCC V

VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V

VIL LOW-level

input voltage

VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V

VI = VIH or VIL

IO = -100 μA;

VCC = 1.65 V to 3.6 V

VCC - 0.2 - - VCC - 0.3 - V

IO = -4 mA; VCC = 1.65 V 1.2 - - 1.05 - V

IO = -8 mA; VCC = 2.3 V 1.8 - - 1.65 - V

IO = -12 mA; VCC = 2.7 V 2.2 - - 2.05 - V

IO = -18 mA; VCC = 3.0 V 2.4 - - 2.25 - V

VOH HIGH-level

output voltage

IO = -24 mA; VCC = 3.0 V 2.2 - - 2.0 - V

VI = VIH or VIL

IO = 100 μA;

VCC = 1.65 V to 3.6 V

- - 0.2 - 0.3 V

IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V

IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V

IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V

VOL LOW-level

output voltage

IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V

IIinput leakage

current

VCC = 3.6 V; VI = 5.5 V or GND - ±0.1 ±5 - ±20 μA

ICC supply current VCC = 3.6 V; VI = VCC or GND;

IO = 0 A

- 0.1 10 - 40 μA

ΔICC additional

supply current

per input pin;

VCC = 2.7 V to 3.6 V;

VI = VCC - 0.6 V; IO = 0 A

- 5 500 - 5000 μA

CIinput

capacitance

VCC = 0 V to 3.6 V;

VI = GND to VCC

- 4.0 - - - pF

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.

Product data sheet Rev. 9 — 24 August 2020 4 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 7.

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ[1] Max Min Max

Unit

nA, nB to nY; see Fig. 6 [2]

VCC = 1.2 V - 14 - - - ns

VCC = 1.65 V to 1.95 V 0.5 4.0 8.6 0.5 10.1 ns

VCC = 2.3 V to 2.7 V 1.0 2.4 4.9 1.0 5.7 ns

VCC = 2.7 V 1.0 2.5 5.1 1.0 6.5 ns

tpd propagation delay

VCC = 3.0 V to 3.6 V 1.0 2.2 4.4 1.0 5.5 ns

tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns

per gate; VI = GND to VCC [4]

VCC = 1.65 V to 1.95 V - 2.5 - - - pF

VCC = 2.3 V to 2.7 V - 5.7 - - - pF

CPD power dissipation

capacitance

VCC = 3.0 V to 3.6 V - 8.5 - - - pF

[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] tpd is the same as tPLH and tPHL.

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL x VCC 2 x fo) = sum of the outputs

Product data sheet Rev. 9 — 24 August 2020 5 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

10.1. Waveforms and test circuit

mna213

nA, nB input

nY output

tPHL tPLH

VOL

VOH

GND

VM = 1.5 V at VCC ≥ 2.7 V.

VM = 0.5 × VCC at VCC < 2.7 V.

VOL and VOH are typical output voltage levels that

occur with the output load.

Fig. 6. The input (nA, nB) to output (nY) propagation

delays

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aaf615

VCC

VIVO

DUT

RTRL

PULSE

GENERATOR

Test data is given in Table 8.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe

capacitance.

RT = Termination resistance should be equal to

output impedance Zo of the pulse generator.

Fig. 7. Test circuit for measuring switching times

Table 8. Test data

Input LoadSupply voltage

VItr, tfCLRL

1.2 V VCC ≤ 2 ns 30 pF 1 kΩ

1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ

2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω

2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω

3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω

Product data sheet Rev. 9 — 24 August 2020 6 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

11. Package outline

UNIT A

max. A

1 A

2 A

3 b

p c D

(1) E

(1) (1)

e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

w M

detail X

v M A

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.35

0.34

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.024

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Fig. 8. Package outline SOT108-1 (SO14)

Product data sheet Rev. 9 — 24 August 2020 7 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

UNIT A

1 A

2 A

3 b

p c D

(1) E

(1) e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05

1.80

1.65 0.25 0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2 0.65 1.25 0.2

7.9

7.6

1.03

0.63

0.9

0.7

1.4

0.9

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-1 99-12-27

03-02-19

(1)

w M

v M A

1 7

14 8

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

max.

Fig. 9. Package outline SOT337-1 (SSOP14)

Product data sheet Rev. 9 — 24 August 2020 8 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

UNIT A

1 A

2 A

3 b

p c D

(1) E (2) (1)

e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3 0.65 6.6

6.2

0.4

0.3

0.72

0.38

0.13 0.1 0.2 1

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

w M

0.25

1 7

14 8

detail X

(A )

v M A

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Fig. 10. Package outline SOT402-1 (TSSOP14)

Product data sheet Rev. 9 — 24 August 2020 9 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT762-1 MO-241

sot762-1_po

15-04-10

15-05-05

Unit

max

nom

min

1 0.05 3.1 1.65 2.6

0.5 2 0.4

A(1)

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1

A1b

0.30

c D(1) DhE(1) Eh

1.00

e e1k

L v

0.1

w y

0.02 0.2 3.0 1.50 2.5 0.10.25 0.05 0.05

0.30.85 0.20.00 2.9 1.35 2.40.18

0.51.15

0 4 mm2

scale

terminal 1

index area

AA1

2 6

13 9

terminal 1

index area

AC B

detail X

Fig. 11. Package outline SOT762-1 (DHVQFN14)

Product data sheet Rev. 9 — 24 August 2020 10 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

12. Abbreviations

Table 9. Abbreviations

Acronym Description

CDM Charged Device Model

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

13. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC02A v.9 20200824 Product data sheet - 74LVC02A v.8

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

•Table 4: Derating values for Ptot total power dissipation have been updated.

•Package outline drawing of SOT762-1 (Fig. 11) updated.

74LVC02A v.8 20111116 Product data sheet - 74LVC02A v.7

Modifications: •Legal pages updated.

•Table 6, bodyrow ΔICC: condition VCC changed.

74LVC02A v.7 20111019 Product data sheet - 74LVC02A v.6

74LVC02A v.6 20110809 Product data sheet - 74LVC02A v.5

74LVC02A v.5 20040312 Product specification - 74LVC02A v.4

74LVC02A v.4 20030501 Product specification - 74LVC02A v.3

74LVC02A v.3 20020305 Product specification - 74LVC02A v.2

74LVC02A v.2 19980428 Product specification - 74LVC02A v.1

74LVC02A v.1 19970811 Product specification - -

Product data sheet Rev. 9 — 24 August 2020 11 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

14. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

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product data given in the Limiting values and Characteristics sections of this

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or warranty that such applications will be suitable for the specified use

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

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In the event that customer uses the product for design-in and use in

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Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Product data sheet Rev. 9 — 24 August 2020 12 / 13

Nexperia 74LVC02A

Quad 2-input NOR gate

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................2

5.1. Pinning.........................................................................2

5.2. Pin description............................................................. 2

6. Functional description................................................. 3

7. Limiting values............................................................. 3

8. Recommended operating conditions..........................3

9. Static characteristics....................................................4

10. Dynamic characteristics............................................ 5

10.1. Waveforms and test circuit........................................ 6

11. Package outline.......................................................... 7

12. Abbreviations............................................................ 11

13. Revision history........................................................11

14. Legal information......................................................12

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 24 August 2020

Product data sheet Rev. 9 — 24 August 2020 13 / 13