Freescale Semiconductor Data Sheet: Technical Data Document Number: K10P32M50SF0 Rev. 4 5/2012 K10P32M50SF0 K10 Sub-Family Supports the following: MK10DN32VFM5, MK10DX32VFM5, MK10DN64VFM5, MK10DX64VFM5, MK10DN128VFM5, MK10DX128VFM5 Features * Operating Characteristics - Voltage range: 1.71 to 3.6 V - Flash write voltage range: 1.71 to 3.6 V - Temperature range (ambient): -40 to 105C * Performance - Up to 50 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz * Memories and memory interfaces - Up to 128 KB program flash. - Up to 32 KB FlexNVM on FlexMemory devices - 2 KB FlexRAM on FlexMemory devices - Up to 16 KB RAM - Serial programming interface (EzPort) * Clocks - 3 to 32 MHz crystal oscillator - 32 kHz crystal oscillator - Multi-purpose clock generator * System peripherals - Multiple low-power modes to provide power optimization based on application requirements - 4-channel DMA controller, supporting up to 41 request sources - External watchdog monitor - Software watchdog - Low-leakage wakeup unit * Security and integrity modules - Hardware CRC module to support fast cyclic redundancy checks - 128-bit unique identification (ID) number per chip * Analog modules - 16-bit SAR ADC - Two analog comparators (CMP) containing a 6-bit DAC and programmable reference input * Timers - Programmable delay block - Eight-channel motor control/general purpose/PWM timer - Two-channel quadrature decoder/general purpose timer - Periodic interrupt timers - 16-bit low-power timer - Carrier modulator transmitter - Real-time clock * Communication interfaces - SPI module - I2C module - Three UART modules - I2S module Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) 2011-2012 Freescale Semiconductor, Inc. Table of Contents 1 Ordering parts...........................................................................3 1.1 Determining valid orderable parts......................................3 5.3.2 General switching specifications...........................20 5.4 Thermal specifications.......................................................21 2 Part identification......................................................................3 5.4.1 Thermal operating requirements...........................21 2.1 Description.........................................................................3 5.4.2 Thermal attributes.................................................21 2.2 Format...............................................................................3 6 Peripheral operating requirements and behaviors....................22 2.3 Fields.................................................................................3 6.1 Core modules....................................................................22 2.4 Example............................................................................4 6.1.1 JTAG electricals....................................................22 3 Terminology and guidelines......................................................4 6.2 System modules................................................................25 3.1 Definition: Operating requirement......................................4 6.3 Clock modules...................................................................25 3.2 Definition: Operating behavior...........................................5 6.3.1 MCG specifications...............................................25 3.3 Definition: Attribute............................................................5 6.3.2 Oscillator electrical specifications.........................27 3.4 Definition: Rating...............................................................6 6.3.3 32 kHz Oscillator Electrical Characteristics...........29 3.5 Result of exceeding a rating..............................................6 3.6 Relationship between ratings and operating requirements......................................................................6 6.4 Memories and memory interfaces.....................................30 6.4.1 Flash electrical specifications................................30 6.4.2 EzPort Switching Specifications............................34 3.7 Guidelines for ratings and operating requirements............7 6.5 Security and integrity modules..........................................35 3.8 Definition: Typical value.....................................................7 6.6 Analog...............................................................................35 3.9 Typical value conditions....................................................8 6.6.1 ADC electrical specifications.................................35 4 Ratings......................................................................................9 6.6.2 CMP and 6-bit DAC electrical specifications.........40 4.1 Thermal handling ratings...................................................9 6.7 Timers................................................................................43 4.2 Moisture handling ratings..................................................9 6.8 Communication interfaces.................................................43 4.3 ESD handling ratings.........................................................9 6.8.1 4.4 Voltage and current operating ratings...............................9 DSPI switching specifications (limited voltage range)....................................................................43 5 General.....................................................................................10 6.8.2 DSPI switching specifications (full voltage range).45 5.1 AC electrical characteristics..............................................10 6.8.3 I2C switching specifications..................................47 5.2 Nonswitching electrical specifications...............................10 6.8.4 UART switching specifications..............................47 6.8.5 I2S/SAI Switching Specifications..........................47 5.2.1 Voltage and current operating requirements.........10 5.2.2 LVD and POR operating requirements.................11 5.2.3 Voltage and current operating behaviors..............12 5.2.4 Power mode transition operating behaviors..........13 7 Dimensions...............................................................................53 5.2.5 Power consumption operating behaviors..............14 7.1 Obtaining package dimensions.........................................53 5.2.6 EMC radiated emissions operating behaviors.......18 8 Pinout........................................................................................53 5.2.7 Designing with radiated emissions in mind...........19 8.1 K10 Signal Multiplexing and Pin Assignments..................53 5.2.8 Capacitance attributes..........................................19 8.2 K10 Pinouts.......................................................................54 5.3 Switching specifications.....................................................19 9 Revision History........................................................................55 5.3.1 6.9 Human-machine interfaces (HMI)......................................51 6.9.1 TSI electrical specifications...................................51 Device clock specifications...................................19 K10 Sub-Family Data Sheet, Rev. 4 5/2012. 2 Freescale Semiconductor, Inc. Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK10 and MK10 . 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status * M = Fully qualified, general market flow * P = Prequalification K## Kinetis family * K10 A Key attribute * D = Cortex-M4 w/ DSP * F = Cortex-M4 w/ DSP and FPU M Flash memory type * N = Program flash only * X = Program flash and FlexMemory Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 3 Terminology and guidelines Field Description Values FFF Program flash memory size * * * * * * 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB R Silicon revision * Z = Initial * (Blank) = Main * A = Revision after main T Temperature range (C) * V = -40 to 105 * C = -40 to 85 PP Package identifier * * * * * * * * * * * * * FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LK = 80 LQFP (12 mm x 12 mm) MB = 81 MAPBGA (8 mm x 8 mm) LL = 100 LQFP (14 mm x 14 mm) ML = 104 MAPBGA (8 mm x 8 mm) MC = 121 MAPBGA (8 mm x 8 mm) LQ = 144 LQFP (20 mm x 20 mm) MD = 144 MAPBGA (13 mm x 13 mm) MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) * * * * * 5 = 50 MHz 7 = 72 MHz 10 = 100 MHz 12 = 120 MHz 15 = 150 MHz N Packaging type * R = Tape and reel * (Blank) = Trays 2.4 Example This is an example part number: MK10DN32VFM5 3 Terminology and guidelines K10 Sub-Family Data Sheet, Rev. 4 5/2012. 4 Freescale Semiconductor, Inc. Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol IWP Description Digital I/O weak pullup/ 10 pulldown current Min. Max. 130 Unit A 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 5 Terminology and guidelines 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. -- Max. 7 Unit pF 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. -0.3 Max. 1.2 Unit V 3.5 Result of exceeding a rating Failures in time (ppm) 40 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic K10 Sub-Family Data Sheet, Rev. 4 5/2012. 6 Freescale Semiconductor, Inc. Terminology and guidelines 3.6 Relationship between ratings and operating requirements e Op ing rat r ( ng ati in. t (m ) n. mi rat e Op ing ) t (m e ir qu re n me ing rat e Op ax .) e ir qu re n me ing rat e Op ng ati ax (m .) r Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure - Operating (power on) g lin nd Ha in rat n.) mi g( nd Ha g lin ing rat ax (m .) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure - Handling (power off) 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 7 Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit A 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (A) 3500 150 C 3000 105 C 2500 25 C 2000 -40 C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 C VDD 3.3 V supply voltage 3.3 V K10 Sub-Family Data Sheet, Rev. 4 5/2012. 8 Freescale Semiconductor, Inc. Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature -55 150 C 1 TSDR Solder temperature, lead-free -- 260 C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes -- 3 -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105C -100 +100 mA ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol VDD Description Min. Max. Unit Digital supply voltage -0.3 3.8 V Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 9 General Symbol IDD Description Digital supply current Min. Max. Unit -- 155 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) -0.3 VDD + 0.3 V VAIO Analog1, RESET, EXTAL, and XTAL input voltage -0.3 VDD + 0.3 V Maximum current single pin limit (applies to all port pins) -25 25 mA VDD - 0.3 VDD + 0.3 V -0.3 3.8 V ID VDDA Analog supply voltage VBAT RTC battery supply voltage 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins * have CL=30pF loads, * are configured for fast slew rate (PORTx_PCRn[SRE]=0), and * are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins * have their passive filter disabled (PORTx_PCRn[PFE]=0) 5.2 Nonswitching electrical specifications K10 Sub-Family Data Sheet, Rev. 4 5/2012. 10 Freescale Semiconductor, Inc. General 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD - VDDA VDD-to-VDDA differential voltage -0.1 0.1 V VSS - VSSA VSS-to-VSSA differential voltage -0.1 0.1 V 1.71 3.6 V * 2.7 V VDD 3.6 V 0.7 x VDD -- V * 1.7 V VDD 2.7 V 0.75 x VDD -- V * 2.7 V VDD 3.6 V -- 0.35 x VDD V * 1.7 V VDD 2.7 V -- 0.3 x VDD V 0.06 x VDD -- V VBAT VIH VIL RTC battery supply voltage Input high voltage Input low voltage VHYS Input hysteresis IICIO I/O pin DC injection current -- single pin 1 mA * VIN < VSS-0.3V (Negative current injection) -3 -- -- +3 -25 -- -- +25 1.2 -- V VPOR_VBAT -- V * VIN > VDD+0.3V (Positive current injection) IICcont Contiguous pin DC injection current --regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins * Negative current injection * Positive current injection VRAM VRFVBAT Notes VDD voltage required to retain RAM VBAT voltage required to retain the VBAT register file mA 1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances. 5.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol VPOR Description Min. Typ. Max. Unit Falling VDD POR detect voltage 0.8 1.1 1.5 V Notes Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 11 General Table 2. VDD supply LVD and POR operating requirements (continued) Symbol VLVDH Description Min. Typ. Max. Unit Falling low-voltage detect threshold -- high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds -- high range 1 VLVW1H * Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H * Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H * Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H * Level 4 falling (LVWV=11) 2.92 3.00 3.08 V -- 80 -- mV 1.54 1.60 1.66 V VHYSH Low-voltage inhibit reset/recover hysteresis -- high range VLVDL Falling low-voltage detect threshold -- low range (LVDV=00) Low-voltage warning thresholds -- low range 1 VLVW1L * Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L * Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L * Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L * Level 4 falling (LVWV=11) 2.04 2.10 2.16 V -- 60 -- mV VHYSL Low-voltage inhibit reset/recover hysteresis -- low range Notes VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period -- factory trimmed 900 1000 1100 s 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes K10 Sub-Family Data Sheet, Rev. 4 5/2012. 12 Freescale Semiconductor, Inc. General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Description Min. Max. Unit * 2.7 V VDD 3.6 V, IOH = - 9 mA VDD - 0.5 -- V * 1.71 V VDD 2.7 V, IOH = -3 mA VDD - 0.5 -- V * 2.7 V VDD 3.6 V, IOH = -2 mA VDD - 0.5 -- V * 1.71 V VDD 2.7 V, IOH = -0.6 mA VDD - 0.5 -- V -- 100 mA * 2.7 V VDD 3.6 V, IOL = 9 mA -- 0.5 V * 1.71 V VDD 2.7 V, IOL = 3 mA -- 0.5 V * 2.7 V VDD 3.6 V, IOL = 2 mA -- 0.5 V * 1.71 V VDD 2.7 V, IOL = 0.6 mA -- 0.5 V -- 100 mA * @ full temperature range -- 1.0 A * @ 25 C -- 0.1 A Notes Output high voltage -- high drive strength Output high voltage -- low drive strength IOHT Output high current total for all ports VOL Output low voltage -- high drive strength Output low voltage -- low drive strength IOLT IIN Output low current total for all ports Input leakage current (per pin) 1 IOZ Hi-Z (off-state) leakage current (per pin) -- 1 A IOZ Total Hi-Z (off-state) leakage current (all input pins) -- 4 A RPU Internal pullup resistors 22 50 k 2 RPD Internal pulldown resistors 22 50 k 3 1. Tested by ganged leakage method 2. Measured at Vinput = VSS 3. Measured at Vinput = VDD 5.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSxRUN recovery times in the following table assume this clock configuration: * CPU and system clocks = 50 MHz * Bus clock = 50 MHz * Flash clock = 25 MHz K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 13 General Table 5. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. * VLLS0 RUN * VLLS1 RUN * VLLS2 RUN * VLLS3 RUN * LLS RUN * VLPS RUN * STOP RUN Min. Max. Unit Notes -- 300 s 1 -- 130 s -- 130 s -- 70 s -- 70 s -- 6 s -- 5.2 s -- 5.2 s 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol IDDA IDD_RUN Description Analog supply current Run mode current -- all peripheral clocks disabled, code executing from flash * @ 1.8V Min. Typ. Max. Unit Notes -- -- See note mA 1 2 -- 13.7 15.1 mA -- 13.9 15.3 mA * @ 3.0V IDD_RUN Run mode current -- all peripheral clocks enabled, code executing from flash 3, 4 -- 16.1 18.2 mA -- 16.3 17.7 mA -- 16.7 18.4 mA * @ 1.8V * @ 3.0V * @ 25C * @ 125C IDD_WAIT Wait mode high frequency current at 3.0 V -- all peripheral clocks disabled -- 7.5 8.4 mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V -- all peripheral clocks disabled -- 5.6 6.4 mA 5 Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 14 Freescale Semiconductor, Inc. General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks disabled -- 867 -- A 6 IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks enabled -- 1.1 -- mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V -- 509 -- A 8 IDD_STOP Stop mode current at 3.0 V * @ -40 to 25C -- 310 426 A * @ 70C -- 384 458 A * @ 105C -- 629 1100 A * @ -40 to 25C -- 3.5 22.6 A * @ 70C -- 20.7 52.9 A * @ 105C -- 85 220 A * @ -40 to 25C -- 2.1 3.7 A * @ 70C -- 7.7 43.1 A * @ 105C -- 32.2 68 A * @ -40 to 25C -- 1.5 2.9 A * @ 70C -- 4.8 22.5 A * @ 105C -- 20 37.8 A * @ -40 to 25C -- 1.4 2.8 A * @ 70C -- 4.1 19.2 A * @ 105C -- 17.3 32.4 A * @ -40 to 25C -- 0.678 1.3 A * @ 70C -- 2.8 13.6 A * @ 105C -- 13.6 24.5 A -- 0.367 1.0 A -- 2.4 13.3 A -- 13.2 24.1 A IDD_VLPS IDD_LLS IDD_VLLS3 IDD_VLLS2 IDD_VLLS1 IDD_VLLS0 Very-low-power stop mode current at 3.0 V Low leakage stop mode current at 3.0 V Very low-leakage stop mode 3 current at 3.0 V Very low-leakage stop mode 2 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled * @ -40 to 25C * @ 70C * @ 105C Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 15 General Table 6. Power consumption operating behaviors (continued) Symbol IDD_VLLS0 Description * @ 70C * @ 105C Max. Unit -- 0.176 0.859 A -- 2.2 13.1 A -- 13 23.9 A -- 0.19 0.22 A -- 0.49 0.64 A -- 2.2 3.2 A Notes Average current with RTC and 32kHz disabled at 3.0 V * @ -40 to 25C * @ 70C * @ 105C IDD_VBAT Typ. Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled * @ -40 to 25C IDD_VBAT Min. Average current when CPU is not accessing RTC registers 9 * @ 1.8V * @ -40 to 25C * @ 70C * @ 105C -- 0.57 0.67 A -- 0.90 1.2 A -- 2.4 3.5 A -- 0.67 0.94 A -- 1.0 1.4 A -- 2.7 3.9 A * @ 3.0V * @ -40 to 25C * @ 70C * @ 105C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 4. Max values are measured with CPU executing DSP instructions 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode. 6. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Includes 32kHz oscillator current and RTC operation. 5.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: * * * * MCG in FBE mode No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFL K10 Sub-Family Data Sheet, Rev. 4 5/2012. 16 Freescale Semiconductor, Inc. General Figure 2. Run mode supply current vs. core frequency K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 17 General Figure 3. VLPR mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 64LQFP Symbol Description Frequency band (MHz) Typ. Unit Notes 1,2 VRE1 Radiated emissions voltage, band 1 0.15-50 19 dBV VRE2 Radiated emissions voltage, band 2 50-150 21 dBV VRE3 Radiated emissions voltage, band 3 150-500 19 dBV VRE4 Radiated emissions voltage, band 4 500-1000 11 dBV IEC level 0.15-1000 L -- VRE_IEC 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported K10 Sub-Family Data Sheet, Rev. 4 5/2012. 18 Freescale Semiconductor, Inc. General emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 C, fOSC = 12 MHz (crystal), fSYS = 48 MHz, fBUS = 48MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to http://www.freescale.com. 2. Perform a keyword search for "EMC design." 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins -- 7 pF CIN_D Input capacitance: digital pins -- 7 pF 5.3 Switching specifications 5.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit Notes Normal run mode fSYS System and core clock -- 50 MHz fBUS Bus clock -- 50 MHz fFLASH Flash clock -- 25 MHz fLPTMR LPTMR clock -- 25 MHz VLPR mode1 fSYS System and core clock -- 4 MHz fBUS Bus clock -- 4 MHz fFLASH Flash clock -- 1 MHz fERCLK External reference clock -- 16 MHz Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 19 General Table 9. Device clock specifications (continued) Symbol Description Min. Max. Unit fLPTMR_pin LPTMR clock -- 25 MHz LPTMR external reference clock -- 16 MHz fI2S_MCLK I2S master clock -- 12.5 MHz fI2S_BCLK I2S bit clock -- 4 MHz fLPTMR_ERCLK Notes 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CMT, and I2C signals. Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path 1.5 -- Bus clock cycles 1, 2 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) -- Asynchronous path 100 -- ns 3 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) -- Asynchronous path 50 -- ns 3 External reset pulse width (digital glitch filter disabled) 100 -- ns 3 2 -- Bus clock cycles Mode select (EZP_CS) hold time after reset deassertion Port rise and fall time (high drive strength) 4 * Slew disabled * 1.71 VDD 2.7V -- * 2.7 VDD 3.6V -- 13 ns ns 7 * Slew enabled * 1.71 VDD 2.7V -- * 2.7 VDD 3.6V -- ns 36 ns 24 Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 20 Freescale Semiconductor, Inc. General Table 10. General switching specifications (continued) Symbol Description Min. Max. Unit Port rise and fall time (low drive strength) Notes 5 * Slew disabled * 1.71 VDD 2.7V -- 12 ns * 2.7 VDD 3.6V -- 6 ns * 1.71 VDD 2.7V -- 36 ns * 2.7 VDD 3.6V -- 24 ns * Slew enabled 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75pF load 5. 15pF load 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature -40 125 C TA Ambient temperature -40 105 C 5.4.2 Thermal attributes Board type Symbol Description Single-layer (1s) RJA Four-layer (2s2p) RJA 32 QFN Unit Notes Thermal 94 resistance, junction to ambient (natural convection) C/W 1, 2 Thermal 32 resistance, junction to ambient (natural convection) C/W 1, 3 Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 21 Peripheral operating requirements and behaviors Board type Symbol Description Unit Notes Single-layer (1s) RJMA Thermal 78 resistance, junction to ambient (200 ft./ min. air speed) C/W 1,3 Four-layer (2s2p) RJMA Thermal 27 resistance, junction to ambient (200 ft./ min. air speed) C/W , -- RJB Thermal 12 resistance, junction to board C/W 5 -- RJC Thermal 1.5 resistance, junction to case C/W 6 -- JT Thermal 6 characterization parameter, junction to package top outside center (natural convection) C/W 7 1. 2. 3. 5. 6. 7. 32 QFN Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions--Forced Convection (Moving Air) with the board horizontal. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions--Junction-to-Board. Board temperature is measured on the top surface of the board near the package. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air). 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 JTAG electricals Table 12. JTAG voltage range electricals Symbol Description Min. Max. Unit Operating voltage 2.7 5.5 V Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 22 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 12. JTAG voltage range electricals (continued) Symbol J1 Description Min. Max. TCLK frequency of operation Unit MHz * JTAG -- 10 * CJTAG -- 5 J2 TCLK cycle period 1/J1 -- ns J3 TCLK clock pulse width * JTAG 100 -- ns * CJTAG 200 -- ns ns J4 TCLK rise and fall times J5 TMS input data setup time to TCLK rise * JTAG * CJTAG J6 TDI input data setup time to TCLK rise J7 TMS input data hold time after TCLK rise * JTAG * CJTAG J8 TDI input data hold time after TCLK rise J9 TCLK low to TMS data valid * JTAG * CJTAG -- 1 53 -- 112 -- 8 -- 3.4 -- 3.4 -- 3.4 -- -- 48 -- 85 ns ns ns ns ns ns J10 TCLK low to TDO data valid -- 48 ns J11 Output data hold/invalid time after clock edge1 -- 3 ns 1. They are common for JTAG and CJTAG. Input transition = 1 ns and Output load = 50pf J2 J3 J3 TCLK (input) J4 J4 Figure 4. Test clock input timing K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 23 Peripheral operating requirements and behaviors TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 5. Boundary scan (JTAG) timing TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 6. Test Access Port timing K10 Sub-Family Data Sheet, Rev. 4 5/2012. 24 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors TCLK J14 J13 TRST Figure 7. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules 6.3.1 MCG specifications Table 13. MCG specifications Symbol Description Min. Typ. Max. Unit -- 32.768 -- kHz 31.25 -- 39.0625 kHz Resolution of trimmed average DCO output frequency at fixed voltage and temperature -- using SCTRIM and SCFTRIM -- 0.3 0.6 %fdco 1 fdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature -- +0.5/-0.7 3 %fdco 1 fdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0-70C -- 0.3 -- %fdco 1 fintf_ft Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25C -- 4 -- MHz fintf_t Internal reference frequency (fast clock) -- user trimmed at nominal VDD and 25 C 3 -- 5 MHz fints_ft Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25 C fints_t Internal reference frequency (slow clock) -- user trimmed fdco_res_t floc_low Loss of external clock minimum frequency -- RANGE = 00 (3/5) x fints_t -- -- kHz floc_high Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 (16/5) x fints_t -- -- kHz Notes FLL Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 25 Peripheral operating requirements and behaviors Table 13. MCG specifications (continued) Symbol ffll_ref fdco Description FLL reference frequency range DCO output frequency range Low range (DRS=00) Min. Typ. Max. Unit 31.25 -- 39.0625 kHz 20 20.97 25 MHz 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz -- 23.99 -- MHz -- 47.97 -- MHz -- 71.99 -- MHz -- 95.98 -- MHz -- 180 -- -- 150 -- -- -- 1 ms 48.0 -- 100 MHz -- 1060 -- A -- 600 -- A 2.0 -- 4.0 MHz Notes 2, 3 640 x ffll_ref Mid range (DRS=01) 1280 x ffll_ref Mid-high range (DRS=10) 1920 x ffll_ref High range (DRS=11) 2560 x ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS=00) 4, 5 732 x ffll_ref Mid range (DRS=01) 1464 x ffll_ref Mid-high range (DRS=10) 2197 x ffll_ref High range (DRS=11) 2929 x ffll_ref Jcyc_fll FLL period jitter * fVCO = 48 MHz * fVCO = 98 MHz tfll_acquire FLL target frequency acquisition time ps 6 PLL fvco VCO operating frequency Ipll PLL operating current * PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) Ipll PLL operating current * PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) fpll_ref PLL reference frequency range Jcyc_pll PLL period jitter (RMS) 7 7 8 * fvco = 48 MHz -- 120 -- ps * fvco = 100 MHz -- 50 -- ps Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 26 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 13. MCG specifications (continued) Symbol Description Min. Jacc_pll PLL accumulated jitter over 1s (RMS) Typ. Max. Unit Notes 8 * fvco = 48 MHz -- 1350 -- ps * fvco = 100 MHz -- 600 -- ps Dlock Lock entry frequency tolerance 1.49 -- 2.98 % Dunl Lock exit frequency tolerance 4.47 -- 5.97 % tpll_lock Lock detector detection time -- -- 150 x 10-6 + 1075(1/ fpll_ref) s 9 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. 6.3.2.1 Symbol VDD IDDOSC Oscillator DC electrical specifications Table 14. Oscillator DC electrical specifications Description Min. Typ. Max. Unit Supply voltage 1.71 -- 3.6 V Supply current -- low-power mode (HGO=0) Notes 1 * 32 kHz -- 500 -- nA * 4 MHz -- 200 -- A * 8 MHz (RANGE=01) -- 300 -- A * 16 MHz -- 950 -- A * 24 MHz -- 1.2 -- mA * 32 MHz -- 1.5 -- mA Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 27 Peripheral operating requirements and behaviors Table 14. Oscillator DC electrical specifications (continued) Symbol Description Min. IDDOSC Supply current -- high gain mode (HGO=1) Typ. Max. Unit Notes 1 * 32 kHz -- 25 -- A * 4 MHz -- 400 -- A * 8 MHz (RANGE=01) -- 500 -- A * 16 MHz -- 2.5 -- mA * 24 MHz -- 3 -- mA * 32 MHz -- 4 -- mA Cx EXTAL load capacitance -- -- -- 2, 3 Cy XTAL load capacitance -- -- -- 2, 3 RF Feedback resistor -- low-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- low-frequency, high-gain mode (HGO=1) -- 10 -- M Feedback resistor -- high-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- high-frequency, high-gain mode (HGO=1) -- 1 -- M Series resistor -- low-frequency, low-power mode (HGO=0) -- -- -- k Series resistor -- low-frequency, high-gain mode (HGO=1) -- 200 -- k Series resistor -- high-frequency, low-power mode (HGO=0) -- -- -- k -- 0 -- k Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) -- VDD -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, high-gain mode (HGO=1) -- VDD -- V RS 2, 4 Series resistor -- high-frequency, high-gain mode (HGO=1) Vpp5 1. 2. 3. 4. VDD=3.3 V, Temperature =25 C See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. K10 Sub-Family Data Sheet, Rev. 4 5/2012. 28 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Symbol Oscillator frequency specifications Table 15. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency -- low frequency mode (MCG_C2[RANGE]=00) 32 -- 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency -- high frequency mode (low range) (MCG_C2[RANGE]=01) 3 -- 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 -- 32 MHz fec_extal Input clock frequency (external clock mode) -- -- 50 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) -- 750 -- ms Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) -- 250 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) -- 0.6 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) -- 1 -- ms tcst Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 6.3.3 32 kHz Oscillator Electrical Characteristics This section describes the module electrical characteristics. 6.3.3.1 Symbol VBAT RF 32 kHz oscillator DC electrical specifications Table 16. 32kHz oscillator DC electrical specifications Description Min. Typ. Max. Unit Supply voltage 1.71 -- 3.6 V -- 100 -- M Internal feedback resistor Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 29 Peripheral operating requirements and behaviors Table 16. 32kHz oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Cpara Parasitical capacitance of EXTAL32 and XTAL32 -- 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation -- 0.6 -- V 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 Symbol 32kHz oscillator frequency specifications Table 17. 32kHz oscillator frequency specifications Min. Typ. Max. Unit Oscillator crystal -- 32.768 -- kHz Crystal start-up time -- 1000 -- ms 1 fec_extal32 Externally provided input clock frequency -- 32.768 -- kHz 2 vec_extal32 Externally provided input clock amplitude 700 -- VBAT mV 2, 3 fosc_lo tstart Description Notes 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. 6.4 Memories and memory interfaces 6.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 6.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 18. NVM program/erase timing specifications Symbol Description thvpgm4 thversscr thversblk32k Min. Typ. Max. Unit Longword Program high-voltage time -- 7.5 18 s Sector Erase high-voltage time -- 13 113 ms 1 Erase Block high-voltage time for 32 KB -- 52 452 ms 1 -- 52 452 ms 1 thversblk128k Erase Block high-voltage time for 128 KB Notes 1. Maximum time based on expectations at cycling end-of-life. K10 Sub-Family Data Sheet, Rev. 4 5/2012. 30 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.4.1.2 Symbol Flash timing specifications -- commands Table 19. Flash command timing specifications Description Min. Typ. Max. Unit Notes Read 1s Block execution time trd1blk32k * 32 KB data flash -- -- 0.5 ms trd1blk128k * 128 KB program flash -- -- 1.7 ms trd1sec1k Read 1s Section execution time (flash sector) -- -- 60 s 1 tpgmchk Program Check execution time -- -- 45 s 1 trdrsrc Read Resource execution time -- -- 30 s 1 tpgm4 Program Longword execution time -- 65 145 s Erase Flash Block execution time 2 tersblk32k * 32 KB data flash -- 55 465 ms tersblk128k * 128 KB program flash -- 61 495 ms -- 14 114 ms tersscr Erase Flash Sector execution time 2 Program Section execution time tpgmsec512 * 512 B flash -- 4.7 -- ms tpgmsec1k * 1 KB flash -- 9.3 -- ms trd1all Read 1s All Blocks execution time -- -- 1.8 ms trdonce Read Once execution time -- -- 25 s Program Once execution time -- 65 -- s tersall Erase All Blocks execution time -- 115 1000 ms 2 tvfykey Verify Backdoor Access Key execution time -- -- 30 s 1 -- 70 -- ms tpgmonce 1 Program Partition for EEPROM execution time tpgmpart32k * 32 KB FlexNVM Set FlexRAM Function execution time: tsetramff * Control Code 0xFF -- 50 -- s tsetram8k * 8 KB EEPROM backup -- 0.3 0.5 ms tsetram32k * 32 KB EEPROM backup -- 0.7 1.0 ms Byte-write to FlexRAM for EEPROM operation teewr8bers Byte-write to erased FlexRAM location execution time -- 175 260 s 3 Byte-write to FlexRAM execution time: teewr8b8k * 8 KB EEPROM backup -- 340 1700 s teewr8b16k * 16 KB EEPROM backup -- 385 1800 s teewr8b32k * 32 KB EEPROM backup -- 475 2000 s Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 31 Peripheral operating requirements and behaviors Table 19. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time -- 175 260 s Word-write to FlexRAM execution time: teewr16b8k * 8 KB EEPROM backup -- 340 1700 s teewr16b16k * 16 KB EEPROM backup -- 385 1800 s teewr16b32k * 32 KB EEPROM backup -- 475 2000 s Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time -- 360 540 s Longword-write to FlexRAM execution time: teewr32b8k * 8 KB EEPROM backup -- 545 1950 s teewr32b16k * 16 KB EEPROM backup -- 630 2050 s teewr32b32k * 32 KB EEPROM backup -- 810 2250 s 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. 6.4.1.3 Flash high voltage current behaviors Table 20. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 6.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation -- 2.5 6.0 mA Average current adder during high voltage flash erase operation -- 1.5 4.0 mA Reliability specifications Table 21. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 -- years tnvmretp1k Data retention after up to 1 K cycles 20 100 -- years nnvmcycp Cycling endurance 10 K 50 K -- cycles 50 -- years 2 Data Flash tnvmretd10k Data retention after up to 10 K cycles 5 Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 32 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 21. NVM reliability specifications (continued) Symbol Description tnvmretd1k Data retention after up to 1 K cycles nnvmcycd Cycling endurance Min. Typ.1 Max. Unit 20 100 -- years 10 K 50 K -- cycles Notes 2 FlexRAM as EEPROM tnvmretee100 Data retention up to 100% of write endurance 5 50 -- years tnvmretee10 20 100 -- years Data retention up to 10% of write endurance Write endurance 3 nnvmwree16 * EEPROM backup to FlexRAM ratio = 16 35 K 175 K -- writes nnvmwree128 * EEPROM backup to FlexRAM ratio = 128 315 K 1.6 M -- writes nnvmwree512 * EEPROM backup to FlexRAM ratio = 512 1.27 M 6.4 M -- writes nnvmwree4k * EEPROM backup to FlexRAM ratio = 4096 10 M 50 M -- writes * EEPROM backup to FlexRAM ratio = 8192 20 M 100 M -- writes nnvmwree8k 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40C Tj 125C. 3. Write endurance represents the number of writes to each FlexRAM location at -40C Tj 125C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum and typical values assume all byte-writes to FlexRAM. 6.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_FlexRAM = EEPROM - 2 x EEESIZE EEESIZE x Write_efficiency x nnvmcycd where * Writes_FlexRAM -- minimum number of writes to each FlexRAM location K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 33 Peripheral operating requirements and behaviors * EEPROM -- allocated FlexNVM based on DEPART; entered with the Program Partition command * EEESIZE -- allocated FlexRAM based on DEPART; entered with the Program Partition command * Write_efficiency -- * 0.25 for 8-bit writes to FlexRAM * 0.50 for 16-bit or 32-bit writes to FlexRAM * nnvmcycd -- data flash cycling endurance (the following graph assumes 10,000 cycles) Figure 8. EEPROM backup writes to FlexRAM 6.4.2 EzPort Switching Specifications Table 22. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 34 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 22. EzPort switching specifications (continued) Num Description Min. Max. Unit EP1 EZP_CK frequency of operation (all commands except READ) -- fSYS/2 MHz EP1a EZP_CK frequency of operation (READ command) -- fSYS/8 MHz EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK -- ns EP3 EZP_CS input valid to EZP_CK high (setup) 5 -- ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 -- ns EP5 EZP_D input valid to EZP_CK high (setup) 2 -- ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 -- ns EP7 EZP_CK low to EZP_Q output valid -- 17 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 -- ns EP9 EZP_CS negation to EZP_Q tri-state -- 12 ns EZP_CK EP3 EP2 EP4 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 9. EzPort Timing Diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 35 Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit ADC operating conditions Table 23. 16-bit ADC operating conditions Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 -- 3.6 V VDDA Supply voltage Delta to VDD (VDDVDDA) -100 0 +100 mV 2 VSSA Ground voltage Delta to VSS (VSSVSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL Reference voltage low VSSA VSSA VSSA V VADIN Input voltage VREFL -- VREFH V CADIN Input capacitance * 16 bit modes -- 8 10 pF * 8/10/12 bit modes -- 4 5 -- 2 5 Symbol RADIN RAS fADCK fADCK Crate Input resistance Analog source resistance 12 bit modes ADC conversion clock frequency bit modes ADC conversion clock frequency 16 bit modes ADC conversion rate bit modes Notes k 3 fADCK < 4MHz -- -- 5 k 4 1.0 -- 18.0 MHz 4 2.0 -- 12.0 MHz 5 No ADC hardware averaging 20.000 -- 818.330 Ksps Continuous conversions enabled, subsequent conversion time Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 36 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 23. 16-bit ADC operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate 16 bit modes Typ.1 Min. Max. Unit Notes 5 No ADC hardware averaging 37.037 -- 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the best results. The results in this datasheet were derived from a system which has <8 analog source resistance. The RAS/ CAS time constant should be kept to <1ns. 4. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/ files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1 SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection Z AS R AS ADC SAR ENGINE R ADIN V ADIN C AS V AS R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 10. ADC input impedance equivalency diagram 6.6.1.2 16-bit ADC electrical characteristics Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current Conditions1 Min. Typ.2 Max. Unit Notes 0.215 -- 1.7 mA 3 Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 37 Peripheral operating requirements and behaviors Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol fADACK Description ADC asynchronous clock source Sample Time TUE DNL INL EFS Conditions1 Min. Typ.2 Max. Unit Notes * ADLPC=1, ADHSC=0 1.2 2.4 3.9 MHz * ADLPC=1, ADHSC=1 3.0 4.0 7.3 MHz tADACK = 1/ fADACK * ADLPC=0, ADHSC=0 2.4 5.2 6.1 MHz * ADLPC=0, ADHSC=1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA See Reference Manual chapter for sample times Total unadjusted error * 12 bit modes -- 4 6.8 * <12 bit modes -- 1.4 2.1 Differential nonlinearity * 12 bit modes -- 0.7 -1.1 to +1.9 * <12 bit modes -- 0.2 * 12 bit modes -- 1.0 * <12 bit modes -- 0.5 -0.7 to +0.5 * 12 bit modes -- -4 -5.4 * <12 bit modes -- -1.4 -1.8 Integral nonlinearity Full-scale error -0.3 to 0.5 -2.7 to +1.9 5 EQ ENOB Quantization error * 16 bit modes -- -1 to 0 -- * bit modes -- -- 0.5 Effective number 16 bit differential mode of bits * Avg=32 * Avg=4 LSB4 6 12.8 14.5 -- bits 11.9 13.8 -- bits 12.2 13.9 -- bits 11.4 13.1 -- bits 16 bit single-ended mode * Avg=32 * Avg=4 SINAD THD Signal-to-noise plus distortion See ENOB Total harmonic distortion 16 bit differential mode 6.02 x ENOB + 1.76 * Avg=32 16 bit single-ended mode * Avg=32 dB 7 -- -94 -- dB -- -85 -- dB Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 38 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol SFDR Description Conditions1 Spurious free dynamic range 16 bit differential mode * Avg=32 16 bit single-ended mode * Avg=32 EIL Min. Typ.2 Max. Unit Notes 7 82 95 -- dB 78 90 -- dB Input leakage error IIn x RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope -40C to 105C -- 1.715 -- mV/C Temp sensor voltage 25C -- 719 -- mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz. K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 39 Peripheral operating requirements and behaviors Figure 11. Typical ENOB vs. ADC_CLK for 16-bit differential mode Figure 12. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode K10 Sub-Family Data Sheet, Rev. 4 5/2012. 40 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.6.2 CMP and 6-bit DAC electrical specifications Table 25. Comparator and 6-bit DAC electrical specifications Symbol VDD Description Min. Typ. Max. Unit Supply voltage 1.71 -- 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) -- -- 200 A IDDLS Supply current, low-speed mode (EN=1, PMODE=0) -- -- 20 A VAIN Analog input voltage VSS - 0.3 -- VDD V VAIO Analog input offset voltage -- -- 20 mV * CR0[HYSTCTR] = 00 -- 5 -- mV * CR0[HYSTCTR] = 01 -- 10 -- mV * CR0[HYSTCTR] = 10 -- 20 -- mV * CR0[HYSTCTR] = 11 -- 30 -- mV VH Analog comparator hysteresis1 VCMPOh Output high VDD - 0.5 -- -- V VCMPOl Output low -- -- 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 -- -- 40 s 6-bit DAC current adder (enabled) -- 7 -- A IDAC6b INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB3 DNL 6-bit DAC differential non-linearity -0.3 -- 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 41 Peripheral operating requirements and behaviors 0.08 0.07 0.06 HYSTCTR Setting CM P Hystereris (V) 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K10 Sub-Family Data Sheet, Rev. 4 5/2012. 42 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP P Hystereris (V) 0.12 HYSTCTR Setting 0.1 00 01 0 08 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.7 Timers See General switching specifications. 6.8 Communication interfaces K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 43 Peripheral operating requirements and behaviors 6.8.1 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 26. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation -- 25 MHz 2 x tBUS -- ns Notes DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 2 -- ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 2 -- ns 2 DS5 DSPI_SCK to DSPI_SOUT valid -- 8 ns DS6 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 14 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS1 DS2 DS4 DSPI_SCK DS8 DS7 (CPOL=0) DSPI_SIN Data First data Last data DS5 DSPI_SOUT First data DS6 Data Last data Figure 15. DSPI classic SPI timing -- master mode Table 27. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.6 V 12.5 MHz Frequency of operation Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 44 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 27. Slave mode DSPI timing (limited voltage range) (continued) Num Description Min. Max. Unit 4 x tBUS -- ns (tSCK/2) - 2 (tSCK/2) + 2 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid -- 20 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 2 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 14 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 14 ns DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DS12 DSPI_SOUT First data DS13 DS16 DS11 Last data Data DS14 DSPI_SIN First data Data Last data Figure 16. DSPI classic SPI timing -- slave mode 6.8.2 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 28. Master mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time Min. Max. Unit Notes 1.71 3.6 V 1 -- 12.5 MHz 4 x tBUS -- ns (tSCK/2) - 4 (tSCK/2) + 4 ns Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 45 Peripheral operating requirements and behaviors Table 28. Master mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit Notes DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 4 -- ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 4 -- ns 3 DS5 DSPI_SCK to DSPI_SOUT valid -- 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid -1.2 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 19.1 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS1 DS2 DS4 DSPI_SCK DS8 DS7 (CPOL=0) DSPI_SIN Data First data Last data DS5 DSPI_SOUT First data DS6 Data Last data Figure 17. DSPI classic SPI timing -- master mode Table 29. Slave mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit 1.71 3.6 V -- 6.25 MHz 8 x tBUS -- ns (tSCK/2) - 4 (tSCK/2) + 4 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid -- 24 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 3.2 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 19 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 19 ns K10 Sub-Family Data Sheet, Rev. 4 5/2012. 46 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Data Last data DS14 First data Data Last data Figure 18. DSPI classic SPI timing -- slave mode 6.8.3 I2C switching specifications See General switching specifications. 6.8.4 UART switching specifications See General switching specifications. 6.8.5 I2S/SAI Switching Specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 47 Peripheral operating requirements and behaviors 6.8.5.1 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 30. I2S/SAI master mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 15 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 25 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 19. I2S/SAI timing -- master modes K10 Sub-Family Data Sheet, Rev. 4 5/2012. 48 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 31. I2S/SAI slave mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 10 -- ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 29 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 10 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 2 -- ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 -- 21 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 20. I2S/SAI timing -- slave modes 6.8.5.2 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 49 Peripheral operating requirements and behaviors Table 32. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 45 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 45 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 45 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 21. I2S/SAI timing -- master modes Table 33. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. S11 Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 -- ns Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. 50 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 33. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 30 -- ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 3 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 63 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 30 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 2 -- ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 -- 72 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 22. I2S/SAI timing -- slave modes 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 34. TSI electrical specifications Symbol Description Min. Typ. Max. Unit VDDTSI Operating voltage 1.71 -- 3.6 V 1 20 500 pF CELE Target electrode capacitance range Notes 1 Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 51 Peripheral operating requirements and behaviors Table 34. TSI electrical specifications (continued) Symbol Description fREFmax fELEmax CREF VDELTA IREF IELE Min. Typ. Max. Unit Notes Reference oscillator frequency -- 8 15 MHz 2, 3 Electrode oscillator frequency -- 1 1.8 MHz 2, 4 Internal reference capacitor -- 1 -- pF Oscillator delta voltage -- 500 -- mV 2, 5 -- 2 3 A 2, 6 -- 36 50 -- 2 3 A 2, 7 -- 36 50 Reference oscillator current source base current * 2 A setting (REFCHRG = 0) * 32 A setting (REFCHRG = 15) Electrode oscillator current source base current * 2 A setting (EXTCHRG = 0) * 32 A setting (EXTCHRG = 15) Pres5 Electrode capacitance measurement precision -- 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision -- 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision -- 8.3333 38400 fF/count 10 MaxSens Maximum sensitivity 0.008 1.46 -- fF/count 11 Resolution -- -- 16 bits Response time @ 20 pF 8 15 25 s Current added in run mode -- 55 -- A Low power mode current adder -- 1.3 2.5 A Res TCon20 ITSI_RUN ITSI_LP 12 13 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10. 5. VDD = 3.0 V. 6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity depends on the configuration used. The documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN) The typical value is calculated with the following configuration: Iext = 6 A (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 A (REFCHRG = 7), Cref = 1.0 pF The minimum value is calculated with the following configuration: Iext = 2 A (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 A (REFCHRG = 15), Cref = 0.5 pF The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be measured by a single count. 12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, EXTCHRG = 7. 13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window. K10 Sub-Family Data Sheet, Rev. 4 5/2012. 52 Freescale Semiconductor, Inc. Dimensions 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawing's document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ARE10566D 8 Pinout 8.1 K10 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 32 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 1 VDD VDD VDD 2 VSS VSS VSS 3 PTE16 ADC0_SE4a ADC0_SE4a PTE16 SPI0_PCS0 UART2_TX FTM_CLKIN0 FTM0_FLT3 4 PTE17 ADC0_SE5a ADC0_SE5a PTE17 SPI0_SCK UART2_RX FTM_CLKIN1 LPTMR0_ALT3 5 PTE18 ADC0_SE6a ADC0_SE6a PTE18 SPI0_SOUT UART2_CTS_b I2C0_SDA 6 PTE19 ADC0_SE7a ADC0_SE7a PTE19 SPI0_SIN UART2_RTS_b I2C0_SCL 7 VDDA VDDA VDDA 8 VSSA VSSA VSSA 9 XTAL32 XTAL32 XTAL32 10 EXTAL32 EXTAL32 EXTAL32 11 VBAT VBAT VBAT 12 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS_ FTM0_CH5 b/ UART0_COL_b JTAG_TCLK/ SWD_CLK EZP_CLK 13 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2 PTA1 UART0_RX JTAG_TDI EZP_DI FTM0_CH6 K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 53 Pinout 32 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 FTM0_CH7 ALT4 ALT5 ALT6 14 PTA2 JTAG_TDO/ TRACE_SWO/ EZP_DO TSI0_CH3 PTA2 UART0_TX 15 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4 PTA3 UART0_RTS_b FTM0_CH0 16 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 FTM0_CH1 17 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0 18 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 19 RESET_b RESET_b RESET_b 20 PTB0/ LLWU_P5 ADC0_SE8/ TSI0_CH0 ADC0_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0 FTM1_QD_ PHA 21 PTB1 ADC0_SE9/ TSI0_CH6 ADC0_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_ PHB 22 PTC1/ LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3 UART1_RTS_b FTM0_CH0 I2S0_TXD0 23 PTC2 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2 UART1_CTS_b FTM0_CH1 I2S0_TX_FS 24 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 I2S0_TX_BCLK 25 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OUT 26 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ALT2 I2S0_RXD0 CMP0_OUT 27 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_EXTRG I2S0_MCLK 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN 29 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1 UART0_RTS_b FTM0_CH4 EWM_IN 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_ FTM0_CH5 b/ UART0_COL_b EWM_OUT_b 31 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FTM0_FLT0 32 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1 ALT7 JTAG_TDO/ TRACE_SWO EzPort EZP_DO JTAG_TMS/ SWD_DIO NMI_b I2S0_RX_BCLK EZP_CS_b LPTMR0_ALT1 I2S0_RX_FS 8.2 K10 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K10 Sub-Family Data Sheet, Rev. 4 5/2012. 54 Freescale Semiconductor, Inc. PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 32 31 30 29 28 27 26 25 Revision History 21 PTB1 PTE18 5 20 PTB0/LLWU_P5 PTE19 6 19 RESET_b VDDA 7 18 PTA19 VSSA 8 17 PTA18 EXTAL32 XTAL32 16 4 PTA4/LLWU_P3 PTE17 15 PTC1/LLWU_P6 PTA3 22 14 3 PTA2 PTE16 13 PTC2 PTA1 23 12 2 PTA0 VSS 11 PTC3/LLWU_P7 VBAT 24 10 1 9 VDD Figure 23. K10 32 QFN Pinout Diagram 9 Revision History The following table provides a revision history for this document. Table 35. Revision History Rev. No. Date 2 2/2012 3 4/2012 Substantial Changes Initial public release * * * * * * * * * * Replaced TBDs throughout. Updated "Power mode transition operating behaviors" table. Updated "Power consumption operating behaviors" table. For "Diagram: Typical IDD_RUN operating behavior" section, added "VLPR mode supply current vs. core frequency" figure. Updated "EMC radiated emissions operating behaviors" section. Updated "Thermal operating requirements" section. Updated "MCG specifications" table. Updated "VREF full-range operating behaviors" table. Updated "I2S/SAI Switching Specifications" section. Updated "TSI electrical specifications" table. Table continues on the next page... K10 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc. 55 Revision History Table 35. Revision History (continued) Rev. No. Date 4 5/2012 Substantial Changes * For the "32kHz oscillator frequency specifications", added specifications for an externally driven clock. * Renamed section "Flash current and power specfications" to section "Flash high voltage current behaviors" and improved the specifications. * For the "VREF full-range operating behaviors" table, removed the Ac (aging coefficient) specification. * Corrected the following DSPI switching specifications: tightened DS5, DS6, and DS7; relaxed DS11 and DS13. * Removed references to USB as non-applicable. * For the "TSI electrical specifications", changed and clarified the example calculations for the MaxSens specification. K10 Sub-Family Data Sheet, Rev. 4 5/2012. 56 Freescale Semiconductor, Inc. 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