ROSGOOORLASIAV FPGAS $= XILINX February 19, 1999 (Version 1.1} Product Specification ACSOOURLA/AY Parmily Features Electrical Features Note: XC4000XLA devices are improved versions of + XLA Devices Require 3.0 - 3.6 V (VCC) XC4000XL devices. The XC4000XV devices have the + XV Devices Require 2.3- 2.7 V (VCCINT) same features as XLA devices, incorporate additional inter- and 3.0 - 3.6 V (VCCIO) connect resources and extend gate capacity to 500,000 * 50VTTL compatible I/O system gates. The XC4000XV devices require a separate * 3.3 VLVTTL, VCMOS compliant I/O 2.5VV power supply for internal logic but maintain 5V I/O * 5.0 Vand 3.0 V PCI Compliant I/O compatibility via a separate 3.3V I/O power supply. For * 12 mAor 24 mA Current Sink Capability additional information about the XC4000XLA/XV device + Sate under All Power-up Sequences architecture, refer to the XC4000E/X FPGA Series general XLA Consumes 40% Less Power than XL and functional descriptions. + XV Consumes 65% Less Power than XL + Systemn-featured Field-Programmable Gate Arrays * Optional Input Clamping to VGC (XLA) or VCCIO (XV) - Select-RAM memory: on-chip ultra-fast RAM with - Synchronous write option Additional Features - Dual-port RAM option + Footprint Compatible with XC4000XL FPGAs - Lower - Flexible function generators and abundant flip-flops cost with improved performance and lower power - Dedicated high-speed carry logic + Advanced Technology 5 layer metal, 0.25 um CMOS - Internal 3-state bus capability process (XV) or 0.35 um CMOS process (XLA} - Eight global low-skew clock or signal distribution * Highest Performance System erformance beyond networks 100 MHz + Flexible Array Architecture + High Capacity Up to 500,000 system gates and Low-power Segmented Routing Architecture 270,000 synchronous SRAM bits + Systems-oriented Features + Low Power 3.3 V/2.5 V technology plus segmented - IEEE 1149.1-compatible boundary scan routing architecture - Individually programmable output slew rate Safe and Easy to Use Interfaces to any combination - Programmable input pull-up or pull-down resistors of 3.3 V and 5.0 V TTL compatible devices - Unlimited reprogrammability * Read Back Capability - Program verification and internal node observability Table 1: XC4000XLA Series Field Programmable Gate Arrays Max Logic | Max. RAM Typical Number Required Logic Gates Bits Gate Range CLB Total of Max. Configur- Device Cells (No RAM) | (No Logic) | (Logic and RAM)* Matrix CLBs | Flip-Flops| User I/O | ation Bits XC4013XLA 1,368 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 192 393,632 XC4020XLA 1,862 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 224 521,880 XC4028XLA 2,432 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 256 668, 184 XC4036XLA 3,078 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 288 832,528 XC4044XLA 3,800 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 320 1,014,928 XC4052XLA 4,598 52,000 61,952 33,000 - 190,000 44x 44 1,936 4,576 352 1,215,368 XC4062XLA 5,472 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 384 1,433,864 XC4085XLA 7,448 85,000 100,352 | 55,000-180,000 | 56x56 3,136 7,168 448 | 1,924,992 XC40110XV 9,728 110,000 | 131,072 | 75,000- 235,000 | 64x64 4,096 9.216 448 |2.686,136 XC40150XV 12,312 150,000 165,888 | 100,000 - 300,000 | 72x72 5,184 11,520 448 3,373,448 XC40200XV 16,758 200,000 225,792 | 130,000-400,000| 84x 84 7,056 15,456 448 | 4,551,056 XC40250XV 20,102 250,000 270,848 | 180,000-500,000 | 92x92 8,464 18,400 448 | 5,433,888 * Maximum values of gate range assume 20-30% of CLBs used as RAM February 19, 1999 (Version 1.1) Product Specification 1$< XILINX XC4000XLA/XV FPGAs, General Description General Description XC4000 Series high-performance, high-capacity Field Pro- grammable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of fifteen years of FPGA design experience and feedback from thousands of customers, these FPGAs com- bine architectural versatility, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs. Figure 1: Cross Section of Xilinx 0.25 micron, 5 layer metal XC4000XV FPGA. Visible features are five layers of metallization, tungsten plug vias and trench isolation. The small gaps above the lowest layer are 0.25 micron polysilicon MOSFET gates. The excellent planarity of each metal layer is due to the use of chemical-mechanical polishing or CMP. In effect, each layer is ground flat before a new layer is added. Technology Advantage XC4000XLA/KXV FPGAs use 5 layer metal silicon technol- ogy to improve performance while reducing device cost and power. In addition, IOB enhancements provide full PC! compliance and the JTAG functionality is expanded. Low Power lternal Logic XC4000XV FPGAs incorporate all the features of the XLA devices but require a separate 2.5V power supply for inter- nal logic. I/O pads are still driven from a 3.3V power supply. The 2.5V logic supply is named VCCINT and the 3.3 VIC supply is named VCCIO. The XV devices also incorporate additional routing resources in the form of & octal-length segmented routing channels vertically and horizontally per row and column. ALA/AY and AL ramily Differences The XC4000XLA/XV families of FPGAs are logically identi- cal to XC4000EX and XC4000XL FPGAs, however |/O, configuration logic, JTAG functionality, and performance have been enhanced. In addition, they deliver: + Improved Performance XLA/XV devices benefit from advance processing technology and a reduction in interconnect capacitance which improves performance over XL devices by more than 30%. + Lower Power XLA/XV devices have reduced power requirements compared to equivalent XL devices. + Shorter routing delays The smaller die of XLA/XV devices directly reduces clock delays and the delay of high-fanout signals. The reduction in clock delay allows improved pin-to-pin I/O specifications. + Lower Cost XLA/XV device cost is directly related to the die size and has been reduced significantly from that of equivalent XL devices. + Express mode configuration Express mode configuration is available on the XLA and XV devices. iOS Enhancements + 12/24 mA Output Drive The XLA/XV family of FPGAs allow individual IOBs to be configured as high drive outputs. Each output can be configured to have 24 mA drive strength as opposed to the standard default strength of 12 mA. + VCC Clamping Diode XLA and XV FPGAs have an optional clamping diode connected from each output to VCC (VCCIO for XV). When enabled they clamp ringing transients back to the 3.3V supply rail. This clamping action is required in 3.3V PCI applications. VCC clamping is a global option affecting all I/O pins. If enabled, TTL I/C compatibility is maintained, but full 5.0 Volt I/O tolerance is sacrificed. Enhanced ESD protection An improved ESD structure allows XV devices to safely pass the stringent 5V PCI (4.2.1.3) ringing test. This test applies an 11 pulse to each IOB for 11 ns viaa 55 ohm resistor, + Full 3.3V and 5.0V PCI compliance The addition of 12/24 mA drive, optional 3.3V clamping and improved ESD provides full compliance with either 3.3V or 5.0V PCI specifications. February 19, 1999 (Version 1.1} Product Specification$< XILINX XC4000XLA/XV FPGAs, Three-State Register Three-Staie Register XC4000XLA/XV devices incorporate an optional register controlling the three-state enable in the IOBs.The use of the three-state control register can significantly improve output enable and disable time. rasiilLk Glock Butters The XLA/XV devices incorporate FastCLK clock buffers. Two FastCLk buffers are available on each of the right and left edges of the die. Each FastCLK buffer can provide a fast clock signal (typically < 1.5 ns clock delay) to all the IOBs within the lOB octant containing the buffer. The Fast- CLK buffers can be instantiated by use of the BUFFCLK symbols. (In addition to FastCLK buffers, the Global Early BUFGE clock buffers #1, #2, #5, and #6 can also provide fast clock signals (typically < 1.6 ns clock delay) to |IOBs on the top and bottom of the die. ALAJRZV Power Requirements XC4000XLA devices require 40% less power per CLB than equivalent XL devices. XC4000XV devices require 42% less power per CLB than equivalent XLA devices and 65% less power than XL devices The representative K-Factor for the following families can be found in faite 2. The K-Factor predicts device current for typical user designs and is based on filling the FPGA with active 16-Bit counters and measuring the device current at 1 MHz. This technique is described in XBRF14 A Simple Method of Estimating Power in XC4000XL/EX/E FPGAs. To predict device power (P} using the K-Factor use the following formula: P=V*K*N*F; where: P= Device Power V= Power supply voltage K= the Device K-Factor N = number of active registers F = Frequency in MHz Table 2: K-Factor and Relative Power. Power Power Relative Relative FPGA Family | K-Factor To XL To XLA XC4000XL 28 1.00 1.65 XC4000XLA 17 0.60 1.00 XC4000XV 13 0.35 0.58 ALA/KY Logic Perlormance XC4000XLA/XV devices feature 30% faster device speed than XL devices, and consistent performance is achieved across all family members. she 2 illustrates the perfor- mance of the XLA devices. For details regarding the imple- mentation of these benchmarks refer to XBRF15 Speed Metrics for High Performance FPGAs. Table 3: XLA/XV Estimated Benchmark Performance Register - Register . Maximum Benchmarks size Frequency 8-Bit 172 MHz Adder 16-Bit 144 MHz 32-Bit 108 MHz 2 Cascaded Adders 16-Bit 94 MHz 4 Cascaded Adders 16-Bit 57 MHz 1 Level 314 MHz 2 Level 193 MHz Cascaded 4LUTs A Level 708 MHz 6 Level 75 MHz 1 CLBs 325 MHz Interconnect acl Bs 260 Miz (Manhattan Distance} 16 CLBs 185 MHz 64 CLBs 108 MHz 128 CLBs 81 MHz Dual Port RAM 8-Bits by 16 172 MHz (Pipelined) 8-Bits by 256 | 172 MHz February 19, 1999 (Version 1.1) Product Specification$< XILINX XC4000XLA/XV FPGAs, Using Fast I/O CLKS Using Fast /O CLES There are several issues associated with implementing fast VO clocks by using multiple FastCLK and BUFGE clock butfers for I/O transfers and a BUFGLS clock buffer for internal logic. Reduced Clock to Out Period - When transterring data from a BUFGLS clocked register to an |OB output register which is clocked with a fast I/O clock, the total amount of time available for the transfer is reduced. Using Fast Capture Latch in IOB input - It is necessary to transfer data captured with the fast I/O clock edge to a delayed BUFGLS clock without error. The use of the Fast Capture Latch in the IOBs provides this functionality. Driving multiple clock inputs - Since each FastCLkK input can only reach one octant of IOBs it will usually be neces- sary to drive multiple FastCLK and BUFGE input pads with a copy of the system clock. Xilinx recommends that sys- tems which use multiple FastCLk and BUFGE input buffers use a Zero Delay clock buffer such as the Cypress CY2308 to drive up to 8 input pins. These devices contain a Phase locked loop to eliminate clock delay, and specify less than 250ps output jitter. PCB layout - The recommended layout is to place the PLL underneath the FPGA on the reverse side of the PCB. All 8 clock lines should be of equal length. This arrangement will allow all the clock line to be less than 2 cm in length which will generally eliminate the need for clock termination. Advancing the FPGAs clock - An additional advantage to using a PLL-equipped clock buffer is that it can advance the FPGA clocks relative to the system clock by incorporating additional board delay in the feedback path. Approximately 6 inches of trace length are necessary to delay the signal by 1 ns. Advancing the FPGAs clock directly reduces input hold requirements and improves clock to out delay. FPGA clocks should not be advanced more than the guaranteed mini- mum Output Hold Time (minus any associated clock jitter) or the outputs may change state before the system clock edge. For XLA and XV FPGAs the Output Hold Time is specified as a minimum Clock to Output Delay in the tables on pages 27, #2, 35, and 24. The maximum recommended clock advance equals this value minus any clock jitter. Instantiating I/O elements- Depending on the design environment, it may be necessary to instantiate the fast I/O elements. They are found in the libraries as: + BUFGE (1,0) - The Global Early Butfer BUFGLS (1,0)- The Global Low Skew Butter * BUFFCLK (1,0) - The FastCLK Buffer + ILFFX (D, GF, CE, C, Q)- The Fast Capture Latch Macro Locating I/O elements - It is necessary to connect these elements to a particular I/O pad in order to select which buffer or fast capture latch will be used. Restricted Clock Loading - Because the input hold requirement is a function of internal clock delay, it may be necessary to restrict the routing of BUFGE to IOBs along the top and bottom of the die to obtain sub-ns clock delays. BUFGE 6 BUFGE 1 _ts a FOLK 1 FOLK 4 FOLK 2 FOLK 3 BUFGLS 2 BUFGE 5 BUFGE 2 IE <14} Figure 2: Location of FastCLK, BUFGE and BUFGLS Clock Buffers in XC4000XLA/XV FPGAs BUFGE1 XC4000XLA BUFGE2 XC4000XV BUFGES BUFGE6 FCLK1 FCLK2 FCLK3 FCLK4 Figure 3: Diagram of XC4000XLA/XV FPGA Connected to PLL Clock Buffer Driving 4 BUFGE and 4 FastCLK Clock Buffers. February 19, 1999 (Version 1.1} Product Specification$< XILINX XC4000XLA/XV FPGAs, JTAG Enhancements JiIAG Enhancemenis XC4000XLA/XV devices have improved JTAG functionality and performance in the following areas: IDCODE - The IDCODE register in JTAG is now supported. All future Xilinx FPGAs will support the IDCODE register. By using the IDCODE, the device connected to the JTAG port can be determined. The use of the IDCODE enables selective configuration dependent upon the FPGA found. The IDCODE register has the following binary format: veuvifffi:fifa:aaaa:aaaa:ccece:cece:cccl Where: c = the company code; a =the array dimension in CLBs; f = the Family code; v = the die version number Family Godes = 01 for XLA; = 02 for SpartanXL; = 03 for Virtex; = 07 for XV. Xilinx company code = 49 (hex) Table 4: IDCODEs assigned to XC4000XLA/XV FPGAs FPGA IDCODE XC4013XLA 0x00218093 XC4020XLA 0x0021 cO93 XC4028XLA 0x00220093 XC4036XLA 0x00224093 XC4044XLA 0x00228093 XC4052XLA Ox0022c093 XC4062XLA 0x00230093 XC4085XLA 0x00238093 XC40110XV ox00e40093 XC40150XV 0x00e48093 XC40200XKV 0x00e54093 XC40250XV Ox00e5c093 * Configuration State - The configuration state is available to JTAG controllers. * Configure Disable - The JTAG port can be prevented from reconfiguring the FPGA + TCK Startup - TCK can now be used to clock the start-up block in addition to other user clocks. * CCLK holdoff - Changed the requirement for Boundary Scan Configure or EXTEST to be issued prior to the release of INIT pin and CCLK cycling. * Reissue configure - The Boundary Scan Configure can be reissued to recover from an unfinished attempt to configure the device. - Bypass FF - Bypass FF and IOB is modified to provide DRGLOCK only during BYPASS for the bypass flip-flop and during EXTEST or SAMPLE/PRELOAD for the lOB register. AV and ALA Family Dittlerences The high density of the XC4000XV family FPGAs is achieved by using advanced 0.25 micron silicon technol- ogy. A 2.5 Volt power supply (VCCINT) is necessary to pro- vide the reduced supply voltage required by 0.25 micron internal logic, however to maintain TTL compatibility a 3.3V power supply (VCCIO} is required by the I/O. To accommodate the higher gate capacity of XV devices, additional interconnect has been added. These differences are detailed below. + VCCINT (2.5 Volt) Power Supply Pins The XV family of FPGAs requires a 2.5V power supply for internal logic, which is named VCCINT. The pins assigned to the VCCINT supply are named in the pinout guide for the XC4000XV FPGAs and in tame Son page ag, + VCCIO (3.3 Volt) Power Supply Pins Both the XV and XLA FPGAs use 4 3.3V power supply to power the I/O pins. The I/O supply is named VCCIC in the XV family. + Octal-Length Interconnect Channels The XC40110XV, XC40150XV, XC-40200XV, and XC40250XV have enhanced routing. Eight routing channels of octal length have been added to each CLB in both vertical and horizontal dimensions. ALs-io-AL Socket Compatibiilty The XC4000XLA devices are generally available in the same packages as equivalent XL devices, however the range of packages available for the XC4085XLA has been extended to include smaller packages such as the HQ240. XV-to-RL/XLA Socket Compatibility XC4000XV devices are available in five package options, pin-grid PG5g9 and ball-grid BGS60, BG432, and BG352 and quad-flatpack HQ240. With the exception of the VCCINT power pins, XC4000XV FPGAs are compatible with XL and XLA devices in these packages if the following guidelines are followed: * Lay out the PCB for the XV pinout. * When an XL or XLA device is installed disconnect the VCCINT (2.5 V) supply. For the PG599, VCCINT should be connected to 3.3V. For BG560, BG432 and BG352 and HQ240 packages, the VCCINT voltage source should be left unconnected. The unused I/O pins in the XL/XLA devices connected to VCCINT will be pulled up to 3.3V. Care must be taken to insure that these pins are not driven when the XL/XLA device is operative. When an XC4000XV is installed, the VCCINT pins must February 19, 1999 (Version 1.1) Product Specification$< XILINX XC4000XLA/XV FPGAs, XV-to-XL/XLA Socket Compatibility be connected to a 2.5V power supply. The differences between the XL and XV packages are detailed below: PGS559 - XLA and XL devices in the PG599 package have 56 VCC pins. The XC4000XV devices allocate 16 of these I/O pins to VCCINT (2.543. BG560 - XLA and XL devices in the BG560 package have 448 I/O pins. The XC4000XV devices allocate 16 of these I/O pins to VCCINT (2.5}. BG432- XLA and XL devices in the BG432 package have 352 I/O pins. The XC4000XV devices allocate 16 of these I/O pins to VCCINT (2.5}. BG352 - XLA and XL devices in the BG352 package have 289 I/O pins. The XC4000XV devices allocate 15 of these I/O pins to VOCINT (2.5V). H@240- XLA and XL devices in the HQ240 package have 193 I/O pins. The XC4000XV devices allocate 15 of these I/O pins to VCCINT (2.5}. Table 5: VCCINT (2.5 V) Pins in XV Packages HQ@240 BG352 BG432 BG560 PG559 P198 DIO A10 E12 H12 P185 D5 AB2 AD2 H18 P164 Ka AB30 AD32 H26 P154 N3 AG28 AK31 H32 P137 We AH15 AM17 Ms P116 AES AH5 AK5 M36 P7104 AC10 AJ10 AK11 V8 P93 AG13 AK22 AN25 V36 P7? AE19 B23 C24 AF8& P55 AB24 B4 D6 AF36 P43 Ve4 C16 C17 AMS8 P27? N24 E28 E30 AM36 P16 J24 K29 K32 AT12 P4 D24 K3 J1 AT18 P225 A20 R2 T3 AT26 - - Reg U32 AT32 February 19, 1999 (Version 1.1} Product Specification$< XILINX XC4000XLA/XV FPGAs, I/O Signalling Standards iO Signalling Standards XLA and XV devices are compatible with TTL, LVTTL, PCI 3V, PCI 5V and LVCMOQS signalling. The various standards are illustrated in iaive 6 and the signaling environment is illustrated in figures 4 me VCC Clamping XLA/XV devices are fully 5V TTL I/O compatible if VCC clamping is not enabled. The I/O pins can withstand input voltages up to 7V. With VCC clamping enabled, the XLA/XV devices will begin to clamp input voltages to one diode volt- age drop above VCC. In both cases negative voltage is clamped to one diode voltage drop below ground. XLA/XV devices maintain LVTTL I/O compatibility when VCC clamping is enabled, however full 5.0V TTL /O com- patibility is sacrificed. Overshoot and Undershoot Ringing wave forms are allowed on XLA/XV inputs as long as undershoot is limited to -2.0V and overshoot is limited to +7.0V and current is limited to 100 mA for less than 10 ns. lf CC clamping is enabled then overshoot will begin to be clamped at VCC/VCCIO plus one diode voltage drop and undershcot will be clamped to ground minus one diode volt- age drop. In either case the current must be limited to 100 mA per pin for less than 10 ns. Table 6: I/O Standards supported by XC4000XLA and XV FPGAs Signaling vcc Standard Clamping | Output Drive} Vin max Vin MIN ViL max Vou MIN VoL max TTL Not allowed 12/24 mA 5.5 2.0 0.8 2.4 0.4 LVTTL OK 12/24 mA 3.6 2.0 0.8 2.4 0.4 PCI5V Not allowed 24 mA 5.5 2.0 0.8 2.4 0.4 PCI3V Required 12 mA 3.6 50% of 30% of 90% of 10% of VCC/VCCIO | VCC/VCCIO | VCCAYCCIO | VCC/VCCIO LVCMOS 3V OK 12/24 mA 3.6 50% of 30% of 90% of 10% of VCOC/VCCIOC | VCC/VCCIO | VCC/ACCIO | VCC/VCCIO 5.0 V Power 3.3 Power e e 2.5 V Power t Voc (5 V) Vecio Vecint Voc (3.3 V) TTL LVTTL 5 Volt Device | =6xc4000XV /|* % 3.3 Volt Device _LVTTL Ground | | | x7147 Figure 4: The Signalling Environment for XLA/XV FPGAS. For XLA devices the VCCIO and VCCINT supplies are replaced by a single 3.3 Volt VCC supply, however, all indicated I/O signalling is still supported. Express Configuration Mode Express configuration mode is similar to Slave Serial con- figuration mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive CCLK, while byte-wide data is loaded directly into the configuration data shift registers (Figure 5). A CCLK frequency of 10 MHz is equivalent to a 80 MHz serial rate, because eight bits of configuration data are loaded per CCLK cycle. Express mode does not sup- February 19, 1999 (Version 1.1) Product Specification$< XILINX XC4000XLA/XV FPGAs, Express Configuration Mode port CRC error checking, but does support constant-field error checking. A length count is not used in Express mode. Express mode must be specified as an option to the BitGen program, which generates the bitstream. The Express mode bitstream is not compatible with the other configura- tion modes. Express mode is selected by a <010> on the mode pins (M2, M1, MO}. The first byte of parallel configuration data must be avail- able at the D inputs of the FPGA a short setup time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge (Fgire &). Pseudo Daisy Chain As illustrated in Figures 5 and 6, multiple devices with dit- ferent configurations can be configured in a pseudo daisy chain provided that all of the devices are in Express mode. A single combined byte-wide data stream is used to config- ure the chain of Express mode devices. CCLK pins are tied together and DO-D7 pins are tied together as a data buss for all devices along the chain. A status signal is passed from DOUT of each device to the CS1 input of the device which follows it in the chain. Frame data is accepted only when C$1 is High and the device's configuration memory is not already full. The lead device in the chain has its CS1 input tied High (or floating, since there is an internal pullup). The status pin DOUT is initially High fer all devices in the chain until the data stream header of seven bytes is loaded. This allows header data to be loaded into all devices in the chain simultaneously. After the header is loaded in all devices, their DOUT pins are pulled Low disabling confiqu- ration of all devices in the chain except the first device. As each device in the chain is filled, its DOUT goes High driv- ing High the CS1 input of the next device, thereby enabling configuration of the next device in the pseudo daisy chain. The requirement that all DONE pins in a daisy chain be wired together applies only to Express mode, and only if all devices in the chain are to become active simultaneously. All 4000XLA/KXV devices in Express mode are synchro- nized to the DONE pin. User I/O for each device becomes active after the DONE pin for that device goes High (The exact timing is determined by BitGen options.) Since the DONE pin is open-drain and does not drive a High value, tying the DONE pins of all devices together pre- vents all devices in the chain from going High until the last device in the chain has completed its configuration cycle. If the DONE pin of a device is left unconnected, the device becomes active as soon as that device has been config- ured. Table 7: Pin Functions During Configuration (4000XLA/XV Express mode only) CONFIGURATION MODE USER <M2:M1:MO> OPERATION EXPRESS MODE PIN FUNCTION <0:1:0> Met LOW), (oc ce M2 MuHa) tt} Mi | MOFLOW) 0). = Mo HDC (HIGH) VO LDC (LOW) 0 INIT V0 DONE PROGRAM CLI : CCLK (I) DATA th vO DATA6 (H. VO if : VO DATA 4 (i): V0 DATA (1 = 0 BATA:2:( VO aA Ta V0 SGCK4-1/0 TDI-/O TOKO TMS-VO TDO-(0) V0 Notes 1. Ashaded table cell represents the internal pull-up used before and during configuration. 2. (l} represents an input; (O) represents an output. 3. INIT is an open-drain output during configuration. Because only XC4000XLA/XV, SpartanXL, and XC5200 devices support Express mode, only these devices can be used to form an Express mode pseudo daisy chain. February 19, 1999 (Version 1.1} Product Specification>: XILINX XC4000XLA/XV FPGAs, Express Configuration Mode ycc 8. = To Additional Mo Mt M2 Mo OMT M2 Optional Daisy-Chained Devices | CS1 DOUT 1 CS1 DOUT DATA BUS 8 | DO-D7 8 | DO-D7 Optional vec Daisy-Chained 4000XLA/XV ADDOXLA/X 4.7K PROGRAM | PROGRAM *| PROGRAM INIT <>| INIT pone L- <>| INIT DONE cc_k cCcLK aA a To Additional a Optional cot pale cranes 99010800 Figure 5: Express Mode Circuit Diagram Table 8: Express Mode Programming Switching Characteristic Description Symbol Min Max Units INIT (High) setup time Tie 5 ps DO - D7 setup time Toc 20 ns DO - D7 hold time T, 0 ns CCLK ep CCLK High time Tecu 45 ns CCLK Low time Teet 45 ns CCLK Frequency Foc 10 MHz oe Preliminary: February 19, 1999 (Version 1.1) Product Specification 9$< XILINX XC4000XLA/XV FPGAs, Express Configuration Mode Do-D7 DOUT csi POO B Cc Header Loated ] pt< First FPGA Filled First FPGA cst 1 y Second K, 3 i FPGA CS? all 1 downstream FPGAS \___-_____________ Byte A is first frame byte for first FPGA Byte Bis last frame byte for first FRGA Byte C is first frame byte for second FPGA 99012600 Note: CS1 must remain High throughout loading of the configuration data stream. In the pseudo daisy chain of Friggin: 3, the 7 byte data stream header is loaded into all devices simultaneously. Each devices data frames are then loaded in turn when its C31 pin is driven High by the DOUT of the preceding device in the chain. Figure 6: Express Mode Circuit Diagram Data Stream Format The data stream (bitstream) format is identical for all serial configuration modes, but different for the AQ000XLA/XV Express mode. In Express mode, the device becomes active when DONE goes High, therefore no length count is required. Additionally, CRC error checking is not supported in Express mode. The data stream format is shown in Tati 2. Express mode data is shown with DO at the left and D7 at the right. The configuration data stream begins with two bytes of eight ones each, a preamble code of one byte, followed by three bytes of eight ones each, and finally an end-of- header field check byte. This header cf seven bytes is fol- lowed by the actual configuration data in frames. The length and number of frames depends on the device type. Each frame begins with a start field and ends with an end-of-frame field check byte. In all cases, additional start-up bytes of data are required to provide six, or more, clocks for the start-up sequence at the end of configuration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are dont-cares; these bytes are not included in bitstreams cre- ated by the Xilinx software. A selection of CRC or non-CRC error checking is allowed by the bitstream generation software. The 4000XLA Express mode only supports non-CRC error checking. The non-GRC error checking tests for a designated end-of-frame field check byte for each frame. non-CRC error checking tests for a designated end-of-frame field check byte for each frame. Table 9: 4000XLA/XV Express Mode Data Stream Format Express Mode Data Type (DO-D7) (4000XLA only) Fill Byte FFFFh Preamble Code 11110010b Fill Byte FFFFFFh End-of-Header 11010010b Field Check Byte Field Check Byte Extend Write Cycle |F FRED Start-Up Bytes FFFEFFFFEFFFh LEGEND: Unshaded Once per data stream ght | Once perdatatrame Detection of an error results in the suspension of data load- ing and the pulling down of the INIT pin. The user must detect INIT and initialize a new configuration by pulsing the PROGRAM pin Low or cycling VCC. 10 February 19, 1999 (Version 1.1} Product Specification>: XILINX XC4000XLA/XV FPGAs, Serial PROM Recommendation Serial PROM Recommendation Taise 72 shows the physical characteristics of each XLA/XV family member and the recommended Xilinx Serial PROM recommended for use as configuration storage. Table 10: Physical Characteristics and Recommended Serial PROM Max. cLB | Total | Logic | Number | Max. RAM | Required Device . of Bits Configur- Serial PROM User lO Matrix CLBs Cells : . : : Flip-Flops |(No Logic)| ation Bits XC4013XLA 192 24 x 24 5/6 1,368 1,536 18,432 393,632 XO17512L XC4020XLA 224 28 x 28 784 1,862 2,016 25,088 521,880 XO17512L XC4028XLA 256 32 x 32 1,024 2,432 2,560 32,768 668,184 XC1701L XC4036XLA 288 36 x 36 1,296 3,078 3,168 41,472 832,528 XC1701L XC4044XLA 320 40 x 40 1,600 3,800 3,840 51,200 | 1,014,928 XC1701L XC4052XLA 352 44x 44 1,936 4,598 4,576 61,952 | 1,215,368 XC1702L XC4062XLA 384 48 x 48 2,304 5,472 5,376 73,728 1,433,864 XC1702L XC4085XLA 448 56 x 56 3,136 7,448 7,168 100,352 1,924,992 XC01702L XC40110XV 448 64 x 64 4,096 9,728 9,216 131,072 | 2,686,136 XC1704L XC401 50XV 448 72x72 5,184 12,312 11,520 165,888 3,373,448 XG1704L XC40200XV 448 84 x 84 7,056 16,758 15,456 225,792 4,551,056 | XC1704L+X017512L XC40250XV 448 92 x 92 8,464 20,102 18,400 270,848 5,433,888 | XC1704L+XC1702L User /O Per Package Taise 7? shows the number of user I/Os available in each package for XC4000XLA/XV-Series devices. Call your local sales office for the latest availability information. Table 11: User I/O Pins Available by Device and Package eee Maximum I/O Accessible per Package Max | & 3 + iO 3 io o @ @ = =_ WN N WN N NM oo 03 Tt WwW) Ww Device WO; ZS i;e@ 1} Fsy2 |S {2 }8 12,3) eg }2 8 XC4013XLA 192 129 160 192 | 192 XC4020XLA 224 129 160 193 | 205 XC4028XLA 256 129 160 193 205 256 256 XC4036XLA 288 129 160 193 256 288 288 XC4044XLA 320 129 160 193 256 289 320 XC4052XLA 352 129 160 193 256 289 352 352 XC4062XLA 384 | 129 160 193 266 | 289 | 352 384 XC4085XLA 448 | 129 160 193 266 | 289 | 352 448 XC40110XV 448 178 274 | 336 432 XC40150XV 448 178 274 | 336 | 448 | 432 XC40200XV 448 336 432 XC40250XV 448 336 | 448 | 432 February 19, 1999 (Version 1.1) Product Specification 11>: XILINX XC4000XLA/XV FPGAs, Product Availability Product Availability XLA Family Table 12 shows the current available package and speed grade combinations for XC4000XLA Series devices. Call your local sales office for the latest availability information, or see the Xilinx WEBLINX at htto:/Avww.xilinx.com for the latest revision of the specifications. Table 12: Component Availability Chart for XC4000XLA FPGAs PINS 84 100 | 100 44 160 | 160 | 176 nN : a on 8 TYPE Ceram. PGA Ceram. PGA Geram. PGA PG299 PG475 PG559 09 XC4013XLA| 08 OF 08 XC4020XLA | 08 OF 09 XC4028XLA |_08 OF 09 XC4036XLA | 08 OF 09 XC4044XLA | 08 OF 09 XC4052XLA |_08 OF 09 XC4062XLA | 08 OF 09 XC4085XLA | 08 OF C = Commercial Ty = 0 to +85C l= Industrial Ty = -40C to +100C 12 February 19, 1999 (Version 1.1} Product Specification>: XILINX XC4000XLA/XV FPGAs, Product Availability XV Family Table 13 show the current available package and speed grade combinations for the XC4000XV Series devices. Call your local sales office for the latest availability information, or see the Xilinx WEBLINX at http:/Avww.xilinx.com for the latest revision of the specifications. Table 13: Component Availability Chart for XC4000XV FPGAs PINS 84 = 160 | 160 7 176 8 a $ $ 8 = re a & QFP ram. PGA eram PGA eram PGA TYPE High-Pert. TQFP High-Pert. QFP High-Pert. TQFP High-Pert. QFP High-Pert. QFP eram PGA High-Pert. HT 144 160 HT176 08 PG299} 04 PG411} PG475| PG559} 09 XC401710XV | 08 OF 09 XC40150XV | 08 OF 09 XC40200XV | 8 07 09 XC40250XV | -08 oF C =Commercial Ty =0 ta +85C l= Industrial Ty = -40C to +100C February 19, 1999 (Version 1.1) Product Specification 133: XILINX XC4000XLA/XV FPGAs, XLA Specification Information ALA Specification Information Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered final. Occasionally, values are of mixed classification. These are highlighted in bold face and the tables involved include a note explaining the nature of the bold face entries. All specifications are subject to change without notice. Additional Specifications Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common tc popular designs and typical applications. ALA OC. Characteristic Guidelines Absolute Maximum Ratings Symbol Description Values Units Vee Supply voltage relative to GND -0.5 to 4.0 Vv Vin Input voltage relative to GND (Note 1} -0.6to 55 Vv Vis Voltage applied to 3-state output (Note 1) -0.6to 55 V Veci Longest Supply Voltage Rise Time from 1 V to 3V 50 ms Tstg Storage temperature (ambient) -65 to +150 C Tso. Maximum soldering temperature (10 s @ 146 in. = 1.5mm) +260 C r Junction temperature Ceramic packages +150 dO 4 Plastic packages 4125 C Notes: 1. Maximum DC overshoot or undershoot above V., or below GND must be limited to either 0.5 V or 10 mA, whichever is 2. easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoct lasts less than 10 ns and with the forcing current being limited to 200 mA. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device a tthese or any other conditions beyond those listed under Operating Conditions is net implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol Description Min Max Units Voc Supply voltage relative to GND, Tj) =0 C to +85C =| Commercial 3.0 3.6 Vv Supply voltage relative to GND, T = -40C to +100C | Industrial 3.0 3.6 Vv Vin High-level input voltage 50% of Voc 5.5 Vv VIL Low-level input voltage G 30% of Voc V Tin Input signal transition time 250 ns Note: At junction temperatures above those listed as Cperating Conditions, all delay parameters increase by 0.35% per C. Input and output measurement threshold is ~50% of Vec. 14 February 19, 1999 (Version 1.1} Product Specification$< XILINX XC4000XLA/XV FPGAs, XLA D.C. Characteristic Guidelines DC Characteristics Over Recommended Operating Conditions Symbol Description Min Max Units Vou High-level output voltage @ Igy = -4.0 MA, Vee min (LYTTL) 2.4 V High-level output voltage @ loy = -500 WA, (LVCMOS} 90% Veco Vv VoL Low-level output voltage @ lo, = 24.0 MA, Vee min (LVTTL) (Note 1} 0.4 V Low-level output voltage @ Ig, = 1500 pA, (LVCMOS} 10% Voc V Vor Data Retention Supply Voltage (below which configuration data may be lost) 2.5 Vv leco Quiescent FPGA supply current (Note 2) 10 mA I Input or output leakage current -10 +10 LA Input capacitance (sample tested) BGA, SBGA, PQ, HQ, MQ packages 10 pF iN PGA packages 16 pF IRPU Pad pull-up (when selected) @ V;, = 0 V (sample tested) 0.02 0.25 mA IRpp Pad pull-down (when selected) @ V,, = 3.6 V (sample tested) 0.02 0.15 mA lALL Horizontal Longline pull-up (when selected) @ lagic Low 0.3 2.0 mA Notes: 1. With up to 64 pins simultaneously sinking 24 mA 2. With no output current loads, no active input or Longline pull-up resistors, all { pins Tri-stated and floating February 19, 1999 (Version 1.1) Product Specification 153: XILINX XC4000XLA/XV FPGAs, XLA AC Characteristic Guidelines ALA AC Cheracteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/608. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible |OB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature. Values apply to all XC4000XLA devices and expressed in nanoseconds unless otherwise noted. Delay Via Global Low Skew Clock Buffer to Clock Speed Grade] All -09 -08 -07 ; Description Symbol Device Min Max | Max | Max Units Delay from pad through Global Low Skew (GLS) clock Tets | XC4013XLAT 0.7 24 2.1 1.9 ns buffer to any clock input, K. xc4oz0xLA] 07 | 26 | 23 | 21 | ns XC4028XLAT 0.8 29 2.6 2.3 ns XC4O036XLAP 0.8 3.2 2.8 25 ns XC4044XLAT 09 3.6 3.1 2.8 ns XC4052XLAF 1.0 3.9 3.4 3.1 ns XC4062XLAF 1.1 42 3.7 3.3 ns XC4O085XLAF 1.2 5.0 4.4 3.9 ns 2 Preliminary) Delay Via FastCLK Buffer to |OB Clock Speed Grade] All -09 -08 -07 Unit nits Description Symbol Device Min Max | Max | Max Delay from pad through FastCLK buffer to any |IOB Tretk | XC4013XLAT 0.4 ee) 13 1.1 ns clock input. xcaoz0xLA] o5 | 15 |] 13 | 12 | ns XC4028XLAF 0.5 1.6 1.4 1.3 ns XC40386XLA J 0.5 1.7 15 1.4 ns XC4044XLA]T 0.5 1.8 16 1.4 ns XC4052XLA FT 0.6 1.9 1.7 1.5 ns XC4062XLAF 0.6 2.0 1.8 1.6 ns XC4085XLAF 0.6 2.3 2.0 1.8 ns Note: Values in bold face are preliminary, all other values are advance. oo Preliminary. 16 February 19, 1999 (Version 1.1} Product Specification$< XILINX XC4000XLA/XV FPGAs, XLA AC Characteristic Guidelines Delay Via Global Early BUFGEs 1, 2, 5, 6 to IOB Clock Speed Grade] All -09 -08 -07 . Description Symbol Device Min | Max | Max | Max Units Delay from pad through Global Early (GE) clock buffer to Tee | XC4013XLAP 0.2 1.7 1.5 13 ns any IOB clock input for BUFGEs 1, 2, &, and 6. XC4020XLAT 02 19 17 15 ns XC4028XLAF 0.2 2.1 1.9 17 ns XC4036XLA[T 0.3 2.4 22 19 ns XC4044XLAFT 0.3 27 | 24 22 ns XC4052XLA] 0.3 3.0 27 2.4 ns XC4062XLAF 0.3 3.3 ) 3.0 27 ns XC4085XLAT 0.3 3.7 3.3 3.0 ns him Delay Via Global Early BUFGEs 3, 4, 7, 8 to IOB Clock Speed Grade] All -09 | -08 | -07 Units Description Symbol Device Min | Max | Max | Max Delay from pad through Global Early (GE) clock buffer to Tee | XC4013XLAF 05 25 | 22 1.9 ns any IOB clock input for BUFGEs 3, 4, 7, and 8. XC4020XLAT 0.6 27 24 2.1 ns XC4028XLAF 06 | 29 | 25 | 23 ns XC4036XLAF 0.7 | 3.1 27 | 24 ns XC4044X1LAF 08 | 33 | 29 | 26 ns XC4052XLAF 0.8 3.6 3.1 2.8 ns XC4062XLAF O09 | 38 | 34 | 30 ns XC4085XLAF 1.0] 43 | 38 | 34 ns February 19, 1999 (Version 1.1) Product Specification 173: XILINX XC4000XLA/XV FPGAs, XLA AC Characteristic Guidelines CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XLA devices and expressed in nanoseconds unless otherwise noted. Speed Grade -09 -08 -07 . - Units Description Min | Max Combinatorial Delays ee F/G inputs to X/ outputs 1.0 0.9 ns F/G inputs via H to X/Y outputs 1.7 1.5 ns F/G inputs via transparent latch to Q outputs Tito 1.8 1.6 ns C inputs via SR/HO via H to X/ outputs THHoo 1.6 1.4 ns C inputs via H1 via H to X/Y outputs TyHio 1.4 1.3 ns C inputs via DIN/H2 via H to X/Y outputs TyH20 . 1.6 1.4 ns C inputs via EC, DIN/H2 te YQ, XQ output (bypass) Tesyp . 1.0 0.9 ns CLB Fast Carry Logic BSS EE SIS a Se Ss EE ESI Operand inputs (F1, F2, G1, G4) to Coy7 Topcy 0.9 0.8 ns Add/Subtract input (F3) to Coy7 Tascy 1.1 1.0 ns Initialization inputs (F1, F3) to SCgy7 Tincy 0.7 0.6 ns Cy through function generators to X/Y outputs Tsum 1.5 1.3 ns Cy, to Coyt, bypass function generators Taye 0.1 0.1 ns Carry Net Delay, Coy to Cyy TNET 0.15 0.13 ns Sequential Delays I ee Clock K to Flip-Flop outputs @ TeKo . 1.3 1.2 ns Clock K to Latch outputs @ Tokio . 1.3 1.2 ns Setup Time before Clock K ee ee F/G inputs Tick 0.7 07 0.6 ns F/G inputs via H Tick 14 1.3 1.2 ns C inputs via HO through H TuHock 1.3 1.2 1.1 ns C inputs via H1 through H THHICK 12 1.4 1.0 ns C inputs via H2 through H THHeck 1.3 1.2 1.4 ns C inputs via DIN Toick 0.6 0.6 0.5 ns C inputs via EC Tecck OF 0.6 0.5 ns C inputs via S/R, going Low (inactive) Trek 0.5 0.4 0.4 ns CIN input via F/G Teex 1.2 1.1 1.0 ns CIN input via F/G and H Teuck 2.0 1.7 1.6 ns Hold Time after Clock K _ ) . All Hold Times 0.0 | | 0.0 | | 0.0 | ns Clock To pf To Clock High time 2.2 ns Clock Low time 2.2 ns Set/Reset Direct po ee jf. Width (High) 2.3 2.3 ns Delay from inputs via S/R, going High to Trio 2.2 2.0 ns Global Set/Reset ee Minimum GSR Pulse Width | 12.8 | | 11.4 | [| 10.2 | ns Delay from GSR input to any Q Tamra See page = for TRAI values per device. Toggle Frequency (MHz) (for export control) Frog | 227 | | 263 | | 294 MHz 18 February 19, 1999 (Version 1.1} Product Specification>: XILINX XC4000XLA/XV FPGAs, XLA AC Characteristic Guidelines CLB RAM Synchronous (Edge-Triggered) Read/Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case quaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XLA devices and are expressed in nanoseconds unless otherwise noted. . Speed Grade -09 -08 -07 Single Port RAM Units Size | Symbol i i i Write Operation S Address write cycle time (clock K period) 16x2 | Twes 6.7 5.9 5.3 ns 32x1 Twets 6.7 5.9 5.3 ns Clock K pulse width (active edge) 16x2 | Twes 3.4 3.0 27 ns 32x11 Twpts 3.4 3.0 ef ns Address setup time before clock K 16x2 | Tass 1.5 1.3 12 ns 32x1 Tasts 1.5 1.3 12 ns Address hold time after clock K 16x2 | Tans 0.0 0.0 0.0 ns 32x1 TauHTs 0.0 0.0 0.0 ns DIN setup time before clock K 16x2 | Toss 1.5 1.3 1.2 ns 32x11 Tpsts 1.8 1.6 15 ns DIN hold time after clock K 16x2 | Tpus 0.0 0.0 0.0 ns 32x1 TpuHTs 0.0 0.0 0.0 ns WE setup time before clock K 16x2 | Twss 1.4 1.3 1.1 ns 32x1 Twsts 1.3 1.2 141 ns WE hold time after clock K 16x2 | Twus 0.0 0.0 0.0 ns 32x11 TwHTs 0.0 0.0 0.0 ns Data valid after clock K 16x2 | Twos 5.0 44 4.0 ns 32x1 Twots 5.8 5.2 A7 ns Read Operation Ts EEE ee Address read cycle time 16x2 . . . ns 32x1 | Trot 3.8 3.8 3.8 ns Data Valid after address change (no Write En-| 16x2 | Tio 11 1.0 0.9 ns able) 32x1 | Tyo 1.9 17 1.5 ns Address setup time before clock K 16x2 | Tick 0.7 0.7 0.6 ns 32x1 Tick 1.4 1.3 12 ns February 19, 1999 (Version 1.1) Product Specification 193: XILINX XC4000XLA/XV FPGAs, XLA AC Characteristic Guidelines Speed Grade -09 -08 -07 Dual Port RAM Units Size | Symbol} Min | Max | Min | Max | Min | Max Address write cycle time (clock K period) 16x1 Tweps | 8.7 5.9 5.3 ns Clock K pulse width (active edge} 16x1 Tweps | 3.4 3.0 2.7 ns Address setup time before clock K 16x41 Tasps | 1.5 1.3 1.2 ns Address hold time after clock K 16x1 Taups | 0.0 0.0 0.0 ns DIN setup time before clock K 16x41 Tpsps | 1.7 1.6 1.4 ns DIN hold time after clock K 16x1 Tpups J 0.0 0.0 0.0 ns WE setup time before clock K 16x41 Twsps | 1.4 1.3 1.1 ns WE hold time after clock K 16x1 Twups | 0.0 0.0 0.0 ns Data valid after clock K 16x1 Twops 5.7 5.1 46 ns Note: Timing for 16x1 option is identical to 16x2 RAM. minary. - Bes CLB RAM Synchronous (Edge-Triggered) Write Timing DATA IN DATA IN ADDRESS ADDRESS DATA OUT : DATA OUT MEAT xG467 Single Port RAM Dual Port RAM 20 February 19, 1999 (Version 1.1} Product Specification>: XILINX XC4000XLA/XV FPGAs, XLA Pin-to-Pin Output Parameter Guide- ALA Pin-to-Pin Quipul Parameter Guidelines Testing ct switching parameters is modeled after testing methods specified by MIL-M-38510/608. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Global Low Skew Clock Input to Output Delay Speed Grade] All -09 -08 -07 ; Description Symbol Device Min | Max | Max | Max Units Global Low Skew (GLS) Clock Input to Gutput Delay us-| Tickor | XC4013XLAF 12 5.6 5.0 45 ns ing Output Flip-Flop XC4020XLAE 1.3 5.8 52 47 ns XC4028XLAP 14 6.1 55 49 ns XC4036XLAF 14 6.4 57 5.4 ns XC4044XLAP 1.5 6.8 6.0 5.4 ns XC4052XLA 1.6 71 63 5.7 ns XC4062XLA] 1.6 74 66 5.9 ns XC4085XLA 1.8 82 73 6.5 ns For output SLOW option add Tstow | All Devices 0.5 17 1.6 14 ns and where all accessible |OB and CLB flip-flops are clocked by the global clack net. Output timing is measured at ~50% Ve threshold with 50 pF external capacitive load. For different loads, see Figurs . FastCLkK Input to Output Delay for BUFNW, BUFSW, BUFNE, & BUFSE Speed Grade| All -09 -08 -07 Unit nits Description Symbol Device Min | Max | Max | Max FastCLk Input to Output Delay using Output Flip-Flop | Tickror | XC4013XLA] 1.0 4.6 4.1 3.6 ns for FastCLk buffers BUFNW, BUFSW, BUFNE, and XC4020XLA| 1.0 46 44 37 ns BUFSE. XC4028XLA 1.0 4.7 4.2 3.8 ns XC4036XLA 1.1 4.8 43 3.9 ns XC4044XLA | 1.1 49 4.4 3.9 ns XC4052XLA | 1.1 5.0 45 40 ns XC4062XLA | 1.1 5.1 46 41 ns XC40B85XLA| 1.2 54 4.8 43 ns preliminary Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible |OB and CLB flip-flops are clocked by the global clock net. Output timing is measured at ~50% Voc threshold with 50 pF external capacitive load. For different loads, see Figure . February 19, 1999 (Version 1.1) Product Specification 213: XILINX XC4000XLA/XV FPGAs, XLA Pin-to-Pin Output Parameter Guidelines Global Early Clock Input to Output Delay for BUFGEs 1, 2, 5, and 6 Speed Grade] All -09 -08 -07 . Description Symbol Device Min Max Max Max Units Global Clock Signal Input to Output Delay using Tickeor | XC4013XLA 0.8 49 4.4 3.9 ns Global Early (GE) clock buffer to clock Output XC4020XLA 0.8 5.1 4.6 4.1 ns Flip-Flop for BUFGEs 1, 2, 5, & 6. XC4028XLA 0.8 5.3 48 43 ns XC4036XLAP 0.8 5.6 5.1 4.5 ns XC4044XLAP 0.9 5.9 5.3 48 ns XC4052XLAP 0.9 6.2 5.6 5.0 ns XC4062XLAP 0.9 6.5 5.9 5.3 ns XC4O085XLAP 0.9 6.9 6.2 5.6 ns preliminary. Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible |OB and CLB flip-flops are clocked by the global clock net. Output timing is measured at ~50% Veco threshold with 50 pF external capacitive load. For different loads, see Mizpire 7. Global Early Clock Input to Output Delay for BUFGEs 3, 4, 7, and 8 Speed Grade] All -09 -08 -07 Units Description Symbol Device Min Max Max Max Global Clock Signal Input to Output Delay using =| Tickegr | XC4013XLA 14 5.7 5.4 45 ns Global Early (GE} clock buffer to clock Output XC4020XLA 11 5.9 5.3 47 ns Flip-Flop for BUFGEs 3, 4,7, &8. XC4028XLA 12 6.1 5.4 49 ns XC4036XLA 13 6.3 5.6 5.0 ns XC4044XLA 13 6.5 5.8 5.2 ns XC4052XLA 14 68 6.0 5.4 ns XC4062XLA 1.5 7.0 63 5.6 ns XC4085XLA 16 75 6.7 6.0 ns Preliminary Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible |OB and CLB flip-flops are clocked by the global clock net. Output timing is measured at ~50% Veo threshold with 50 pF external capacitive load. For different loads, see Figtice 7. Capacitive Load Factor 3 Fite shows the relationship between I/O output delay > and load capacitance. It allows a user to adjust the speci- na fied output delay if the load capacitance is different than = 4 50 pF. For example, if the actual load capacitance is a 120 pF, add 2.5 ns to the specified delay. If the load capac- 2 0 itance is 20 pF, subtract 0.8 ns from the specified output & delay. 2-1 rigure Y is usable over the specified operating conditions of > voltage and temperature and is independent of the output slew rate control. oO 20 40 60 80 100 120 140 Capacitance (pF) Figure 7: Delay Factor at Various Capacitive Loads 22 February 19, 1999 (Version 1.1} Product Specification$< XILINX XC4000XLA/XV FPGAs, XLA Pin-to-Pin Set-up and Hold Parameter ALA Fin-to-Pin Set-up and Mold Parameter Guidelines Testing ct switching parameters is modeled after testing methods specified by MIL-M-38510/608. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Global Low Skew Clock Set-Up and Hold IFF = Input Flip-Flop or Latch Note: Speed Grade -09 08 07 Units Description | Symbol | Device Min Min Min Input Setup and Hold Time Relative to Global Clock Input Signal : SE 8 No Delay XC4013XLA J 1.0/3.0 08/26 02/25, Global Low Skew Clock and IFF TpsnTpun | XC4020XLA 0.9/3.2 0.7/2.9 01/27 ns XC4028XLA 0.8/3.8 06/33 0.0/3.0 ns XC4036XLA 0.6/40 0.4/3.5 0.0/3.3 ns XC4044XLA 0.4/4.4 0.2/3.9 0.0/3.6 ns XC4052XLA 0.3/46 02/44 0.0/3.9 ns XC4062XLA 0.2/5.0 0.1/4.5 0.0/42 ns XC4085XLA 0.0/5.4 00/48 0.0/4.5 ns Partial Delay XC4013XLA 44/05 41/03 3.7/0.0 ns Global Low Skew Clock and IFF Tpsp/Tpyp | XC4020XLA 4.5/0.6 41/03 3.7/0.0 ns XC4028XLA 46/07 4.2/0.4 3.7/0.0 ns XC4036XLA 46/08 4.2/0.4 3.7/0.0 ns XC4044XLA 47/09 43/05 3.8/0.0 ns XC4052XLA 4.8/1.0 43/06 3.8/0.2 ns XC4062XLA 5.0/1.0 44/07 3.8/0.4 ns XC4085XLA 6.6/1.2 47/09 3.38/06 ns Full Delay XC4013XLA 4.4/0.0 4.1/0.0 3.7/0.0 ns Global Low Skew Clock and IFF Tpsp/Tpup | XC4020XLA 4.6/0.0 4.2/0.0 3.8/0.0 ns XC4028XKLA 4.8/0.0 44/00 3.9/0.0 ns XC4036XLA 4.9/0.0 4.5/0.0 4.0/0.0 ns XC4044XLA 5.0/0.0 46/0.0 4.1/0.0 ns XC4052XLA 5.2/0.0 4.7/0.0 4.2/0.0 ns XC4062XLA 5.6/0.0 49/00 4.3/0.0 ns XC4085XLA 6.0/0.0 5.2/0.0 44/00 ns Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time ts 2 peimnay measured relative to the Global Clock input signal using the furthest distance and a reference load af one clock pin per two IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions. February 19, 1999 (Version 1.1) Product Specification 23