R5F6417BHDFB - Renesas Electronics

RENESAS MCU

M16C Family / R32C/100 Series

Rev.1.20 Feb 2013

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest informaton published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

User's Manual

www.renesas.com

R32C/117 Group

User’s Manual: Hardware

R32C/117 Group User’s Manual: Hardware

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,

and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you

or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics

does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages

incurred by you resulting from errors in or omissions from the information included herein.

3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of

thir d parties by or ari s ing from t he use of Renesas Electro nics products or technical information described in this document. No

license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of

Renesas Electronics or others.

4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration,

modification, copy or otherwise misappropriation of Renesas Electronics product.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The

recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; and safety equipment etc.

Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to

human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property

damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas

Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any

application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred

by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas

Electronics.

6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or

damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have

specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,

Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to

guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas

Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and

malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation

of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by

you.

8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility

of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and

regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive.

Renesas Electronics assume s no liability for damages or losse s occurring as a result of your noncompliance with applicable laws

and regulations.

9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose

manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use

Renesas Electronics products or technology described in this document for any purpose relating to military applications or use

by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas

Electronics products or technology described in this document, you should comply with the applicable export control laws and

regulations and follow the procedures required by such laws and regulations.

10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise

places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this

document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of

unauthorized use of Renesas Electronics products.

11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document

or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

owned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(2012.4)

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the

vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur

due to the false recognition of the pin state as an input signal become possible. Unused

pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset

process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset

function are not guaranteed from the moment when power is supplied until the power

reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock

signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of

the clock signal. Moreover, when switching to a clock signal produced with an external

resonator (or by an external oscillator) while program execution is in progress, wait until

the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When

changing to products of different part numbers, implement a system-evaluation test for

each of the products.

About This Manual

1. Purpose and Target User

This manual is designed to be read primarily by application developers who have an understanding of this

microcomputer (MCU) including its hardware functions and electrical characteristics. The user should have

a basic understanding of electric circuits, logic circuits and, MCUs.

This manual consists of 29 chapters covering six main categories: Overview, CPU, System Control,

Peripherals, Electrical Characteristics, and Usage Notes.

The R32C/117 Group includes the documents listed below. Verify this manual is the latest version by visiting

the Renesas Electronics website.

Carefully read all notes in this document prior to use. Notes are found throughout each chapter, at the end

of each chapter, and in the dedicated Usage Notes chapter.

The Revision History at the end of this manual summarizes primary modifications and additions to the

previous versions. For details, please refer to the relative chapters or sections of this manual.

Type of Document Contents Document Name Document Number

Datasheet Overview of Hardware and Electrical

Characteristics

R32C/117 Group

Datasheet

R01DS0064EJ0120

User’s Manual:

Hardware

Specifications and detailed

descriptions of:

-pin layout

-memory map

-peripherals

-electrical characteristics

-timing characteristics

Refer to the Application Manual for

peripheral usage.

R32C/117 Group

User’s Manual:

Hardware

This publication

User’s Manual:

Software/Software

Manual

Descriptions of instruction set R32C/100 Series

Software Manual

REJ09B0267-0100

Application Note -Usages

-Applications

-Sample programs

-Programing technics using

Assembly language or C

programming language

Available on the Renesas Electronics

website.

Renesas Technical

Update

Bulletins on product specifications,

documents, etc.

2. Numbers and Symbols

The following explains the denotations used in this manual for registers, bits, pins and various numbers.

(1) Registers, bits, and pins

Registers, bits, and pins are indicated by symbols. Each symbol has a register/bit/pin identifier

after the symbol.

Example: PM03 bit in the PM0 register

P3_5 pin, VCC pin

(2) Numbers

A binary number has the suffix “b” except for a 1-bit value.

A hexadecimal number has the suffix “h”.

A decimal number has no suffix.

Example: Binary notation: 11b

Hexadecimal notation: EFA0h

Decimal notation: 1234

3. Registers

The following illustration describes registers used throughout this manual.

• • • Register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol

• • • •

Address

• • • h

Reset Value

• • • • • b

Bit Symbol Bit Name Function RW

Blank box: Set this bit to 0 or 1 according to the function.

0: Set this bit to 0.

1: Set this bit to 1.

X: Nothing is assigned to this bit.

RW: Read and write

RO: Read only

WO: Write only (the read value is undefined)

—: Not applicable

0 1

• • • 0

• • • 1

—

(b2)

—

(b3)

—

(b4)

• • • 5

• • • 6

• • • 7

—

• • • Bit

No register bit. If necessary, set to 0. When read, the read value is

undefined.

Reserved Should be written with 1

• • • Bit

• • • Flag

Reserved

0: • • • • •

1: • • • • •

Functions vary with operating modes

Should be written with 0 and read as

undefined value

Reserved bit: This bit field is reserved. Set this bit to a specified value. For RW bits, the written value is

read unless otherwise noted.

No register bit(s): No register bit(s) is/are assigned to this field. If necessary, set to 0 for possible future

implementation.

Do not use this combination: Proper operation is not guaranteed when this value is set.

Functions vary with operating modes: Functions vary with peripheral operating modes. Refer to register

illustrations of the respective mode.

b2 b1

0 0 : • • • • •

0 1 : • • • • •

1 0 : Do not use this combination

1 1 : • • • • •

4. Abbreviations and Acronyms

The following acronyms and terms are used throughout this manual.

All trademarks and registered trademarks are the property of their respective owners.

Abbreviation/Acronym Meaning

ACIA Asynchronous Communications Interface Adapter

bps bits per second

CRC Cyclic Redundancy Check

DMA Direct Memory Access

DMAC Direct Memory Access Controller

GSM Global System for Mobile Communications

Hi-Z High Impedance

IEBus Inter Equipment Bus

I/O Input/Output

IrDA Infrared Data Association

LSB Least Significant Bit

MSB Most Significant Bit

NC Non-Connection

PLL Phase Locked Loop

PWM Pulse Width Modulation

SIM Subscriber Identity Module

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator

A- 1
TABLE OF CONTENTS
Overview 1
1 Features........................................................................................................................................... 1
1.1 Applications .............................................................................................................................. 1
1.2 Performance Overview ............................................................................................................. 2
2 Product Information ......................................................................................................................... 6
3 Block Diagram ................................................................................................................................. 9
4 Pin Assignments ............................................................................................................................ 10
5 Pin Definitions and Functions ........................................................................................................ 19
Central Processing Unit (CPU) 24
1 General Purpose Registers ........................................................................................................... 25
1.1 Data Registers (R2R0, R3R1, R6R4, and R7R5)................................................................... 25
1.2 Address Registers (A0, A1, A2, and A3) ................................................................................ 25
1.3 Static Base Register (SB) ....................................................................................................... 25
1.4 Frame Base Register (FB)...................................................................................................... 25
1.5 Program Counter (PC)............................................................................................................ 25
1.6 Interrupt Vector Table Base Register (INTB) .......................................................................... 25
1.7 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................. 25
1.8 Flag Register (FLG)................................................................................................................ 25
2 Fast Interrupt Registers ................................................................................................................. 27
2.1 Save Flag Register (SVF)....................................................................................................... 27
2.2 Save PC Register (SVP) ........................................................................................................ 27
2.3 Vector Register (VCT) ............................................................................................................ 27
3 DMAC-associated Registers.......................................................................................................... 27
3.1 DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3) .................................................... 27
3.2 DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3) ........................................ 27
3.3 DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3) .......................... 27
3.4 DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3) ....................................... 27
3.5 DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3).......................... 27
3.6 DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3) ............................... 27
3.7 DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and DDR3) .................. 27
Memory 28
Special Function Registers (SFRs) 29
Resets 68
1 Hardware Reset............................................................................................................................. 68
2 Software Reset .............................................................................................................................. 71
3 Watchdog Timer Reset .................................................................................................................. 71
4 Reset Vector .................................................................................................................................. 71

A- 2
Power Management 72
1 Voltage Regulators for Internal Logic............................................................................................. 72
1.1 Decoupling Capacitor ............................................................................................................. 73
2 Low Voltage Detector..................................................................................................................... 74
2.1 Operational State of Low Voltage Detector............................................................................. 77
2.2 Low Voltage Detection Interrupt ............................................................................................. 77
2.3 Application Example of the Low Voltage Detector .................................................................. 78
Processor Mode 79
1 Types of Processor Modes ............................................................................................................ 79
2 Processor Mode Setting ................................................................................................................ 79
Clock Generator 82
1 Clock Generator Types .................................................................................................................. 82
1.1 Main Clock.............................................................................................................................. 91
1.2 Sub Clock (fC) ........................................................................................................................ 92
1.3 PLL Clock ............................................................................................................................... 93
1.4 On-chip Oscillator Clock ......................................................................................................... 96
2 Oscillator Stop Detection ............................................................................................................... 97
2.1 How to Use Oscillator Stop Detection..................................................................................... 97
3 Base Clock..................................................................................................................................... 97
4 CPU Clock and Peripheral Bus Clock............................................................................................ 98
5 Peripheral Clock ............................................................................................................................ 98
6 Clock Output Function ................................................................................................................... 99
7 Power Control .............................................................................................................................. 100
7.1 Normal Operating Mode ....................................................................................................... 101
7.2 Wait Mode............................................................................................................................. 106
7.3 Stop Mode ............................................................................................................................ 109
8 System Clock Protection...............................................................................................................111
9 Notes on Clock Generator ............................................................................................................112
9.1 Sub Clock ..............................................................................................................................112
9.2 Power Control........................................................................................................................112
Bus 113
1 Bus Settings..................................................................................................................................113
2 Peripheral Bus Timing Setting ......................................................................................................114
3 External Bus Setting .....................................................................................................................115
3.1 External Address Space Setting ............................................................................................115
3.2 External Data Bus Width Setting .......................................................................................... 121
3.3 Separate Bus/Multiplexed Bus Selection.............................................................................. 123
3.4 Read and Write Signals........................................................................................................ 126
3.5 External Bus Timing.............................................................................................................. 128

A- 3
3.6 ALE Signal............................................................................................................................ 132
3.7 RDY Signal ........................................................................................................................... 133
3.8 HOLD Signal......................................................................................................................... 136
3.9 BCLK Output ........................................................................................................................ 136
4 External Bus State when Accessing Internal Space .................................................................... 136
5 Notes on Bus ............................................................................................................................... 137
5.1 Notes on Designing a System .............................................................................................. 137
5.2 Notes on Register Settings................................................................................................... 137
Protection 138
1 Protect Register (PRCR Register) ............................................................................................... 138
2 Protect Register 2 (PRCR2 Register) .......................................................................................... 139
3 Protect Register 3 (PRCR3 Register) .......................................................................................... 139
4 Protect Release Register (PRR Register) ................................................................................... 140
Interrupts 141
1 Interrupt Types............................................................................................................................. 141
2 Software Interrupts ...................................................................................................................... 142
3 Hardware Interrupts ..................................................................................................................... 143
3.1 Special Interrupts.................................................................................................................. 143
3.2 Peripheral Interrupts ............................................................................................................. 143
4 Fast Interrupt ............................................................................................................................... 144
5 Interrupt Vectors .......................................................................................................................... 144
5.1 Fixed Vector Table ................................................................................................................ 145
5.2 Relocatable Vector Table...................................................................................................... 145
6 Interrupt Request Acceptance ..................................................................................................... 150
6.1 I Flag and IPL ....................................................................................................................... 150
6.2 Interrupt Control Registers ................................................................................................... 151
6.3 Wake-up IPL Setting Register .............................................................................................. 154
6.4 Interrupt Sequence ............................................................................................................... 155
6.5 Interrupt Response Time ...................................................................................................... 156
6.6 IPL after Accepting an Interrupt Request ............................................................................. 157
6.7 Register Saving .................................................................................................................... 157
7 Register Restoring from Interrupt Handler................................................................................... 158
8 Interrupt Priority ........................................................................................................................... 158
9 Priority Resolver .......................................................................................................................... 158
10 External Interrupt ......................................................................................................................... 160
11 NMI .............................................................................................................................................. 161
12 Key Input Interrupt ....................................................................................................................... 162
13 Intelligent I/O Interrupt ................................................................................................................. 163
14 Notes on Interrupts ...................................................................................................................... 166
14.1 ISP Setting............................................................................................................................ 166

A- 4
14.2 NMI ....................................................................................................................................... 166
14.3 External Interrupts ................................................................................................................ 166
Watchdog Timer 167
DMAC 169
1 Transfer Cycle.............................................................................................................................. 178
1.1 Effect of Transfer Address and Data Bus Width ................................................................... 178
1.2 Effect of Bus Timing.............................................................................................................. 179
1.3 Effect of RDY Signal............................................................................................................. 179
2 DMA Transfer Cycle..................................................................................................................... 181
3 Channel Priority and DMA Transfer Timing ................................................................................. 182
4 Notes on DMAC........................................................................................................................... 183
4.1 DMAC-associated Register Settings .................................................................................... 183
4.2 Reading DMAC-associated Registers .................................................................................. 183
DMAC II 184
1 DMAC II Settings ......................................................................................................................... 184
1.1 Registers RIPL1 and RIPL2 ................................................................................................. 185
1.2 DMAC II Index ...................................................................................................................... 186
1.3 Interrupt Control Register of the Peripherals ........................................................................ 189
1.4 Relocatable Vector Table of the Peripherals......................................................................... 189
1.5 IRLT Bit in the IIOiIE Register (i = 0 to 11)............................................................................ 189
2 DMAC II Operation ...................................................................................................................... 189
3 Transfer Types ............................................................................................................................. 189
3.1 Memory-to-memory Transfer ................................................................................................ 189
3.2 Immediate Data Transfer ...................................................................................................... 190
3.3 Calculation Result Transfer .................................................................................................. 190
4 Transfer Modes............................................................................................................................ 190
4.1 Single Transfer ..................................................................................................................... 190
4.2 Burst Transfer ....................................................................................................................... 190
4.3 Multiple Transfer ................................................................................................................... 190
5 Chain Transfer ............................................................................................................................. 191
6 DMA II Transfer Complete Interrupt............................................................................................. 191
7 Execution Time ............................................................................................................................ 192
Programmable I/O Ports 193
1 Port Pi Register (Pi register, i = 0 to 15) ...................................................................................... 195
Timers 196
1 Timer A ........................................................................................................................................ 198
1.1 Timer Mode........................................................................................................................... 205
1.2 Event Counter Mode............................................................................................................. 207

A- 5
1.3 One-shot Timer Mode............................................................................................................211
1.4 Pulse-width Modulation Mode............................................................................................... 213
2 Timer B ........................................................................................................................................ 216
2.1 Timer Mode........................................................................................................................... 219
2.2 Event Counter Mode............................................................................................................. 221
2.3 Pulse Period/Pulse-width Measure Mode............................................................................. 223
3 Notes on Timers........................................................................................................................... 226
3.1 Timer A and Timer B............................................................................................................. 226
3.2 Timer A ................................................................................................................................. 226
3.3 Timer B ................................................................................................................................. 228
Three-phase Motor Control Timers 229
1 Modulation Modes of Three-phase Motor Control Timers ........................................................... 236
2 Timer B2 ...................................................................................................................................... 237
3 Timers A4, A1, and A2................................................................................................................. 239
4 Simultaneous Conduction Prevention and Dead Time Timer ...................................................... 242
5 Three-phase Motor Control Timer Operation............................................................................... 243
6 Notes on Three-phase Motor Control Timers .............................................................................. 246
6.1 Shutdown.............................................................................................................................. 246
6.2 Register Setting .................................................................................................................... 246
Serial Interface 247
1 Synchronous Serial Interface Mode............................................................................................. 264
1.1 Reset Procedure on Transmit/Receive Error........................................................................ 269
1.2 CLK Polarity.......................................................................................................................... 269
1.3 LSB First and MSB First Selection ....................................................................................... 270
1.4 Continuous Receive Mode ................................................................................................... 270
1.5 Serial Data Logic Inversion................................................................................................... 271
1.6 CTS/RTS Function................................................................................................................ 271
2 Asynchronous Serial Interface Mode (UART Mode).................................................................... 272
2.1 Bit Rate................................................................................................................................. 277
2.2 Reset Procedure on Transmit/Receive Error........................................................................ 278
2.3 LSB First and MSB First Selection ....................................................................................... 278
2.4 Serial Data Logic Inversion................................................................................................... 279
2.5 TXD and RXD I/O Polarity Inversion .................................................................................... 280
2.6 CTS/RTS Function................................................................................................................ 280
3 Special Mode 1 (I2C Mode).......................................................................................................... 281
3.1 START Condition and STOP Condition Detection................................................................ 287
3.2 START Condition and STOP Condition Generation ............................................................. 287
3.3 Arbitration ............................................................................................................................. 288
3.4 SCL Control and Clock Synchronization .............................................................................. 289
3.5 SDA Output .......................................................................................................................... 291

A- 6
3.6 SDA Input ............................................................................................................................. 291
3.7 Acknowledge ........................................................................................................................ 291
3.8 Transmit/Receive Operation Reset....................................................................................... 291
4 Special Mode 2 ............................................................................................................................ 292
4.1 SSi Input Pin Function (i = 0 to 6)......................................................................................... 294
4.2 Clock Phase Setting ............................................................................................................. 295
5 Notes on Serial Interface ............................................................................................................. 297
5.1 Changing the UiBRG Register (i = 0 to 8) ............................................................................ 297
5.2 Synchronous Serial Interface Mode ..................................................................................... 297
5.3 Special Mode 1 (I2C Mode) .................................................................................................. 297
5.4 Reset Procedure on Communication Error........................................................................... 298
A/D Converter 299
1 Mode Descriptions ....................................................................................................................... 307
1.1 One-shot Mode..................................................................................................................... 307
1.2 Repeat Mode ........................................................................................................................ 308
1.3 Single Sweep Mode.............................................................................................................. 309
1.4 Repeat Sweep Mode 0 ......................................................................................................... 310
1.5 Repeat Sweep Mode 1 ..........................................................................................................311
1.6 Multi-port Single Sweep Mode.............................................................................................. 312
1.7 Multi-port Repeat Sweep Mode 0 ......................................................................................... 313
2 Functions ..................................................................................................................................... 314
2.1 Resolution Selection............................................................................................................. 314
2.2 Sample and Hold Function ................................................................................................... 314
2.3 Trigger Selection................................................................................................................... 314
2.4 DMAC Operating Mode ........................................................................................................ 314
2.5 Function-extended Analog Input Pins................................................................................... 315
2.6 External Operating Amplifier (Op-Amp) Connection Mode................................................... 315
2.7 Power Saving ....................................................................................................................... 316
2.8 Output Impedance of Sensor Equivalent Circuit under A/D Conversion .............................. 316
3 Notes on A/D Converter............................................................................................................... 318
3.1 Notes on Designing Boards.................................................................................................. 318
3.2 Notes on Programming......................................................................................................... 319
D/A Converter 320
CRC Calculator 322
X-Y Conversion 325
1 Data Conversion When Reading ................................................................................................. 326
2 Data Conversion When Writing.................................................................................................... 328

A- 7
Intelligent I/O 329
1 Base Timer for Groups 0 to 2....................................................................................................... 344
2 Time Measurement for Groups 0 and 1 ....................................................................................... 350
3 Waveform Generation for Groups 0 to 2...................................................................................... 354
3.1 Single-phase Waveform Output Mode for Groups 0 to 2...................................................... 355
3.2 Inverted Waveform Output Mode for Groups 0 to 2.............................................................. 357
3.3 Set/Reset Waveform Output Mode (SR Waveform Output Mode) for Groups 0 to 2 ........... 359
3.4 Bit Modulation PWM Output Mode for Group 2 .................................................................... 362
3.5 Real-time Port Output Mode (RTP Output Mode) for Group 2 ............................................. 364
3.6 Parallel Real-time Port Output Mode (RTP Output Mode) for Group 2 ................................ 366
4 Group 2 Serial Interface............................................................................................................... 368
4.1 Variable Synchronous Serial Interface Mode for Group 2 .................................................... 373
Multi-master I2C-bus Interface 376
1 Multi-master I2C-bus Interface-associated Registers .................................................................. 378
1.1 I2C-bus Transmit/Receive Shift Register (I2CTRSR) ........................................................... 378
1.2 I2C-bus Slave Address Register (I2CSAR) .......................................................................... 379
1.3 I2C-bus Control Register 0 (I2CCR0) ................................................................................... 380
1.4 I2C-bus Clock Control Register (I2CCCR)............................................................................ 382
1.5 I2C-bus START and STOP Conditions Control Register (I2CSSCR) ................................... 384
1.6 I2C-bus Control Register 1 (I2CCR1) ................................................................................... 385
1.7 I2C-bus Control Register 2 (I2CCR2) ................................................................................... 388
1.8 I2C-bus Status Register (I2CSR) .......................................................................................... 390
1.9 I2C-bus Mode Register (I2CMR) .......................................................................................... 394
2 Generating a START Condition ................................................................................................... 395
3 Generating a STOP Condition ..................................................................................................... 397
4 START Condition Redundancy Prevention Function ................................................................... 398
5 Detecting START and STOP Conditions ..................................................................................... 399
6 Data Transmission and Reception............................................................................................... 401
6.1 Master Transmission ............................................................................................................ 402
6.2 Slave Reception ................................................................................................................... 403
7 Notes on Using Multi-master I2C-bus Interface ........................................................................... 404
7.1 Accessing Multi-master I2C-bus Interface-associated Registers.......................................... 404
7.2 Generating a Repeated START condition ............................................................................ 406
CAN Module 407
1 CAN SFRs ................................................................................................................................... 410
1.1 CAN0 Control Register (C0CTLR) ........................................................................................411
1.2 CAN0 Clock Select Register (C0CLKR)  .............................................................................. 415
1.3 CAN0 Bit Configuration Register (C0BCR)  ......................................................................... 416
1.4 CAN0 Mask Register k (C0MKRk) (k = 0 to 7) ..................................................................... 418
1.5 CAN0 FIFO Received ID Compare Register n (C0FIDCR0 and C0FIDCR1) 

A- 8
(n = 0, 1) ............................................................................................................................... 419
1.6 CAN0 Mask Invalid Register (C0MKIVLR) .......................................................................... 421
1.7 CAN0 Mailbox (C0MBj) (j = 0 to 31) ..................................................................................... 422
1.8 CAN0 Mailbox Interrupt Enable Register (C0MIER) ............................................................ 426
1.9 CAN0 Message Control Register j (C0MCTLj) (j = 0 to 31).................................................. 427
1.10 CAN0 Receive FIFO Control Register (C0RFCR)  ............................................................... 430
1.11 CAN0 Receive FIFO Pointer Control Register (C0RFPCR)  ................................................ 433
1.12 CAN0 Transmit FIFO Control Register (C0TFCR) .............................................................. 434
1.13 CAN0 Transmit FIFO Pointer Control Register (C0TFPCR) ................................................ 436
1.14 CAN0 Status Register (C0STR)  .......................................................................................... 437
1.15 CAN0 Mailbox Search Mode Register (C0MSMR)  .............................................................. 440
1.16 CAN0 Mailbox Search Status Register (C0MSSR)  ............................................................. 441
1.17 CAN0 Channel Search Support Register (C0CSSR)  .......................................................... 443
1.18 CAN0 Acceptance Filter Support Register (C0AFSR) ......................................................... 444
1.19 CAN0 Error Interrupt Enable Register (C0EIER) ................................................................. 445
1.20 CAN0 Error Interrupt Factor Judge Register (C0EIFR)  ....................................................... 447
1.21 CAN0 Receive Error Count Register (C0RECR) ................................................................. 450
1.22 CAN0 Transmit Error Count Register (C0TECR)  ................................................................ 451
1.23 CAN0 Error Code Store Register (C0ECSR) ....................................................................... 452
1.24 CAN0 Time Stamp Register (C0TSR)  ................................................................................. 454
1.25 CAN0 Test Control Register (C0TCR) ................................................................................. 455
2 Operating Modes ......................................................................................................................... 458
2.1 CAN Reset Mode.................................................................................................................. 459
2.2 CAN Halt Mode..................................................................................................................... 460
2.3 CAN Sleep Mode.................................................................................................................. 461
2.4 CAN Operation Mode (Excluding Bus-off State)................................................................... 462
2.5 CAN Operation Mode (Bus-off State) ................................................................................... 463
3 CAN Communication Speed Configuration.................................................................................. 464
3.1 CAN Clock Configuration...................................................................................................... 464
3.2 Bit Timing Configuration ....................................................................................................... 464
3.3 Bit rate .................................................................................................................................. 465
4 Mailbox and Mask Register Structure .......................................................................................... 466
5 Acceptance Filtering and Masking Function ................................................................................ 468
6 Reception and Transmission ....................................................................................................... 471
6.1 Reception ............................................................................................................................. 472
6.2 Transmission ........................................................................................................................ 474
7 CAN Interrupts ............................................................................................................................. 475
I/O Pins 476
1 Port Pi Direction Register (PDi Register, i = 0 to 15) ................................................................... 477
2 Output Function Select Registers ................................................................................................ 478

A- 9
3 Input Function Select Registers................................................................................................... 496
4 Pull-up Control Registers 0 to 4 (Registers PUR0 to PUR4) ....................................................... 501
5 Port Control Register (PCR Register).......................................................................................... 504
6 Configuring Unused Pins ............................................................................................................. 505
Flash Memory 508
1 Overview...................................................................................................................................... 508
2 Flash Memory Protection............................................................................................................. 510
2.1 Lock Bit Protection................................................................................................................ 510
2.2 ROM Code Protection .......................................................................................................... 510
2.3 ID Code Protection ................................................................................................................511
2.4 Forcible Erase Function........................................................................................................ 512
2.5 Standard Serial I/O Mode Disable Function ......................................................................... 513
3 CPU Rewrite Mode ...................................................................................................................... 514
3.1 CPU Operating Mode and Flash Memory Rewrite ............................................................... 522
3.2 Flash Memory Rewrite Bus Timing....................................................................................... 523
3.3 Software Commands ............................................................................................................ 527
3.4 Mode Transition .................................................................................................................... 528
3.5 Issuing Software Commands................................................................................................ 529
3.6 Status Check ........................................................................................................................ 535
4 Standard Serial I/O Mode ............................................................................................................ 536
5 Parallel I/O mode ......................................................................................................................... 539
6 Notes on Flash Memory Rewriting............................................................................................... 540
6.1 Note on Power Supply.......................................................................................................... 540
6.2 Note on Hardware Reset ...................................................................................................... 540
6.3 Note on Flash Memory Protection ........................................................................................ 540
6.4 Notes on Programming......................................................................................................... 540
6.5 Notes on Interrupts ............................................................................................................... 540
6.6 Notes on Rewrite Control Program....................................................................................... 541
6.7 Notes on Number of Program/Erase Cycles and Software Command Execution Time ....... 541
6.8 Other Notes .......................................................................................................................... 541
Electrical Characteristics 542
Usage Notes 583
1 Notes on Board Designing........................................................................................................... 583
1.1 Power Supply Pins ............................................................................................................... 583
1.2 Supply Voltage...................................................................................................................... 583
2 Notes on Register Setting............................................................................................................ 584
2.1 Registers with Write-only Bits ............................................................................................... 584
3 Notes on Clock Generator ........................................................................................................... 586
3.1 Sub Clock ............................................................................................................................. 586

A- 10
3.2 Power Control....................................................................................................................... 586
4 Notes on Bus ............................................................................................................................... 587
4.1 Notes on Designing a System .............................................................................................. 587
4.2 Notes on Register Settings................................................................................................... 587
5 Notes on Interrupts ...................................................................................................................... 588
5.1 ISP Setting............................................................................................................................ 588
5.2 NMI ....................................................................................................................................... 588
5.3 External Interrupts ................................................................................................................ 588
6 Notes on DMAC........................................................................................................................... 589
6.1 DMAC-associated Register Settings .................................................................................... 589
6.2 Reading DMAC-associated Registers .................................................................................. 589
7 Notes on Timers........................................................................................................................... 590
7.1 Timer A and Timer B............................................................................................................. 590
7.2 Timer A ................................................................................................................................. 590
7.3 Timer B ................................................................................................................................. 592
8 Notes on Three-phase Motor Control Timers .............................................................................. 593
8.1 Shutdown.............................................................................................................................. 593
8.2 Register Setting .................................................................................................................... 593
9 Notes on Serial Interface ............................................................................................................. 594
9.1 Changing the UiBRG Register (i = 0 to 8) ............................................................................ 594
9.2 Synchronous Serial Interface Mode ..................................................................................... 594
9.3 Special Mode 1 (I2C Mode) .................................................................................................. 594
9.4 Reset Procedure on Communication Error........................................................................... 595
10 Notes on A/D Converter............................................................................................................... 596
10.1 Notes on Designing Boards.................................................................................................. 596
10.2 Notes on Programming......................................................................................................... 597
11 Notes on Flash Memory Rewriting............................................................................................... 598
11.1 Note on Power Supply.......................................................................................................... 598
11.2 Note on Hardware Reset ...................................................................................................... 598
11.3 Note on Flash Memory Protection ........................................................................................ 598
11.4 Notes on Programming......................................................................................................... 598
11.5 Notes on Interrupts ............................................................................................................... 598
11.6 Notes on Rewrite Control Program....................................................................................... 599
11.7 Notes on Number of Program/Erase Cycles and Software Command Execution Time ....... 599
11.8 Other Notes .......................................................................................................................... 599
Appendix 1. Package Dimensions 600
INDEX 601

R01UH0211EJ0120 Rev.1.20 Page 1 of 604

Feb 18, 2013

R32C/117 Group

RENESAS MCU

R01UH0211EJ0120

Rev.1.20

Feb 18, 2013

1. Overview

1.1 Features

The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM

code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing

in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from

low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral

functions, provides support for a vast range of application fields.

The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory

space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture,

multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of on-

chip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I2C, and watchdog timer

enables to minimize external components.

The R32C/117 Group is the standard MCU within the R32C/100 Series. This product, provided as 100-pin

and 144-pin plastic molded LQFP packages, has nine channels of serial interface, one channel of multi-

master I2C-bus interface, and one channel of CAN module.

1.1.1 Applications

Car audio, audio, printer, office/industrial equipment, etc.

R01UH0211EJ0120 Rev.1.20 Page 2 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

1.1.2 Performance Overview

Tables 1.1 to 1.4 list the performance overview of the R32C/117 Group.

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Table 1.1 Performance Overview for the 144-pin Package (1/2)

Unit Function Explanation

CPU Central

processing unit

R32C/100 Series CPU Core

• Basic instructions: 108

• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)

• Multiplier: 32-bit × 32-bit  64-bit

• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit  64-bit

• IEEE-754 compatible FPU: Single precision

• 32-bit barrel shifter

• Operating mode: Single-chip mode, memory expansion mode,

microprocessor mode (optional (1))

Memory Flash memory: 384 Kbytes to 1 Mbyte

RAM: 40 K/48 K/63 Kbytes

Data flash: 4 Kbytes × 2 blocks

Refer to Table 1.5 for each product’s memory size

Voltage

Detector

Low voltage

detector

Optional (1)

Low voltage detection interrupt

Clock Clock generator • 4 circuits (main clock, sub clock, PLL, on-chip oscillator)

• Oscillation stop detector: Main clock oscillator stop/restart detection

• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable

• Low power modes: Wait mode, stop mode

External Bus

Expansion

Bus and memory

expansion

• Address space: 4 Gbytes (of which up to 64 Mbytes is user

accessible)

• External bus Interface: Support for wait-state insertion, 4 chip select

outputs

• Bus format: Separate bus/Multiplexed bus selectable, data bus width

selectable (8/16/32 bits)

Interrupts Interrupt vectors: 261

External interrupt inputs: NMI, INT × 9, key input × 4

Interrupt priority levels: 7

Watchdog Timer 15 bits × 1 (selectable input frequency from prescaler output)

DMA DMAC 4 channels

• Cycle-steal transfer mode

• Request sources: 57

• 2 transfer modes: Single transfer, repeat transfer

DMAC II • Triggered by an interrupt request of any peripheral

• 3 characteristic transfer functions: Immediate data transfer,

calculation result transfer, chain transfer

I/O Ports Programmable

I/O ports

• 2 input-only ports

• 120 CMOS I/O ports (of which 32 are 5 V tolerant)

• A pull-up resistor is selectable for every 4 input ports (except 5 V

tolerant inputs)

R01UH0211EJ0120 Rev.1.20 Page 3 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Table 1.2 Performance Overview for the 144-pin Package (2/2)

Unit Function Explanation

Timer Timer A 16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width

modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (two-

phase encoder input) × 3

Timer B 16-bit timer × 6

Timer mode, event counter mode, pulse frequency measurement

mode, pulse-width measurement mode

Three-phase

motor control

timer

Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)

8-bit programmable dead time timer

Serial

Interface

UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels

•I

2C-bus (UART0 to UART6)

• Special mode 2 (UART0 to UART6)

• IEBus (optional (1)) (UART0 to UART6)

A/D Converter 10-bit resolution × 34 channels

Sample and hold functionality integrated

D/A Converter 8-bit resolution × 2

CRC Calculator CRC-CCITT (X16 + X12 + X5 + 1)

X-Y Converter 16 bits × 16 bits

Intelligent I/O Time measurement (input capture): 16 bits × 16

Waveform generation (output compare): 16 bits × 24

Serial interface: Variable-length synchronous serial I/O mode, IEBus

mode (optional (1))

Multi-master I2C-bus Interface 1 channel

CAN Module 1 channel

CAN functionality compliant with ISO 11898-1

32 mailboxes

Flash Memory Programming and erasure supply voltage: VCC = 3.0 to 5.5 V

Minimum endurance: 1,000 program/erase cycles

Security protection: ROM code protect, ID code protect

Debugging: On-chip debug, on-board flash programming

Operating Frequency/Supply

Voltage

64 MHz (high speed version)/VCC = 3.0 to 5.5 V

50 MHz (normal speed version)/VCC = 3.0 to 5.5 V

Operating Temperature -20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

Current Consumption 45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)

35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)

8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)

Package 144-pin plastic molded LQFP (PLQP0144KA-A)

R01UH0211EJ0120 Rev.1.20 Page 4 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Table 1.3 Performance Overview for the 100-pin Package (1/2)

Unit Function Explanation

CPU Central

processing unit

R32C/100 Series CPU Core

• Basic instructions: 108

• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)

• Multiplier: 32-bit × 32-bit  64-bit

• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit  64-bit

• IEEE-754 compatible FPU: Single precision

• 32-bit barrel shifter

• Operating mode: Single-chip mode, memory expansion mode,

microprocessor mode (optional (1))

Memory Flash memory: 128 Kbytes to 1 Mbyte

RAM: 20 K/40 K/48 K/63 Kbytes

Data flash: 4 Kbytes × 2 blocks

Refer to Table 1.5 for each product’s memory size

Voltage

Detector

Low voltage

detector

Optional (1)

Low voltage detection interrupt

Clock Clock generator • 4 circuits (main clock, sub clock, PLL, on-chip oscillator)

• Oscillation stop detector: Main clock oscillator stop/restart detection

• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable

• Low power modes: Wait mode, stop mode

External Bus

Expansion

Bus and memory

expansion

• Address space: 4 Gbytes (of which up to 64 Mbytes is user

accessible)

• External bus Interface: Support for wait-state insertion, 4 chip select

outputs

• Bus format: Separate bus/Multiplexed bus selectable, data bus width

selectable (8/16 bits)

Interrupts Interrupt vectors: 261

External interrupt inputs: NMI, INT × 6, key input × 4

Interrupt priority levels: 7

Watchdog Timer 15 bits × 1 (selectable input frequency from prescaler output)

DMA DMAC 4 channels

• Cycle-steal transfer mode

• Request sources: 51

• 2 transfer modes: Single transfer, repeat transfer

DMAC II • Triggered by an interrupt request of any peripheral

• 3 characteristic transfer functions: Immediate data transfer,

calculation result transfer, chain transfer

I/O Ports Programmable

I/O ports

• 2 input-only ports

• 84 CMOS I/O ports (of which 32 are 5 V tolerant)

• A pull-up resistor is selectable for every 4 input ports (except 5 V

tolerant inputs)

R01UH0211EJ0120 Rev.1.20 Page 5 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Table 1.4 Performance Overview for the 100-pin Package (2/2)

Unit Function Explanation

Timer Timer A 16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width

modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (two-

phase encoder input) × 3

Timer B 16-bit timer × 6

Timer mode, event counter mode, pulse frequency measurement

mode, pulse-width measurement mode

Three-phase

motor control

timer

Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)

8-bit programmable dead time timer

Serial

Interface

UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels

•I

2C-bus (UART0 to UART6)

• Special mode 2 (UART0 to UART6)

• IEBus (optional (1)) (UART0 to UART6)

A/D Converter 10-bit resolution × 26 channels

Sample and hold functionality integrated

D/A Converter 8-bit resolution × 2

CRC Calculator CRC-CCITT (X16 + X12 + X5 + 1)

X-Y Converter 16 bits × 16 bits

Intelligent I/O Time measurement (input capture): 16 bits × 16

Waveform generation (output compare): 16 bits × 19

Serial interface: Variable-length synchronous serial I/O mode, IEBus

mode (optional (1))

Multi-master I2C-bus Interface 1 channel

CAN Module 1 channel

CAN functionality compliant with ISO 11898-1

32 mailboxes

Flash Memory Programming and erasure supply voltage: VCC = 3.0 to 5.5 V

Minimum endurance: 1,000 program/erase cycles

Security protection: ROM code protect, ID code protect

Debugging: On-chip debug, on-board flash programming

Operating Frequency/Supply

Voltage

64 MHz (high speed version)/VCC = 3.0 to 5.5 V

50 MHz (normal speed version)/VCC = 3.0 to 5.5 V

Operating Temperature -20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

Current Consumption 45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)

35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)

8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)

Package 100-pin plastic molded LQFP (PLQP0100KB-A)

R01UH0211EJ0120 Rev.1.20 Page 6 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

1.2 Product Information

Tables 1.5 and 1.6 list the product information and Figure 1.1 shows the details of the part number.

Notes:

1. The old package codes are as follows:

PLQP0100KB-A: 100P6Q-A; PLQP0144KA-A: 144P6Q-A

2. “8 Kbytes” in the ROM capacity indicates the data flash memory capacity.

Table 1.5 R32C/117 Group Product List for Normal Speed Version (1/2) As of February, 2013

Part Number Package Code (1) ROM Capacity (2) RAM Capacity Remarks

R5F6417BNFB (P)

PLQP0100KB-A 128 Kbytes

+ 8 Kbytes

20 Kbytes

-20°C to 85°C (N version)

R5F6417BDFB -40°C to 85°C (D version)

R5F6417BPFB -40°C to 85°C (P version)

R5F6417ANFB (P)

PLQP0100KB-A 256 Kbytes

+ 8 Kbytes

-20°C to 85°C (N version)

R5F6417ADFB -40°C to 85°C (D version)

R5F6417APFB -40°C to 85°C (P version)

R5F64175NFD (P)

PLQP0144KA-A

384 Kbytes

+ 8 Kbytes

40 Kbytes

-20°C to 85°C (N version)

R5F64175DFD -40°C to 85°C (D version)

R5F64175PFD -40°C to 85°C (P version)

R5F64175NFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64175DFB -40°C to 85°C (D version)

R5F64175PFB -40°C to 85°C (P version)

R5F64176NFD (P)

PLQP0144KA-A

512 Kbytes

+ 8 Kbytes

-20°C to 85°C (N version)

R5F64176DFD -40°C to 85°C (D version)

R5F64176PFD -40°C to 85°C (P version)

R5F64176NFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64176DFB -40°C to 85°C (D version)

R5F64176PFB -40°C to 85°C (P version)

R5F64177NFD (P)

PLQP0144KA-A

640 Kbytes

+ 8 Kbytes 48 Kbytes

-20°C to 85°C (N version)

R5F64177DFD -40°C to 85°C (D version)

R5F64177PFD -40°C to 85°C (P version)

R5F64177NFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64177DFB -40°C to 85°C (D version)

R5F64177PFB -40°C to 85°C (P version)

R5F64178NFD (P)

PLQP0144KA-A

768 Kbytes

+ 8 Kbytes

63 Kbytes

-20°C to 85°C (N version)

R5F64178DFD -40°C to 85°C (D version)

R5F64178PFD -40°C to 85°C (P version)

R5F64178NFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64178DFB -40°C to 85°C (D version)

R5F64178PFB -40°C to 85°C (P version)

R5F64179NFD (P)

PLQP0144KA-A

1 Mbyte

+ 8 Kbytes

-20°C to 85°C (N version)

R5F64179DFD -40°C to 85°C (D version)

R5F64179PFD -40°C to 85°C (P version)

R5F64179NFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64179DFB -40°C to 85°C (D version)

R5F64179PFB -40°C to 85°C (P version)

(P): On planning phase

R01UH0211EJ0120 Rev.1.20 Page 7 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Notes:

1. The old package codes are as follows:

PLQP0100KB-A: 100P6Q-A; PLQP0144KA-A: 144P6Q-A

2. “8 Kbytes” in the ROM capacity indicates the data flash memory capacity.

Table 1.6 R32C/117 Group Product List for High Speed Version (2/2) As of February, 2013

Part Number Package Code (1) ROM Capacity (2) RAM Capacity Remarks

R5F6417BHNFB (P)

PLQP0100KB-A 128 Kbytes

+ 8 Kbytes

20 Kbytes

-20°C to 85°C (N version)

R5F6417BHDFB -40°C to 85°C (D version)

R5F6417BHPFB -40°C to 85°C (P version)

R5F6417AHNFB (P)

PLQP0100KB-A 256 Kbytes

+ 8 Kbytes

-20°C to 85°C (N version)

R5F6417AHDFB -40°C to 85°C (D version)

R5F6417AHPFB -40°C to 85°C (P version)

R5F64175HNFD (P)

PLQP0144KA-A

384 Kbytes

+ 8 Kbytes

40 Kbytes

-20°C to 85°C (N version)

R5F64175HDFD -40°C to 85°C (D version)

R5F64175HPFD -40°C to 85°C (P version)

R5F64175HNFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64175HDFB -40°C to 85°C (D version)

R5F64175HPFB -40°C to 85°C (P version)

R5F64176HNFD (P)

PLQP0144KA-A

512 Kbytes

+ 8 Kbytes

-20°C to 85°C (N version)

R5F64176HDFD -40°C to 85°C (D version)

R5F64176HPFD -40°C to 85°C (P version)

R5F64176HNFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64176HDFB -40°C to 85°C (D version)

R5F64176HPFB -40°C to 85°C (P version)

R5F64177HNFD (P)

PLQP0144KA-A

640 Kbytes

+ 8 Kbytes 48 Kbytes

-20°C to 85°C (N version)

R5F64177HDFD -40°C to 85°C (D version)

R5F64177HPFD -40°C to 85°C (P version)

R5F64177HNFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64177HDFB -40°C to 85°C (D version)

R5F64177HPFB -40°C to 85°C (P version)

R5F64178HNFD (P)

PLQP0144KA-A

768 Kbytes

+ 8 Kbytes

63 Kbytes

-20°C to 85°C (N version)

R5F64178HDFD -40°C to 85°C (D version)

R5F64178HPFD -40°C to 85°C (P version)

R5F64178HNFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64178HDFB -40°C to 85°C (D version)

R5F64178HPFB -40°C to 85°C (P version)

R5F64179HNFD (P)

PLQP0144KA-A

1 Mbyte

+ 8 Kbytes

-20°C to 85°C (N version)

R5F64179HDFD -40°C to 85°C (D version)

R5F64179HPFD -40°C to 85°C (P version)

R5F64179HNFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64179HDFB -40°C to 85°C (D version)

R5F64179HPFB -40°C to 85°C (P version)

(P): On planning phase

R01UH0211EJ0120 Rev.1.20 Page 8 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Figure 1.1 Part Numbering

Part Number

R5 F 64 17 9 H P XXX FD

Package Code

FB : PLQP0100KB-A

FD : PLQP0144KA-A

ROM Number

Omitted in the flash memory version

ROM/RAM Capacity

B : 128 KB/20 KB

A : 256 KB/20 KB

5 : 384 KB/40 KB

6 : 512 KB/40 KB

7 : 640 KB/48 KB

8 : 768 KB/63 KB

9 : 1 MB/63 KB

Temperature Code

N : -20°C to 85°C

D : -40°C to 85°C

P : -40°C to 85°C

Memory Type

F : Flash memory version

R32C/117 Group

R32C/100 Series

Rated Operating Frequency

H : 64 MHz (High speed version)

None : 50 MHz (Normal speed version)

R01UH0211EJ0120 Rev.1.20 Page 9 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

1.3 Block Diagram

Figure 1.2 shows the block diagram for the R32C/117 Group.

Figure 1.2 R32C/117 Group Block Diagram

Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6

8888888

Port P7 P8_5 Port P9 Port P10

8 7 8 (3) 8

Peripherals

Timers:

Timer A 16 bits × 5 timers

Timer B 16 bits × 6 timers

Three-phase motor

controller

Watchdog timer:

15 bits

D/A converter:

8 bits × 2 channels

A/D converter:

10 bits × 1 circuit

Standard: 10 inputs

Maximum: 34 inputs (1)

Serial interface:

9 channels X-Y converter:

16 bits × 16 bits

Clock generator:

4 circuits

- XIN-XOUT

- XCIN-XCOUT

- On-chip oscillator

- PLL frequency synthesizer

DMAC

CRC calculator (CCITT)

X16 + X12 + X5 + 1

Intelligent I/O

Time measurement: 16

Wave generation: 24 (2)

Serial interface:

- Variable-length

synchronous serial I/O

- IEBus

R32C/100 Series CPU Core

R2R0

R3R1

R6R4

R7R5

FLG

INTB

ISP

USP

SVF

SVP

VCT

R2R0

R3R1

R6R4

R7R5

Memory

ROM

RAM

Multiplier

Port P14 Port P14_1 Port P11Port P12Port P13

4 588

DMAC II

Floating-point unit

Port P8

Port P15

(Note 4)

Notes:

1. The 144-pin package has 34 inputs. The 100-pin package can have up to 26 inputs.

2. The 144-pin package has 24 outputs. The 100-pin package has 19 outputs.

3. The 144-pin package has eight ports. The 100-pin package has five I/O ports and one input-only port

(P9_1).

4. Ports P11 to P15 are only available in the 144-pin package.

Multi-master I2C-bus

interface:

1 channel

CAN module:

1 channel